Pixel circuit, driving method and display device

Abstract

The application provides a pixel circuit, a driving method and a display device. The pixel circuit comprises a light emitting element, a driving circuit, a on-off control circuit, a first energy storage circuit and a data writing circuit. The on-off control circuit controls the connection or disconnection between the first node and the second node under the control of a on-off control signal. The first energy storage circuit is electrically connected with the second node and the writing node respectively. The data writing circuit provides a data voltage to the writing node under the control of a scanning signal. In the light emitting stage, the on-off control circuit controls the disconnection between the first node and the second node under the control of the on-off control signal, so that the potential of the first node is not affected by the floating writing node, the potential of the first node is stable, and the display uniformity is improved.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a pixel circuit, driving method, and display device. Background Technology

[0002] In the relevant pixel circuit, during the light-emitting stage, the potential of the first node is affected by the floating write node, making the potential of the first node unstable. The first node is electrically connected to the gate of the driving transistor included in the driving circuit of the pixel circuit, thereby affecting the display uniformity. Summary of the Invention

[0003] The main objective of this invention is to provide a pixel circuit, driving method, and display device to solve the problem in the prior art where, during the light-emitting stage, the potential of the first node is affected by the floating write node, causing the potential of the first node to be unstable, thereby affecting the uniformity of the display.

[0004] In one aspect, embodiments of the present invention provide a pixel circuit, including a light-emitting element, a driving circuit, an on / off control circuit, a first energy storage circuit, and a data writing circuit;

[0005] The control terminal of the driving circuit is electrically connected to the first node, and the driving circuit is used to generate a driving current to drive the light-emitting element under the control of the potential of the first node.

[0006] The on / off control circuit is electrically connected to the on / off control terminal, the first node and the second node respectively, and is used to control the connection or disconnection between the first node and the second node under the control of the on / off control signal provided by the on / off control terminal.

[0007] The first energy storage circuit is electrically connected to the second node and the write node, respectively;

[0008] The data writing circuit is electrically connected to the scanning end, the data line and the writing node, respectively, and is used to provide the data voltage provided by the data line to the writing node under the control of the scanning signal provided by the scanning end.

[0009] The pixel circuit described in at least one embodiment of the present invention further includes a second energy storage circuit and a bias control circuit;

[0010] The first end of the second energy storage circuit is electrically connected to the first node, and the second end of the second energy storage circuit is electrically connected to the third node;

[0011] The bias control circuit is electrically connected to the bias control terminal, the bias voltage terminal, and the third node, respectively, and is used to write the bias voltage provided by the bias voltage terminal into the third node under the control of the bias control signal provided by the bias control terminal.

[0012] The pixel circuit described in at least one embodiment of the present invention further includes a first control circuit;

[0013] The first control circuit is electrically connected to the first control terminal, the first voltage terminal, and the third node, respectively, and is used to control the connection or disconnection between the first voltage terminal and the third node under the control of the first control signal provided by the first control terminal.

[0014] The pixel circuit described in at least one embodiment of the present invention further includes a second energy storage circuit;

[0015] The second energy storage circuit is electrically connected to the first node and is used to maintain the potential of the first node.

[0016] The pixel circuit described in at least one embodiment of the present invention further includes a first initialization circuit, a second initialization circuit, and a compensation control circuit;

[0017] The first terminal of the driving circuit is electrically connected to the first voltage terminal, and the second terminal of the driving circuit is electrically connected to the fourth node;

[0018] The first initialization circuit is electrically connected to the first reset control terminal and the first initial voltage terminal respectively. The first initialization circuit is also electrically connected to the first node or the fourth node. The first initialization circuit is used to write the first initial voltage provided by the first initial voltage terminal into the first node or the fourth node under the control of the first reset control signal provided by the first reset control terminal.

[0019] The second initialization circuit is electrically connected to the second reset control terminal, the reference voltage terminal and the write node, respectively, and is used to write the reference voltage provided by the reference voltage terminal into the write node under the control of the second reset control signal provided by the second reset control terminal;

[0020] The compensation control circuit is electrically connected to the compensation control terminal, the first node, and the fourth node, respectively, and is used to control the connection or disconnection between the first node and the fourth node under the control of the compensation control signal provided by the compensation control terminal.

[0021] The pixel circuit described in at least one embodiment of the present invention further includes a light-emitting control circuit and a third initialization circuit; the first terminal of the driving circuit is electrically connected to the first voltage terminal, and the second terminal of the driving circuit is electrically connected to the fourth node;

[0022] The light-emitting control circuit is electrically connected to the light-emitting control terminal, the fourth node, and the first electrode of the light-emitting element, respectively, and is used to control the connection or disconnection between the fourth node and the first electrode of the light-emitting element under the control of the light-emitting control signal provided by the light-emitting control terminal;

[0023] The third initialization circuit is electrically connected to the third reset control terminal, the second initial voltage terminal, and the first electrode of the light-emitting element, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element under the control of the third reset control signal provided by the third reset control terminal.

[0024] The second electrode of the light-emitting element is electrically connected to the second voltage terminal.

[0025] Optionally, the on / off control circuit includes a first transistor; the first energy storage circuit includes a first capacitor; and the data writing circuit includes a second transistor.

[0026] The gate of the first transistor is electrically connected to the on / off control terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the second node.

[0027] The first terminal of the first capacitor is electrically connected to the second node, and the second terminal of the first capacitor is electrically connected to the write node;

[0028] The gate of the second transistor is electrically connected to the scan terminal, the first terminal of the second transistor is electrically connected to the data line, and the second terminal of the second transistor is electrically connected to the write node.

[0029] Optionally, the second energy storage circuit includes a second capacitor, and the bias control circuit includes a third transistor;

[0030] The first terminal of the second capacitor is electrically connected to the first node, and the second terminal of the second capacitor is electrically connected to the third node;

[0031] The gate of the third transistor is electrically connected to the bias control terminal, the first terminal of the third transistor is electrically connected to the bias voltage terminal, and the second terminal of the third transistor is electrically connected to the third node.

[0032] Optionally, the first control circuit includes a fourth transistor;

[0033] The gate of the fourth transistor is electrically connected to the first control terminal, the first terminal of the fourth transistor is electrically connected to the first voltage terminal, and the second terminal of the fourth transistor is electrically connected to the third node.

[0034] In a second aspect, embodiments of the present invention provide a driving method applied to the aforementioned pixel circuit, wherein the display cycle of the pixel circuit includes a light-emitting phase; the driving method includes:

[0035] During the light-emitting stage, the on / off control circuit controls the disconnection between the first node and the second node under the control of the on / off control signal.

[0036] Optionally, the pixel circuit further includes a second energy storage circuit and a bias control circuit; the display cycle further includes a bias phase set before the light emission phase; the driving method further includes:

[0037] During the biasing phase, the biasing control circuit writes the bias voltage into the third node under the control of the biasing control signal.

[0038] Optionally, the pixel circuit further includes a first control circuit; the driving method further includes:

[0039] During the biasing phase, the first control circuit, under the control of the first control signal, controls the first voltage terminal to disconnect from the third node.

[0040] Optionally, the display cycle includes a data writing phase set during the bias phase; the driving method further includes:

[0041] During the data writing phase, the data writing circuit, under the control of the scanning signal provided by the scanning end, provides the data voltage provided by the data line to the writing node, and the on / off control circuit, under the control of the on / off control signal, controls the connection between the first node and the third node.

[0042] Optionally, the display cycle further includes a compensation phase; the compensation phase is independent of the data writing phase; the pixel circuit further includes a second initialization circuit and a compensation control circuit; the driving method further includes:

[0043] During the compensation phase, the on / off control circuit controls the connection between the first node and the third node under the control of the on / off control signal. The second initialization circuit provides the reference voltage provided by the reference voltage terminal to the write node under the control of the second reset control signal. The compensation control circuit controls the connection between the first node and the fourth node under the control of the compensation control signal provided by the compensation control terminal.

[0044] In a third aspect, embodiments of the present invention provide a display device including the pixel circuit described above.

[0045] The pixel circuit, driving method, and display device described in this embodiment of the invention can, during the light-emitting stage, control the disconnection between the first node and the second node through the on / off control circuit under the control of the on / off control signal, so that the potential of the first node is not affected by the floating write node, thereby stabilizing the potential of the first node and improving display uniformity. Attached Figure Description

[0046] Figure 1A This is a circuit diagram of at least one embodiment of a pixel circuit;

[0047] Figure 1B yes Figure 1A The timing diagram of at least one embodiment of the pixel circuit shown;

[0048] Figure 1C This is a circuit diagram of at least one embodiment of a pixel circuit;

[0049] Figure 1D This is a circuit diagram of at least one embodiment of a pixel circuit;

[0050] Figure 1E yes Figure 1D The timing diagram of at least one embodiment of the pixel circuit shown;

[0051] Figure 2 This is a structural diagram of the pixel circuit according to at least one embodiment of the present invention;

[0052] Figure 3 This is a structural diagram of the pixel circuit according to at least one embodiment of the present invention;

[0053] Figure 4 This is a structural diagram of the pixel circuit according to at least one embodiment of the present invention;

[0054] Figure 5 This is a structural diagram of the pixel circuit according to at least one embodiment of the present invention;

[0055] Figure 6 This is a structural diagram of the pixel circuit according to at least one embodiment of the present invention;

[0056] Figure 7 This is a structural diagram of the pixel circuit according to at least one embodiment of the present invention;

[0057] Figure 8 This is a circuit diagram of the pixel circuit according to at least one embodiment of the present invention;

[0058] Figure 9 yes Figure 8 The timing diagram of at least one embodiment of the pixel circuit shown;

[0059] Figure 10 This is a circuit diagram of the pixel circuit according to at least one embodiment of the present invention;

[0060] Figure 11 yes Figure 10 The timing diagram of at least one embodiment of the pixel circuit shown;

[0061] Figure 12 This is a circuit diagram of the pixel circuit according to at least one embodiment of the present invention;

[0062] Figure 13 yes Figure 12The timing diagram of at least one embodiment of the pixel circuit shown;

[0063] Figure 14 This is a circuit diagram of the pixel circuit according to at least one embodiment of the present invention;

[0064] Figure 15 This is a circuit diagram of the pixel circuit according to at least one embodiment of the present invention. Detailed Implementation

[0065] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0066] In all embodiments of this invention, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In these embodiments, to distinguish between the two terminals of the transistor other than the gate, one terminal is referred to as the first terminal, and the other as the second terminal.

[0067] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0068] like Figure 1A As shown, at least one embodiment of the pixel circuit may include an organic light-emitting diode O1, a driving transistor T0, a second transistor T2, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a first capacitor C1, and a second capacitor C2.

[0069] The gate of T0 is electrically connected to the first node N1, the source of T0 is electrically connected to the power supply voltage terminal VDD, and the drain of T0 is electrically connected to the fourth node N4.

[0070] The gate of T2 is electrically connected to the scan terminal GT, the source of T2 is electrically connected to the data line DL, and the drain of T2 is electrically connected to the second terminal of C1; the first terminal of C1 is electrically connected to the first node N1; and the second terminal of C1 is electrically connected to the write node NX.

[0071] The first terminal of C2 is electrically connected to the first node N1, and the second terminal of C2 is electrically connected to the power supply voltage terminal VDD.

[0072] The gate of T5 is electrically connected to the first reset control terminal RST1, the source of T5 is electrically connected to the first initial voltage terminal I1, and the drain of T5 is electrically connected to the fourth node N4.

[0073] The gate of T6 is electrically connected to the second reset control terminal RST2, the source of T6 is electrically connected to the reference voltage terminal REF, and the drain of T6 is electrically connected to the second terminal of C1.

[0074] The gate of T7 is electrically connected to the light-emitting control terminal EM, the source of T7 is electrically connected to the fourth node N4, the drain of T7 is electrically connected to the anode of O1, and the cathode of O1 is electrically connected to the low voltage terminal VSS.

[0075] The gate of T8 is electrically connected to the first reset control terminal RST1, the source of T8 is electrically connected to the second initial voltage terminal I2, and the drain of T8 is electrically connected to the anode of O1.

[0076] The gate of T9 is electrically connected to the second reset control terminal RST2, the source of T9 is electrically connected to the first node N1, and the drain of T9 is electrically connected to the fourth node N4.

[0077] exist Figure 1A In at least one embodiment shown, all transistors are p-type transistors, but this is not a limitation.

[0078] Figure 1B yes Figure 1A The timing diagram shows the operation of at least one embodiment of the pixel circuit.

[0079] Figure 1A At least one embodiment of the pixel circuit shown can separate data voltage writing and threshold voltage compensation during operation, so that the threshold voltage compensation time is not limited by the line period, and the threshold voltage compensation time can be increased to fully compensate the threshold voltage and power supply voltage of the driving transistor.

[0080] like Figure 1B As shown, Figure 1A When at least one embodiment of the pixel circuit shown is in operation, the display cycle may include a reset phase S1, a compensation phase S2, a data writing phase S3, and a light emission phase S4 arranged sequentially.

[0081] During the reset phase S1, EM provides a high voltage signal, RST1 provides a low voltage signal, RST2 provides a low voltage signal, GT provides a high voltage signal, T7 is turned off, T2 is turned off, T5 and T9 are turned on, I1 provides the first initial voltage Vinit1 to N1 and N4, T6 is turned on, REF provides the reference voltage Vref to NX, T8 is turned on, and I2 provides the second initial voltage Vinit2 to clear the residual charge on the anode of O1.

[0082] During the compensation phase S2, EM provides a high voltage signal, RST1 provides a high voltage signal, RST2 provides a low voltage signal, GT provides a high voltage signal, T6 is turned on, and T9 is turned on.

[0083] At the start of the compensation phase S2, T0 is turned on, and Vref is charged through C1, T9 and the turned-on T0, changing the potential of N1 until the potential of N1 becomes Vdd+Vth, at which point T0 is turned off, completing the threshold voltage compensation; where Vdd is the voltage value of the power supply voltage provided by VDD, and Vth is the threshold voltage of T0.

[0084] During the data writing phase S3, EM provides a high voltage signal, RST1 provides a high voltage signal, RST2 provides a high voltage signal, GT provides a low voltage signal, T2 is turned on, and DL provides the data voltage Vdata to NX. Through the coupling effect of C1, the potential of N1 changes from Vdd+Vth to Vdd+Vth-Vref+Vdata.

[0085] During the light-emitting phase S4, EM provides a low-voltage signal, while RST1, RST2, and GT all provide high-voltage signals. T2 and T6 are turned off, and NX is in a floating state to prevent the potential of N1 from being affected by the potential of NX, thus maintaining the stability of N1's potential. T7 is turned on, and T0 drives O1 to emit light. At this time, the current value of the driving current generated by T0 to drive O1 is K×(Vdd+Vth-Vref+Vdata-Vdd-Vth). 2 =K×(Vdata-Vref) 2 Where K is the current coefficient of T0, it can be seen that Id is independent of Vdd and Vth, which can compensate for the uneven display caused by the uneven driving current caused by Vdd and Vth.

[0086] Figure 1C At least one embodiment of the pixel circuit shown is Figure 1A The difference in at least one embodiment of the pixel circuit shown is as follows: the drain of T5 is electrically connected to N1.

[0087] Figure 1D At least one embodiment of the pixel circuit shown is Figure 1A The differences between at least one embodiment of the pixel circuit shown are as follows:

[0088] It also includes a bias control circuit and a first control circuit; the bias control circuit includes a third transistor T3; the first control circuit includes a fourth transistor T4;

[0089] The second terminal of the second capacitor C2 is electrically connected to the third node N3;

[0090] The gate of the third transistor T3 is electrically connected to the bias control terminal SP, the source of the third transistor T3 is electrically connected to the bias voltage terminal VB, and the drain of the third transistor T3 is electrically connected to the third node N3.

[0091] The gate of the fourth transistor T4 is electrically connected to the first control terminal SC, the source of the fourth transistor T4 is electrically connected to the power supply voltage terminal VDD, and the drain of the fourth transistor T4 is electrically connected to the third node N3.

[0092] T3 and T4 are p-type transistors.

[0093] like Figure 1E As shown, the present invention Figure 1D When at least one embodiment of the pixel circuit shown is in operation, the display cycle may include a reset phase S1, a compensation phase S2, a writing phase S3, a bias phase S0, and a light emission phase S4 arranged sequentially.

[0094] During the reset phase S1, EM provides a high voltage signal, RST1 provides a low voltage signal, RST2 provides a low voltage signal, GT provides a high voltage signal, SP provides a high voltage signal, SC provides a low voltage signal, T3 is turned off, T4 is turned on, VDD is connected to N3, T7 is turned off, T2 is turned off, T5 and T9 are turned on, I1 provides the first initial voltage Vinit1 to N1 and N4, T6 is turned on, REF provides the reference voltage Vref to NX, T8 is turned on, and I2 provides the second initial voltage Vinit2, clearing the residual charge on the anode of O1;

[0095] During the compensation phase S2, EM provides a high voltage signal, RST1 provides a high voltage signal, RST2 provides a low voltage signal, GT provides a high voltage signal, SP provides a high voltage signal, SC provides a low voltage signal, T3 is off, T4 is on, VDD and N3 are connected, T6 is on, and T9 is on.

[0096] At the start of the compensation phase S2, T0 is turned on, and Vref is charged through C1, T9 and the turned-on T0, changing the potential of N1 until the potential of N1 becomes Vdd+Vth, at which point T0 is turned off, completing the threshold voltage compensation; where Vdd is the voltage value of the power supply voltage provided by VDD, and Vth is the threshold voltage of T0.

[0097] During the data writing phase S3, EM provides a high voltage signal, RST1 provides a high voltage signal, RST2 provides a high voltage signal, GT provides a low voltage signal, ST provides a low voltage signal, SP provides a high voltage signal, SC provides a low voltage signal, T3 is turned off, T4 is turned on, VDD and N3 are connected, T2 is turned on, DL provides the data voltage Vdata to NX, and through the coupling effect of C1, the potential of N1 changes from Vdd+Vth to Vdd+Vth-Vref+Vdata;

[0098] During the biasing phase S0, EM provides a high voltage signal, RST1 provides a high voltage signal, RST2 provides a high voltage signal, GT provides a high voltage signal, SP provides a low voltage signal, and SC provides a high voltage signal. T4 is turned off and T4 is turned on. VB provides a bias voltage Vbias to N3, and the potential of N3 changes from Vdd to Vbias. Due to the coupling effect of C2, the potential of N1 changes from Vdd+Vth-Vref+Vdata to Vdd+Vth-Vref+Vdata+Vbias-Vdd, that is, it becomes Vth-Vref+Vdata+Vbias, in order to improve the hysteresis phenomenon of T0. The bias effect on T0 can be adjusted by adjusting the voltage value of Vbias and the number of effective pulses of the bias control signal provided by SP.

[0099] During the light-emitting phase S4, EM provides a low-voltage signal, RST1, RST2, and GT all provide high-voltage signals, ST provides a high-voltage signal, SP provides a high-voltage signal, and SC provides a low-voltage signal. T3 is off, T4 is on, and N3 is connected to VDD. The potential of N3 changes from Vbias to Vdd. Due to the coupling effect of C2, the potential of N1 changes back to Vdd + Vth - Vref + Vdata. T2 and T6 are off, and NX is in a floating state to prevent the potential of N1 from being affected by the potential of NX, thus maintaining the stability of the potential of N1. T7 is on, and T0 drives O1 to emit light. At this time, the current value of the driving current generated by T0 to drive O1 is K × (Vdd + Vth - Vref + Vdata - Vdd - Vth). 2 =K×(Vdata-Vref) 2 Where K is the current coefficient of T0, it can be seen that Id is independent of Vdd and Vth, which can compensate for the uneven display caused by the uneven driving current caused by Vdd and Vth.

[0100] Figure 1A , Figure 1C , Figure 1D In at least one embodiment of the pixel circuit shown, during operation, in the light-emitting phase, the potential of the first node is unstable due to the influence of the floating write node.

[0101] like Figure 2 As shown, the pixel circuit of at least one embodiment of the present invention includes a light-emitting element E1, a driving circuit 10, an on / off control circuit 11, a first energy storage circuit 12, and a data writing circuit 13.

[0102] The control terminal of the driving circuit 10 is electrically connected to the first node N1. The driving circuit 10 is used to generate a driving current to drive the light-emitting element E1 under the control of the potential of the first node N1.

[0103] The on / off control circuit 11 is electrically connected to the on / off control terminal ST, the first node N1 and the second node N2 respectively, and is used to control the connection or disconnection between the first node N1 and the second node N2 under the control of the on / off control signal provided by the on / off control terminal ST.

[0104] The first energy storage circuit 12 is electrically connected to the second node N2 and the write node NX respectively; the first energy storage circuit 12 is used to store electrical energy;

[0105] The data writing circuit 13 is electrically connected to the scanning end GT, the data line DL and the writing node NX, respectively, and is used to provide the data voltage provided by the data line DL to the writing node NX under the control of the scanning signal provided by the scanning end GT.

[0106] This invention Figure 2 In at least one embodiment of the pixel circuit shown, when in operation, the display cycle of the pixel circuit includes a light-emitting phase;

[0107] During the light emission stage, the on / off control circuit 11 controls the first node N1 and the second node N2 to disconnect under the control of the on / off control signal, so that the potential of the first node N1 is not affected by the floating write node NX, and the potential of the first node N1 is stable.

[0108] like Figure 3 As shown, in Figure 2 Based on at least one embodiment of the pixel circuit shown, the pixel circuit of at least one embodiment of the present invention further includes a second energy storage circuit 21 and a bias control circuit 22;

[0109] The first end of the second energy storage circuit 21 is electrically connected to the first node N1, and the second end of the second energy storage circuit 21 is electrically connected to the third node N3. The second energy storage circuit 21 is used to store electrical energy.

[0110] The bias control circuit 22 is electrically connected to the bias control terminal SP, the bias voltage terminal VB, and the third node N3, respectively, and is used to write the bias voltage Vbias provided by the bias voltage terminal VB into the third node N3 under the control of the bias control signal provided by the bias control terminal SP.

[0111] This invention Figure 3 In at least one embodiment of the pixel circuit shown, the display cycle includes a data writing phase and a bias phase that are set sequentially before the light emission phase.

[0112] During the data writing phase, the data writing circuit 13, under the control of the scanning signal provided by the scanning end GT, provides the data voltage Vdata provided by the data line DL to the writing node NX;

[0113] During the biasing phase, the bias control circuit 22, under the control of the bias control signal provided by the bias control terminal SP, writes the bias voltage Vbias provided by the bias voltage terminal VB into the third node N3, so that the driving transistor included in the driving circuit 10 is in a biased state, which can improve the hysteresis phenomenon of the driving transistor.

[0114] In at least one embodiment of the present invention, when the driving transistor is a p-type transistor, during the biasing phase, by providing Vbias to N3, the potential of N1 is changed accordingly, so that the gate-source voltage of the driving transistor is less than or greater than that of the driving transistor. During the data writing phase, the gate-source voltage of the driving transistor is adjusted to improve the hysteresis phenomenon of the driving transistor.

[0115] In a preferred embodiment, when the driving transistor is a p-type transistor, during the biasing phase, by providing Vbias to N3, the potential of N1 is changed accordingly, such that the gate-source voltage of the driving transistor is less than the gate-source voltage of the driving transistor during the data writing phase.

[0116] In at least one embodiment of the present invention, when the driving transistor is an n-type transistor, during the biasing phase, by providing Vbias to N3, the potential of N1 is changed accordingly, such that the gate-source voltage of the driving transistor is less than or greater than that of the driving transistor. During the data writing phase, the gate-source voltage of the driving transistor is adjusted to improve the hysteresis phenomenon of the driving transistor.

[0117] like Figure 4 As shown, in Figure 3 Based on at least one embodiment of the pixel circuit shown, the pixel circuit of at least one embodiment of the present invention further includes a first control circuit 31;

[0118] The first control circuit 31 is electrically connected to the first control terminal SC, the first voltage terminal V1 and the third node N3 respectively, and is used to control the connection or disconnection between the first voltage terminal V1 and the third node N3 under the control of the first control signal provided by the first control terminal SC.

[0119] Optionally, the first voltage terminal can be a power supply voltage terminal, but it is not limited to this.

[0120] This invention Figure 4 In at least one embodiment of the pixel circuit shown, during the biasing phase, the first control circuit 31, under the control of the first control signal, controls the first voltage terminal V1 to disconnect from the third node N3.

[0121] During the time period included in the display cycle, excluding the bias phase, the first control circuit 31 can control the connection between the first voltage terminal V1 and the third node N3 under the control of the first control signal.

[0122] The pixel circuit described in at least one embodiment of the present invention further includes a second energy storage circuit;

[0123] The second energy storage circuit is electrically connected to the first node and is used to maintain the potential of the first node.

[0124] like Figure 5 As shown, in Figure 2 Based on at least one embodiment of the pixel circuit shown, the pixel circuit of at least one embodiment of the present invention further includes a second energy storage circuit 21;

[0125] The second energy storage circuit 21 is electrically connected to the first node N1 and is used to maintain the potential of the first node N1.

[0126] The pixel circuit described in at least one embodiment of the present invention further includes a first initialization circuit, a second initialization circuit, and a compensation control circuit;

[0127] The first terminal of the driving circuit is electrically connected to the first voltage terminal, and the second terminal of the driving circuit is electrically connected to the fourth node;

[0128] The first initialization circuit is electrically connected to the first reset control terminal and the first initial voltage terminal respectively. The first initialization circuit is also electrically connected to the first node or the fourth node. The first initialization circuit is used to write the first initial voltage provided by the first initial voltage terminal into the first node or the fourth node under the control of the first reset control signal provided by the first reset control terminal.

[0129] The second initialization circuit is electrically connected to the second reset control terminal, the reference voltage terminal and the write node, respectively, and is used to write the reference voltage provided by the reference voltage terminal into the write node under the control of the second reset control signal provided by the second reset control terminal;

[0130] The compensation control circuit is electrically connected to the compensation control terminal, the first node, and the fourth node, respectively, and is used to control the connection or disconnection between the first node and the fourth node under the control of the compensation control signal provided by the compensation control terminal.

[0131] In a specific implementation, the pixel circuit may further include a first initialization circuit, a second initialization circuit, and a compensation control circuit; the first initialization circuit, under the control of a first reset control signal, writes a first initial voltage into the first node or the fourth node; the second initialization circuit, under the control of a second reset control signal, writes a reference voltage into the writing node; the compensation control circuit, under the control of the compensation control signal, controls the connection or disconnection between the first node and the fourth node.

[0132] The pixel circuit described in at least one embodiment of the present invention further includes a light-emitting control circuit and a third initialization circuit; the first terminal of the driving circuit is electrically connected to the first voltage terminal, and the second terminal of the driving circuit is electrically connected to the fourth node;

[0133] The light-emitting control circuit is electrically connected to the light-emitting control terminal, the fourth node, and the first electrode of the light-emitting element, respectively, and is used to control the connection or disconnection between the fourth node and the first electrode of the light-emitting element under the control of the light-emitting control signal provided by the light-emitting control terminal;

[0134] The third initialization circuit is electrically connected to the third reset control terminal, the second initial voltage terminal, and the first electrode of the light-emitting element, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element under the control of the third reset control signal provided by the third reset control terminal.

[0135] The second electrode of the light-emitting element is electrically connected to the second voltage terminal.

[0136] Optionally, the second voltage terminal can be a low voltage terminal.

[0137] In a specific implementation, the pixel circuit may further include a light-emitting control circuit and a third initialization circuit; the light-emitting control circuit, under the control of the light-emitting control signal, controls the connection or disconnection between the fourth node and the first electrode of the light-emitting element to perform light-emitting control; the third initialization circuit, under the control of the third reset control signal, writes the second initial voltage into the first electrode of the light-emitting element to clear the residual charge on the first electrode of the light-emitting element.

[0138] like Figure 6 As shown, in Figure 4 Based on at least one embodiment of the pixel circuit shown, the pixel circuit of at least one embodiment of the present invention further includes a first initialization circuit 51, a second initialization circuit 52, and a compensation control circuit 53;

[0139] The first terminal of the driving circuit 10 is electrically connected to the first voltage terminal V1, and the second terminal of the driving circuit 10 is electrically connected to the fourth node N4.

[0140] The first initialization circuit 51 is electrically connected to the first reset control terminal RST1 and the first initial voltage terminal I1 respectively. The first initialization circuit 51 is also electrically connected to the fourth node N4. The first initialization circuit 51 is used to write the first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the fourth node N4 under the control of the first reset control signal provided by the first reset control terminal RST1.

[0141] The second initialization circuit 52 is electrically connected to the second reset control terminal RST2, the reference voltage terminal REF, and the write node NX, respectively, and is used to write the reference voltage Vref provided by the reference voltage terminal REF to the write node NX under the control of the second reset control signal provided by the second reset control terminal RST2.

[0142] The compensation control circuit 53 is electrically connected to the compensation control terminal SK, the first node N1 and the fourth node N4 respectively, and is used to control the connection or disconnection between the first node N1 and the fourth node N4 under the control of the compensation control signal provided by the compensation control terminal SK.

[0143] The pixel circuit described in at least one embodiment of the present invention further includes a light-emitting control circuit 54 and a third initialization circuit 55; the first terminal V1 of the driving circuit 10 is electrically connected to the first voltage terminal, and the second terminal of the driving circuit 10 is electrically connected to the fourth node N4.

[0144] The light-emitting control circuit 54 is electrically connected to the light-emitting control terminal EM, the fourth node N4, and the first pole of the light-emitting element E1, respectively, and is used to control the connection or disconnection between the fourth node N4 and the first pole of the light-emitting element E1 under the control of the light-emitting control signal provided by the light-emitting control terminal EM.

[0145] The third initialization circuit 55 is electrically connected to the third reset control terminal RST3, the second initial voltage terminal I2 and the first pole of the light-emitting element E1, respectively, and is used to write the second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the first pole of the light-emitting element E1 under the control of the third reset control signal provided by the third reset control terminal RST3.

[0146] The second electrode of the light-emitting element E1 is electrically connected to the second voltage terminal V2.

[0147] like Figure 7 As shown, in Figure 5 Based on at least one embodiment of the pixel circuit shown, the pixel circuit of at least one embodiment of the present invention further includes a first initialization circuit 51, a second initialization circuit 52, and a compensation control circuit 53;

[0148] The first terminal of the driving circuit 10 is electrically connected to the first voltage terminal V1, and the second terminal of the driving circuit 10 is electrically connected to the fourth node N4.

[0149] The first initialization circuit 51 is electrically connected to the first reset control terminal RST1 and the first initial voltage terminal I1 respectively. The first initialization circuit 51 is also electrically connected to the fourth node N4. The first initialization circuit 51 is used to write the first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the fourth node N4 under the control of the first reset control signal provided by the first reset control terminal RST1.

[0150] The second initialization circuit 52 is electrically connected to the second reset control terminal RST2, the reference voltage terminal REF, and the write node NX, respectively, and is used to write the reference voltage Vref provided by the reference voltage terminal REF to the write node NX under the control of the second reset control signal provided by the second reset control terminal RST2.

[0151] The compensation control circuit 53 is electrically connected to the compensation control terminal SK, the first node N1 and the fourth node N4 respectively, and is used to control the connection or disconnection between the first node N1 and the fourth node N4 under the control of the compensation control signal provided by the compensation control terminal SK.

[0152] The pixel circuit described in at least one embodiment of the present invention further includes a light-emitting control circuit 54 and a third initialization circuit 55; the first terminal V1 of the driving circuit 10 is electrically connected to the first voltage terminal, and the second terminal of the driving circuit 10 is electrically connected to the fourth node N4.

[0153] The light-emitting control circuit 54 is electrically connected to the light-emitting control terminal EM, the fourth node N4, and the first pole of the light-emitting element E1, respectively, and is used to control the connection or disconnection between the fourth node N4 and the first pole of the light-emitting element E1 under the control of the light-emitting control signal provided by the light-emitting control terminal EM.

[0154] The third initialization circuit 55 is electrically connected to the third reset control terminal RST3, the second initial voltage terminal I2 and the first pole of the light-emitting element E1, respectively, and is used to write the second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the first pole of the light-emitting element E1 under the control of the third reset control signal provided by the third reset control terminal RST3.

[0155] The second electrode of the light-emitting element E1 is electrically connected to the second voltage terminal V2.

[0156] Optionally, the on / off control circuit includes a first transistor; the first energy storage circuit includes a first capacitor; and the data writing circuit includes a second transistor.

[0157] The gate of the first transistor is electrically connected to the on / off control terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the second node.

[0158] The first terminal of the first capacitor is electrically connected to the second node, and the second terminal of the first capacitor is electrically connected to the write node;

[0159] The gate of the second transistor is electrically connected to the scan terminal, the first terminal of the second transistor is electrically connected to the data line, and the second terminal of the second transistor is electrically connected to the write node.

[0160] Optionally, the second energy storage circuit includes a second capacitor, and the bias control circuit includes a third transistor;

[0161] The first terminal of the second capacitor is electrically connected to the first node, and the second terminal of the second capacitor is electrically connected to the third node;

[0162] The gate of the third transistor is electrically connected to the bias control terminal, the first terminal of the third transistor is electrically connected to the bias voltage terminal, and the second terminal of the third transistor is electrically connected to the third node.

[0163] Optionally, the first control circuit includes a fourth transistor;

[0164] The gate of the fourth transistor is electrically connected to the first control terminal, the first terminal of the fourth transistor is electrically connected to the first voltage terminal, and the second terminal of the fourth transistor is electrically connected to the third node.

[0165] like Figure 8 As shown, in Figure 7 Based on at least one embodiment of the pixel circuit shown, the on / off control circuit includes a first transistor T1; the first energy storage circuit includes a first capacitor C1; the data writing circuit includes a second transistor T2; and the driving circuit includes a driving transistor T0.

[0166] The gate of T0 is electrically connected to the first node N1, the source of T1 is electrically connected to the power supply voltage terminal VDD, and the drain of T1 is electrically connected to the fourth node N4.

[0167] The gate of the first transistor T1 is electrically connected to the light-emitting control terminal EM, the drain of the first transistor T1 is electrically connected to the first node N1, and the source of the first transistor is electrically connected to the second node N2.

[0168] The first terminal of the first capacitor C1 is electrically connected to the second node N2, and the second terminal of the first capacitor C1 is electrically connected to the write node NX;

[0169] The gate of the second transistor T2 is electrically connected to the scan terminal GT, the source of the second transistor T2 is electrically connected to the data line DL, and the drain of the second transistor T2 is electrically connected to the write node NX.

[0170] The second energy storage circuit includes a second capacitor C2;

[0171] The first terminal of the second capacitor C2 is electrically connected to the first node N1, and the second terminal of the second capacitor C2 is electrically connected to the power supply voltage terminal VDD.

[0172] The first initialization circuit includes a fifth transistor T5, the second initialization circuit includes a sixth transistor T6, the light-emitting control circuit includes a seventh transistor T7, the third initialization circuit includes an eighth transistor T8, the compensation control circuit includes a ninth transistor T9, and the light-emitting element is an organic light-emitting diode O1.

[0173] The gate of T5 is electrically connected to the first reset control terminal RST1, the source of T5 is electrically connected to the first initial voltage terminal I1, and the drain of T5 is electrically connected to the fourth node N4.

[0174] The gate of T6 is electrically connected to the second reset control terminal RST2, the source of T6 is electrically connected to the reference voltage terminal REF, and the drain of T6 is electrically connected to the write node NX.

[0175] The gate of T7 is electrically connected to the light-emitting control terminal EM, the source of T7 is electrically connected to the fourth node N4, and the drain of T7 is electrically connected to the anode of O1.

[0176] The gate of T8 is electrically connected to the first reset control terminal RST1, the source of T8 is electrically connected to the second initial voltage terminal I2, the drain of T8 is electrically connected to the anode of O1, and the cathode of O1 is electrically connected to the low voltage terminal VSS.

[0177] The gate of T9 is electrically connected to the second reset control terminal RST2, the source of T9 is electrically connected to the first node N1, and the drain of T9 is electrically connected to the fourth node N4.

[0178] exist Figure 8 In at least one of the embodiments shown, the first reset control terminal and the third reset control terminal can be the same reset control terminal, the on / off control terminal and the light emission control terminal are the same control terminal, and the compensation control terminal and the second reset control terminal are the same control terminal, so as to reduce the number of control terminals used.

[0179] exist Figure 8In at least one embodiment shown, T1 is an n-type transistor, and T0, T2, T5, T6, T7, T8 and T9 are all p-type transistors.

[0180] like Figure 9 As shown, the present invention Figure 8 When at least one embodiment of the pixel circuit shown is in operation, the display cycle of the pixel circuit includes a reset phase S1, a compensation phase S2, a data writing phase S3, and a light emission phase S4 arranged sequentially.

[0181] During the reset phase S1, EM provides a high voltage signal, RST1 provides a low voltage signal, RST2 provides a low voltage signal, GT provides a high voltage signal, T7 is turned off, T2 is turned off, T1 is turned on to connect N1 and N2, T5 and T9 are turned on, I1 provides a first initial voltage Vinit1 to N1 and N4, T6 is turned on, REF provides a reference voltage Vref to NX, T8 is turned on, and I2 provides a second initial voltage Vinit2 to clear the residual charge on the anode of O1.

[0182] During the compensation phase S2, EM provides a high voltage signal, RST1 provides a high voltage signal, RST2 provides a low voltage signal, GT provides a high voltage signal, T1 is turned on, T6 is turned on, and T9 is turned on.

[0183] At the start of the compensation phase S2, T0 is turned on, and Vref is charged through C1, T1, T9 and the turned-on T0, changing the potential of N1 until the potential of N1 becomes Vdd+Vth, at which point T0 is turned off, completing the threshold voltage compensation; where Vdd is the voltage value of the power supply voltage provided by VDD, and Vth is the threshold voltage of T0.

[0184] During the data writing phase S3, EM provides a high voltage signal, RST1 provides a high voltage signal, RST2 provides a high voltage signal, GT provides a low voltage signal, T1 is turned on, T2 is turned on, DL provides the data voltage Vdata to NX, and through the coupling effect of C1, the potential of N1 changes from Vdd+Vth to Vdd+Vth-Vref+Vdata.

[0185] During the light-emitting phase S4, EM provides a low-voltage signal, while RST1, RST2, and GT all provide high-voltage signals. T1 is turned off to disconnect N1 from N2. T2 and T6 are also turned off, and NX is in a floating state to prevent the potential of N1 from being affected by the potential of NX, thus maintaining the stability of N1's potential. T7 is turned on, and T0 drives O1 to emit light. At this time, the driving current generated by T0 to drive O1 is K×(Vdd+Vth-Vref+Vdata-Vdd-Vth). 2 =K×(Vdata-Vref) 2Where K is the current coefficient of T0, it can be seen that Id is independent of Vdd and Vth, which can compensate for the uneven display caused by the uneven driving current caused by Vdd and Vth.

[0186] In related technologies, uneven display quality is caused by inconsistent threshold voltages of driving transistors due to process variations. Furthermore, voltage drops in the power supply voltage received by pixel circuits in the far-end display area of ​​the display panel also contribute to uneven display quality. At least one embodiment of the present invention can compensate for the threshold voltage and power supply voltage of the driving transistors, thereby improving the uneven display phenomenon.

[0187] Furthermore, when the pixel circuit described in at least one embodiment of the present invention is in operation, it can separate the data voltage writing and threshold voltage compensation, so that the threshold voltage compensation time is not limited by the row period, and the threshold voltage compensation time can be increased so as to fully compensate the threshold voltage and power supply voltage of the driving transistor.

[0188] This invention Figure 10 At least one embodiment of the pixel circuit shown is related to the present invention. Figure 8 The difference in at least one embodiment of the pixel circuit shown is that:

[0189] T1 is a p-type transistor, and its gate is electrically connected to the on / off control terminal ST.

[0190] exist Figure 10 In at least one of the embodiments shown, the drain of T5 can also be electrically connected to N1.

[0191] like Figure 11 As shown, the present invention Figure 10 When at least one embodiment of the pixel circuit shown is in operation, the display cycle of the pixel circuit includes a reset phase S1, a compensation phase S2, a data writing phase S3, and a light emission phase S4 arranged sequentially.

[0192] During the reset phase S1, EM provides a high voltage signal, RST1 provides a low voltage signal, RST2 provides a low voltage signal, GT provides a high voltage signal, ST provides a low voltage signal, T7 is turned off, T2 is turned off, T1 is turned on to connect N1 and N2, T5 and T9 are turned on, I1 provides a first initial voltage Vinit1 to N1 and N4, T6 is turned on, REF provides a reference voltage Vref to NX, T8 is turned on, and I2 provides a second initial voltage Vinit2 to clear the residual charge on the anode of O1.

[0193] During the compensation phase S2, EM provides a high voltage signal, RST1 provides a high voltage signal, RST2 provides a low voltage signal, GT provides a high voltage signal, ST provides a low voltage signal, T1 is turned on, T6 is turned on, and T9 is turned on.

[0194] At the start of the compensation phase S2, T0 is turned on, and Vref is charged through C1, T1, T9 and the turned-on T0, changing the potential of N1 until the potential of N1 becomes Vdd+Vth, at which point T0 is turned off, completing the threshold voltage compensation; where Vdd is the voltage value of the power supply voltage provided by VDD, and Vth is the threshold voltage of T0.

[0195] During the data writing phase S3, EM provides a high voltage signal, RST1 provides a high voltage signal, RST2 provides a high voltage signal, GT provides a low voltage signal, ST provides a low voltage signal, T1 is turned on, T2 is turned on, DL provides the data voltage Vdata to NX, and through the coupling effect of C1, the potential of N1 changes from Vdd+Vth to Vdd+Vth-Vref+Vdata.

[0196] During the light-emitting phase S4, EM provides a low-voltage signal, while RST1, RST2, and GT all provide high-voltage signals. ST provides a high-voltage signal. T1 is turned off to disconnect N1 from N2. T2 and T6 are also turned off, and NX is in a floating state to prevent the potential of N1 from being affected by the potential of NX, thus maintaining the stability of N1's potential. T7 is turned on, and T0 drives O1 to emit light. At this time, the driving current generated by T0 to drive O1 is K×(Vdd+Vth-Vref+Vdata-Vdd-Vth). 2 =K×(Vdata-Vref) 2 Where K is the current coefficient of T0, it can be seen that Id is independent of Vdd and Vth, which can compensate for the uneven display caused by the uneven driving current caused by Vdd and Vth.

[0197] This invention Figure 12 At least one embodiment of the pixel circuit shown is related to the present invention. Figure 8 The pixel circuit shown in at least one embodiment differs as follows: it further includes a bias control circuit and a first control circuit; the bias control circuit includes a third transistor T3; the first control circuit includes a fourth transistor T4;

[0198] The second terminal of the second capacitor C2 is electrically connected to the third node N3;

[0199] The gate of the third transistor T3 is electrically connected to the bias control terminal SP, the source of the third transistor T3 is electrically connected to the bias voltage terminal VB, and the drain of the third transistor T3 is electrically connected to the third node N3.

[0200] The gate of the fourth transistor T4 is electrically connected to the first control terminal SC, the source of the fourth transistor T4 is electrically connected to the power supply voltage terminal VDD, and the drain of the fourth transistor T4 is electrically connected to the third node N3.

[0201] T3 and T4 are p-type transistors.

[0202] like Figure 13 As shown, the present invention Figure 12 When at least one embodiment of the pixel circuit shown is in operation, the display cycle may include a reset phase S1, a compensation phase S2, a writing phase S3, a bias phase S0, and a light emission phase S4 arranged sequentially.

[0203] During the reset phase S1, EM provides a high voltage signal, RST1 provides a low voltage signal, RST2 provides a low voltage signal, GT provides a high voltage signal, SP provides a high voltage signal, SC provides a low voltage signal, T3 is turned off, T4 is turned on, VDD is connected to N3, T7 is turned off, T2 is turned off, T1 is turned on to connect N1 and N2, T5 and T9 are turned on, I1 provides the first initial voltage Vinit1 to N1 and N4, T6 is turned on, REF provides the reference voltage Vref to NX, T8 is turned on, and I2 provides the second initial voltage Vinit2 to clear the residual charge on the anode of O1.

[0204] During the compensation phase S2, EM provides a high voltage signal, RST1 provides a high voltage signal, RST2 provides a low voltage signal, GT provides a high voltage signal, SP provides a high voltage signal, SC provides a low voltage signal, T3 is off, T4 is on, VDD and N3 are connected, T1 is on, T6 is on, and T9 is on.

[0205] At the start of the compensation phase S2, T0 is turned on, and Vref is charged through C1, T1, T9 and the turned-on T0, changing the potential of N1 until the potential of N1 becomes Vdd+Vth, at which point T0 is turned off, completing the threshold voltage compensation; where Vdd is the voltage value of the power supply voltage provided by VDD, and Vth is the threshold voltage of T0.

[0206] During the data writing phase S3, EM provides a high voltage signal, RST1 provides a high voltage signal, RST2 provides a high voltage signal, GT provides a low voltage signal, ST provides a low voltage signal, SP provides a high voltage signal, SC provides a low voltage signal, T3 is off, T4 is on, VDD and N3 are connected, T1 is on, T2 is on, DL provides the data voltage Vdata to NX, and through the coupling effect of C1, the potential of N1 changes from Vdd+Vth to Vdd+Vth-Vref+Vdata;

[0207] During the biasing phase S0, EM provides a high voltage signal, RST1 provides a high voltage signal, RST2 provides a high voltage signal, GT provides a high voltage signal, SP provides a low voltage signal, and SC provides a high voltage signal. T4 is turned off and T4 is turned on. VB provides a bias voltage Vbias to N3, and the potential of N3 changes from Vdd to Vbias. Due to the coupling effect of C2, the potential of N1 changes from Vdd+Vth-Vref+Vdata to Vdd+Vth-Vref+Vdata+Vbias-Vdd, that is, it becomes Vth-Vref+Vdata+Vbias, in order to improve the hysteresis phenomenon of T0. The bias effect on T0 can be adjusted by adjusting the voltage value of Vbias and the number of effective pulses of the bias control signal provided by SP.

[0208] During the light-emitting phase S4, EM provides a low-voltage signal, RST1, RST2, and GT all provide high-voltage signals, ST provides a high-voltage signal, SP provides a high-voltage signal, and SC provides a low-voltage signal. T3 is off, T4 is on, and N3 is connected to VDD. The potential of N3 changes from Vbias to Vdd. Due to the coupling effect of C2, the potential of N1 changes back to Vdd + Vth - Vref + Vdata. T1 is off to disconnect N1 from N2. T2 and T6 are off, and NX is in a floating state to prevent the potential of N1 from being affected by the potential of NX, thus maintaining the stability of the potential of N1. T7 is on, and T0 drives O1 to emit light. At this time, the current value of the driving current generated by T0 to drive O1 is K × (Vdd + Vth - Vref + Vdata - Vdd - Vth). 2 =K×(Vdata-Vref) 2 Where K is the current coefficient of T0, it can be seen that Id is independent of Vdd and Vth, which can compensate for the uneven display caused by the uneven driving current caused by Vdd and Vth.

[0209] This invention Figure 14 At least one embodiment of the pixel circuit shown is related to the present invention. Figure 8 The differences between at least one embodiment of the pixel circuit shown are as follows:

[0210] The drain of T5 is electrically connected to the first node N1.

[0211] This invention Figure 14 In at least one embodiment of the pixel circuit shown, during operation, in the reset phase, RST1 provides a low voltage signal, T5 is turned on, and I1 can directly provide a first initial voltage Vinit1 to N1 so that T0 can be turned on at the start of the compensation phase.

[0212] This invention Figure 15 At least one embodiment of the pixel circuit shown is related to the present invention. Figure 12 The differences between at least one embodiment of the pixel circuit shown are as follows:

[0213] The drain of T5 is electrically connected to the first node N1.

[0214] This invention Figure 15 In at least one embodiment of the pixel circuit shown, during operation, in the reset phase, RST1 provides a low voltage signal, T5 is turned on, and I1 can directly provide a first initial voltage Vinit1 to N1 so that T0 can be turned on at the start of the compensation phase.

[0215] The driving method described in this embodiment of the invention is applied to the pixel circuit described above, wherein the display cycle of the pixel circuit includes a light-emitting phase; the driving method includes:

[0216] During the light-emitting stage, the on / off control circuit, under the control of the on / off control signal, controls the disconnection between the first node and the second node, so that the potential of the first node is not affected by the floating write node, thus stabilizing the potential of the first node.

[0217] In at least one embodiment of the present invention, a biasing phase precedes the light emission phase; the driving method further includes:

[0218] During the biasing phase, the biasing control circuit, under the control of the biasing control signal, writes the bias voltage into the third node to improve the hysteresis phenomenon of the driving transistor included in the driving circuit.

[0219] In at least one embodiment of the present invention, the pixel circuit further includes a first control circuit; the driving method further includes:

[0220] During the biasing phase, the first control circuit, under the control of the first control signal, controls the first voltage terminal to disconnect from the third node.

[0221] In at least one embodiment of the present invention, the display cycle includes a data writing phase set during the bias phase; the driving method further includes:

[0222] During the data writing stage, the data writing circuit, under the control of the scanning signal provided by the scanning end, provides the data voltage provided by the data line to the writing node. The on / off control circuit, under the control of the on / off control signal, controls the connection between the first node and the third node to perform data voltage writing.

[0223] In at least one embodiment of the present invention, the display cycle further includes a compensation phase; the compensation phase is independent of the data writing phase; the pixel circuit further includes a second initialization circuit and a compensation control circuit; the driving method further includes:

[0224] During the compensation phase, the on / off control circuit controls the connection between the first node and the third node under the control of the on / off control signal. The second initialization circuit provides the reference voltage provided by the reference voltage terminal to the write node under the control of the second reset control signal. The compensation control circuit controls the connection between the first node and the fourth node under the control of the compensation control signal provided by the compensation control terminal to perform threshold voltage compensation.

[0225] The display device described in this embodiment of the invention includes the pixel circuit described above.

[0226] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A pixel circuit, characterized in that, It includes a light-emitting element, a driving circuit, an on / off control circuit, a first energy storage circuit, and a data writing circuit; The control terminal of the driving circuit is electrically connected to the first node, and the driving circuit is used to generate a driving current to drive the light-emitting element under the control of the potential of the first node. The on / off control circuit is electrically connected to the on / off control terminal, the first node and the second node respectively, and is used to control the connection or disconnection between the first node and the second node under the control of the on / off control signal provided by the on / off control terminal. The first energy storage circuit is electrically connected to the second node and the write node, respectively; The data writing circuit is electrically connected to the scanning end, the data line and the writing node respectively, and is used to provide the data voltage provided by the data line to the writing node under the control of the scanning signal provided by the scanning end; The pixel circuit also includes a second energy storage circuit and a bias control circuit; The first end of the second energy storage circuit is electrically connected to the first node, and the second end of the second energy storage circuit is electrically connected to the third node; The bias control circuit is electrically connected to the bias control terminal, the bias voltage terminal, and the third node, respectively, and is used to write the bias voltage provided by the bias voltage terminal into the third node under the control of the bias control signal provided by the bias control terminal.

2. The pixel circuit as described in claim 1, characterized in that, It also includes a first control circuit; The first control circuit is electrically connected to the first control terminal, the first voltage terminal, and the third node, respectively, and is used to control the connection or disconnection between the first voltage terminal and the third node under the control of the first control signal provided by the first control terminal.

3. The pixel circuit as described in claim 1, characterized in that, It also includes a second energy storage circuit; The second energy storage circuit is electrically connected to the first node and is used to maintain the potential of the first node.

4. The pixel circuit according to any one of claims 1 to 3, characterized in that, It also includes a first initialization circuit, a second initialization circuit, and a compensation control circuit; The first terminal of the driving circuit is electrically connected to the first voltage terminal, and the second terminal of the driving circuit is electrically connected to the fourth node; The first initialization circuit is electrically connected to the first reset control terminal and the first initial voltage terminal respectively. The first initialization circuit is also electrically connected to the first node or the fourth node. The first initialization circuit is used to write the first initial voltage provided by the first initial voltage terminal into the first node or the fourth node under the control of the first reset control signal provided by the first reset control terminal. The second initialization circuit is electrically connected to the second reset control terminal, the reference voltage terminal and the write node, respectively, and is used to write the reference voltage provided by the reference voltage terminal into the write node under the control of the second reset control signal provided by the second reset control terminal; The compensation control circuit is electrically connected to the compensation control terminal, the first node, and the fourth node, respectively, and is used to control the connection or disconnection between the first node and the fourth node under the control of the compensation control signal provided by the compensation control terminal.

5. The pixel circuit according to any one of claims 1 to 3, characterized in that, It also includes a light-emitting control circuit and a third initialization circuit; the first terminal of the driving circuit is electrically connected to the first voltage terminal, and the second terminal of the driving circuit is electrically connected to the fourth node; The light-emitting control circuit is electrically connected to the light-emitting control terminal, the fourth node, and the first electrode of the light-emitting element, respectively, and is used to control the connection or disconnection between the fourth node and the first electrode of the light-emitting element under the control of the light-emitting control signal provided by the light-emitting control terminal; The third initialization circuit is electrically connected to the third reset control terminal, the second initial voltage terminal, and the first electrode of the light-emitting element, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element under the control of the third reset control signal provided by the third reset control terminal. The second electrode of the light-emitting element is electrically connected to the second voltage terminal.

6. The pixel circuit according to any one of claims 1 to 3, characterized in that, The on / off control circuit includes a first transistor; the first energy storage circuit includes a first capacitor; and the data writing circuit includes a second transistor. The gate of the first transistor is electrically connected to the on / off control terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the second node. The first terminal of the first capacitor is electrically connected to the second node, and the second terminal of the first capacitor is electrically connected to the write node; The gate of the second transistor is electrically connected to the scan terminal, the first terminal of the second transistor is electrically connected to the data line, and the second terminal of the second transistor is electrically connected to the write node.

7. The pixel circuit as described in claim 1, characterized in that, The second energy storage circuit includes a second capacitor, and the bias control circuit includes a third transistor; The first terminal of the second capacitor is electrically connected to the first node, and the second terminal of the second capacitor is electrically connected to the third node; The gate of the third transistor is electrically connected to the bias control terminal, the first terminal of the third transistor is electrically connected to the bias voltage terminal, and the second terminal of the third transistor is electrically connected to the third node.

8. The pixel circuit as described in claim 2, characterized in that, The first control circuit includes a fourth transistor; The gate of the fourth transistor is electrically connected to the first control terminal, the first terminal of the fourth transistor is electrically connected to the first voltage terminal, and the second terminal of the fourth transistor is electrically connected to the third node.

9. A driving method applied to a pixel circuit as described in any one of claims 1 to 8, characterized in that, The display cycle of the pixel circuit includes a light-emitting phase; the driving method includes: During the light-emitting stage, the on / off control circuit controls the disconnection between the first node and the second node under the control of the on / off control signal; The pixel circuit further includes a second energy storage circuit and a bias control circuit; the display cycle further includes a bias phase set before the light emission phase; the driving method further includes: During the biasing phase, the biasing control circuit writes the bias voltage to the third node under the control of the biasing control signal.

10. The driving method as described in claim 9, characterized in that, The pixel circuit further includes a first control circuit; the driving method further includes: During the biasing phase, the first control circuit, under the control of the first control signal, controls the first voltage terminal to disconnect from the third node.

11. The driving method as described in claim 9 or 10, characterized in that, The display cycle includes a data writing phase set during the bias phase; the driving method further includes: During the data writing phase, the data writing circuit, under the control of the scanning signal provided by the scanning end, provides the data voltage provided by the data line to the writing node, and the on / off control circuit, under the control of the on / off control signal, controls the connection between the first node and the third node.

12. The driving method as described in claim 11, characterized in that, The display cycle further includes a compensation phase; the compensation phase is independent of the data writing phase; the pixel circuit further includes a second initialization circuit and a compensation control circuit; the driving method further includes: During the compensation phase, the on / off control circuit controls the connection between the first node and the third node under the control of the on / off control signal. The second initialization circuit provides the reference voltage provided by the reference voltage terminal to the write node under the control of the second reset control signal. The compensation control circuit controls the connection between the first node and the fourth node under the control of the compensation control signal provided by the compensation control terminal.

13. A display device, characterized in that, Includes the pixel circuit as described in any one of claims 1 to 8.

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