Refreshing circuit and refreshing method

Abstract

The invention relates to a refresh circuit and a refresh method. The refresh circuit comprises a refresh control circuit used for receiving first refresh commands and counting the first refresh commands; and generating a second refresh control signal based on the count value of the first refresh command; the refresh pulse generation circuit is used for receiving first refresh commands and generating a first refresh pulse based on each first refresh command; receiving a second refresh control signal, and generating at least one second refresh pulse based on the first refresh command and the second refresh control signal; and the refresh operation circuit is used for executing a first refresh operation once according to each first refresh pulse and executing a second refresh operation once according to each second refresh pulse. According to the method, extra refreshing operation is added in a conventional refreshing process so as to execute redundant line / line hammer refreshing; on the basis of meeting the time requirement of the conventional refreshing operation, the redundant row / row hammer address is refreshed.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a refresh circuit and a refresh method. Background Art

[0002] Low Power Double Data Rate SDRAM (LPDDR) is a low-power memory communication standard developed by the Joint Electron Device Engineering Council (JEDEC) for portable electronic terminals. It can be simply divided into five generations of products: LPDDR, LPDDR2, LPDDR3, LPDDR4 (including LPDDR4X) and LPDDR5.

[0003] JEDEC requires that when refreshing a dynamic random access memory (DRAM) chip, 8K must be refreshed within 32ms. However, the LPDDR5 DRAM chip has 64K word lines (WL). Currently, 8WLs can only be refreshed within 32ms.

[0004] However, in addition to performing a regular refresh of the 64K WLs, it is also necessary to perform a redundant row refresh and / or a row hammer refresh. Summary of the invention

[0005] Based on this, it is necessary to provide a refresh circuit and refresh method for inserting redundant row refresh and / or row hammer refresh during a normal refresh process.

[0006] In one aspect, a refresh circuit is provided, the refresh circuit comprising:

[0007] A refresh control circuit, configured to receive a first refresh command, count the first refresh command, and generate a second refresh control signal based on the count value of the first refresh command;

[0008] a refresh pulse generating circuit, configured to receive the first refresh command and generate a first refresh pulse based on each of the first refresh commands; and receive the second refresh control signal and generate at least one second refresh pulse based on the first refresh command and the second refresh control signal;

[0009] The refresh operation circuit is used to perform a first refresh operation according to each of the first refresh pulses, and to perform a second refresh operation according to each of the second refresh pulses.

[0010] In one of the embodiments, the refresh pulse generating circuit is further configured to generate a reset signal based on the second refresh pulse;

[0011] The refresh control circuit is further configured to receive the reset signal and clear the count value of the first refresh command based on the reset signal.

[0012] In one embodiment, the refresh control circuit is used to generate a second refresh control signal at a valid level when the count value of the first refresh command reaches a first preset value; and to generate a second refresh control signal at an invalid level when the count value of the first refresh command does not reach the first preset value;

[0013] The refresh pulse generating circuit is configured to generate at least one of the second refresh pulses based on each of the first refresh pulses in response to a second refresh control signal at an active level.

[0014] In one of the embodiments, the refresh control circuit is further configured to stop counting the first refresh command while the second refresh control signal is at a valid level.

[0015] In one embodiment, the refresh control circuit includes:

[0016] a counter control circuit, configured to receive the first refresh command and the second refresh control signal, and output the first refresh command when the second refresh control signal is at an invalid level; and not output the first refresh command when the second refresh control signal is at a valid level;

[0017] a first counter, configured to receive the first refresh command output by the counter control circuit, count the first refresh command, generate and output a count value of the first refresh command; and receive the reset signal, and clear the count value of the first refresh command according to the reset signal;

[0018] A first decoder is used to receive the count value of the first refresh command and generate a second refresh control signal at a valid level when the count value of the first refresh command reaches a first preset value; and generate a second refresh control signal at an invalid level when the count value of the first refresh command does not reach the first preset value.

[0019] In one embodiment, the counter control circuit includes:

[0020] a first NOT gate, wherein an input end of the first NOT gate is used to receive the second refresh control signal;

[0021] A first NAND gate, wherein the first input end of the first NAND gate is used to receive the first refresh command, the second input end of the first NAND gate is connected to the output end of the first NAND gate, and the output end of the first NAND gate is used to output the first refresh command.

[0022] In one embodiment, the first counter comprises:

[0023] N first D flip-flops, a clock terminal of a first of the first D flip-flops being connected to an output terminal of the first NAND gate, for receiving the first refresh command, N≥2 and N is an integer;

[0024] N second NOT gates, corresponding one to one with the N first D flip-flops, the input end of each second NOT gate being connected to the positive phase output end of the corresponding first D flip-flop, and the output end of each second NOT gate being connected to the input end of the corresponding first D flip-flop;

[0025] N third NOT gates, corresponding one to one with the N first D flip-flops, the input end of each of the third NOT gates being connected to the output end of the corresponding second NOT gate, the clock end of the i-th first D flip-flop being connected to the output end of the third NOT gate corresponding to the i-1-th first D flip-flop, N≥i≥2 and i is an integer;

[0026] The output ends of the N third NOT gates serve as the output ends of the first counter, and are used to output the count value of the first refresh command.

[0027] In one embodiment, the first preset value includes an N-bit preset reference signal; and the first decoder includes:

[0028] N comparators, corresponding one to one with the N third NOT gates, a first input end of each comparator connected to an output end of a corresponding third NOT gate, and a second input end of each comparator used to access a corresponding one-bit preset reference signal;

[0029] A first AND gate, wherein an input end of the first AND gate is connected to the output ends of the N comparators in a one-to-one correspondence, and an output end of the first AND gate is used to output the second refresh control signal.

[0030] In one embodiment, the refresh pulse generating circuit comprises:

[0031] a pulse generating circuit, configured to receive the first refresh command and generate one first refresh pulse based on each first refresh command;

[0032] a second refresh command generating circuit, connected to the pulse generating circuit, configured to receive the second refresh control signal and the first refresh pulse, and to generate and output at least one second refresh command based on each of the first refresh pulses during a period in which the second refresh control signal is at an effective level;

[0033] The pulse generating circuit is further used for receiving the second refresh command and generating a second refresh pulse based on each second refresh command;

[0034] A reset signal generating circuit is connected to the second refresh command generating circuit and is used to generate a reset signal based on the second refresh command.

[0035] In one embodiment, the second refresh command generating circuit includes:

[0036] a second AND gate, wherein a first input terminal of the second AND gate is used to receive the second refresh control signal, and a second input terminal of the second AND gate is used to receive the first refresh pulse;

[0037] a first delay unit, wherein an input end of the first delay unit is connected to an output end of the second AND gate, and an output end of the first delay unit is used to output the delayed first refresh pulse;

[0038] A pulse generating unit, wherein an input end of the pulse generating unit is connected to an output end of the first delay unit, and is used for generating and outputting the second refresh command based on the delayed first refresh pulse.

[0039] In one embodiment, the pulse generating circuit is used to generate one second refresh pulse based on the first refresh command each time the second refresh control signal is at a valid level; or to generate multiple second refresh pulses based on the first refresh command each time the second refresh control signal is at a valid level.

[0040] In one embodiment, when the pulse generating circuit generates a second refresh pulse based on the first refresh command each time the second refresh control signal is at an effective level, the reset signal generating circuit includes:

[0041] a fourth NOT gate, wherein an input end of the fourth NOT gate is connected to an output end of the pulse generating unit and is used for receiving the second refresh command;

[0042] a second delay unit, wherein an input end of the second delay unit is connected to an output end of the fourth NOT gate;

[0043] a third AND gate, wherein a first input terminal of the third AND gate is connected to the output terminal of the second delay unit, and a second input terminal of the third AND gate is connected to the output terminal of the pulse generating unit;

[0044] A third delay unit, wherein the input end of the third delay unit is connected to the output end of the third AND gate, and the output end of the third delay unit is used to output the reset signal.

[0045] In one embodiment, when the pulse generating circuit generates a plurality of second refresh pulses based on the first refresh command each time the second refresh control signal is at an effective level, the reset signal generating circuit includes:

[0046] a second counter connected to the pulse generating unit, configured to receive the second refresh pulse, count the second refresh pulse, generate and output a count value of the second refresh pulse;

[0047] A second decoder is connected to the second counter, and is used to receive the count value of the second refresh pulse, and generate a reset signal at a valid level when the count value of the second refresh pulse reaches a second preset value; and generate a reset signal at an invalid level when the count value of the second refresh pulse does not reach the second preset value.

[0048] In one embodiment, the second counter comprises:

[0049] M second D flip-flops, a clock terminal of a first of the second D flip-flops being connected to the output terminal of the pulse generating unit, for receiving the second refresh command, M≥2 and M is an integer;

[0050] M fifth NOT gates, corresponding one to one with the M second D flip-flops, the input end of each of the fifth NOT gates being connected to the non-phase output end of the corresponding second D flip-flop, and the output end of each of the fifth NOT gates being connected to the input end of the corresponding second D flip-flop;

[0051] M sixth NOT gates, corresponding one to one with the M second D flip-flops, the input end of each of the sixth NOT gates being connected to the output end of the corresponding fifth NOT gate, the clock end of the jth second D flip-flop being connected to the output end of the sixth NOT gate corresponding to the j-1th second D flip-flop, M≥j≥2 and j is an integer;

[0052] The output ends of the M sixth NOT gates serve as the output ends of the second counter, and are used to output the count value of the second refresh pulse.

[0053] In one embodiment, the second refresh operation is a redundant row refresh and / or a row hammer refresh.

[0054] On the other hand, a refreshing method is provided, the refreshing method comprising:

[0055] receiving a first refresh command;

[0056] generating a first refresh pulse based on each of the first refresh commands, and performing a first refresh operation according to each of the first refresh pulses;

[0057] Counting the first refresh command and generating a second refresh control signal based on the count value of the first refresh command;

[0058] At least one second refresh pulse is generated based on the first refresh command and the second refresh control signal, and a second refresh operation is performed once according to each of the second refresh pulses.

[0059] The above refresh circuit and refresh method can perform a second refresh operation according to each second refresh pulse by counting the first refresh command and generating a second refresh control signal based on the count value of the first refresh command, and then generating at least one second refresh pulse based on the first refresh command and the second refresh control signal. A first refresh pulse is generated based on each first refresh command, and a first refresh operation can be performed according to each first refresh pulse. In this way, after performing multiple first refresh operations, a second refresh operation can be performed, thereby inserting redundant row refresh and / or row hammer refresh in the process of performing regular refresh to meet the refresh requirements of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0061] Figure 1 is a structural schematic diagram of a refresh circuit according to an embodiment;

[0062] Figure 2 for Figure 1 The circuit timing diagram corresponding to the refresh circuit shown;

[0063] Figure 3 is a structural schematic diagram of a refresh circuit according to an embodiment;

[0064] Figure 4 for Figure 3 The circuit timing diagram corresponding to the refresh circuit shown;

[0065] Figure 5A schematic structural diagram of a refresh control circuit according to an embodiment;

[0066] Figure 6 for Figure 5 The circuit timing diagram corresponding to the refresh control circuit shown;

[0067] Figure 7 A schematic diagram of the structure of a counter control circuit according to an embodiment;

[0068] Figure 8 is a schematic structural diagram of a first counter according to an embodiment;

[0069] Fig. 9 is a schematic structural diagram of a first decoder according to an embodiment;

[0070] Fig.10 is a schematic structural diagram of a first decoder according to an embodiment;

[0071] Fig.11 for Fig.10 The circuit timing diagram corresponding to the refresh pulse generating circuit shown;

[0072] Fig.12 is a structural schematic diagram of a second refresh command generating circuit according to an embodiment;

[0073] Fig.13 A schematic diagram of the structure of a reset signal generating circuit according to an embodiment;

[0074] Fig.14 for Fig.13 The circuit timing diagram corresponding to the reset signal generating circuit shown;

[0075] Fig.15 A schematic diagram of the structure of a reset signal generating circuit according to an embodiment;

[0076] Fig.16 for Fig.15 The circuit timing diagram corresponding to the reset signal generating circuit shown;

[0077] Fig.17 is a schematic structural diagram of a second counter in one embodiment;

[0078] Fig.18 FIG. 4 is a flow chart of a refreshing method according to an embodiment of the present invention.

[0079] Description of reference numerals:

[0080] 10. refresh control circuit, 20. refresh pulse generating circuit, 30. refresh operation circuit;

[0081] 11. a counter control circuit, 111. a first NOT gate, 112. a first NAND gate;

[0082] 12, a first counter, 121, a first D flip-flop, 122, a second NOT gate, 123, a third NOT gate;

[0083] 13. a first decoder, 131. a comparator, 132. a first AND gate;

[0084] 21. Pulse generating circuit;

[0085] 22. A second refresh command generating circuit, 221. A second AND gate, 222. A first delay unit, 223. A pulse generating unit;

[0086] 23. reset signal generating circuit, 231. fourth NOT gate, 232. second delay unit, 233. third AND gate, 234. third delay unit, 235. second counter, 2351. second D flip-flop, 2352. fifth NOT gate, 2353. sixth NOT gate, 236. second decoder. DETAILED DESCRIPTION

[0087] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0088] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0089] It is understood that the terms "first", "second", etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0090] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.

[0091] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the relevant listed items.

[0092] Figure 1 FIG. 1 is a schematic diagram of a refresh circuit according to an embodiment of the present invention. Figure 1 As shown, a refresh circuit of an embodiment includes a refresh control circuit 10, a refresh pulse generating circuit 20 and a refresh operation circuit 30. The refresh control circuit 10 is used to receive a first refresh command REFab CMD and count the first refresh command REFab CMD; and generate a second refresh control signal Pulse2 enable based on the count value REFAB conuter of the first refresh command. The refresh pulse generating circuit 20 is used to receive the first refresh command REFab CMD and generate a first refresh pulse Pulse1 based on each first refresh command REFab CMD; and receive the second refresh control signal Pulse2 enable, and generate at least one second refresh pulse Pulse2 based on the first refresh command REFab CMD and the second refresh control signal Pulse2 enable. The refresh operation circuit 30 is used to perform a first refresh operation according to each first refresh pulse Pulse1, and perform a second refresh operation according to each second refresh pulse Pulse2.

[0093] Figure 2 yes Figure 1 The circuit timing diagram corresponding to the refresh circuit shown in FIG. Figure 2 As shown, a first refresh pulse Pulse1 is generated based on each first refresh command REFab CMD. If the count value REFAB conuter of the first refresh command does not reach the set value, the second refresh control signal Pulse2 enable is at an invalid level. If the count value REFAB conuter of the first refresh command reaches the set value, the second refresh control signal Pulse2 enable is at a valid level, and a second refresh pulse Pulse2 is generated after the first refresh pulse Pulse1.

[0094] It should be noted that, during the period when the second refresh control signal Pulse2 enable is at the effective level, based on each first refresh command REFab CMD, a first refresh pulse Pulse1 can be generated, and multiple second refresh pulses Pulse2 can be generated. The present invention is only described by taking the example of generating a second refresh pulse Pulse2 based on each first refresh command REFab CMD, which is not a limitation of the present invention.

[0095] In addition, the number of rows refreshed in one refresh operation (ie, the number of word lines) can be configured according to the capacity of the memory and the internal refresh control circuit, such as setting or modifying the parameters in the mode register.

[0096] The above refresh circuit counts the first refresh command, generates a second refresh control signal based on the count value of the first refresh command, and then generates at least one second refresh pulse based on the first refresh command and the second refresh control signal, and can perform a second refresh operation according to each second refresh pulse. Based on each first refresh command, a first refresh pulse is generated, and a first refresh operation can be performed according to each first refresh pulse. In this way, after performing multiple first refresh operations, a second refresh operation can be performed, thereby inserting redundant row refresh and / or row hammer refresh in the process of performing regular refresh, meeting the refresh requirements of the chip.

[0097] Figure 3 FIG. 1 is a schematic diagram of a refresh circuit according to an embodiment of the present invention. Figure 3 As shown, in one embodiment, the refresh pulse generating circuit 20 is further used to generate a reset signal Counter Rst based on the second refresh pulse Pulse2. The refresh control circuit 10 is further used to receive the reset signal Counter Rst and clear the count value REFAB conuter of the first refresh command based on the reset signal Counter Rst.

[0098] Figure 4 yes Figure 3 The circuit timing diagram corresponding to the refresh circuit shown in FIG. Figure 4 As shown, a reset signal Counter Rst is generated based on the second refresh pulse Pulse2. The count value REFABconuter of the first refresh command is cleared based on the reset signal Counter Rst, and based on the cleared count value REFABconute, the second refresh control signal Pulse2 enable restores the invalid level.

[0099] In the above embodiment, by generating a reset signal Counter Rst based on the second refresh pulse Pulse2, the count value REFAB conuter of the first refresh command can be cleared based on the reset signal Counter Rst, thereby re-counting the first refresh command REFab CMD, and generating a second refresh control signal Pulse2 enable based on the count value REFAB conuter of the first refresh command, thereby generating at least one second refresh pulse Pulse2 based on the first refresh command REFab CMD and the second refresh control signal Pulse2enable, and then performing a second refresh operation according to each second refresh pulse Pulse2, so that a second refresh operation is performed once for every multiple first refresh operations, and redundant row refreshes and / or row hammer refreshes are inserted at equal intervals during the execution of regular refreshes.

[0100] For example, Figure 2 and Figure 4 As shown, the refresh control circuit 10 is used to generate a second refresh control signal Pulse2enable at an effective level when the count value REFAB conuter of the first refresh command reaches a first preset value; and to generate a second refresh control signal Pulse2 enable at an invalid level when the count value REFAB conuter of the first refresh command does not reach the first preset value. The refresh pulse generating circuit 20 is used to generate at least one second refresh pulse Pulse2 based on each first refresh pulse Pulse1 in response to the second refresh control signal Pulse2 enable at an effective level.

[0101] In the above embodiment, by comparing whether the count value REFAB conuter of the first refresh command reaches the first preset value, it is controlled whether the second refresh control signal Pulse2 enable is at a valid level, and then it is controlled whether the second refresh pulse Pulse2 is generated based on the first refresh pulse Pulse1. In this way, according to the ratio of the number of the first refresh operation to the second refresh operation, part of the first refresh pulse Pulse1 can be used to generate the second refresh pulse Pulse2 for performing the second refresh operation, thereby realizing the insertion of redundant row refresh and / or row hammer refresh during the execution of regular refresh.

[0102] Alternatively, if Figure 2 and Figure 4 As shown, the refresh control circuit 10 is further configured to stop counting the first refresh command REFab CMD during the period when the second refresh control signal Pulse2enable is at the effective level.

[0103] In the above embodiment, the refresh control circuit 10 stops counting the first refresh command REFab CMD while the second refresh control signal Pulse2 enable is at a valid level. At this time, the count value REFABconuter of the first refresh command remains at a set value, and the second refresh control signal Pulse2 enable is always at a valid level. A second refresh pulse Pulse2 can be generated based on each first refresh pulse Pulse1, so that multiple first refresh pulses Pulse1 can generate multiple second refresh pulses Pulse2, thereby performing the required number of second refresh operations.

[0104] Figure 5 FIG. 1 is a schematic diagram of a refresh control circuit according to an embodiment of the present invention. Figure 5 As shown, in one embodiment, the refresh control circuit 10 includes a counter control circuit 11, a first counter 12 and a first decoder 13. The counter control circuit 11 is used to receive a first refresh command REFab CMD and a second refresh control signal Pulse2 enable, and output the first refresh command REFab CMD when the second refresh control signal Pulse2 enable is at an invalid level; and when the second refresh control signal Pulse2 enable is at a valid level, the first refresh command REFab CMD is not output. The first counter 12 is used to receive the first refresh command REFab CMD output by the counter control circuit 11, count the first refresh command REFab CMD, generate and output the count value REFAB conuter of the first refresh command; and receive a reset signal Counter Rst, and clear the count value REFAB conuter of the first refresh command according to the reset signal Counter Rst. The first decoder 13 is used to receive the count value REFAB conuter of the first refresh command, and generate a second refresh control signal Pulse2 enable at a valid level when the count value REFAB conuter of the first refresh command reaches a first preset value; and generate a second refresh control signal Pulse2 enable at an invalid level when the count value REFAB conuter of the first refresh command does not reach the first preset value.

[0105] Figure 6 yes Figure 5 The circuit timing diagram corresponding to the refresh control circuit shown in FIG. Figure 6As shown, when the count value REFAB conuter of the first refresh command does not reach the first preset value, the second refresh control signal Pulse2enable is at an invalid level, and the first refresh command REFab CMD is counted. When the count value REFAB conuter of the first refresh command reaches the first preset value, the second refresh control signal Pulse2 enable is at a valid level, and the first refresh command REFabCMD is not counted at this time, until the count value REFAB conuter of the first refresh command is cleared according to the reset signal Counter Rst, and based on the cleared count value REFAB conute, the second refresh control signal Pulse2 enable restores the invalid level.

[0106] In the above embodiment, the counter control circuit 11 outputs the first refresh command REFab CMD only when the second refresh control signal Pulse2 enable is at an invalid level, and the first counter 12 only counts the first refresh command REFab CMD output by the counter control circuit 11, generates and outputs the count value REFAB conuter of the first refresh command, and the first decoder 13 generates the second refresh control signal Pulse2 enable at an effective level when the count value REFAB conuter of the first refresh command reaches the first preset value, and generates the second refresh control signal Pulse2 enable at an invalid level when the count value REFAB conuter of the first refresh command does not reach the first preset value. In this way, the counter control circuit 11, the first counter 12 and the first decoder 13 cooperate to achieve the second refresh control signal Pulse2 enable at an effective level when the count value REFAB conuter of the first refresh command reaches the first preset value; and generate the second refresh control signal Pulse2 enable at an invalid level when the count value REFAB conuter of the first refresh command does not reach the first preset value, and stop the first refresh command REFab In addition, the first counter 12 can receive a reset signal CounterRst, and clear the count value REFAB conuter of the first refresh command according to the reset signal Counter Rst.

[0107] Figure 7 FIG. 1 is a schematic diagram of a counter control circuit according to an embodiment of the present invention. Figure 7As shown, optionally, the counter control circuit 11 includes a first NOT gate 111 and a first NAND gate 112. The input end of the first NOT gate 111 is used to receive the second refresh control signal Pulse2 enable. The first input end of the first NAND gate 112 is used to receive the first refresh command REFab CMD, the second input end of the first NAND gate 112 is connected to the output end of the first NOT gate 111, and the output end of the first NAND gate 112 is used to output the first refresh command REFab CMD.

[0108] Taking the low level as the effective level and the high level as the invalid level as an example, if the second refresh control signal Pulse2enable is at a high level, the output end of the first NOT gate 111 is at a low level. Since the first refresh command REFab CMD is at a high level, the output end of the first NAND gate 112 is at a high level, that is, when the second refresh control signal Pulse2 enable is at an invalid level, the first refresh command REFab CMD is output.

[0109] Similarly, if the second refresh control signal Pulse2 enable is at a low level, the output of the first NOT gate 111 is at a high level. Since the first refresh command REFab CMD is at a high level, the output of the first NAND gate 112 is at a low level, that is, when the second refresh control signal Pulse2 enable is at a valid level, the first refresh command REFabCMD is not output.

[0110] In the above embodiment, the counter control circuit 11 is implemented by cooperating with the first NOT gate 111 and the first NAND gate 112. When the second refresh control signal Pulse2 enable is at an invalid level, the first refresh command REFab CMD can be output, so that the counter counts based on the output first refresh command REFab CMD, and when the second refresh control signal Pulse2enable is at a valid level, the first refresh command REFab CMD is not output, so as to stop counting the first refresh command REFabCMD.

[0111] Figure 8 : is a schematic diagram of the structure of a first counter according to an embodiment of the present invention. Figure 8As shown, optionally, the first counter 12 includes N first D flip-flops 121, N second NOT gates 122, and N third NOT gates 123. The clock terminal of the first first D flip-flop 121 is connected to the output terminal of the first NAND gate 112, for receiving the first refresh command REFab CMD, N≥2 and N is an integer. The N second NOT gates 122 correspond to the N first D flip-flops 121 one by one, the input terminal of each second NOT gate 122 is connected to the positive phase output terminal of the corresponding first D flip-flop 121, and the output terminal of each second NOT gate 122 is connected to the input terminal of the corresponding first D flip-flop 121. The N third NOT gates 123 correspond to the N first D flip-flops 121 one by one, the input terminal of each third NOT gate 123 is connected to the output terminal of the corresponding second NOT gate 122, and the clock terminal of the i-th first D flip-flop 121 is connected to the output terminal of the third NOT gate 123 corresponding to the i-1-th first D flip-flop 121, N≥i≥2 and i is an integer. The output ends of the N third NOT gates 123 serve as the output end of the first counter 11 for outputting the count value REFAB conuter of the first refresh command.

[0112] Taking N=5 as an example, the clock terminal of the first first D flip-flop 121 receives the first first refresh command REFabCMD, and the output signal REFABCNT of the first third NOT gate 123 is <0> becomes 1, and the output signal REFABCNT of the second third NOT gate 123 <1> , the output signal REFABCNT of the third third NOT gate 123 <2> , the output signal REFABCNT of the fourth third NOT gate 123 <3> , the output signal REFABCNT of the fifth third NOT gate 123 <4> are all 0, and the count value REFAB conuter of the first refresh command is 00001.

[0113] The clock terminal of the first first D flip-flop 121 receives the second first refresh command REFab CMD, and the output signal REFABCNT of the first third NOT gate 123 <0> becomes 0, and the output signal REFABCNT of the second third NOT gate 123 <1> becomes 1, and the output signal REFABCNT of the third third NOT gate 123 <2> , the output signal REFABCNT of the fourth third NOT gate 123 <3> , the output signal REFABCNT of the fifth third NOT gate 123 <4> are all 0, and the count value REFAB conuter of the first refresh command is 00010.

[0114] The clock terminal of the first first D flip-flop 121 receives the third first refresh command REFab CMD, and the output signal REFABCNT of the first third NOT gate 123 <0> becomes 1, and the output signal REFABCNT of the second third NOT gate 123 <1> Still 1, the output signal REFABCNT of the third third NOT gate 123 <2> , the output signal REFABCNT of the fourth third NOT gate 123 <3> , the output signal REFABCNT of the fifth third NOT gate 123 <4> are all 0, and the count value REFAB conuter of the first refresh command is 00011.

[0115] By analogy, each time the clock terminal of the first D flip-flop 121 receives a first refresh command REFabCMD, the count value REFAB conuter of the first refresh command increases by one until it is reset.

[0116] In the above embodiment, N first D flip-flops 121, N second NOT gates 122 and N third NOT gates 123 cooperate to implement the first counter 12, which can count the first refresh command REFab CMD, generate and output the count value REFAB conuter of the first refresh command.

[0117] Fig. 9 FIG. 1 is a schematic diagram of the structure of a first decoder according to an embodiment of the present invention. Fig. 9 As shown, optionally, the first preset value includes an N-bit preset reference signal. The first decoder 13 includes N comparators 131 and a first AND gate 132. The N comparators 131 correspond one-to-one to the N third NOT gates 123, and the first input end of each comparator 131 is connected to the output end of a corresponding third NOT gate 123, and the second input end of each comparator 131 is used to access the corresponding one-bit preset reference signal. The input end of the first AND gate 132 is connected one-to-one to the output end of the N comparators 131, and the output end of the first AND gate 132 is used to output the second refresh control signal Pulse2 enable.

[0118] When the count value REFAB conuter of the first refresh command reaches the first preset value, all comparators 131 output a high level, the first AND gate 132 outputs a high level, and the second refresh control signal Pulse2 enable at a valid level is generated. When the count value REFAB conuter of the first refresh command does not reach the first preset value, at least one comparator 131 outputs a low level, the first AND gate 132 outputs a low level, and the second refresh control signal Pulse2 enable at an invalid level is generated.

[0119] In the above embodiment, N comparators 131 and the first AND gate 132 cooperate to implement the first decoder 13, which can generate a second refresh control signal Pulse2 enable at a valid level when the count value REFAB conuter of the first refresh command reaches a first preset value, and generate a second refresh control signal Pulse2 enable at an invalid level when the count value REFAB conuter of the first refresh command does not reach the first preset value.

[0120] In practical applications, a NOT gate may be provided at the output end of the first AND gate 132 to adjust the level state of the second refresh control signal Pulse2 enable. Taking a low level as a valid level and a high level as an invalid level as an example, if the first AND gate 132 outputs a high level, the first AND gate 132 outputs a low level second refresh control signal Pulse2 enable through the NOT gate, so that the second refresh control signal Pulse2 enable is at a valid level; if the first AND gate 132 outputs a low level, the first AND gate 132 outputs a high level second refresh control signal Pulse2 enable through the NOT gate, so that the second refresh control signal Pulse2 enable is at an invalid level.

[0121] Fig.10 FIG. 1 is a schematic diagram of the structure of a first decoder according to an embodiment of the present invention. Fig.10 As shown, in one embodiment, the refresh pulse generating circuit 20 includes a pulse generating circuit 21, a second refresh command generating circuit 22 and a reset signal generating circuit 23. The pulse generating circuit 21 is used to receive the first refresh command REFab CMD, and generate a first refresh pulse Pulse1 based on each first refresh command REFab CMD. The second refresh command generating circuit 22 is connected to the pulse generating circuit 21, and is used to receive the second refresh control signal Pulse2enable and the first refresh pulse Pulse1, and during the period when the second refresh control signal Pulse2enable is at an effective level, generates and outputs at least one second refresh command Ref pulse2 based on each first refresh pulse Pulse1. The pulse generating circuit 21 is also used to receive the second refresh command Ref pulse2, and generate a second refresh pulse Pulse2 based on each second refresh command Ref pulse2. The reset signal generating circuit 23 is connected to the second refresh command generating circuit 22, and is used to generate a reset signal Counter Rst based on the second refresh command Ref pulse2.

[0122] Fig.11 yes Fig.10 The circuit timing diagram corresponding to the refresh pulse generating circuit shown in FIG. Fig.11As shown, a first refresh pulse Pulse1 is generated based on each first refresh command REFab CMD. When the first refresh command REFab CMD reaches a set number, the second refresh control signal Pulse2 enable is at an effective level, at least one second refresh command Ref pulse2 is generated based on each first refresh pulse Pulse1, and a second refresh pulse Pulse2 is generated based on each second refresh command Ref pulse2. When the second refresh command Ref pulse2 reaches a set number, a reset signal Counter Rst is generated based on the second refresh command Refpulse2.

[0123] In the above embodiment, the pulse generating circuit 21 , the second refresh command generating circuit 22 and the reset signal generating circuit 23 cooperate to implement various functions of the refresh pulse generating circuit 20 .

[0124] Fig.12 FIG. 1 is a schematic diagram of the structure of a second refresh command generating circuit according to an embodiment of the present invention. Fig.12 As shown, optionally, the second refresh command generating circuit 22 includes a second AND gate 221, a first delay unit 222 and a pulse generating unit 223. The first input end of the second AND gate 221 is used to receive the second refresh control signal Pulse2enable, and the second input end of the second AND gate 221 is used to receive the first refresh pulse Pulse1. The input end of the first delay unit 222 is connected to the output end of the second AND gate 221, and the output end of the first delay unit 222 is used to output the delayed first refresh pulse Pulse1. The input end of the pulse generating unit 223 is connected to the output end of the first delay unit 222, and is used to generate and output the second refresh command Ref pulse2 based on the delayed first refresh pulse Pulse1.

[0125] If the second refresh control signal Pulse2 enable is in the effective level period, the second refresh control signal Pulse2 enable is high level, and the first refresh pulse Pulse1 is high level, the second AND gate 221 and the first delay unit 222 cooperate to output a high level to generate a delayed first refresh pulse Pulse1. The pulse generating unit 223 generates and outputs a second refresh command Ref pulse2 based on the delayed first refresh pulse Pulse1.

[0126] In the above embodiment, the second AND gate 221, the first delay unit 222 and the pulse generating unit 223 cooperate to implement the second refresh command generating circuit 22, which can generate and output at least one second refresh command Ref pulse2 based on each first refresh pulse Pulse1 while the second refresh control signal Pulse2 enable is at a valid level.

[0127] Exemplarily, the second AND gate 221 can be implemented by a NAND gate and a NOT gate, and the input end of the NOT gate is connected to the output end of the NAND gate. The pulse generating unit 223 can be implemented by a NOT gate, a delay unit and a NOR gate, and the input end of the delay unit is connected to the output end of the NOT gate, one input end of the NOR gate is connected to the output end of the delay unit, and the other input end of the NOR gate is connected to the input end of the NOT gate.

[0128] Exemplarily, the pulse generating circuit 21 is used to generate a second refresh pulse Pulse2 (eg, Figure 2 or Figure 4 or, during each time the second refresh control signal Pulse2 enable is at an effective level, a plurality of second refresh pulses Pulse2 (such as Fig.11 shown).

[0129] In the above embodiment, the pulse generating circuit 21 can generate a second refresh pulse Pulse2 based on the first refresh command REFab CMD each time the second refresh control signal Pulse2 enable is at a valid level, or can generate multiple second refresh pulses Pulse2 based on the first refresh command REFab CMD. The number of second refresh pulses Pulse2 generated can be adjusted according to actual needs to meet various refresh requirements.

[0130] Fig.13 FIG. 1 is a schematic diagram of a reset signal generating circuit according to an embodiment of the present invention. Fig.13 As shown, optionally, when the pulse generating circuit 21 generates a second refresh pulse Pulse2 based on the first refresh command REFab CMD each time the second refresh control signal Pulse2 enable is at an effective level, the reset signal generating circuit 23 includes a fourth NOT gate 231, a second delay unit 232, a third AND gate 233 and a third delay unit 234. The input end of the fourth NOT gate 231 is connected to the output end of the pulse generating unit 223 for receiving the second refresh command Ref pulse2. The input end of the second delay unit 232 is connected to the output end of the fourth NOT gate 231. The first input end of the third AND gate 233 is connected to the output end of the second delay unit 232, and the second input end of the third AND gate 233 is connected to the output end of the pulse generating unit 223. The input end of the third delay unit 234 is connected to the output end of the third AND gate 233, and the output end of the third delay unit 234 is used to output the reset signal Counter Rst.

[0131] Fig.14 yes Fig.13 The circuit timing diagram corresponding to the reset signal generating circuit shown in FIG. Fig.14 As shown, the fourth NOT gate 231 and the second delay unit 232 cooperate to invert and delay the second refresh command Ref pulse2, and the third AND gate 233 and the third delay unit 234 cooperate to perform logic AND and delay on the second refresh command Ref pulse2 and its inverted and delayed signal to generate a reset signal Counter Rst.

[0132] In the above embodiment, the fourth NOT gate 231, the second delay unit 232, the third AND gate 233 and the third delay unit 234 cooperate to realize that when the pulse generating circuit 21 generates a second refresh pulse Pulse2 based on the first refresh command REFab CMD each time the second refresh control signal Pulse2 enable is at a valid level, a reset signal Counter Rst is generated based on the second refresh command Refpulse2.

[0133] Fig.15 FIG. 1 is a schematic diagram of a reset signal generating circuit according to an embodiment of the present invention. Fig.15 As shown, optionally, when the pulse generating circuit 21 generates a plurality of second refresh pulses Pulse2 based on the first refresh command REFab CMD each time the second refresh control signal Pulse2 enable is at an effective level, the reset signal generating circuit 23 includes a second counter 235 and a second decoder 236. The second counter 235 is connected to the pulse generating unit 223, and is used to receive the second refresh pulse Pulse2, count the second refresh pulse Pulse2, generate and output the count value Pulse2 count of the second refresh pulse. The second decoder 236 is connected to the second counter 235, and is used to receive the count value Pulse2 count of the second refresh pulse, and when the count value Pulse2 count of the second refresh pulse reaches the second preset value, generate a reset signal Counter Rst at an effective level; and when the count value Pulse2 count of the second refresh pulse does not reach the second preset value, generate a reset signal Counter Rst at an invalid level.

[0134] Fig.16 yes Fig.15 The circuit timing diagram corresponding to the reset signal generating circuit shown in FIG. Fig.16As shown, the second refresh pulse Pulse2 is counted, and the count value Pulse2 count of the second refresh pulse is generated and output. When the count value Pulse2 count of the second refresh pulse does not reach the second preset value, a reset signal Counter Rst at an invalid level is generated. When the count value Pulse2 count of the second refresh pulse reaches the second preset value, a reset signal Counter Rst at a valid level is generated.

[0135] In the above embodiment, the second counter 235 counts the second refresh pulse Pulse2, generates and outputs the count value Pulse2 count of the second refresh pulse, and the second decoder 236 generates a reset signal Counter Rst at a valid level when the count value Pulse2 count of the second refresh pulse reaches the second preset value, and generates a reset signal Counter Rst at an invalid level when the count value Pulse2 count of the second refresh pulse does not reach the second preset value, thereby achieving that when the pulse generating circuit 21 generates multiple second refresh pulses Pulse2 based on the first refresh command REFab CMD each time the second refresh control signal Pulse2 enable is at a valid level, the reset signal Counter Rst is generated based on the second refresh command Ref pulse2.

[0136] Fig.17 FIG. 4 is a schematic diagram of the structure of a second counter according to an embodiment of the present invention. Fig.17 As shown, illustratively, the second counter 235 includes M second D flip-flops 2351, M fifth NOT gates 2352 and M sixth fourth NOT gates 2353. The clock end of the first second D flip-flop 2351 is connected to the output end of the pulse generating unit 223, for receiving the second refresh command Ref pulse2, M ≥ 2 and M is an integer. The M fifth NOT gates 2352 correspond to the M second D flip-flops 2351 one by one, the input end of each fifth NOT gate 2352 is connected to the positive phase output end of the corresponding second D flip-flop 2351, and the output end of each fifth NOT gate 2352 is connected to the input end of the corresponding second D flip-flop 2351. The M sixth NOT gates 2353 correspond to the M second D flip-flops 2351 one by one, the input end of each sixth NOT gate 2353 is connected to the output end of the corresponding fifth NOT gate 2352, the clock end of the j-th second D flip-flop 2351 is connected to the output end of the sixth NOT gate 2353 corresponding to the j-1-th second D flip-flop 2351, M≥j≥2 and j is an integer. The output ends of the M sixth NOT gates 2353 serve as the output ends of the second counter, and are used to output the count value Pulse2count of the second refresh pulse.

[0137] Taking M=2 as an example, the clock terminal of the first second D flip-flop 2351 receives the first second refresh command Refpulse2, and the output signal Pulse2Cnt of the first sixth NOT gate 2353 is <0> becomes 1, the output signal Pulse2Cnt of the second sixth NOT gate 2353 <1> is 0, and the count value of the second refresh pulse Pulse2 count is 01.

[0138] The clock terminal of the first second D flip-flop 2351 receives the second second refresh command Ref pulse2, and the output signal Pulse2Cnt of the first sixth NOT gate 2353 <0> becomes 0, the output signal Pulse2Cnt of the second sixth NOT gate 2353 <1> becomes 1, and the count value of the second refresh pulse Pulse2 count is 10.

[0139] In the above embodiment, M second D flip-flops 2351, M fifth NOT gates 2352 and M sixth fourth NOT gates 2353 cooperate to implement the second counter 235, which can count the second refresh pulse Pulse2, generate and output the count value Pulse2 count of the second refresh pulse.

[0140] In one embodiment, the second refresh operation is a redundant row refresh and / or a row hammer refresh.

[0141] Based on the same inventive concept, a refreshing method is also provided. Fig.18 Flow chart of a refreshing method according to an embodiment of the present invention. Fig.18 As shown, the refreshing method includes the following steps:

[0142] S1801, receiving a first refresh command.

[0143] S1802, generating a first refresh pulse based on each first refresh command, and performing a first refresh operation according to each first refresh pulse.

[0144] S1803, counting the first refresh command, and generating a second refresh control signal based on the count value of the first refresh command.

[0145] S1804, generating at least one second refresh pulse based on the first refresh command and the second refresh control signal, and performing a second refresh operation according to each second refresh pulse.

[0146] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0147] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0148] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A refresh circuit, characterized in that: The refresh circuit comprises: A refresh control circuit, configured to receive a first refresh command, count the first refresh command, and generate a second refresh control signal based on the count value of the first refresh command; a refresh pulse generating circuit, configured to receive the first refresh command and generate a first refresh pulse based on each of the first refresh commands; and receive the second refresh control signal and generate at least one second refresh pulse based on the first refresh command and the second refresh control signal; The refresh operation circuit is used to perform a first refresh operation according to each of the first refresh pulses, and to perform a second refresh operation according to each of the second refresh pulses.

2. The refresh circuit according to claim 1, characterized in that: The refresh pulse generating circuit is further configured to generate a reset signal based on the second refresh pulse; The refresh control circuit is further configured to receive the reset signal and clear the count value of the first refresh command based on the reset signal.

3. The refresh circuit according to claim 2, characterized in that: The refresh control circuit is used to generate a second refresh control signal at a valid level when the count value of the first refresh command reaches a first preset value; and to generate a second refresh control signal at an invalid level when the count value of the first refresh command does not reach the first preset value; The refresh pulse generating circuit is configured to generate at least one of the second refresh pulses based on each of the first refresh pulses in response to a second refresh control signal at an active level.

4. The refresh circuit according to claim 3, characterized in that: The refresh control circuit is further configured to stop counting the first refresh command while the second refresh control signal is at a valid level.

5. The refresh circuit according to claim 4, characterized in that: The refresh control circuit comprises: a counter control circuit, configured to receive the first refresh command and the second refresh control signal, and output the first refresh command when the second refresh control signal is at an invalid level; and not output the first refresh command when the second refresh control signal is at a valid level; a first counter, configured to receive the first refresh command output by the counter control circuit, count the first refresh command, generate and output a count value of the first refresh command; and receive the reset signal, and clear the count value of the first refresh command according to the reset signal; A first decoder is used to receive the count value of the first refresh command and generate a second refresh control signal at a valid level when the count value of the first refresh command reaches a first preset value; and generate a second refresh control signal at an invalid level when the count value of the first refresh command does not reach the first preset value.

6. The refresh circuit according to claim 5, characterized in that: The counter control circuit comprises: a first NOT gate, wherein an input end of the first NOT gate is used to receive the second refresh control signal; A first NAND gate, wherein the first input end of the first NAND gate is used to receive the first refresh command, the second input end of the first NAND gate is connected to the output end of the first NAND gate, and the output end of the first NAND gate is used to output the first refresh command.

7. The refresh circuit according to claim 6, characterized in that: The first counter comprises: N first D flip-flops, a clock terminal of a first of the first D flip-flops being connected to an output terminal of the first NAND gate, for receiving the first refresh command, N≥2 and N is an integer; N second NOT gates, corresponding one to one with the N first D flip-flops, the input end of each second NOT gate being connected to the positive phase output end of the corresponding first D flip-flop, and the output end of each second NOT gate being connected to the input end of the corresponding first D flip-flop; N third NOT gates, corresponding one to one with the N first D flip-flops, the input end of each of the third NOT gates being connected to the output end of the corresponding second NOT gate, the clock end of the i-th first D flip-flop being connected to the output end of the third NOT gate corresponding to the i-1-th first D flip-flop, N≥i≥2 and i is an integer; The output ends of the N third NOT gates serve as the output ends of the first counter, and are used to output the count value of the first refresh command.

8. The refresh circuit according to claim 7, characterized in that: The first preset value includes an N-bit preset reference signal; the first decoder includes: N comparators, corresponding one to one with the N third NOT gates, a first input end of each comparator connected to an output end of a corresponding third NOT gate, and a second input end of each comparator used to access a corresponding one-bit preset reference signal; A first AND gate, wherein an input end of the first AND gate is connected to the output ends of the N comparators in a one-to-one correspondence, and an output end of the first AND gate is used to output the second refresh control signal.

9. The refresh circuit according to any one of claims 3 to 8, characterized in that: The refresh pulse generating circuit comprises: a pulse generating circuit, configured to receive the first refresh command and generate one first refresh pulse based on each first refresh command; a second refresh command generating circuit, connected to the pulse generating circuit, configured to receive the second refresh control signal and the first refresh pulse, and to generate and output at least one second refresh command based on each of the first refresh pulses during a period in which the second refresh control signal is at an effective level; The pulse generating circuit is further used for receiving the second refresh command and generating a second refresh pulse based on each second refresh command; A reset signal generating circuit is connected to the second refresh command generating circuit and is used to generate a reset signal based on the second refresh command.

10. The refresh circuit according to claim 9, characterized in that: The second refresh command generating circuit comprises: a second AND gate, wherein a first input terminal of the second AND gate is used to receive the second refresh control signal, and a second input terminal of the second AND gate is used to receive the first refresh pulse; a first delay unit, wherein an input end of the first delay unit is connected to an output end of the second AND gate, and an output end of the first delay unit is used to output the delayed first refresh pulse; A pulse generating unit, wherein an input end of the pulse generating unit is connected to an output end of the first delay unit, and is used for generating and outputting the second refresh command based on the delayed first refresh pulse.

11. The refresh circuit according to claim 10, characterized in that: The pulse generating circuit is used to generate one second refresh pulse based on the first refresh command each time the second refresh control signal is at a valid level; or to generate multiple second refresh pulses based on the first refresh command each time the second refresh control signal is at a valid level.

12. The refresh circuit according to claim 11, characterized in that: When the pulse generating circuit generates a second refresh pulse based on the first refresh command each time the second refresh control signal is at an effective level, the reset signal generating circuit includes: a fourth NOT gate, wherein an input end of the fourth NOT gate is connected to an output end of the pulse generating unit and is used for receiving the second refresh command; a second delay unit, wherein an input end of the second delay unit is connected to an output end of the fourth NOT gate; a third AND gate, wherein a first input terminal of the third AND gate is connected to the output terminal of the second delay unit, and a second input terminal of the third AND gate is connected to the output terminal of the pulse generating unit; A third delay unit, wherein the input end of the third delay unit is connected to the output end of the third AND gate, and the output end of the third delay unit is used to output the reset signal.

13. The refresh circuit according to claim 11, characterized in that: When the pulse generating circuit generates a plurality of second refresh pulses based on the first refresh command each time the second refresh control signal is at an effective level, the reset signal generating circuit includes: a second counter connected to the pulse generating unit, configured to receive the second refresh pulse, count the second refresh pulse, generate and output a count value of the second refresh pulse; A second decoder is connected to the second counter, and is used to receive the count value of the second refresh pulse, and generate a reset signal at a valid level when the value of the second count refresh pulse reaches a second preset value; and generate a reset signal at an invalid level when the count value of the second refresh pulse does not reach the second preset value.

14. The refresh circuit according to claim 13, characterized in that: The second counter comprises: M second D flip-flops, a clock terminal of a first of the second D flip-flops being connected to the output terminal of the pulse generating unit, for receiving the second refresh command, M≥2 and M is an integer; M fifth NOT gates, corresponding one to one with the M second D flip-flops, the input end of each of the fifth NOT gates being connected to the non-phase output end of the corresponding second D flip-flop, and the output end of each of the fifth NOT gates being connected to the input end of the corresponding second D flip-flop; M sixth NOT gates, corresponding one to one with the M second D flip-flops, the input end of each of the sixth NOT gates being connected to the output end of the corresponding fifth NOT gate, the clock end of the jth second D flip-flop being connected to the output end of the sixth NOT gate corresponding to the j-1th second D flip-flop, M≥j≥2 and j is an integer; The output ends of the M sixth NOT gates serve as the output ends of the second counter, and are used to output the count value of the second refresh pulse.

15. The refresh circuit according to claim 1, characterized in that: The second refresh operation is a redundant row refresh and / or a row hammer refresh.

16. A refreshing method, characterized in that: The refreshing method comprises: receiving a first refresh command; generating a first refresh pulse based on each of the first refresh commands, and performing a first refresh operation according to each of the first refresh pulses; Counting the first refresh command and generating a second refresh control signal based on the count value of the first refresh command; At least one second refresh pulse is generated based on the first refresh command and the second refresh control signal, and a second refresh operation is performed once according to each of the second refresh pulses.

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