Memory, built-in self-test method and electronic equipment

Abstract

The invention provides a memory, a built-in self-test method and electronic equipment, and the method comprises the steps: decoding a row address signal through an address module in a built-in self-test process, and outputting a position indication signal; the position indication signal represents that the target word line is located in the odd storage part or the even storage part; furthermore, according to the position indication signal, the initial test data or the inverted data of the initial test data are output as target test data, and the target test data are used for being written into a target word line.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to a memory, a built-in self-test method and an electronic device. Background Art

[0002] With the continuous development of semiconductor technology, people have put forward higher and higher requirements on the data transmission speed when manufacturing and using computers and other equipment. Taking Dynamic Random Access Memory (DRAM) as an example, in order to ensure the correctness of its storage function, it is necessary to test the memory, such as performing a memory built-in self-test (MBIST). However, the current built-in self-test still has some defects, and the test effect is not satisfactory. Summary of the invention

[0003] The present disclosure provides a memory, a built-in self-test method and an electronic device.

[0004] The technical solution of the present disclosure is achieved as follows:

[0005] In a first aspect, an embodiment of the present disclosure provides a memory, comprising a plurality of storage parts arranged along a first direction, a sense amplifier being arranged between adjacent storage parts, the plurality of storage parts being odd storage parts and even storage parts alternately arranged in the first direction, an odd bit line of the odd storage part being connected to the sense amplifier adjacent to the first side, and an even bit line of the odd storage part being connected to the sense amplifier adjacent to the second side; an odd bit line of the even storage part being connected to the sense amplifier adjacent to the second side, and an even bit line of the even storage part being connected to the sense amplifier adjacent to the first side;

[0006] The memory also includes a built-in self-test module, the built-in self-test module including:

[0007] An address module is configured to receive a row address signal and decode the row address signal to output a position indication signal; wherein the row address signal is used to select a target word line, and the position indication signal indicates that the target word line is located in the odd storage part or the even storage part;

[0008] The data module is connected to the address module and is configured to receive initial test data and the position indication signal, and output the initial test data or the inverted data of the initial test data as target test data according to the position indication signal, and the target test data is used to write the target word line.

[0009] In some embodiments, the address module is specifically configured to output the position indication signal of a first state if the target word line is located in the odd storage unit; and output the position indication signal of a second state if the target word line is located in the even storage unit;

[0010] The data module is specifically configured to output the initial test data as the target test data if the position indication signal is in the second state; and to invert the initial test data to generate inverted data of the initial test data, and output the inverted data of the initial test data as the target test data if the position indication signal is in the first state.

[0011] In some embodiments, every N consecutive storage units along the first direction are divided into a storage domain; N is an odd number; the row address signal includes a first address signal group and a second address signal, and the address module includes:

[0012] A first decoding module is configured to receive a first address signal group, decode the first address signal group, and generate a positioning signal, wherein the positioning signal represents a position of the storage portion corresponding to the target word line in the storage domain;

[0013] The second decoding module is configured to receive a second address signal and the positioning signal, perform a logic operation on the second address signal and the positioning signal, and generate the position indication signal; the second address signal represents the parity of the storage domain number to which the target word line belongs.

[0014] In some embodiments, when N is an even number, the address module includes:

[0015] A third decoding module is configured to receive the first address signal group, decode the first address signal group, and generate the positioning signal, wherein the positioning signal represents the position of the storage part corresponding to the target word line in the storage domain;

[0016] The fourth decoding module is configured to receive a positioning signal, and generate the position indication signal based on the positioning signal.

[0017] In some embodiments, the positioning signal includes N positioning sub-signals, and the i-th positioning sub-signal indicates whether the target word line is located in the i-th storage part of one of the storage domains;

[0018] The second decoding module includes an even decoding unit, an odd decoding unit and an operator;

[0019] The even decoding unit is configured to perform a logic operation on the even-numbered bit of the locator signal and the second address signal; if the operation result indicates that the target word line is located in the even-numbered storage part in the odd-numbered storage domain, then output an even indication signal of a third state; if the operation result indicates that the target word line is not located in the even-numbered storage part in the odd-numbered storage domain, then output an even indication signal of a fourth state;

[0020] The odd decoding unit is configured to perform a logic operation on the odd-numbered bit of the locator signal and the inverted signal of the second address signal; if the operation result indicates that the target word line is located in the odd-numbered storage part in the even-numbered storage domain, then output an odd indication signal of a fifth state; if the operation result indicates that the target word line is not located in the odd-numbered storage part in the even-numbered storage domain, then output an odd indication signal of a sixth state;

[0021] The operator is connected to the odd decoding unit and the even decoding unit, and is configured to output the position indication signal of the first state if the even indication signal is in the third state or the odd indication signal is in the fifth state; and to output the position indication signal of the second state if the even indication signal is in the fourth state and the odd indication signal is in the sixth state.

[0022] In some embodiments, the odd decoding unit includes a first decoding unit and a second decoding unit;

[0023] The first decoding unit is configured to perform a logic operation on the odd-numbered bits of the positioning sub-signal and output a first intermediate signal; wherein the first intermediate signal indicates whether the target word line is located in the odd-numbered storage part in one of the storage domains;

[0024] The second decoding unit is connected to the first decoding unit, and is configured to perform logic processing on the first intermediate signal and the inverted signal of the second address signal, and output the odd indication signal.

[0025] In some embodiments, the even decoding unit includes a third decoding unit and a fourth decoding unit;

[0026] The third decoding unit is configured to perform a logic operation on the even-numbered bits of the positioning sub-signal and output a second intermediate signal; wherein the second intermediate signal indicates whether the target word line is located in the even-numbered storage section in one of the storage domains;

[0027] The fourth decoding unit is connected to the third decoding unit, and is configured to perform logic processing on the second intermediate signal and the second address signal, and output the even indication signal.

[0028] In some embodiments, the data module includes a tri-state transmission gate, a tri-state inverter, and an inverter;

[0029] For the three-state transmission gate and the three-state inverter, their input ends are used to receive the initial test data, their output ends are connected to the input end of the inverter, and their control ends receive the position indication signal; the inverter is used to output the target test data; wherein, the three-state transmission gate is enabled based on the position indication signal in the first state, and the three-state inverter is enabled based on the position indication signal in the second state.

[0030] In a second aspect, an embodiment of the present disclosure provides a built-in self-test method, which is applied to a memory, wherein the memory includes a plurality of storage parts arranged along a first direction, a sense amplifier is provided between adjacent storage parts, the plurality of storage parts are odd storage parts and even storage parts alternately arranged in the first direction, an odd bit line of the odd storage part is connected to the sense amplifier adjacent to the first side, and an even bit line is connected to the sense amplifier adjacent to the second side; an odd bit line of the even storage part is connected to the sense amplifier adjacent to the second side, and an even bit line is connected to the sense amplifier adjacent to the first side; the method includes:

[0031] receiving a row address signal and decoding the row address signal, and outputting a position indication signal; wherein the row address signal is used to select a target word line, and the position indication signal indicates that the target word line is located in the odd storage part or the even storage part;

[0032] Initial test data is received, and according to the position indication signal, the initial test data or inverted data of the initial test data is output as target test data, and the target test data is used to write into the target word line.

[0033] In a third aspect, an embodiment of the present disclosure provides an electronic device, wherein the electronic device includes the memory described in the first aspect.

[0034] The embodiments of the present disclosure provide a memory, a built-in self-test method and an electronic device, which can make the data actually written into different storage units the same, thereby obtaining a better test effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 A schematic diagram of the structure of a memory provided by an embodiment of the present disclosure;

[0036] Figure 2 A schematic diagram of the working process of a memory;

[0037] Figure 3 A schematic diagram of the structure of another memory provided by an embodiment of the present disclosure;

[0038] Figure 4 A schematic diagram of a working process of a memory provided by an embodiment of the present disclosure;

[0039] Figure 5 A partial structure diagram of a memory provided in an embodiment of the present disclosure Figure 1 ;

[0040] Figure 6 A partial structure diagram of a memory provided in an embodiment of the present disclosure Figure 2 ;

[0041] Figure 7 A partial structure diagram of a memory provided in an embodiment of the present disclosure Figure 3 ;

[0042] Figure 8 A flow chart of a built-in self-test method provided in an embodiment of the present disclosure;

[0043] Fig. 9 A schematic diagram of the structure of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0044] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. It is understood that the specific embodiments described herein are only used to explain the relevant application, rather than to limit the application. It should also be noted that, for ease of description, only the parts related to the relevant application are shown in the drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by technicians in the technical field of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure. In the following description, "some embodiments" are involved, which describe a subset of all possible embodiments, but it is understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict. It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are only used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that shown or described; in addition, "odd" and "even" in the subsequent description of the embodiments of the present disclosure only refer to a relative characteristic, not an absolute characteristic.

[0045] The following are explanations of professional terms involved in the embodiments of the present disclosure and the corresponding relationships of some terms:

[0046] Synchronous Dynamic Random Access Memory (SDRAM);

[0047] Double Data Rate SDRAM (DDR);

[0048] Low Power DDR (LPDDR).

[0049] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0050] See also Figure 1 , which shows a schematic diagram of the structure of a memory 10 provided by an embodiment of the present disclosure. Figure 1 As shown, the memory 10 includes a plurality of storage parts arranged along a first direction, a sense amplifier SA is provided between adjacent storage parts, and the plurality of storage parts are even storage parts 11_e and odd storage parts 11_o alternately arranged in the first direction.

[0051] Please note that, see Figure 2 , each storage unit has a plurality of bit lines extending along the first direction ( Figure 2 Only a portion, namely, BLA0-7, BLB0-7) and a plurality of word lines extending along the second direction ( Figure 2 Only one word line is shown for each storage unit, and a storage cell Cell is formed at the intersection of a bit line and a word line.

[0052] From a classification perspective (position number of the bit line), the bit lines in each storage unit are divided into even bit lines ( Figure 2 BLA0 to BLA7 in (a) Figure 2 BLB0~BLB7) and odd bit lines ( Figure 2 BLB0 to BLB7 in (a) Figure 2 In (b) (BLA0~BLA7), the odd bit lines and the even bit lines are arranged crosswise along the second direction. Simply put, along the second direction, the even-numbered bit lines (starting from 0) in each storage unit are all even bit lines, and the odd-numbered bit lines in each storage unit are all odd bit lines; that is, counting from the left, the 0th, 2nd, 4th, 6th... bit lines are even bit lines, and the 1st, 3rd, 5th, 7th... bit lines are odd bit lines. It can be understood that the above-mentioned odd and even numbers refer to the numbers that sort the actual physical positions of the bit lines in the second direction, and do not refer to the numbers in the figure marks. The second direction is another direction perpendicular to the first direction.

[0053] It should be noted that "odd" and "even" in the subsequent description of the embodiments of the present disclosure refer only to a relative characteristic, not an absolute characteristic. For example, the bit lines with even numbers (starting from 0) in each storage unit can be defined as odd bit lines, and the bit lines with odd numbers in each storage unit can be defined as even bit lines; that is, from the left, the 0th, 2nd, 4th, 6th, ... bit lines are odd bit lines, and the 1st, 3rd, 5th, 7th, ... bit lines are even bit lines.

[0054] See also Figure 2 In (a), the even bit lines (BLA0-BLA7) of the even storage unit 11_e are connected to the sense amplifier SA adjacent to the first side, and the odd bit lines (BLB0-BLB7) of the even storage unit 11_e are connected to the sense amplifier SA adjacent to the second side. Figure 2 In (b), the odd bit lines (BLA0 to BLA7) of the odd storage unit 11_o are connected to the sense amplifier SA adjacent to the first side, and the even bit lines (BLB0 to BLB7) of the odd storage unit 11_o are connected to the sense amplifier SA adjacent to the second side.

[0055] In addition, from another classification perspective (the connection relationship between the bit line and the sense amplifier), since the connection position between the local transmission line IO and the bit line BL, and the position between the bit line BL and the sense amplifier SA are always fixed, and the local transmission line IO is only connected to the bit line BL on one side of the sense amplifier SA, the sense amplifier SA always sends the data input from the local transmission line IO to the bit line BL on one side, and sends the inverted data to the bit line BL on the other side. Specifically, the bit lines in each storage unit can also be classified as positive bit lines BLA or complementary bit lines BLB. When writing data to the storage unit, the corresponding sense amplifier SA always writes the data transmitted from the local transmission line IO to the positive bit line BLA, and writes the inverted data of the data transmitted from the local transmission line IO to the complementary bit line BLB. In order to save the number of local data lines IO, the positive bit line BLA and the complementary bit line BLB are currently used to write data to the storage unit corresponding to the same word line.

[0056] In some embodiments, for the even storage unit 11_e, the even bit lines therein are all positive bit lines BLA, and the odd bit lines therein are all complementary bit lines BLB; for the odd storage unit 11_o, the odd bit lines therein are all positive bit lines BLA, and the even bit lines therein are all complementary bit lines BLB.

[0057] In particular, there is also a global transmission line YIO<7:0> in the memory 10; during the data writing process, the first data DATA<7:0> is transmitted one-to-one to the corresponding sensitive amplifier SA by different global transmission lines YIO<7:0>, and then the sensitive amplifier SA writes the received data into the corresponding storage unit through signal amplification processing.

[0058] For example, the first data DATA<0:7>=ABCDEFGH to be written is taken as an example. In some embodiments, since there are specific requirements for the relationship between the final data written into the storage unit and the initial data initially input into the global transmission line YIO<7:0>, the transmission process of part of the data is controlled so that part of the first data DATA<7:0> is flipped before being transmitted to the bit line BL.

[0059] Specifically, (1) for the even storage unit 11_e, see Figure 2 In (a), the first data DATA<0:3> is transmitted via the global transmission line YIO<0:3> to generate the corresponding second data IOe<0:3>, and the first data DATA<0:3> and the second data IOe<0:3> are identical in one-to-one correspondence; the first data DATA<4:7> is transmitted via the global transmission line YIO<4:7> to generate the corresponding second data IOo<0:3>, and the first data DATA<4:7> and the second data IOo<0:3> are opposite in one-to-one correspondence.

[0060] That is to say, the second data IOe<0:3>=ABCD, the second data IOo<0:3>=E'F'G'H' (' represents inversion); further, the second data IOe<0:3> is written via BLA<0:3>, and the second data IOo<0:3> is written via BLB<4:7>; as mentioned above, the second data IOo<0:3> written via the complementary bit line BLB will change into inverted data, and therefore, the target data DataF<0:7> finally written=ABCDGHEF.

[0061] In some embodiments, 100 <0> Via BLB <6> Write, IO <1> Via BLB <7> Write, IO <2> Via BLB <4> Write, IO <3> Via BLB <5> The target data DataF<4:5> finally written corresponds to the first data DATA<6:7>, and the target data DataF<6:7> corresponds to the first data DATA<4:5>; in other embodiments, IOo <0> Via BLB <4> Write, IO <1> Via BLB <5> Write, IO <2> Via BLB <6> Write, IO <3> Via BLB <7> The target data DataF<4:5> finally written corresponds to the first data DATA<4:5>, and the target data DataF<6:7> corresponds to the first data DATA<6:7>.

[0062] (2) For odd storage unit 11_o, see Figure 2(b) is similar to the above. After the first data DATA<0:3> is transmitted via the global transmission line YIO<0:3>, the corresponding second data IOe<0:3> is generated. After the first data DATA<4:7> is transmitted via the global transmission line YIO<4:7>, the corresponding second data IOo<0:3> is generated. The second data IOe<0:3>=ABCD, IOo<0:3>=E'F'G'H'; however, the second data IOe<0:3> is written via BLB<0:3>, and the second data IOo<0:3> is written via BLA<4:7>; as mentioned above, the data written via the complementary bit line BLB will actually change to inverted data. Therefore, the target data DataF<0:7> finally written is=A'B'C'D'G'H'E'F'. In some other embodiments, by adjusting the correspondence between the global transmission line YIO and the local transmission line IO, the target data DataF<0:7> to be written finally may be equal to A'B'C'D'G'H'E'F'.

[0063] In some embodiments, the number of word lines included in the odd storage unit and the even storage unit may be the same or different.

[0064] It can be seen from the above that for the same test data, the data finally written into the odd storage unit 11_o and the data finally written into the even storage unit 11_e are opposite, which brings some problems to the test process of the memory 10.

[0065] See also Figure 3 , which shows a schematic diagram of the structure of another memory 10 provided in an embodiment of the present disclosure. Figure 3 As shown, the memory 10 further includes a built-in self-test module 12, and the built-in self-test module 12 includes:

[0066] The address module 121 is configured to receive a row address signal and decode the row address signal, and output a position indication signal; wherein the row address signal is used to select a target word line, and the position indication signal indicates that the target word line is located in the odd storage part 11_o or the even storage part 11_e;

[0067] The data module 122 is connected to the address module 121 and is configured to receive the initial test data and the position indication signal, and output the initial test data or the inverted data of the initial test data as the target test data according to the position indication signal, and the target test data is used to write the target word line. More specifically, the target test data is used to write the storage unit on the target word line.

[0068] It should be noted that the built-in self-test module 10 can be applied to various types of memories 10, such as DRAM, SDRAM, DDR, LPDDR, etc.

[0069] It should be understood that the inverted data of data 0 is data 1, and the inverted data of data 1 is data 0.

[0070] In this way, during the built-in self-test process, the data used when writing to the odd storage unit 11_o and the data used when writing to the even storage unit 11_e are inverted data of each other, so that the data finally written to the odd storage unit 11_o and the data finally written to the even storage are exactly the same, which can more accurately control the data stored in each storage unit and the data environment in which it is located, thereby improving the test effect.

[0071] In some embodiments, the address module 121 is specifically configured to output a position indication signal of a first state if the target word line is located in the odd storage unit 11_o; and output a position indication signal of a second state if the target word line is located in the even storage unit 11_e;

[0072] The data module 122 is specifically configured to output the initial test data as target test data if the position indication signal is in the second state; if the position indication signal is in the first state, invert the initial test data to generate inverted data of the initial test data, and output the inverted data of the initial test data as target test data.

[0073] It should be noted that the first state and the second state are different, the first state is a high level, and the second state is a low level; or, the first state is a low level, and the second state is a high level.

[0074] Thus, during the built-in self-test process, for the odd storage unit 11_o, a write operation is performed based on the initial test data; for the even storage unit 11_e, a write operation is performed based on the inverted data of the initial test data to ensure that the data written into the storage cells at the same position in each storage unit are the same.

[0075] In one case, the initial test data can be understood as the aforementioned first data DATA<7:0>, and the aforementioned writing process is still taken as an example: it is assumed that the first data DATA<7:0>=ABCDEFGH.

[0076] Specifically, (1) for the even storage unit 11_e, see Figure 4 (a) in the figure is the same as stated above, and the target data finally written is DataF<0:7>=ABCDGHEF.

[0077] (2) For odd storage unit 11_o, see Figure 4In (b), it is necessary to write according to the inverted data DATA'<7:0>=A'B'C'D'E'F'G'H' of the first data. After being transmitted via the global transmission line YIO, the second data IOe<0:3>=A'B'C'D', the second data IOo<0:3>=GHEF. At the same time, since the second data IOe<0:3> is written via the complementary bit line BLB<0:3>, the target data DataF<0:7> actually written is finally ABCDGHEF.

[0078] That is, the data actually written into the odd storage unit 11_o and the even storage unit 11_e are completely the same.

[0079] In another case, the initial test data can also be understood as the aforementioned second data IOe<0:3> and IOo<0:3>. Still taking the aforementioned writing process as an example: assuming that the written data DATA<0:7>=ABCDEFGH.

[0080] Specifically, (1) for the even storage unit 11_e, as described above, the target data finally written is DataF<0:7>=ABCDGHEF.

[0081] (2) For the odd storage unit 11_o, due to the existence of the data module 122, after being transmitted via the global transmission line YIO, the second data IOe<0:3>=ABCD, and the second data IOo<0:3>=E'F'G'H'. At this time, the data module 122 will flip the second data to obtain the flipped second data IOe<0:3>=A'B'C'D', and the flipped second data IOo<0:3>=GHEF, and then use the flipped second data for writing. At the same time, since the second data IOe<0:3> is written via the complementary bit line BLB<0:3>, the target data DataF<0:7> that is actually written is finally ABCDGHEF.

[0082] That is, the data actually written into the odd storage unit 11_o and the even storage unit 11_e are completely the same.

[0083] In some embodiments, every N consecutive storage units along the first direction are divided into a storage domain; N is an odd number. Please refer to Table 1 below, which takes 36 storage units and N=9 as an example for explanation. As shown in Table 1, the 0th storage unit to the 8th storage unit belong to the 0th storage domain, the 9th storage unit to the 17th storage unit belong to the 1st storage domain, the 18th storage unit to the 26th storage unit belong to the 2nd storage domain, and the 27th storage unit to the 35th storage unit belong to the 3rd storage domain. At the same time, from another perspective, for each storage domain, the storage units therein are numbered starting from 0, that is, the 9th storage unit in the overall numbering is also the 0th storage unit of the 1st storage domain.

[0084] In this case, since the odd storage unit 11_o and the even storage unit 11_e are arranged crosswise, and each storage domain includes an odd number of storage units. Therefore, the 0th / 2nd / 4th / 6th / 8th storage unit in the 0th storage domain is the even storage unit 11_e, the 1st / 3rd / 5th / 7th storage unit in the 0th storage domain is the odd storage unit 11_o, the 0th / 2nd / 4th / 6th / 8th storage unit in the 1st storage domain is the odd storage unit 11_o, the 1st / 3rd / 5th / 7th storage unit in the 1st storage domain is the even storage unit 11_e... That is, the even-numbered storage unit in the even-numbered storage domain and the odd-numbered storage unit in the odd-numbered storage domain are all even storage units 11_e, and the odd-numbered storage unit in the even-numbered storage domain and the even-numbered storage unit in the odd-numbered storage domain are odd storage units 11_o. In addition, the storage domain numbering also starts with 0.

[0085] Table 1

[0086]

[0087]

[0088] Accordingly, the row address signal includes a first address signal group and a second address signal, see Figure 5 , the address module 121 includes:

[0089] A first decoding module 21 is configured to receive a first address signal group, decode the first address signal group, and generate a positioning signal, wherein the positioning signal represents a position of a storage portion corresponding to a target word line in a storage domain;

[0090] The second decoding module 22 is connected to the first decoding module 21 and is configured to receive a second address signal and a positioning signal, perform a logic operation on the second address signal and the positioning signal, and generate a position indication signal; the second address signal represents the parity of the storage domain number to which the target word line belongs.

[0091] Here, the positioning signal may be a multi-bit signal, in which case the positioning signal may indicate the specific position number of the storage unit corresponding to the target word line in the storage domain. Alternatively, the positioning signal may be a single-bit signal, indicating only the parity of the position number of the storage unit corresponding to the target word line in the storage domain.

[0092] In this way, the position information of the selected storage unit in its storage domain (i.e., the positioning signal) and the position information of the selected storage domain (i.e., the second address signal) are used together to calculate a position indication signal, thereby determining whether the data module 122 needs to flip the initial test data.

[0093] In some implementations, the positioning signal includes N positioning sub-signals, and the i-th positioning sub-signal indicates whether the target word line is located in the i-th storage portion of one of the storage domains.

[0094] The following is a specific example: See Table 1 and Figure 6 The initial address signal generated during the built-in self-test process can be expressed as BistRA. BistRA has many bit sub-signals. The embodiment of the present disclosure only involves BistRA<13:0>. Please refer to Figure 6 , wherein the first address signal group BistRA<12:0> is passed through the first decoding module 21 to generate the positioning signal Sec<8:0>, and at this time, at most one positioning sub-signal in the positioning signal Sec<8:0> is in the enabled state, and the rest of the positioning sub-signals are in the disabled state. In simple terms, if the positioning sub-signal Sec <0> In the enabled state, it indicates that the storage unit corresponding to the target word line is located in the first storage domain of a storage unit (ie, storage unit 0 in a storage domain); if the positioning sub-signal Sec <1> In the enabled state, it indicates that the storage unit corresponding to the target word line is located in the second storage domain of a certain storage unit (that is, storage unit 1 in a certain storage domain)...

[0095] like Figure 6 As shown, the second decoding module 22 includes an even decoding unit 221, an odd decoding unit 222 and an operator 223. Among them:

[0096] The even decoding unit 221 is configured to decode the even-bit localizer signal (e.g. Figure 6 Sec <0> Sec <2> Sec <4> Sec <6> Sec <8> ) and a second address signal (eg Figure 6 BistRA13 in the memory domain performs a logic operation; if the operation result indicates that the target word line is located in an even-numbered storage portion in an odd-numbered storage domain, an even indication signal of a third state is output; if the operation result indicates that the target word line is not located in an even-numbered storage portion in an odd-numbered storage domain, an even indication signal of a fourth state is output;

[0097] The odd decoding unit 222 is configured to decode the odd-numbered bits of the localization sub-signal (e.g. Figure 6 Sec <1> Sec <3> Sec <5> Sec <7> ) and the inverted signal of the second address signal (eg Figure 6 If the result of the operation indicates that the target word line is located in the odd-numbered storage part in the even-numbered storage domain, an odd indication signal of the fifth state is output; if the result of the operation indicates that the target word line is not located in the odd-numbered storage part in the even-numbered storage domain, an odd indication signal of the sixth state is output;

[0098] The operator 223 is connected to the odd decoding unit 222 and the even decoding unit 221, and is configured to output a position indication signal of the second state if the even indication signal is in the third state or the odd indication signal is in the fifth state; if the even indication signal is in the fourth state and the odd indication signal is in the sixth state, output a position indication signal of the first state.

[0099] In some embodiments, Figure 6 As shown, the odd decoding unit 222 includes a first decoding unit 33 and a second decoding unit 34;

[0100] The first decoding unit 33 is configured to perform a logic operation on the stator bit signal of the odd bit and output a first intermediate signal; wherein the first intermediate signal indicates whether the target word line is located in an odd-numbered storage part in one of the storage domains;

[0101] The second decoding unit 34 is connected to the first decoding unit 33, and is configured to perform logic processing on the first intermediate signal and the inverted signal BistRA13N of the second address signal, and output an odd indication signal.

[0102] In some embodiments, the even decoding unit 221 includes a third decoding unit 31 and a fourth decoding unit 32;

[0103] The third decoding unit 31 is configured to perform a logic operation on the even-numbered positioning sub-signal and output a second intermediate signal; wherein the second intermediate signal indicates whether the target word line is located in an even-numbered storage part in one of the storage domains;

[0104] The fourth decoding unit 32 is connected to the third decoding unit 31, and is configured to perform logic processing on the second intermediate signal and the second address signal BistRA13, and output an even indication signal.

[0105] A specific setting scenario is provided below: the enable state, the first state, the fourth state, and the sixth state of the positioning sub-signal are all high levels, the disable state, the second state, the third state, and the fifth state of the positioning sub-signal are all low levels, and when the second address signal is high, it indicates that the storage domain number corresponding to the target word line is odd, and when the second address signal is low, it indicates that the storage domain number corresponding to the target word line is even. In addition to the position indication signal SecOdd, a complementary position indication signal SecEven is also provided, and the levels of the complementary position indication signal SecEven and the position indication signal SecOdd are opposite.

[0106] Only for the above state definition, such as Figure 6 As shown, for the even decoding unit 221, the first decoding unit 31 includes a first NOR gate 301, a second NOR gate 302 and a first NAND gate 303, the second decoding unit 32 includes a second NAND gate, the third decoding unit 33 includes a third NOR gate 304, a fourth NOR gate 305 and a third NAND gate 306, and the fourth decoding unit 34 includes a fourth NAND gate; the operator 223 includes a fifth NAND gate and a NOT gate. Its working principle is as follows:

[0107] (1) Assume that the target word line is located in the 0th storage unit (i.e., the even storage unit) in storage domain 0. <0> =1, BistRA13=0; further, the first NOR gate 301 outputs a low level, the second NOR gate 302 to the fourth NOR gate 305 all output a high level, the first NAND gate 303 outputs a high level, the even indication signal output by the second NAND gate is a high level (fourth state), the third NAND gate 306 outputs a low level, and the odd indication signal output by the second NAND gate is a high level (sixth state), so that the position indication signal SecOdd is a low level (i.e., the second state), and the complementary position indication signal SecEven is a high level, so there is no need to flip the initial test data;

[0108] (2) Assume that the target word line is located in the 0th storage unit (i.e., the odd storage unit) in storage domain 1. <0> =1, BistRA13=1; further, the first NOR gate 301 outputs a low level, the second NOR gate 302 to the fourth NOR gate 305 all output a high level, the first NAND gate 303 outputs a high level, the even indication signal output by the second NAND gate is a low level (the third state), the third NAND gate 306 outputs a low level, and the odd indication signal output by the second NAND gate is a high level (the sixth state), so that the position indication signal SecOdd is a high level (i.e., the first state), and the complementary position indication signal SecEven is a low level, so the initial test data needs to be flipped.

[0109] Please adapt to other situations.

[0110] In addition, if the definition of the above states changes, the specific components of the even decoding unit 221, the odd decoding unit 222 and the operator 223 can be adaptively adjusted.

[0111] In some other embodiments, every N storage parts arranged adjacently along the first direction are divided into a storage domain; when N is an even number, the address module 121 includes:

[0112] A third decoding module is configured to receive the first address signal group, decode the first address signal group, and generate a positioning signal, wherein the positioning signal represents a position of the storage portion corresponding to the target word line in the storage domain;

[0113] The fourth decoding module is configured to receive a positioning signal, and generate the position indication signal based on the positioning signal.

[0114] In this case, since each storage domain includes an even number of storage units, no matter it is an odd numbered storage domain or an even numbered storage domain, the 0th / 2nd / 4th / 6th / 8th storage units are all even storage units 11_e, and the 1st / 3rd / 5th / 7th storage units are all odd storage units 11_o. In this way, no matter it is an even numbered storage domain or an odd numbered storage domain, the even numbered storage units therein are all even storage units 11_e, and the odd numbered storage units therein are all odd storage units 11_o. Based on this, it is only necessary to determine the position of the storage unit corresponding to the target word line in the storage domain to obtain the position indication signal.

[0115] In a specific embodiment, see Figure 7 , the data module 122 includes a tri-state transmission gate 401, a tri-state inverter 402 and an inverter 403;

[0116] For the three-state transmission gate 401 and the three-state inverter 402, their input ends are used to receive the initial test data Data, their output ends are connected to the input end of the inverter 403, and their control ends receive the position indication signal; the inverter 403 is used to output the target test data BistData; wherein, the three-state transmission gate 401 is enabled based on the position indication signal of the first state, and the three-state inverter 402 is enabled based on the position indication signal of the second state.

[0117] In this way, if the position indication signal is in the first state, the three-state transmission gate 401 outputs the initial data signal Data, and the three-state inverter 402 shields the input terminal signal; the inverter 403 inverts the initial data signal Data obtained from the three-state transmission gate 401, thereby outputting the inverted data of the initial data signal Data as the target test data BistData; on the contrary, if the position indication signal is in the second state, the three-state transmission gate 401 shields the input terminal signal, and the three-state inverter 402 inverts the initial data signal Data and outputs it; the inverter 403 inverts the inverted data of the initial data signal Data obtained from the three-state inverter 402 again, thereby outputting the initial data signal Data as the target test data BistData.

[0118] In particular, such as Figure 7 As shown, the complementary position indication signal SecEven and the position indication signal SecOdd jointly achieve the control effect. In some embodiments, the position indication signal SecOdd and the complementary position indication signal SecEven can be used as power switch signals of the tri-state transmission gate 401 and the tri-state inverter 402, so that the tri-state transmission gate 401 and the tri-state inverter 402 are connected to the corresponding power signal, thereby controlling them to achieve their corresponding functions.

[0119] In simple terms, during the built-in self-test process, external commands can be considered invalid and cannot enter the circuit to participate in the work. The built-in self-test relies on the internal oscillation clock signal to decode the internal command, transfer the test data to the storage array, and implement the test of different types of test data. In particular, during the test phase of the aging test (Burn In), since the purpose of the test is to perform a stress test on the weak storage unit for repeated reading and writing (i.e., stress weak cell), it is hoped that all the data written will point to the actual physical location, and the written address is the same, so that the actual read and write data location can be clearly defined. However, due to the influence of the SA structure, the data written to the odd storage unit and the even storage unit are opposite. The built-in self-test module provided by the embodiment of the present disclosure can process this part of the opposite data so that the actual data written is the desired test data, thereby improving the accuracy of the test.

[0120] In another embodiment of the present disclosure, a built-in self-test method is provided. The built-in self-test method is applied to Figure 1 and Figure 2The memory 10 shown in the figure comprises a plurality of storage units arranged along a first direction, a sensitive amplifier is provided between adjacent storage units, the plurality of storage units are odd storage units and even storage units alternately arranged in the first direction, the odd bit line of the odd storage unit is connected to the sensitive amplifier adjacent to the first side, and the even bit line is connected to the sensitive amplifier adjacent to the second side; the odd bit line of the even storage unit is connected to the sensitive amplifier adjacent to the second side, and the even bit line is connected to the sensitive amplifier adjacent to the first side.

[0121] See also Figure 8 , which shows a flow chart of a built-in self-test method provided by an embodiment of the present disclosure. Figure 8 The method comprises:

[0122] S501: Receive a row address signal and decode the row address signal, and output a position indication signal; wherein the row address signal is used to select a target word line, and the position indication signal indicates whether the target word line is located in an odd storage unit or an even storage unit.

[0123] S502: receiving initial test data, and outputting the initial test data or inverted data of the initial test data as target test data according to a position indication signal, and the target test data is used to write into a target word line.

[0124] In some embodiments, step S501 specifically includes: if the target word line is located in the odd storage unit, outputting a position indication signal of a first state; if the target word line is located in the even storage unit, outputting a position indication signal of a second state.

[0125] Correspondingly, step S502 specifically includes: if the position indication signal is in the second state, the initial test data is output as the target test data; if the position indication signal is in the first state, the initial test data is inverted to generate the inverted data of the initial test data, and the inverted data of the initial test data is output as the target test data.

[0126] In some embodiments, every N consecutive storage sections along the first direction are divided into a storage domain; N is an odd number; the row address signal includes a first address signal group and a second address signal, and the receiving and decoding of the row address signal and the outputting of the position indication signal include:

[0127] The first address signal group is decoded to generate a positioning signal, which represents the position of the storage unit corresponding to the target word line in the storage domain; a logical operation is performed on the second address signal and the positioning signal to generate a position indication signal; the second address signal represents the parity of the storage domain number to which the target word line belongs.

[0128] In some other embodiments, when N is an even number, the receiving the row address signal and decoding the row address signal, and outputting the position indication signal, includes:

[0129] The first address signal group is decoded to generate a positioning signal, wherein the positioning signal represents the position of the storage portion corresponding to the target word line in the storage domain; a logical operation is performed on the positioning signal to generate a position indication signal.

[0130] In another embodiment of the present disclosure, see Fig. 9 , which shows an electronic device 60 provided by an embodiment of the present disclosure, and the electronic device 60 at least includes the aforementioned memory 10.

[0131] The above are only preferred embodiments of the present disclosure and are not intended to limit the scope of protection of the present disclosure. It should be noted that in the present disclosure, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such a process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes one..." does not exclude the presence of other identical elements in the process, method, article or device including the element. The above serial numbers of the embodiments of the present disclosure are only for description and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments. The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A memory, characterized in that: The invention comprises a plurality of storage parts arranged along a first direction, a sense amplifier is arranged between adjacent storage parts, the plurality of storage parts are odd storage parts and even storage parts arranged alternately in the first direction, an odd bit line of the odd storage part is connected to the sense amplifier adjacent to the first side, and an even bit line of the odd storage part is connected to the sense amplifier adjacent to the second side; an odd bit line of the even storage part is connected to the sense amplifier adjacent to the second side, and an even bit line of the even storage part is connected to the sense amplifier adjacent to the first side; The memory also includes a built-in self-test module, the built-in self-test module including: An address module is configured to receive a row address signal and decode the row address signal to output a position indication signal; wherein the row address signal is used to select a target word line, and the position indication signal indicates that the target word line is located in the odd storage part or the even storage part; The data module is connected to the address module and is configured to receive initial test data and the position indication signal, and output the initial test data or the inverted data of the initial test data as target test data according to the position indication signal, and the target test data is used to write the target word line.

2. The memory according to claim 1, characterized in that: The address module is specifically configured to output the position indication signal of a first state if the target word line is located in the odd storage part; and output the position indication signal of a second state if the target word line is located in the even storage part; The data module is specifically configured to output the initial test data as the target test data if the position indication signal is in the second state; and to invert the initial test data to generate inverted data of the initial test data, and output the inverted data of the initial test data as the target test data if the position indication signal is in the first state.

3. The memory according to claim 1, characterized in that: Every N consecutive storage parts along the first direction are divided into a storage domain; N is an odd number; the row address signal includes a first address signal group and a second address signal, and the address module includes: A first decoding module is configured to receive a first address signal group, decode the first address signal group, and generate a positioning signal, wherein the positioning signal represents a position of the storage portion corresponding to the target word line in the storage domain; The second decoding module is configured to receive a second address signal and the positioning signal, perform a logic operation on the second address signal and the positioning signal, and generate the position indication signal; the second address signal represents the parity of the storage domain number to which the target word line belongs.

4. The memory according to claim 3, characterized in that: When N is an even number, the address module includes: A third decoding module is configured to receive the first address signal group, decode the first address signal group, and generate the positioning signal, wherein the positioning signal represents the position of the storage part corresponding to the target word line in the storage domain; The fourth decoding module is configured to receive a positioning signal and generate the position indication signal based on the positioning signal.

5. The memory according to claim 3, characterized in that: The positioning signal includes N positioning sub-signals, and the i-th positioning sub-signal indicates whether the target word line is located in the i-th storage part of one of the storage domains; The second decoding module includes an even decoding unit, an odd decoding unit and an operator; The even decoding unit is configured to perform a logic operation on the even-numbered bit of the locator signal and the second address signal; if the operation result indicates that the target word line is located in the even-numbered storage part in the odd-numbered storage domain, then output an even indication signal of a third state; if the operation result indicates that the target word line is not located in the even-numbered storage part in the odd-numbered storage domain, then output an even indication signal of a fourth state; The odd decoding unit is configured to perform a logic operation on the odd-numbered bit of the locator signal and the inverted signal of the second address signal; if the operation result indicates that the target word line is located in the odd-numbered storage part in the even-numbered storage domain, then output an odd indication signal of a fifth state; if the operation result indicates that the target word line is not located in the odd-numbered storage part in the even-numbered storage domain, then output an odd indication signal of a sixth state; The operator is connected to the odd decoding unit and the even decoding unit, and is configured to output the position indication signal of the first state if the even indication signal is in the third state or the odd indication signal is in the fifth state; and to output the position indication signal of the second state if the even indication signal is in the fourth state and the odd indication signal is in the sixth state.

6. The memory according to claim 5, characterized in that: The odd decoding unit includes a first decoding unit and a second decoding unit; The first decoding unit is configured to perform a logic operation on the odd-numbered bits of the positioning sub-signal and output a first intermediate signal; wherein the first intermediate signal indicates whether the target word line is located in the odd-numbered storage part in one of the storage domains; The second decoding unit is connected to the first decoding unit, and is configured to perform logic processing on the first intermediate signal and the inverted signal of the second address signal, and output the odd indication signal.

7. The memory according to claim 5, characterized in that: The even decoding unit includes a third decoding unit and a fourth decoding unit; The third decoding unit is configured to perform a logic operation on the even-numbered bits of the positioning sub-signal and output a second intermediate signal; wherein the second intermediate signal indicates whether the target word line is located in the even-numbered storage section in one of the storage domains; The fourth decoding unit is connected to the third decoding unit, and is configured to perform logic processing on the second intermediate signal and the second address signal, and output the even indication signal.

8. The memory according to claim 1, characterized in that: The data module includes a tri-state transmission gate, a tri-state inverter and an inverter; For the three-state transmission gate and the three-state inverter, their input ends are used to receive the initial test data, their output ends are connected to the input end of the inverter, and their control ends receive the position indication signal; the inverter is used to output the target test data; wherein, the three-state transmission gate is enabled based on the position indication signal in the first state, and the three-state inverter is enabled based on the position indication signal in the second state.

9. A built-in self-test method, characterized in that: Applied to a memory, the memory comprises a plurality of storage parts arranged along a first direction, a sense amplifier is arranged between adjacent storage parts, the plurality of storage parts are odd storage parts and even storage parts alternately arranged in the first direction, an odd bit line of the odd storage part is connected to the sense amplifier adjacent to the first side, and an even bit line is connected to the sense amplifier adjacent to the second side; an odd bit line of the even storage part is connected to the sense amplifier adjacent to the second side, and an even bit line is connected to the sense amplifier adjacent to the first side; the method comprises: receiving a row address signal and decoding the row address signal, and outputting a position indication signal; wherein the row address signal is used to select a target word line, and the position indication signal indicates that the target word line is located in the odd storage part or the even storage part; Initial test data is received, and according to the position indication signal, the initial test data or inverted data of the initial test data is output as target test data, and the target test data is used to write into the target word line.

10. An electronic device, characterized in that: The electronic device comprises the memory according to any one of claims 1-8.

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