Message forwarding systems, devices and clusters

Abstract

The present application provides a message forwarding system, device and cluster. The system includes: a host, including a kernel space and a user space, the user space runs a data plane development kit and an open virtual switch, a network card, including a first port, a second port and a third port, the first port and the second port form a logically single port, the first port includes a first queue and a second queue, there is an address mapping relationship between the first queue and the third queue of the kernel space, the first queue and the third queue are used to transmit control messages of the link aggregation port between the network card and the kernel space, there is an address mapping relationship between the second queue and the fourth queue in the data plane development kit, the link aggregation port is used to transmit the data message to the fourth queue in the data plane development kit through the second queue after receiving the data message; the data plane development kit is used to send the data message to the third port of the network card with the assistance of the open virtual switch.

Description

Technical Field

[0001] The present application relates to the computer field, and in particular to a message forwarding system, device and cluster. Background Art

[0002] Link aggregation refers to the aggregation of multiple physical ports to form a logical port, i.e., a link aggregation port, to achieve load sharing of inbound / outbound traffic throughput among member ports. Link aggregation is an important technology in increasing link bandwidth, achieving link transmission elasticity and engineering redundancy. The main purpose of link aggregation is to improve network bandwidth and reliability. By bundling multiple physical links together to form a logical link, the bandwidth can be significantly increased. Theoretically, the maximum bandwidth is the sum of the member bandwidths, which effectively increases the bandwidth. In addition, link aggregation also improves the reliability of the link through the backup link mechanism. When a physical link fails or is disconnected, the data can be automatically switched to other normally functioning links to ensure the normal operation of the network.

[0003] However, currently link aggregation ports are all created in the kernel space. Therefore, data packets involving link aggregation ports must be processed through the kernel space. Therefore, one data packet forwarding requires two copies, and these two copies require switching between the user space and the kernel space, resulting in a lot of performance waste. Summary of the invention

[0004] The present application provides a message forwarding system, device and cluster, which can bypass the kernel space to forward data messages involving link aggregation ports, thereby avoiding performance waste.

[0005] In a first aspect, a message forwarding system is provided, including:

[0006] A host, including a kernel space and a user space, wherein the user space runs a data plane development kit and an open virtual switch,

[0007] A network card, comprising a first port, a second port and a third port, wherein the first port and the second port form a logically single link aggregation port through link aggregation, the first port comprises a first queue and a second queue, wherein an address mapping relationship exists between the first queue and the third queue of the kernel space, the first queue and the third queue are used to transmit control messages of the link aggregation port between the network card and the kernel space, and an address mapping relationship exists between the second queue and a fourth queue in the data plane development kit,

[0008] The link aggregation port is used to transmit the data message to the fourth queue in the data plane development kit through the second queue after receiving the data message;

[0009] The data plane development kit is used to determine, with the assistance of the open virtual switch, that the third port is the egress port of the data message, and send the data message to the third port of the network card.

[0010] In the above scheme, the forwarding of data packets on the link aggregation port is all performed in the user space, which can effectively avoid frequent switching between the kernel space and the user space, resulting in waste of resources.

[0011] In some possible designs, the first port and the third port are managed by the open virtual switch.

[0012] The kernel space is used to reserve the first queue of the first port and release the second queue of the first port to the open virtual switch for management after determining that the first port is managed by the open virtual switch.

[0013] In some possible designs, the first port is used to transmit the first data packet to a fourth queue in the data plane development kit through the second queue after receiving the first data packet; or,

[0014] The second port is used to transmit the second data packet to the fourth queue in the data plane development kit through the second queue after receiving the second data packet.

[0015] In some possible designs, the kernel space is used to create the link aggregation port and save information of the link aggregation port, wherein the information of the link aggregation port includes members of the link aggregation port.

[0016] In some possible designs, the data plane development kit is used to periodically obtain the information of the link aggregation port from the kernel space.

[0017] In the above solution, the data plane development kit periodically obtains changes in the link aggregation port from the kernel space, thereby preventing the change in the link aggregation port from causing problems in the data plane development kit's processing of data packets.

[0018] In some possible designs, the data plane development kit is used to determine that the first port belongs to the link aggregation port based on the information of the link aggregation port, replace the source port of the extended header of the data packet with the link aggregation port, and send the replaced data packet to the open virtual switch.

[0019] In some possible designs, the data plane development kit is used to copy the first address resolution protocol message to obtain a second address resolution protocol message when the data message is a first address resolution protocol message, and save the second address resolution protocol message into a huge page of the data plane development kit.

[0020] In the above solution, the replication of the address resolution protocol message occurs in the data plane development kit. The data plane development kit uses huge pages, which can effectively reduce the occurrence of memory fragmentation.

[0021] In some possible designs, the data plane development kit is used to send the data message to the open virtual switch;

[0022] The open virtual switch is used to determine that the egress port of the data message is the third port, and send the data message to the data plane development kit;

[0023] The data plane development kit is used to send the data message to the third port of the network card.

[0024] In a second aspect, a computing device is provided, including a message forwarding system and a storage unit, wherein the message forwarding system and the storage unit can communicate with each other, and the message forwarding system is a system as described in any one of the first aspects.

[0025] In a third aspect, a computing device cluster is provided, comprising a plurality of computing devices, at least one computing device comprising a message forwarding system and a storage unit, the message forwarding system and the storage unit being able to communicate with each other, and the message forwarding system being a system as described in any one of the first aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the background technology, the drawings required for use in the embodiments of the present invention or the background technology will be described below.

[0027] Figure 1 It is a structural diagram of a software defined network (SDN) provided in this application;

[0028] Figure 2 It is a structural diagram of a message forwarding system provided by the present application;

[0029] Figure 3 It is a structural schematic diagram of a message forwarding system provided by the prior art;

[0030] Figure 4 It is a structural schematic diagram of a computing device provided by this application. DETAILED DESCRIPTION

[0031] The embodiments of the present invention are described below in conjunction with the accompanying drawings in the embodiments of the present invention. The terms used in the implementation mode of the present invention are only used to explain the specific embodiments of the present invention, and are not intended to limit the present invention.

[0032] See also Figure 1 , Figure 1 This is a schematic diagram of the structure of a software-defined network provided by this application. Figure 1 As shown, the software defined network of the present application includes: an SDN controller 110 and an open virtual switch (open vSwitch, OVS) 120.

[0033] The SDN controller 110 is a core component in the SDN architecture, which is responsible for the centralized management and control of the entire network. The SDN controller separates the control plane of the network from the data plane, thereby providing a more flexible, programmable and scalable network management method. The main functions of the SDN controller include: managing the control plane of the entire network, including topology discovery, route calculation, flow table delivery, etc. Specifically, the SDN controller 110 collects the topology information of the network by communicating with OVS120, calculates the route according to the application requirements, and then delivers the flow table to OVS120. Secondly, the SDN controller 110 can dynamically adjust the network routing and traffic distribution according to the characteristics and requirements of the traffic, thereby achieving load balancing, congestion control and service quality assurance of the traffic; it can implement security measures such as access control, traffic filtering and intrusion detection, and respond to network security events in a timely manner to protect the network from malicious attacks and data leakage threats, etc. The SDN controller 110 can be a physical device or a virtual device. When the number of SDN controllers 110 is multiple, physical devices and virtual devices can also be used in combination. The SDN controller 110 can run in physical servers, virtual machines, containers, cloud platforms, and bare metal servers.

[0034] OVS120 is an open source virtual switch software that implements a flexible, programmable and scalable switch platform for communicating with the SDN controller through the OpenFlow protocol, receiving the flow table issued by the SDN controller 110, and implementing traffic forwarding and routing according to the flow table. OVS120 supports packet switching and routing in Layer 2 and Layer 3 networks, so OVS120 supports the processing of Ethernet data frames and data packets, etc. OVS120 can run on physical servers, virtual machines, containers, cloud platforms, and bare metal servers. OVS120 can also be used in combination with physical switches, etc.

[0035] The SDN controller 110 and OVS120 can both be set in a container. In this case, the SDN controller 110 and OVS120 can be concentrated in the same container or distributed in different containers. The SDN controller 110 and OVS120 can both be set in a virtual machine. In this case, the SDN controller 110 and OVS120 can be concentrated in the same virtual machine or distributed in different virtual machines. The SDN controller 110 and OVS120 can both be set in a server. In this case, the SDN controller 110 and OVS120 can be concentrated in the same server or distributed in different servers. The SDN controller 110 and OVS120 can both be set in a bare metal server. In this case, the SDN controller 110 and OVS120 can be concentrated in the same bare metal server or distributed in different bare metal servers. Alternatively, the SDN controller 110 is set in a container, and OVS120 is set in any one of a virtual machine, a server, and a bare metal server. The SDN controller 110 is set in the virtual machine, and the OVS 120 is set in any one of the container, the server, and the bare metal server. The SDN controller 110 is set in the server, and the OVS 120 is set in any one of the container, the virtual machine, and the bare metal server. The SDN controller 110 is set in the bare metal server, and the OVS 120 is set in any one of the container, the virtual machine, and the server.

[0036] The above-mentioned OVS120 is usually virtualized using computing resources (eg, processor), storage resources, and network resources (eg, network card) of a computing device.

[0037] In the above example, the controller is an SDN controller and the forwarding device is OVS. In actual applications, the controller can also be other open source controllers such as OpenStack, Kubernetes, etc. In addition, the controller can also be a privately developed controller, and the forwarding device can also be other privately developed forwarding devices, etc., which are not specifically limited here.

[0038] See also Figure 2 , Figure 2 This is a schematic diagram of the structure of a message forwarding system provided by this application. Figure 2 As shown, the message forwarding system of the present application includes: a host 210 and a network card 220.

[0039] The host 210 includes a kernel space 211 and a user space 212. The kernel space and the user space are two different operating environments in the operating system, and have different permissions and functions.

[0040] The kernel space has the highest permissions and can access all system resources, including hardware, memory, etc. The kernel space can run the kernel code of the operating system and is responsible for the core functions of the system, such as process management, memory management, device drivers, network protocol stack, etc. The code execution of the kernel space is protected to ensure the stability and security of the system. The permissions of the user space are limited and can only access some restricted resources. The user space runs user programs and applications, such as office software, games, browsers, etc. The programs in the user space request higher-privilege operations from the kernel through system calls (SystemCall). The kernel space is used to create link aggregation ports and save the information of link aggregation ports, where the information of link aggregation ports includes the members of the link aggregation ports.

[0041] The user space 212 runs the above-mentioned OVS. In order to improve the forwarding performance of OVS, it is often necessary to set up a data plane development kit (Data Plane Development Kit, DPDK). DPDK is a set of libraries and drivers for fast packet processing. It bypasses the kernel protocol stack and directly processes packets in the user space, thereby improving data processing performance.

[0042] The network card (NIC) 220, also known as a network adapter, is used to connect the host to the network. The main functions of the network card include: converting the data generated by the host into network signals and sending them out, and converting the received network signals into data recognizable by the host. The network card 220 has a unique physical address (MAC address) for identifying the network card in the network. The network card 220 supports various network protocols, such as Ethernet protocol. There are many types of network cards, including wired network cards (such as Ethernet network cards) and wireless network cards (such as Wi-Fi network cards). The network card includes a first port, a second port and a third port. The first port and the second port form a logically single link aggregation port through link aggregation. Link aggregation is a technology that combines multiple physical network links into a logical link. Its main purpose is to increase the bandwidth of the link, improve the reliability of the link and achieve load balancing. For example, by aggregating multiple physical links together, data can be transmitted on these links at the same time, thereby achieving a higher data transmission rate. When one of the links fails, the data can be automatically switched to other normal links for transmission, which enhances the fault tolerance and stability of the network. During the data transmission process, data traffic can also be dynamically allocated according to the load of the link, making full use of all available link resources and improving the overall performance and efficiency of the network. Here, only the link aggregation port including the first port and the second port is used as an example for explanation. In actual applications, the link aggregation port can also include more ports, which are not specifically limited here. The third port can be an ordinary port or one of the ports of another link aggregation port, which is not specifically limited here.

[0043] The first port includes multiple queues. For example, the queues of the first port are numbered 0-15. When a link aggregation port is created in the kernel space, multiple queues of the first port will be managed, so control messages and data messages between the kernel space and the network card can be transmitted through these queues. Figure 3As shown, when the link aggregation port receives a data message from the network, the data message will be transmitted to the kernel protocol stack of the kernel space through the queue, and the kernel protocol stack will copy a data message and send it to the user space. After receiving the data message, the user space will copy another data message and send it to the kernel socket in the kernel space, and the kernel socket in the kernel space will send it to the specified network card. This will cause the forwarding of the data message to be copied twice, and the user space and kernel space need to be switched, which wastes a lot of performance. For this reason, the first port can be added to the open virtual switch management. After the first port is managed by the open virtual switch, the first queue of the first port is retained, and the second queue of the first port is released to the open virtual switch management. There is an address mapping relationship between the first queue and the third queue of the kernel space, and the first queue and the third queue are used to transmit the control message of the link aggregation port between the network card and the kernel space. There is an address mapping relationship between the second queue and the fourth queue in the data plane development kit. The second queue and the fourth queue are used to transmit the data message of the link aggregation port between the network card and the data plane development kit. The number of the first queue and the second queue can be set as needed. For example, when the queue of the first port includes queues with sequence numbers 0-15, the queue with sequence number 0 can be reserved for transmitting control messages, and the queues with sequence numbers 1-15 can be released to the open virtual switch to transmit data messages between the network card and the DPDK. Since the first port and the second port are both link aggregation ports, it is only necessary to add the first port to the open virtual switch management, and it is not necessary to add the second port to the open virtual switch management. Non-link aggregation ports can add themselves to the open virtual switch management. For example, the third port can add itself to the open virtual switch management.

[0044] The data plane development kit periodically obtains the information of the link aggregation port from the kernel space. The information of the link aggregation port may include the information of the members of the link aggregation port, such as the first port and the second port, etc. The periodic time length can be set as needed, for example, it can be microsecond level, millisecond level, second level, etc. When the link aggregation port changes, the data plane development kit can be informed, for example, when the members of the link aggregation port are added or deleted, or when the link aggregation port is created or cancelled, the data plane development kit can be informed in time.

[0045] After receiving the data packet, the link aggregation port transmits the data packet to the fourth queue in the data plane development kit through the second queue. Since the first port is added to the open virtual switch management, whether the first port or the second port receives the data packet, the data packet can be sent to the data plane development kit through the second queue. After receiving the first data packet, the first port transmits the data packet to the fourth queue in the data plane development kit through the second queue; after receiving the second data packet, the second port transmits the data packet to the fourth queue in the data plane development kit through the second queue. The second queue and the fourth queue can be transmitted through direct memory access (DMA), so the host processor does not need to intervene.

[0046] After receiving the data message, the data plane development kit determines whether the first port belongs to the link aggregation port. If it belongs to the link aggregation port, the source port of the extended header of the data message is replaced with the link aggregation port, and the replaced data message is sent to the open virtual switch. Among them, the extended header may include the source port, the destination port, the sequence number, the confirmation number, the header length, the flag bit, the checksum, etc. The source port is the inbound port of the data message, and the destination port is the outbound port of the data message. The sequence number is used to ensure the order and reliability of the data. The confirmation number is used to confirm the received data. The header length is used to indicate the length of the header. The flag bit can be synchronization (SYN), confirmation (ACK), end (FIN), etc., which are used to control the establishment, confirmation and closing of the connection. The checksum is used to detect errors in the data transmission process. In addition, if it is the Internet Protocol version 6 (IPv6) protocol, the extended header may also include a hop-by-hop option header, a destination option header, a routing header, a fragmentation header, an authentication header, an encapsulating security payload header, etc.

[0047] The open virtual switch is used to determine that the egress port of the data message is the third port and send the data message to the data plane development kit. The open virtual switch maintains a series of flow tables, which contain matching fields and corresponding actions. When the data message enters OVS, it will be matched according to the rules in the flow table. If the matched flow table indicates that the corresponding action is to output the data message from the third port, then the third port will be selected as the egress port.

[0048] The data plane development kit sends the data message to the third port of the network card. The third port may include a fifth queue, and there is an address mapping relationship between the fourth queue and the fifth queue, and the fourth queue and the fifth queue may be used to realize the transmission between data messages. The fourth queue and the fifth queue may be transmitted through direct memory access DMA, so the host processor does not need to intervene.

[0049] When the data message is a first address resolution protocol message, after receiving the data message, the link aggregation port transmits the first address resolution protocol message to the fourth queue in the data plane development kit through the second queue. After receiving the first address resolution protocol message, the data plane development kit copies the first address resolution protocol message to obtain a second address resolution protocol message, and saves the second address resolution protocol message to the huge page of the data plane development kit. Among them, the huge page can be 1 megabyte or 1 gigabyte. In the prior art, the copying of the first address resolution protocol message occurs in the kernel space, and the pages in the kernel space are ordinary 4-kilobyte pages, so there will be more memory fragmentation. For example, when three 3-kilobyte address resolution protocol messages are received continuously, three pages are required to store the copied address resolution protocol messages, and each page has 1 kilobyte of memory fragmentation left. Copying the ARP message in the data plane development kit can effectively reduce the occurrence of memory fragmentation. For example, when three 3-kilobyte ARP messages are received consecutively, only one 1-megabyte huge page is needed to store the copied ARP messages, and this huge page has only one 1-kilobyte memory fragment.

[0050] For example, the first port and the second port are 25 Gbytes respectively, and the link aggregation port is 50 Gbytes. However, when forwarding through the kernel space, the forwarding rate of the link aggregation port is 20 Gbytes, and when forwarding through the user space, the forwarding rate of the link aggregation port is 40 Gbytes. The performance is successfully improved by 2 times.

[0051] See also Figure 4 , Figure 4 4 is a schematic diagram of a computing device provided by the present application. The computing device 400 includes: one or more processing units 410 , a communication interface 420 and a storage unit 430 .

[0052] The processing unit 410, the communication interface 420 and the storage unit 430 are interconnected via a bus 440. Optionally, the computing device 400 may also include an input / output interface 450, which is connected to an input / output device for receiving parameters set by a user, etc. The computing device 400 can be used to implement some or all of the functions of the device embodiment or system embodiment in the above-mentioned embodiment of the present application; the processing unit 410 can also be used to implement some or all of the operation steps of the method embodiment in the above-mentioned embodiment of the present application. For example, the specific implementation of the various operations performed by the computing device 400 can refer to the specific details in the above-mentioned embodiment, such as the processing unit 410 is used to perform some or all of the steps in the above-mentioned method embodiment or some or all of the operations in the above-mentioned method embodiment. For another example, in the embodiment of the present application, the computing device 400 can be used to implement some or all of the functions of one or more components in the above-mentioned device embodiment, and the communication interface 420 can be specifically used for the communication functions necessary to implement the functions of these devices and components, and the processing unit 410 can be specifically used for the processing functions necessary to implement the functions of these devices and components, etc.

[0053] Figure 4 The computing device 400 may include one or more processing units 410, and the multiple processing units 410 may provide processing capabilities in a coordinated manner in a parallel connection manner, a serial connection manner, a serial-parallel connection manner, or any connection manner, or the multiple processing units 410 may constitute a processor sequence or a processor array, or the multiple processing units 410 may be divided into a main processor and an auxiliary processor, or the multiple processing units 410 may have different architectures such as a heterogeneous computing architecture. In addition, Figure 4 The computing device 400 shown in the figure, and the related structural description and functional description are exemplary and non-limiting. In some exemplary embodiments, the computing device 400 may include Figure 4 More or fewer components may be shown, or some components may be combined or separated, or may have a different arrangement of components.

[0054] The processing unit 410 may have a variety of specific implementation forms. For example, the processing unit 410 may include a processor (central processing unit, CPU), a graphic processing unit (graphic processing unit, GPU), a neural-network processing unit (neural-network processing unit, NPU), a tensor processing unit (tensor processing unit, TPU) or a data processing unit (data processing unit, DPU) and other combinations thereof, which are not specifically limited in the embodiments of the present application. The processing unit 410 may also be a single-core processor or a multi-core processor. The processing unit 410 may be a combination of a CPU and a hardware chip. The above-mentioned hardware chip may be an application-specific integrated circuit (application-specific integrated circuit, ASIC), a programmable logic device (programmable logic device, PLD) or a combination thereof. The above-mentioned PLD may be a complex programmable logic device (complex programmable logic device, CPLD), a field-programmable gate array (field-programmable gate array, FPGA), a generic array logic (generic array logic, GAL) or any combination thereof. The processing unit 410 may also be implemented using a logic device with built-in processing logic alone, such as an FPGA or a digital signal processor (digital signal processor, DSP), etc. The communication interface 420 may be a wired interface or a wireless interface for communicating with other modules or devices. The wired interface may be an Ethernet interface, a local interconnect network (LIN), etc., and the wireless interface may be a cellular network interface or a wireless local area network interface, etc.

[0055] The storage unit 430 may be a non-volatile memory, such as a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The storage unit 430 may also be a volatile memory, which may be a random access memory (RAM) used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous connection dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM). The storage unit 430 may also be used to store program codes and data, so that the processing unit 410 can call the program codes stored in the storage unit 430 to execute some or all of the operation steps in the above method embodiment, or to execute the corresponding functions in the above device embodiment. Figure 4 Show more or fewer components, or have different component configurations.

[0056] The bus 440 may be a peripheral component interconnect express (PCIe) bus, an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a compute express link (CXL), a cache coherent interconnect for accelerators (CCIX), etc. The bus 440 may be divided into an address bus, a data bus, a control bus, etc. In addition to the data bus, the bus 440 may also include a power bus, a control bus, and a status signal bus, etc. However, for the sake of clarity, Figure 4 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0057] The present application also provides a system, which includes multiple computing devices, and the structure of each computing device can refer to the structure of the computing device described above. The functions or operations that can be implemented by the system can refer to the specific implementation steps in the above method embodiment and / or the specific functions described in the above device embodiment, which will not be repeated here.

[0058] In the above embodiments, all or part of the embodiments can be implemented by software, hardware, firmware or any combination thereof. When implemented by software, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one network site, computer, server or data center to another network site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, microwave, etc.) means. The computer-readable storage medium can be any available medium that can be accessed by a computer, or it can be a data storage device such as a server or data center that includes one or more available media integrated. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape, etc.), an optical medium (e.g., a DVD, etc.), or a semiconductor medium (e.g., a solid-state hard disk), etc. In the above embodiments, the description of each embodiment has different emphases. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

Claims

1. A message forwarding system, characterized in that: include: A host, including a kernel space and a user space, wherein the user space runs a data plane development kit and an open virtual switch, A network card, comprising a first port, a second port and a third port, wherein the first port and the second port form a logically single link aggregation port through link aggregation, the first port comprises a first queue and a second queue, wherein an address mapping relationship exists between the first queue and the third queue of the kernel space, the first queue and the third queue are used to transmit control messages of the link aggregation port between the network card and the kernel space, and an address mapping relationship exists between the second queue and a fourth queue in the data plane development kit, The link aggregation port is used to transmit the data message to the fourth queue in the data plane development kit through the second queue after receiving the data message; The data plane development kit is used to determine, with the assistance of the open virtual switch, the third port as the egress port of the data message, and send the data message to the third port of the network card; The first port and the third port are managed by the open virtual switch, The kernel space is used to reserve the first queue of the first port and release the second queue of the first port to the open virtual switch for management after determining that the first port is managed by the open virtual switch.

2. The system according to claim 1, characterized in that The first port is used to transmit the first data message to the fourth queue in the data plane development kit through the second queue after receiving the first data message; or, The second port is used to transmit the second data packet to the fourth queue in the data plane development kit through the second queue after receiving the second data packet.

3. The system according to claim 1, characterized in that The kernel space is used to create the link aggregation port and save information of the link aggregation port, wherein the information of the link aggregation port includes members of the link aggregation port.

4. The system according to claim 3, characterized in that The data plane development kit is used to periodically obtain the information of the link aggregation port from the kernel space.

5. The system according to claim 3, characterized in that The data plane development kit is used to determine that the first port belongs to the link aggregation port according to the information of the link aggregation port, replace the source port of the extended header of the data message with the link aggregation port, and send the replaced data message to the open virtual switch.

6. The system according to claim 1, characterized in that The data plane development kit is used for copying the first address resolution protocol message to obtain a second address resolution protocol message when the data message is a first address resolution protocol message, and saving the second address resolution protocol message into a huge page of the data plane development kit.

7. The system according to claim 6, characterized in that The data plane development kit is used to send the data message to the open virtual switch; The open virtual switch is used to determine that the egress port of the data message is the third port, and send the data message to the data plane development kit; The data plane development kit is used to send the data message to the third port of the network card.

8. A computing device, characterized in that It comprises a message forwarding system and a storage unit, the message forwarding system and the storage unit can communicate with each other, and the message forwarding system is a system as described in any one of claims 1-7.

9. A computing device cluster, characterized in that: It includes multiple computing devices, at least one computing device includes a message forwarding system and a storage unit, the message forwarding system and the storage unit can communicate with each other, and the message forwarding system is a system as described in any one of claims 1-7.

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