Method of manufacturing a power semiconductor and power semiconductor structure

Abstract

The embodiment of the present specification provides a power semiconductor preparation method and a power semiconductor structure, wherein the semiconductor preparation method comprises: depositing a first N-type epitaxial layer on a silicon substrate, and depositing a second N-type epitaxial layer on the first N-type epitaxial layer; etching to remove the second N-type epitaxial layer of a target region, and depositing a third N-type epitaxial layer on the second N-type epitaxial layer and the target region; etching the first N-type epitaxial layer, the second N-type epitaxial layer and the third N-type epitaxial layer to form a trench; by setting an epitaxial layer with a medium doping concentration only on the upper part and the middle part outside the outermost peripheral trench of the terminal area, the space charge region is diffused outside the outermost peripheral terminal trench, the electric field strength at this position is reduced, the terminal structure withstand voltage is improved, the cell size is reduced without increasing the thickness of the oxide layer at the bottom of the trench of the separation gate trench MOSFET to ensure the terminal withstand voltage, and the on-resistance of the device is reduced.

Description

TECHNICAL FIELD

[0001] Embodiments of the present specification relate to the technical field of semiconductor technology, and particularly relate to a power semiconductor preparation method and a power semiconductor structure. BACKGROUND

[0002] Split Gate Trench MOSFET (SGT MOS) is particularly suitable for low-power power supply systems due to low on-resistance and high switching speed characteristics.

[0003] In the prior art, three epitaxial layers are generally used to form the drift region of the device to optimize the electric field distribution of the trench bottom and the drift region between trenches of the device cell, so as to achieve low on-resistance and high blocking voltage. In the scheme of forming the drift region by three epitaxial layers, an intermediate outer layer with high impurity concentration is generally arranged in the middle of the trench to reduce the on-resistance of the drift region, but this will cause the space charge region of the outermost trench of the device terminal structure in the middle high-doped layer region to be compressed, and breakdown will occur when the electric field exceeds the adjacent breakdown electric field strength. To reduce the electric field strength in the middle of the outermost trench of the terminal structure, the thickness of the oxide layer at the bottom of the SGT MOS trench needs to be increased. The scheme of increasing the thickness of the oxide layer will increase the cell size, thereby increasing the on-resistance of the device and increasing the conduction loss.

[0004] Therefore, a better scheme is urgently needed. SUMMARY

[0005] Therefore, one or more embodiments of the present specification also relate to a semiconductor to solve the technical defects in the prior art.

[0006] According to a first aspect of an embodiment of the present specification, a power semiconductor preparation method is provided, comprising:

[0007] depositing a first N-type epitaxial layer on a silicon substrate, and depositing a second N-type epitaxial layer on the first N-type epitaxial layer; wherein the doping concentration of the first N-type epitaxial layer is lower than the doping concentration of the second N-type epitaxial layer;

[0008] etching to remove the second N-type epitaxial layer in a target region, and depositing a third N-type epitaxial layer on the second N-type epitaxial layer and the target region; wherein the doping concentration of the third N-type epitaxial layer is higher than the doping concentration of the first N-type epitaxial layer;

[0009] etching the first N-type epitaxial layer, the second N-type epitaxial layer, and the third N-type epitaxial layer to form a trench; wherein the trench comprises an active region trench and a terminal region trench;

[0010] Forming a bottom oxide layer in the trench by thermal growth and deposition, depositing polysilicon on the surface of the bottom oxide layer, and etching the polysilicon to form a polysilicon structure;

[0011] Forming an intermediate oxide layer on the polysilicon structure of the active region trench, forming a gate oxide layer structure on the sidewall of the active region trench, filling polysilicon in the active region trench to form a gate polysilicon structure, and forming a shielding oxide layer on the gate polysilicon structure;

[0012] Forming a base region by ion implantation on the third N-type epitaxial layer and annealing the base region to form an implantation shielding layer between the active region trench and the termination region trench; forming a source region by ion implantation on the third N-type epitaxial layer and annealing the source region, forming a dielectric oxide layer on the source region, forming a metal electrode contact hole on the dielectric oxide layer, performing a contact region implantation and annealing on the metal electrode contact hole, and forming a source electrode, a gate electrode and a cutoff electrode on the metal electrode contact hole;

[0013] Forming a passivation structure on the electrode structure, and forming a drain electrode below the silicon substrate.

[0014] In a possible implementation, the doping concentration of the first N-type epitaxial layer ranges from 1.0E15 to 7.5E15 cm -3 ;

[0015] The doping concentration of the second N-type epitaxial layer ranges from 2.0E16 to 7.5E16 cm -3 ;

[0016] The doping concentration of the third N-type epitaxial layer ranges from 5.0E15 to 2.5E16 cm -3 .

[0017] In a possible implementation, the depth of the trench is 3-7 μm;

[0018] The width of the trench is 0.5-2.0 μm;

[0019] The thickness of the bottom oxide layer is 0.4-0.9 μm;

[0020] The thickness of the intermediate oxide layer is 0.3-0.6 μm;

[0021] The thickness of the gate oxide layer structure is 0.04-0.09 μm;

[0022] The thickness of the shielding oxide layer is 0.05-0.1 μm.

[0023] In a possible implementation, forming a base region by ion implantation on the third N-type epitaxial layer and annealing the base region, comprises:

[0024] The ion implantation is arsenic ion implantation, the implantation energy is 60-150 KeV, and the implantation dose is 0.6E13-1.5E13 cm -2 ;

[0025] The annealing temperature of the annealing is 1000-1150℃, and the annealing time is 30-120 min.

[0026] In a possible implementation, the ion implantation is performed on the third N-type epitaxial layer to form a source region, and the source region is annealed to form a dielectric oxide layer on the source region, and the method comprises the following steps:

[0027] The ion implantation is arsenic ion implantation;

[0028] The annealing temperature of the annealing is 950-1000℃, and the annealing time is 90-120 min.

[0029] In a possible implementation, the metal electrode contact hole is subjected to contact region implantation and annealing, and the method comprises the following steps:

[0030] The metal electrode contact hole is subjected to BF2 implantation; the implantation energy of the BF2 implantation is 60-80 KeV, and the implantation dose is 3E14-5E14 cm -2 ;

[0031] The annealing temperature of the annealing is 900-1000℃, and the annealing time is 20-30 min.

[0032] In a possible implementation, a source electrode, a gate electrode and a stop electrode are formed on the metal electrode contact hole, and the method comprises the following steps:

[0033] An AlSiCu metal layer is deposited on the metal electrode contact hole, and the source electrode, the gate electrode and the stop electrode are formed through a photolithography and etching process; wherein the thickness of the AlSiCu metal layer is 4-6 μm.

[0034] In a possible implementation, a passivation structure is formed on the electrode structure, and a drain electrode is formed below the silicon substrate, and the method comprises the following steps:

[0035] A passivation layer is deposited on the electrode structure, and the passivation structure is formed through a photolithography and etching process;

[0036] A metal layer is evaporated below the silicon substrate to form the drain electrode; wherein the metal layer comprises any one of Ti, Ni and Ag.

[0037] According to a second aspect of the embodiments of the present specification, a power semiconductor structure is provided, comprising: a substrate, a first epitaxial layer, a second epitaxial layer and a third epitaxial layer;

[0038] The first epitaxial layer is arranged on the substrate;

[0039] The second epitaxial layer is disposed on the first epitaxial layer, and a width of the second epitaxial layer is smaller than that of the first epitaxial layer;

[0040] The third epitaxial layer is disposed on the first epitaxial layer and the second epitaxial layer;

[0041] The trench is formed in the first epitaxial layer, the second epitaxial layer and the third epitaxial layer;

[0042] The electrode structure is disposed on the trench.

[0043] In a possible implementation, the trench includes an active region trench and a termination region trench;

[0044] The active region trench is formed in the first epitaxial layer, the second epitaxial layer and the third epitaxial layer;

[0045] The termination region trench is formed in the first epitaxial layer and the third epitaxial layer;

[0046] The doping concentration of the first epitaxial layer is lower than that of the second epitaxial layer;

[0047] The doping concentration of the third epitaxial layer is higher than that of the first epitaxial layer.

[0048] The embodiment of the present specification provides a power semiconductor preparation method and a power semiconductor structure, wherein the semiconductor preparation method comprises: depositing a first N-type epitaxial layer on a silicon substrate, and depositing a second N-type epitaxial layer on the first N-type epitaxial layer; etching to remove the second N-type epitaxial layer in a target region, and depositing a third N-type epitaxial layer on the second N-type epitaxial layer and the target region; etching the first N-type epitaxial layer, the second N-type epitaxial layer and the third N-type epitaxial layer to form a trench; by setting only an epitaxial layer with a medium doping concentration on the upper part and the middle part outside the outermost peripheral trench of the termination region, the space charge region is diffused outside the outermost peripheral termination trench, the electric field strength at this position is reduced, the termination structure withstand voltage is improved, the cell size is reduced without increasing the thickness of the oxide layer at the bottom of the separation gate trench MOSFET trench to ensure the termination withstand voltage, and the on-resistance of the device is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0049] Figure 1 FIG. 1 is a flowchart of a power semiconductor preparation method provided by an embodiment of the present specification;

[0050] Figure 2 FIG. 2 is a first structural schematic diagram of a power semiconductor preparation method provided by an embodiment of the present specification;

[0051] Figure 3 FIG. 3 is a second structural schematic diagram of a power semiconductor preparation method provided by an embodiment of the present specification;

[0052] Figure 4is a third structural schematic diagram of a power semiconductor preparation method provided by one embodiment of the present specification;

[0053] Figure 5 is a fourth structural schematic diagram of a power semiconductor preparation method provided by one embodiment of the present specification;

[0054] Figure 6 is a fifth structural schematic diagram of a power semiconductor preparation method provided by one embodiment of the present specification;

[0055] Figure 7 is a sixth structural schematic diagram of a power semiconductor preparation method provided by one embodiment of the present specification;

[0056] Figure 8 is a seventh structural schematic diagram of a power semiconductor preparation method provided by one embodiment of the present specification;

[0057] Figure 9 is an eighth structural schematic diagram of a power semiconductor preparation method provided by one embodiment of the present specification;

[0058] Figure 10 is a structural schematic diagram of a semiconductor provided by one embodiment of the present specification. DETAILED DESCRIPTION

[0059] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present specification. However, the present specification can be practiced without the specific details, other than in the examples, set forth in this description. Those skilled in the art, in light of the description, can implement the present specification without limiting the same to the specific details presented herein. The description is not meant to be limiting.

[0060] The terminology used in one or more embodiments of the present specification is for the purpose of describing particular embodiments only and is not intended to be limiting of one or more embodiments of the present specification. As used in one or more embodiments of the present specification and the accompanying claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in one or more embodiments of the present specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0061] It should be understood that, although the terms first, second, etc. can be employed in describing various information in one or more embodiments of the present specification, such information should not be limited to these terms. These terms are only used to differentiate one piece of information from another piece of information of the same type. For example, without departing from the scope of one or more embodiments of the present specification, first can also be referred to as second, and similarly, second can also be referred to as first. Depending on the context, the word "if" as used herein can be interpreted as "when" or "upon" or "in response to determining".

[0062] Firstly, the noun terms related to one or more embodiments of the present specification are explained.

[0063] Substrate is the basic material used to support and build other functional layers in the semiconductor device manufacturing process.

[0064] Epitaxy refers to the process of growing a new single crystal layer on a single crystal substrate that has been carefully processed by cutting, grinding, and polishing, etc. The new single crystal can be the same material as the substrate or a different material.

[0065] In the present specification, a semiconductor preparation method is provided, and the present specification also relates to a semiconductor, which are described in detail one by one in the following embodiments.

[0066] Referring to Figure 1 , Figure 1 A flow chart of a power semiconductor preparation method according to one embodiment of the present specification is shown, which specifically includes the following steps.

[0067] Step 101: depositing a first N-type epitaxial layer on a silicon substrate, and depositing a second N-type epitaxial layer on the first N-type epitaxial layer; wherein the doping concentration of the first N-type epitaxial layer is lower than the doping concentration of the second N-type epitaxial layer.

[0068] In one possible implementation, the doping concentration of the first N-type epitaxial layer ranges from 1.0E15 to 7.5E15 cm -3 ; and the doping concentration of the second N-type epitaxial layer ranges from 2.0E16 to 7.5E16 cm -3 .

[0069] In practical applications, referring to Figure 2 , an N+ type silicon substrate 1 is selected, and a first N-type epitaxial layer 21 with low doping concentration and a second N-type epitaxial layer 22 with high doping concentration are deposited on the N+ type silicon substrate in sequence.

[0070] The impurity doping concentration of the first N-type epitaxial layer with low doping concentration ranges from 1.0E15 to 7.5E15 cm -3 ; and the impurity doping concentration of the second N-type epitaxial layer with high doping concentration ranges from 2.0E16 to 7.5E16 cm-3 .

[0071] Step 102: etching to remove the second N-type epitaxial layer in the target region, and depositing a third N-type epitaxial layer on the second N-type epitaxial layer and in the target region; wherein the doping concentration of the third N-type epitaxial layer is higher than the doping concentration of the first N-type epitaxial layer.

[0072] The doping concentration of the third N-type epitaxial layer ranges from 5.0E15 to 2.5E16 cm -3 .

[0073] In practical applications, referring to Figure 3 , by means of photolithography definition, using photolithography etching technology, and adopting dry etching process, the second N-type epitaxial layer with high doping concentration outside the outermost trench of the termination region is etched to be removed, so that only the first N-type epitaxial layer with low doping concentration is reserved outside the outermost trench of the termination region; the third N-type epitaxial layer with medium doping concentration is deposited on the second N-type epitaxial layer with high doping concentration inside the outermost trench of the termination region and the first N-type epitaxial layer with low doping concentration at the bottom of the trench outside the outermost trench of the termination region, and the impurity doping concentration of the third N-type epitaxial layer with medium doping concentration ranges from 5.0E15 to 2.5E16 cm -3 .

[0074] The embodiments of the present application realize different epitaxial layer structures in the inner and outer regions of the outermost trench of the termination structure by means of selective photolithography etching, i.e., three layers of epitaxial layers are formed inside the outermost trench of the termination region, and two layers of epitaxial layers are formed outside the outermost trench, so as to reduce the electric field intensity outside the outermost trench of the termination structure and improve the blocking voltage of the termination structure of the device. Without increasing the thickness of the oxide layer at the bottom of the MOSFET cell trench by means of the method of increasing the separation gate trench, a smaller cell unit size can be realized, and the on-resistance of the device is reduced.

[0075] Step 103: etching the first N-type epitaxial layer, the second N-type epitaxial layer and the third N-type epitaxial layer to form a trench; wherein the trench includes an active region trench and a termination region trench.

[0076] In a possible implementation manner, the depth of the trench is 3-7 μm, and the width of the trench is 0.5-2.0 μm.

[0077] In practical applications, referring to Figure 4 , the first N-type epitaxial layer, the second N-type epitaxial layer and the third N-type epitaxial layer are subjected to photolithography and etching process to form the active region cell trench 31 and the termination region trench 32 with a depth of 3-7 μm and a width of 0.5-2.0 μm.

[0078] Step 104: Forming a bottom oxide layer in the trench by thermal growth and deposition, depositing polysilicon on the surface of the bottom oxide layer, and etching the polysilicon to form a polysilicon structure.

[0079] In one possible implementation, the thickness of the bottom oxide layer is 0.4-0.9 μm.

[0080] In practical applications, referring to Figure 5 , a bottom oxide layer 4 with a thickness of 0.4-0.9 μm is formed in the trench by thermal growth and deposition in sequence; polysilicon is deposited on the wafer surface where the bottom oxide layer is formed to fill the trench structure, and the polysilicon in the active region trench is etched by lithography and etching to form an active region cell polysilicon structure 51 and a terminal region polysilicon structure 52.

[0081] Step 105: Forming an intermediate oxide layer on the polysilicon structure of the active region trench, forming a gate oxide layer structure on the sidewall of the active region trench, filling the active region trench with polysilicon to form a gate polysilicon structure, and forming a shielding oxide layer on the gate polysilicon structure.

[0082] In one possible implementation, the thickness of the intermediate oxide layer is 0.3-0.6 μm; the thickness of the gate oxide layer structure is 0.04-0.09 μm; and the thickness of the shielding oxide layer is 0.05-0.1 μm.

[0083] In practical applications, referring to Figure 6 , the trench structure is filled again by an oxide deposition process, the excess oxide layer on the silicon surface is removed, and the deposited oxide layer in the active region cell trench is etched by lithography and etching to form an intermediate oxide layer 6 with a thickness of 0.3-0.6 μm on the active region cell polysilicon structure 51.

[0084] Further, referring to Figure 7 , a gate oxide layer structure 7 with a thickness of 0.04-0.09 μm is formed on the sidewall of the active region cell trench by a dry oxygen oxidation process; then the active region cell trench is filled with polysilicon to form a gate polysilicon structure 8; and a shielding oxide layer 9 with a thickness of 0.05-0.1 μm is formed on the top of the gate polysilicon by a dry oxygen oxidation process again.

[0085] Step 106: Forming a base region by ion implantation on the third N-type epitaxial layer and annealing the base region to form an implantation shielding layer between the active region trench and the terminal region trench; forming a source region by ion implantation on the third N-type epitaxial layer and annealing the source region to form a dielectric oxide layer on the source region, a metal electrode contact hole on the dielectric oxide layer, a contact region implantation and annealing on the metal electrode contact hole, and a source electrode, a gate electrode, and a cutoff electrode on the metal electrode contact hole.

[0086] The stop electrode can be a stop ring.

[0087] In a possible implementation, ion implantation is performed on the third N-type epitaxial layer to form a base region, and the base region is annealed, including: the ion implantation energy is 60-150 KeV, and the implantation dose is 0.6E13-1.5E13 cm -2 The annealing temperature is 1000-1150 °C, and the annealing time is 30-120 min.

[0088] In actual application, referring to Figure 8 The silicon surface is globally implanted, the implantation energy is 60-150 KeV, and the implantation dose is 0.6E13-1.5E13 cm -2 After the P base region 10 ion implantation is completed, the base region implantation is annealed, the annealing temperature is 1000-1150 °C, and the annealing time is 30-120 min.

[0089] In a possible implementation, ion implantation is performed on the third N-type epitaxial layer to form a source region, and the source region is annealed, and a dielectric oxide layer is formed on the source region, including: the ion implantation is arsenic ion implantation; the annealing temperature is 950-1000 °C, and the annealing time is 90-120 min.

[0090] In actual application, referring to Figure 8 An implantation shielding layer is formed between the active region and the outermost terminal trench by using a photolithography process, and N+ type source region arsenic ion implantation is performed outside the active region and the outermost terminal trench; after the source region arsenic ion implantation, annealing is performed, the annealing temperature is 950-1000 °C, the annealing time is 90-120 min, an N+ type source region 11 is formed, and a dielectric oxide layer with a thickness of 1.0-1.5 μm is deposited on the wafer on which the N+ type source region is formed.

[0091] In a possible implementation, contact region implantation and annealing are performed on a metal electrode contact hole, including: BF2 implantation is performed on the metal electrode contact hole; the implantation energy of the BF2 implantation is 60-80 KeV, and the implantation dose is 3E14-5E14 cm -2 The annealing temperature is 900-1000 °C, and the annealing time is 20-30 min.

[0092] In actual application, referring to Figure 8 After the dielectric oxide layer is formed, a metal electrode contact hole is formed on the dielectric oxide layer by using a photolithography process; a source electrode contact region BF2 implantation process is performed through the metal electrode contact hole, and annealing is performed after implantation, the implantation energy is 60-80 KeV, and the implantation dose is 3E14-5E14 cm -2The annealing temperature is 900-1000℃, and the annealing time is 20-30 min.

[0093] In a possible implementation, the source electrode, the gate electrode and the cutoff electrode are formed on the metal electrode contact hole, including: depositing an AlSiCu metal layer on the metal electrode contact hole, and forming the source electrode, the gate electrode and the cutoff electrode through a photolithography and etching process; and the thickness of the AlSiCu metal layer is 4-6 μm.

[0094] Specifically, referring to Figure 8 The wafer upper surface of the electrode contact hole is deposited with an AlSiCu metal layer with a thickness of 4-6 μm, and the source electrode 12, the gate electrode 13 and the Ring (cutoff ring) electrode 14 are formed through a photolithography and etching process.

[0095] Step 107: forming a passivation structure on the electrode structure, and forming a drain electrode below the silicon substrate.

[0096] The electrode structure can include a source electrode, a gate electrode and a Ring electrode.

[0097] In a possible implementation, the passivation structure is formed on the electrode structure, and the drain electrode is formed below the silicon substrate, including: depositing a passivation layer on the electrode structure, and forming the passivation structure through a photolithography and etching process; and evaporating a metal layer below the silicon substrate to form the drain electrode; and the metal layer includes any one of Ti, Ni and Ag.

[0098] In actual application, referring to Figure 9 The passivation layer is deposited on the electrode structure, and the passivation structure 15 is formed through a photolithography and etching process; the Ti / Ni / Ag metal layer is evaporated on the lower surface of the silicon substrate 1 to form the drain electrode 16, and the preparation of the separate gate trench MOSFET structure is completed.

[0099] The semiconductor preparation method includes: depositing a first N-type epitaxial layer on a silicon substrate, and depositing a second N-type epitaxial layer on the first N-type epitaxial layer; etching to remove the second N-type epitaxial layer in a target region, and depositing a third N-type epitaxial layer on the second N-type epitaxial layer and the target region; etching the first N-type epitaxial layer, the second N-type epitaxial layer and the third N-type epitaxial layer to form a trench; and diffusing a space charge region outside the outermost peripheral terminal trench by setting an epitaxial layer with a medium doping concentration only on the upper part and the middle part outside the outermost peripheral trench of the terminal region, reducing the electric field intensity at the position, improving the terminal structure withstand voltage, reducing the cell size without increasing the thickness of the oxide layer at the bottom of the separate gate trench MOSFET trench to ensure the terminal withstand voltage, and reducing the on-resistance of the device.

[0100] Referring to Figure 10, Figure 10 A structural diagram of a power semiconductor preparation method according to one embodiment of the present specification is shown, and the power semiconductor structure includes: a semiconductor prepared by the above-mentioned semiconductor preparation method, specifically including a substrate, a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer;

[0101] The first epitaxial layer is arranged on the substrate; the second epitaxial layer is arranged on the first epitaxial layer, and the width of the second epitaxial layer is smaller than that of the first epitaxial layer; the third epitaxial layer is arranged on the first epitaxial layer and the second epitaxial layer; a trench is arranged on the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer; and an electrode structure is arranged on the trench.

[0102] In one possible implementation, the trench includes an active region trench and a termination region trench; the active region trench is arranged on the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer; the termination region trench is arranged on the first epitaxial layer and the third epitaxial layer; the doping concentration of the first epitaxial layer is lower than that of the second epitaxial layer; and the doping concentration of the third epitaxial layer is higher than that of the first epitaxial layer.

[0103] Specifically, the semiconductor can be a MOSFET semiconductor, referring to Figure 10 The structure of the MOSFET semiconductor includes a substrate 1, a first epitaxial layer 21, a second epitaxial layer 22, a third epitaxial layer 23, an active region cell trench 31, a termination region trench 32, a bottom oxide layer 4, a polycrystalline structure 5, an intermediate oxide layer 6, a gate oxide layer 7, a gate polysilicon structure 8, a base region 10, a source region 11, a source electrode 12, a gate electrode 13, a cutoff electrode 14, a passivation structure 15, and a drain electrode 16.

[0104] The polycrystalline structure 5 includes an active region cell polycrystalline structure and a termination region polycrystalline structure, the active region cell polycrystalline structure is arranged in the active region cell trench 31, and the termination region polycrystalline structure is arranged in the termination region trench 32.

[0105] Compared with the existing SGT MOS structure formed by a three-layer epitaxial process, the structure of the split gate trench MOSFET of the present specification forms a trench bottom low-doping-concentration epitaxial layer and a trench middle high-doping-concentration epitaxial layer on the surface of a substrate wafer, defines a pattern by photolithography, removes the trench middle high-doping-concentration epitaxial layer outside the outermost peripheral trench of the termination region by using a dry etching technique to make the outermost peripheral trench of the termination region only retain the trench bottom low-doping-concentration epitaxial layer, and then deposits a middle-doping-concentration epitaxial layer on the trench middle high-doping-concentration epitaxial layer inside the outermost peripheral trench of the termination region and the trench bottom low-doping-concentration epitaxial layer outside the outermost peripheral trench of the termination region, so as to form three-layer and two-layer epitaxial layer drift regions inside and outside the outermost peripheral trench of the termination region, respectively.

[0106] It should be noted that, for the foregoing method embodiments, the sequences of the described operations are presented for the sake of clarity and pedagogy, but the order of operations in the embodiments described herein can be modified so that the described implementations can be performed in other sequences. Also, some steps can be performed in parallel or with no time in between. Furthermore, the described embodiments are not necessarily limited to the described orders of operations.

[0107] In the above embodiments, the description of each embodiment is focused on different aspects, and the parts not described in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0108] The preferred embodiments of the present specification disclosed above are only used to help explain the present specification. The alternative embodiments do not describe all the details and limit the invention to the specific embodiments described. Obviously, according to the content of the embodiments of the present specification, many modifications and changes can be made, and a plurality of epitaxial layers can be continuously added on the third layer, and the epitaxial layers in the target area are removed by etching. The structure needs to keep the drift region of the outermost trench in the terminal area as two epitaxial layers, which can reduce the electric field intensity here, improve the terminal structure voltage resistance, reduce the cell size, and reduce the on-resistance of the device.

[0109] The present specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the embodiments of the present specification, so that those skilled in the art can well understand and utilize the present specification. The present specification is limited only by the claims and their full scope and equivalents.

Claims

1. A method of preparing a power semiconductor, characterized by, The method comprises the following steps: depositing a first N-type epitaxial layer on a silicon substrate, and depositing a second N-type epitaxial layer on the first N-type epitaxial layer; wherein the doping concentration of the first N-type epitaxial layer is lower than the doping concentration of the second N-type epitaxial layer; etching to remove the second N-type epitaxial layer in a target region, and depositing a third N-type epitaxial layer on the second N-type epitaxial layer and the target region; wherein the doping concentration of the third N-type epitaxial layer is higher than the doping concentration of the first N-type epitaxial layer, and the doping concentration of the third N-type epitaxial layer is lower than the doping concentration of the second N-type epitaxial layer, and the target region is a terminal region; etching the first N-type epitaxial layer, the second N-type epitaxial layer and the third N-type epitaxial layer to form a trench; wherein the trench comprises an active region trench and a terminal region trench; forming a bottom oxide layer in the trench by thermal growth and deposition, depositing polysilicon on the surface of the bottom oxide layer, and etching the polysilicon to form a polycrystalline structure; forming an intermediate oxide layer on the polycrystalline structure of the active region trench, forming a gate oxide layer structure on the side wall of the active region trench, filling the active region trench with polysilicon to form a gate polysilicon structure, and forming a shielding oxide layer on the gate polysilicon structure; forming a base region by ion implantation on the third N-type epitaxial layer, and annealing the base region to form an implantation shielding layer between the active region trench and the terminal region trench; forming a source region by ion implantation on the third N-type epitaxial layer, and annealing the source region to form a dielectric oxide layer on the source region, forming a metal electrode contact hole on the dielectric oxide layer, performing contact region implantation and annealing on the metal electrode contact hole, and forming a source electrode, a gate electrode and a cutoff electrode on the metal electrode contact hole; forming a passivation structure on the source electrode, the gate electrode and the cutoff electrode, and forming a drain electrode below the silicon substrate.

2. The method of claim 1, wherein, The doping concentration of the first N-type epitaxial layer ranges from 1.0E15 to 7.5E15 cm -3 ; The doping concentration of the second N-type epitaxial layer ranges from 2.0E16 to 7.5E16 cm -3 ; The third N-type epitaxial layer has a doping concentration ranging from 5.0E15 to 2.5E16 cm -3 .

3. The method of claim 1, wherein, The depth of the trench is 3-7 μm; The width of the trench is 0.5-2.0 μm; The thickness of the bottom oxide layer is 0.4-0.9 μm; The thickness of the intermediate oxide layer is 0.3-0.6 μm; The thickness of the gate oxide layer structure is 0.04-0.09 μm; The thickness of the shielding oxide layer is 0.05-0.1 μm.

4. The method of claim 1, wherein, Forming a base region by ion implantation on the third N-type epitaxial layer, and annealing the base region, comprises: The ion implantation has an implantation energy of 60-150 KeV and an implantation dose of 0.6E13-1.5E13 cm -2 ; The annealing temperature of the annealing is 1000-1150 ℃, and the annealing time is 30-120 min.

5. The method of claim 1, wherein, Forming a source region by ion implantation on the third N-type epitaxial layer, and annealing the source region to form a dielectric oxide layer on the source region, comprises: The ion implantation is arsenic ion implantation; The annealing temperature of the annealing is 950-1000 ℃, and the annealing time is 90-120 min.

6. The method of claim 1, wherein, Performing contact region implantation and annealing on the metal electrode contact hole, comprises: BF2 implantation is performed on the metal electrode contact hole; the implantation energy of the BF2 implantation is 60-80 KeV, and the implantation dose is 3E14-5E14 cm -2 ; The annealing temperature of the annealing is 900-1000 ℃, and the annealing time is 20-30 min.

7. The method of claim 1, wherein, Forming a source electrode, a gate electrode and a cutoff electrode on the metal electrode contact hole, comprises: Depositing an AlSiCu metal layer on the metal electrode contact hole, and forming a source electrode, a gate electrode and a stop electrode through a photoetching and etching process; wherein the thickness of the AlSiCu metal layer is 4-6 μm.

8. The method of claim 1, wherein, Forming a passivation structure on the source electrode, the gate electrode and the stop electrode, and forming a drain electrode below the silicon substrate, comprising: Depositing a passivation layer on the source electrode, the gate electrode and the stop electrode, and forming a passivation structure through a photoetching and etching process; Evaporating a metal layer below the silicon substrate to form a drain electrode; wherein the metal layer comprises any one of Ti, Ni and Ag.

9. A power semiconductor structure, characterized by The power semiconductor structure is prepared by the power semiconductor preparation method of any one of claims 1-8, comprising a substrate, a first epitaxial layer, a second epitaxial layer and a third epitaxial layer; The first epitaxial layer is arranged on the substrate; The second epitaxial layer is arranged on the first epitaxial layer, and the width of the second epitaxial layer is smaller than that of the first epitaxial layer; The third epitaxial layer is arranged on the first epitaxial layer and the second epitaxial layer; A trench is formed on the first epitaxial layer, the second epitaxial layer and the third epitaxial layer; An electrode structure is arranged on the trench.

10. The power semiconductor structure of claim 9, wherein, The trench comprises an active region trench and a termination region trench; The active region trench is formed on the first epitaxial layer, the second epitaxial layer and the third epitaxial layer; The termination region trench is formed on the first epitaxial layer and the third epitaxial layer; The doping concentration of the first epitaxial layer is lower than that of the second epitaxial layer; The doping concentration of the third epitaxial layer is higher than that of the first epitaxial layer.

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