Cell structure of MOSFET device and preparation method thereof

Abstract

The present application discloses a cell structure of a MOSFET device and a preparation method thereof, wherein the cell structure comprises: a substrate; a first epitaxial layer, the first epitaxial layer having a first surface on a side away from the substrate, the first epitaxial layer having a first doping type; a first doping region, located in the first epitaxial layer, the first doping region being formed by ion implantation from the first surface toward the substrate, the first surface having a plurality of spacing regions where the first doping region is not formed, the first doping region being located between any two adjacent spacing regions; a second epitaxial layer, located on the first surface, the second epitaxial layer at least covering a portion of the first doping region, the doping concentration of the second epitaxial layer being lower than the doping concentration of the first doping region, the first doping region or the second epitaxial layer having a plurality of protrusions. The doping configuration below the channel and the channel width are optimized, and the forward conduction characteristics of the MOS device are improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor devices, and in particular, to a cell structure of a MOSFET device, a preparation method, a MOSFET device, and a layout of a MOSFET device. Background Art

[0002] The channel width of conventional planar gate field-effect transistor (MOSFET, Meta-Oxide-Semiconductor Field-Effect Transistor, referred to as MOS) devices is only distributed on the surface of part of the active area, and the forward conduction characteristics of MOS devices are poor. In addition, the gate's ability to control the drain current through the channel depends on the gate voltage, gate capacitance, and the doping concentration of the well region. The effect of the gate voltage on the channel of conventional planar gate effect transistors will cause different changes in the potential at the channel due to different well region doping, resulting in reduced gate control ability and thus poor conduction characteristics. Summary of the invention

[0003] The present application provides a cell structure of a MOSFET device, a preparation method, a MOSFET device and a layout of a MOSFET device to solve the problem in the related art that the gate voltage control capability of the MOS device is reduced and the channel width is insufficient, thereby resulting in poor forward conduction characteristics of the MOS device.

[0004] According to one aspect of the present application, a cell structure of a MOSFET device is provided, comprising: a substrate having a first doping type; a first epitaxial layer located on one side of the substrate, the first epitaxial layer having a first surface on a side facing away from the substrate, and the first epitaxial layer having a first doping type; a first doped region located in the first epitaxial layer, the first doped region being formed by ion implantation from the first surface toward the substrate, the first surface having a plurality of spacing regions where the first doped region is not formed, the first doped region being located between any two adjacent spacing regions, and the first doped region having a second doping type; a second epitaxial layer located on the first surface, the second epitaxial layer at least covering a portion of the first doped region, the second epitaxial layer having a second doping type, a doping concentration of the second epitaxial layer being lower than a doping concentration of the first doped region, and the first doped region or the second epitaxial layer having a plurality of protrusions.

[0005] According to another aspect of the present application, a method for preparing a cell structure of a MOSFET device is provided, comprising: providing a substrate, the substrate having a first doping type; forming a first epitaxial layer on one side of the substrate, the first epitaxial layer having a first surface on a side facing away from the substrate, the first epitaxial layer having a first doping type; ion implanting in the first epitaxial layer to form a first doping region, the first surface having a plurality of spacing regions where the first doping region is not formed, the first doping region being located between any two adjacent spacing regions, the first doping region having a second doping type; forming a second epitaxial layer on the first surface, the second epitaxial layer at least covering a portion of the first doping region, the second epitaxial layer having a second doping type, the doping concentration of the second epitaxial layer being lower than the doping concentration of the first doping region, the first doping region or the second epitaxial layer having a plurality of protrusions.

[0006] According to another aspect of the present application, a MOSFET device is provided, including at least one cell structure of the MOSFET device.

[0007] According to another aspect of the present application, a layout of a MOSFET device is provided, including at least one cell structure of the MOSFET device.

[0008] A cell structure of a MOSFET device provided by the present application includes a substrate, a first epitaxial layer, a first doped region, and a second epitaxial layer, wherein a first doped region and a second epitaxial layer are formed on the first epitaxial layer, ion implantation is performed on the first epitaxial layer to form a first doped region, and then epitaxy is performed on the first doped region to form a second epitaxial layer, the first doped region or the second epitaxial layer has a plurality of protrusions, and the doping concentration of the second epitaxial layer is lower than the doping concentration of the first doped region, the doping configuration under the channel is optimized, the transfer characteristics are improved, the gate control capability is improved, and in addition, the channel width perpendicular to the surface of the cell region is increased, thereby improving the problem of poor forward conduction characteristics of the MOS device. The problem of poor transfer characteristics and insufficient channels of the MOS device in the related art, which leads to poor forward conduction characteristics of the MOS device, is solved. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The drawings constituting a part of the present application are used to provide a further understanding of the present application. The illustrative embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0010] Figure 1 is a schematic cross-sectional structure diagram of a cell structure of a first MOSFET device provided in an embodiment of the present application;

[0011] Figure 2 is a schematic cross-sectional structure diagram of a cell structure of a second MOSFET device provided in an embodiment of the present application;

[0012] Figure 3 is a schematic diagram of a top view of a cell structure of a first MOSFET device provided in an embodiment of the present application;

[0013] Figure 4 is a schematic cross-sectional structure diagram of a cell structure of a third MOSFET device provided in an embodiment of the present application;

[0014] Figure 5 is a schematic cross-sectional structure diagram of a cell structure of a fourth MOSFET device provided according to an embodiment of the present application;

[0015] Figure 6 is a schematic diagram of a top view of a cell structure of a second MOSFET device provided in an embodiment of the present application;

[0016] Figure 7 is a schematic diagram of a top view of a cell structure of a third MOSFET device provided in an embodiment of the present application;

[0017] Figure 8 is a schematic diagram of a top view of a cell structure of a fourth MOSFET device provided in an embodiment of the present application;

[0018] Fig. 9 is a schematic cross-sectional structural diagram of a cell structure of a fifth MOSFET device provided according to an embodiment of the present application;

[0019] Fig.10 is a schematic cross-sectional structure diagram of a cell structure of a sixth MOSFET device provided according to an embodiment of the present application;

[0020] Fig.11 It is a schematic flow chart of a method for preparing a cell structure of a MOSFET device provided in an embodiment of the present application;

[0021] Fig.12 It is a cross-sectional schematic diagram of a base body after providing a substrate, and forming a buffer layer and a first epitaxial layer on the substrate in a method for preparing a cell structure of a MOSFET device provided in an embodiment of the present application;

[0022] Fig.13 is Fig.12 A schematic diagram of a top view structure of a substrate after a first doped region is formed in a first epitaxial layer formed in the substrate;

[0023] Fig.14 is Fig.13 A schematic diagram of the cross-sectional structure of the substrate after forming a convex portion of the first doped region, forming a second epitaxial layer thereon, forming a second doped region and a third doped region in the first doped region, and forming a JFET region in the second epitaxial layer;

[0024] Fig.15 is Fig.14 A schematic diagram of a cross-sectional structure of a substrate after a gate structure is formed on the second epitaxial layer formed in the process and a first conductive layer is formed on the second doping region and the third doping region;

[0025] Fig.16 is Fig.15 A schematic diagram of a cross-sectional structure of a substrate after a second conductive layer is formed on the JFET region in the structure and a third conductive layer is formed on the other side of the substrate;

[0026] Fig.17 is Fig.12 A schematic diagram of the cross-sectional structure of the substrate after forming a first doped region and a second epitaxial layer in the first epitaxial layer formed in the substrate, forming a protrusion on part of the second epitaxial layer, and forming a first conductive layer on the second doped region and the third doped region;

[0027] Fig.18 is Fig.17 A schematic cross-sectional structure diagram of a substrate after a gate structure is formed on the second epitaxial layer formed in the step of forming the substrate, and a first conductive layer is formed on the second doping region and the third doping region;

[0028] Fig.19 is Fig.18 A schematic diagram of a cross-sectional structure of a substrate after a second conductive layer is formed on the JFET region in the structure and a third conductive layer is formed on the other side of the substrate;

[0029] Fig. 20 is Fig.12 A schematic diagram of the cross-sectional structure of the substrate after forming a first doped region and a first sub-epitaxial layer in a first epitaxial layer formed by one of the above methods, forming a convex portion on a portion of the first sub-epitaxial layer, and forming a second sub-epitaxial layer, a first conductive layer, a gate structure, a second conductive layer, and a third conductive layer;

[0030] Fig.21 is Fig.12 A schematic diagram of the cross-sectional structure of the substrate after forming a first doped region and a first sub-epitaxial layer in another formed first epitaxial layer and forming a convex portion on a portion of the first sub-epitaxial layer;

[0031] Fig. 22 is Fig.12 A schematic diagram of the cross-sectional structure of the substrate after forming a first doped region and a first sub-epitaxial layer in another formed first epitaxial layer and forming a convex portion on a portion of the first sub-epitaxial layer;

[0032] Fig.23 It is a schematic diagram of the layout structure of a MOSFET device provided according to an embodiment of the present application;

[0033] Fig.24It is a schematic diagram of the layout structure of another MOSFET device provided according to an embodiment of the present application;

[0034] Fig.25 It is a schematic diagram of the layout structure of another MOSFET device provided according to an embodiment of the present application.

[0035] The above drawings include the following reference numerals:

[0036] 10. substrate; 20. first epitaxial layer; 30. first doped region; 40. second epitaxial layer; 41. first sub-epitaxial layer; 42. second sub-epitaxial layer; 50. raised portion; 51. prepared raised portion region; 60. buffer layer; 70. gate structure; 71. first portion; 72. second portion; 73. gate oxide layer; 74. gate; 80. JFET region; 81. first overlapping region; 90. second doped region; 100. third doped region; 110. first conductive layer; 120. second conductive layer; 130. third conductive layer. DETAILED DESCRIPTION

[0037] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0038] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0039] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0040] As mentioned in the background technology, during the operation of the SiC body diode, there may be a recombination process of electrons and holes, which can easily cause the expansion of silicon carbide material defects, causing device characteristics to degrade and affecting the device's service life. In addition, the channel width of conventional field effect transistor devices is not large enough, and the forward conduction characteristics of MOS devices are poor. To this end, the present application proposes a cell structure of a MOSFET device, a preparation method, a MOSFET device, and a layout of a MOSFET device.

[0041] In order to solve the above technical problems, according to an embodiment of the present application, a MOSFET device cell structure is provided. Figure 1 and Figure 2 is a cross-sectional schematic diagram of a cell structure of a MOSFET device according to an embodiment of the present application. Figure 1 and Figure 2 As shown, it includes: a substrate 10, having a first doping type; a first epitaxial layer 20, located on one side of the substrate 10, the first epitaxial layer 20 has a first surface on the side away from the substrate 10, and the first epitaxial layer 20 has a first doping type; a first doping region 30, located in the first epitaxial layer 20, the first doping region 30 is formed by ion implantation from the first surface toward the substrate 10, the first surface has a plurality of spacing regions where the first doping region 30 is not formed, the first doping region 30 is located between any two adjacent spacing regions, and the first doping region 30 has a second doping type; a second epitaxial layer 40, located on the first surface, the second epitaxial layer 40 at least covers a portion of the first doping region 30, the second epitaxial layer 40 has a second doping type, the doping concentration of the second epitaxial layer 40 is lower than the doping concentration of the first doping region 30, and the first doping region 30 or the second epitaxial layer 40 has a plurality of protrusions 50.

[0042] The cell structure of the MOSFET device includes a substrate, a first epitaxial layer, a first doped region and a second epitaxial layer, wherein the first doped region and the second epitaxial layer are formed on the first epitaxial layer, ion implantation is performed on the first epitaxial layer to form the first doped region, and then the second epitaxial layer is formed on the first doped region by epitaxy, so that the first doped region has an independently controllable doping concentration, optimizes the doping configuration under the channel, improves the transfer characteristics, and improves the gate control capability. The first doped region or the second epitaxial layer has a plurality of protrusions, so that the gate of the MOS device is arranged in the horizontal and vertical directions of the protrusions, thereby increasing the channel width of the MOS device and improving the forward conduction characteristics of the MOS device. The problem of low gate voltage control capability and insufficient channel of the MOS device in the related art, which leads to poor forward conduction characteristics of the MOS device, is solved.

[0043] In the above optional implementation, if Figure 1 and Figure 2As shown, a buffer layer 60 may be provided between the substrate 10 and the first epitaxial layer 20. Figure 1 As shown, the first doping region 30 has a protrusion 50, and the second epitaxial layer 40 covers the first doping region 30. The doping concentration of the second epitaxial layer 40 can be 1E16~5E17cm -3 The thickness (implantation depth) can be 0.01 μm~1 μm, and the doping ions can be P-type doping ions such as aluminum ions. The second epitaxial layer 40 is prepared on the first doping region 30 by the epitaxial method, which avoids the interface state problems caused by ion implantation (such as surface roughness, hanging parts, carbon clusters, implantation damage, etc.), improves the channel mobility of the MOS device, reduces the carbon vacancy concentration of the second epitaxial layer 40, and improves the carbon vacancy leakage problem; the second epitaxial layer 40 is prepared by the epitaxial method, the doping controllability of the second epitaxial layer 40 is strong, and the doping concentration distribution is uniform, which is convenient for the regulation of the threshold. In addition, it provides the possibility for the vertical arrangement of the channel.

[0044] Specifically, the second epitaxial layer at least covers part of the first doped region, and the second epitaxial layer has an opening so that the conductive layer in the MOS device contacts the first doped layer through the opening to form an ohmic contact. The first doped region has a non-uniform doping concentration, and the doping concentration of the first doped region as a protrusion is lower than the doping concentration of the first doped region in other regions. The doping concentration of the first doped region with low doping concentration is 1E16cm -3 ~5E18cm -3 The doping concentration of the first doping region with high doping concentration is 5E19cm -3 ~1E20cm -3 .

[0045] In the above optional implementation, if Figure 2 As shown, the second epitaxial layer 40 has a protrusion 50. In this case, the doping concentration of the second epitaxial layer 40 may be 1E16-5E17 cm -3 , with a thickness of 0.01μm~1μm. The gate of the MOS device is set in the horizontal and vertical directions of the above-mentioned protrusion, thereby increasing the channel width of the MOS device and improving the forward conduction characteristics of the MOS device. The first doping region has a non-uniform doping concentration. The doping concentration of the first doping region 30 near the channel of the protrusion 50 of the second epitaxial layer 40 is lower than the doping concentration of the first doping region 30 not near the channel. The region near the channel has a lower, independently controllable doping concentration, which optimizes the doping configuration below the channel, improves the transfer characteristics, and improves the gate control capability.

[0046] Since the doping concentration of the second epitaxial layer is uniform and easy to control, the concentration gradient in the thickness direction is almost zero, and the first doping region has the above-mentioned non-uniform doping concentration. The transition from the second epitaxial layer to the first doping region will reduce the overall concentration and concentration gradient of the second epitaxial layer and the first doping region within a certain depth in the thickness direction of the channel position. When the gate is forward biased, a depletion layer will be formed in the second epitaxial layer and the first doping region below the channel. The amount of charge in the depletion layer will affect the threshold voltage of the channel, thereby affecting the transfer characteristics of the device; in the prior art, when the gate is forward biased, a depletion layer will be formed in the well region doping region below the channel. Since the injection concentration of the well region doping region is not well controlled, the doping concentration gradient may be relatively large, resulting in a relatively large concentration in the range of the depletion layer depth in the thickness direction. When the thickness of the depletion layer is 0.5 μm, the concentration and concentration gradient of the depletion layer in the prior art will be respectively greater than the overall concentration and concentration gradient of the second epitaxial layer and the first doping region of the present application. Therefore, compared with the prior art, the threshold voltage of the present application will be lower, the channel pressure will be reduced, and the transfer characteristics of the device will be better improved.

[0047] In the above optional implementation, the substrate may be a silicon carbide substrate, specifically 4H-SiC, with a doping concentration of 5E18~1E21cm -3 , thickness is 50~500μm, the buffer layer material can be silicon carbide, and the doping concentration can be 5E15~1E19cm -3 The thickness can be 1 ~50μm; the first epitaxial layer can be an N-type silicon carbide epitaxial layer, the doping ions can be N-type doping ions such as nitrogen ions, and the doping concentration can be 1E14~5E17cm -3 , the thickness can be 5~150μm; the first doping region is P-type doped, the doping ions can be P-type doping ions such as aluminum ions, and the doping concentration of the first doping region can be 1E16~1E20cm -3 .

[0048] In the above optional embodiment, the doping concentration of the second epitaxial layer is lower than the doping concentration of the first doping region. The first doping region serving as the region protrusion and the first doping region in other regions have non-uniform doping concentrations, and have a lower and independently controllable doping concentration near the channel, thereby further optimizing the doping configuration below the channel, improving the transfer characteristics, and enhancing the gate voltage's ability to control the channel.

[0049] In some optional embodiments, such as Figure 1 and Figure 2 As shown, the cell structure further includes a gate structure 70 , which is located on the side of the second epitaxial layer 40 facing away from the substrate 10 . The gate structure 70 includes a first portion 71 and a second portion 72 . The first portion 71 protrudes from the protrusion 50 , and the second portion 72 is located between adjacent protrusions 50 .

[0050] In the above optional implementation, if Figure 1 and Figure 2 As shown, a gate structure 70 is arranged on the second epitaxial layer 40, a first portion 71 of the gate structure 70 is located in the horizontal direction of the device (the side of the protrusion 50 away from the substrate 10), and a second portion 72 of the gate structure 70 is located in the vertical direction of the device (along the protrusion extension direction of the protrusion 50), thereby increasing the channel width of the MOS device and improving the forward MOS conduction characteristics of the device. The gate structure 70 further includes a gate oxide layer 73 and a gate 74, wherein the material of the gate oxide layer 73 may be silicon oxide and silicon dioxide, and the gate 74 may be polysilicon.

[0051] In some optional embodiments, the first doped region has a first projection on the first surface, and the projection of the gate structure on the first surface is located in the first projection.

[0052] In the above optional embodiment, the first part protrudes from the raised portion, the second part is located between adjacent raised portions, and the setting area of ​​the first doped region is larger than the setting area of ​​the gate structure, so that the projection of the gate structure on the first surface is located in the first projection, and the first doped region wraps the gate structure, which can improve the electric field distribution between the gate and the drain of the MOS device, avoid the generation of gate-drain capacitance, and thus improve the high-frequency switching characteristics of the MOS device, and also improve the electric field at the gate oxide layer, thereby improving the reliability of the gate oxide layer. In addition, the first doped region wraps the gate structure and can also perform field shielding on the gate structure, reduce the short-circuit channel effect, and improve the short-circuit characteristics.

[0053] In some optional embodiments, such as Figures 3 to 5 As shown, the MOSFET device further includes a plurality of JFET regions 80 , at least some of the JFET regions 80 are located in the spacing regions in a one-to-one correspondence, and some of the second portions 72 are located on a side of the JFET region 80 away from the first doping region 30 .

[0054] In the above optional implementation, Figure 4 and Figure 5 In the case where the second epitaxial layer 40 has a protruding portion and the case where the first doping region 30 has a protruding portion, respectively, Figure 3 A-A' and B-B' cross-sections, and Figure 4 and Figure 5 The channel lengths of the devices in the embodiment are consistent, and the channel length in the BB' direction is narrower than the width of the gate 74; Figure 1 and Figure 2 In the case where the first doping region 30 has a protruding portion and in the case where the second epitaxial layer 40 has a protruding portion, respectively, Figure 3 Cross-sectional view in the C-C' direction. Figures 4 to 5As shown, at least part of the JFET region 80 is located between the first portion 71 of the gate structure 70 and the first doping region 30. In other words, the channel of the MOS device at the first portion 71 protrudes from the first doping region 30, and the entire channel between the gate structure 70 and the second epitaxial layer 40 is retained. If the channel does not protrude from the first doping region 30, the channel will be "killed" due to the high doping concentration of the first doping region 30, which will reduce the flow channel of the current. The doping concentration of the JFET region 80 can be 5E15~1E19cm -3 The thickness can be 0.5-3 μm. The JFET region 80 can be formed by epitaxial growth or ion implantation. Figure 4 In order to show the device cross-section diagram formed by using the process of digging holes in the second epitaxial layer 40 , the second epitaxial layer 40 in other regions except the protruding portion may also be etched. Figure 5 2 is a cross-sectional view of a device formed by etching the first doping region 30 in areas other than the protruding portion, and may also be formed by digging holes in the first doping region 30 .

[0055] In the above optional implementation, from Figure 3 The local enlarged view in the dotted frame can show a first overlapping region 81 between the gate structure 70 and the JFET region 80 (which may also be absent and is not specifically limited), the JFET region 80 and the first doping region 30 may have a second overlapping region (not shown in the figure), and the projection of the gate structure 70 on the first surface is located in the first projection, that is, the first doping region 30 wraps up the bottom of the gate structure 70, plays a field shielding role for the gate structure 70, improves the electric field at the gate oxide layer 73, and improves the reliability of the gate oxide layer 73.

[0056] In some optional embodiments, such as Figures 3 to 5 As shown, the cell structure also includes: a second doping region 90 and at least a third doping region 100, wherein: at least part of the second doping region 90 and at least part of the third doping region 100 are located in the second epitaxial layer 40, and at least part of the second doping region 90 and at least part of the third doping region 100 are located on the side of the first doping region 30 away from the substrate 10; the projection of the second doping region 90 on the first surface is located in the first projection, part of the second part is located on the side of the second doping region 90 away from the first doping region 30, and the second doping region 90 has the first doping type; the second doping region 90 is arranged around the third doping region 100, the second doping region 90 is in contact with the third doping region 100, and the third doping region 100 has the second doping type.

[0057] In the above optional implementation, if Figure 3As shown, the second doping region 90 is in contact with the third doping region 100, and the second doping region 90 wraps around the third doping region 100 in a top view. Figures 4 to 5 As shown, at least part of the second doping region 90 is located between the first portion 71 of the gate structure and the first doping region 30, that is, the channel of the MOS device at the first portion 71 protrudes from the first doping region 30, and the entire channel between the gate structure and the second epitaxial layer 40 is retained. By adjusting the parameters of ion implantation, the second doping region 90 can partially penetrate into the first doping region 30.

[0058] In the above optional implementation, the doping ions in the second doping region may be N-type doping ions such as nitrogen ions, and the doping concentration may be 1E18~5E21cm -3 The thickness can be 0.2~1μm, the doping ions in the third doping region can be P-type doping ions such as aluminum ions, and the doping concentration can be 5E17~5E21cm -3 , the thickness can be 0.2~2μm.

[0059] In the above optional implementation, the second epitaxial layer is relatively thin and has a low doping concentration, thereby avoiding the punch-through problem between the JFET region and the second doped region, and the punch-through problem between the JFET region and the second epitaxial layer, caused by the second epitaxial layer being too thick.

[0060] In some optional embodiments, such as Figure 6 to Figure 7 As shown, the combined projection pattern of the third doping region 100 and the second doping region 90 on the first surface is a centrally symmetrical pattern.

[0061] In the above optional implementation, if Figure 6 As shown, the third doping region 100 can also be circular in top view and located in the central area of ​​the second doping region 90; Figure 7 As shown, the third doping region 100 can also be a circle or a plurality of rectangle-like combination patterns when viewed from above.

[0062] In some optional embodiments, such as Figures 3 to 7 As shown, the cell structure further includes: a first conductive layer 110 , and the first conductive layer 110 covers the third doping region 100 and a portion of the second doping region 90 .

[0063] In the above optional implementation, if Figures 3 to 7As shown, there is also an isolation oxide layer (not shown in the figure) between the gate structure and the first conductive layer 110, the isolation oxide layer covers the gate structure, the JFET region 80, the second doping region 90 and the third doping region 100, the first conductive layer 110 is in contact with the second doping region 90 through a through hole penetrating the isolation oxide layer, and the first conductive layer 110 is in contact with the third doping region 100 through a through hole penetrating the isolation oxide layer to form an ohmic contact. There is a gap between the first conductive layer 110 and the gate structure, and the above gap can be 0.3~1.5μm.

[0064] In some optional embodiments, such as Figures 8 to 10 As shown, the cell structure further includes: a plurality of second conductive layers 120 , and the second conductive layers 120 cover a partial area of ​​each of the plurality of JFET regions 80 in a one-to-one correspondence.

[0065] In the above optional implementation, if Figures 8 to 10 As shown, the isolation oxide layer also covers the JFET region 80, and the second conductive layer 120 contacts the JFET region through the through hole penetrating the isolation oxide layer to form a Schottky contact. The material of the second conductive layer 120 can be Ti, Ni and other materials and alloys thereof. The second conductive layer 120 will form a Schottky electrode after annealing. The MOS device and the Schottky diode share the resistance of the JFET region, the resistance of the first epitaxial layer 20 and the resistance of the substrate 10, and part of the current path is shared. In addition, the integration of the Schottky diode in the MOS device can have the characteristics of lower forward conduction voltage drop and fast reverse recovery.

[0066] The on-resistance of a MOSFET device mainly includes the source region resistance, the channel region resistance, the JFET region resistance, the drift region resistance, and the substrate resistance, etc. The on-resistance of a Schottky diode mainly includes the JFET region resistance, the drift region resistance, and the substrate resistance, etc. Therefore, the present application uses the JFET region resistance, the first epitaxial layer resistance, and the substrate resistance as a common material, and the Schottky diode formed by the Schottky contact and the MOS device formed by the ohmic contact are both connected to the first epitaxial layer through the second epitaxial layer of the JFET region, and the third doped region is in contact with the second doped region and connected to the first doped region.

[0067] like Figure 1 to Figure 2 , Figures 4 to 5 and Figures 9 and 10 As shown, the MOSFET device further includes a third conductive layer 130, which is located on the side of the substrate 10 away from the first epitaxial layer 20. The material of the third conductive layer 130 can be Ag, Au, etc., or a composite material of Cu, Ti and Ni.

[0068] According to another aspect of the present application, a method for preparing a cell structure of a MOSFET device is provided, such as Fig.11As shown, including:

[0069] Step S101: providing a substrate, wherein the substrate has a first doping type;

[0070] Step S102: forming a first epitaxial layer on one side of the substrate, wherein the first epitaxial layer has a first surface on a side facing away from the substrate, and the first epitaxial layer has a first doping type;

[0071] Step S103: ion implantation is performed in the first epitaxial layer to form a first doped region, the first surface has a plurality of spacing regions where the first doped region is not formed, the first doped region is located between any two adjacent spacing regions, and the first doped region has a second doping type;

[0072] Step S104: forming a second epitaxial layer on the first surface, the second epitaxial layer at least covering a portion of the first doped region, the second epitaxial layer having a second doping type, a doping concentration of the second epitaxial layer lower than a doping concentration of the first doped region, and the first doped region or the second epitaxial layer having a plurality of protrusions.

[0073] The cell structure of the above-mentioned MOSFET device prepared by the above-mentioned preparation method has a first doped region formed by ion implantation on the first epitaxial layer, and a second epitaxial layer formed by epitaxy on the first doped region, so that the first doped region has an independently controllable doping concentration, optimizes the doping configuration below the channel, and improves the transfer characteristics; the above-mentioned first doped region or the second epitaxial layer has a plurality of protrusions, so that the gate of the MOS device is set in the horizontal and vertical directions of the above-mentioned protrusions, thereby increasing the channel width of the MOS device and improving the forward conduction characteristics of the MOS device.

[0074] The exemplary embodiments of the method for preparing the cell structure of the MOSFET device provided by the present invention will be described in more detail below in conjunction with the accompanying drawings. However, these exemplary embodiments can be implemented in a variety of different forms and should not be interpreted as being limited to the embodiments described herein. It should be understood that these embodiments are provided to make the disclosure of this application thorough and complete, and to fully convey the concepts of these exemplary embodiments to those of ordinary skill in the art.

[0075] First, if Fig.12 As shown, step S102 is performed: providing a substrate 10, wherein the substrate 10 has a first doping type.

[0076] Specifically, the substrate 10 may be silicon carbide, specifically 4H-SiC, with a doping concentration of 2E18-1E21cm -3 , thickness is 50~500μm.

[0077] After the step of providing a substrate, as Fig.12As shown, step S102 is performed: a first epitaxial layer 20 is formed on one side of the substrate 10 , the first epitaxial layer 20 has a first surface on a side facing away from the substrate 10 , and the first epitaxial layer 20 has a first doping type.

[0078] Specifically, before forming the first epitaxial layer 20, a buffer layer 60 may be formed on one side of the substrate 10. The doping concentration of the buffer layer 60 may be 5E15-2E19 cm -3 The first epitaxial layer 20 may be an N-type silicon carbide epitaxial layer, and the doping ions may be N-type doping ions such as nitrogen ions, and the doping concentration may be 1E14~5E17cm -3 , the thickness can be 5~150μm.

[0079] After the step of forming the first epitaxial layer, as Fig.13 As shown, step S103 is performed: ion implantation is performed in the first epitaxial layer 20 to form a first doping region 30, and a plurality of spacing regions where the first doping region 30 is not formed are provided in the first surface, and the first doping region 30 is located between any two adjacent spacing regions, and the first doping region 30 has a second doping type. The spacing region is a region divided on the first surface except for the first doping region 30, and other structures will be formed in this region later.

[0080] After the step of forming the first doping region, Figures 13 to 19 As shown, step S104 is performed: a second epitaxial layer 40 is formed on the first surface, the second epitaxial layer 40 at least covers a portion of the first doping region 30, the second epitaxial layer 40 has a second doping type, the doping concentration of the second epitaxial layer 40 is lower than the doping concentration of the first doping region 30, and the first doping region 30 or the second epitaxial layer 40 has a plurality of protrusions 50.

[0081] In some optional embodiments, such as Fig.13 and Fig.14 As shown, in the case where the first doping region 30 has a plurality of protrusions, the steps of forming the second epitaxial layer 40 include: forming a first preliminary doping region in the first epitaxial layer 20 using an ion implantation process; etching the first epitaxial layer 20 and a portion of the first preliminary doping region so that the first preliminary doping region has a plurality of protrusions 50 to form the first doping region 30, and the first doping region 30 has a non-uniform doping concentration; forming the second epitaxial layer 40 on the first surface, and the second epitaxial layer 40 covers the protrusions 50.

[0082] In the above optional implementation, if Fig.13 As shown, the four corner regions of the first epitaxial layer 20 where the first doping region 30 is not formed are multiple spacing regions when viewed from the top. Fig.14As shown, the viewing angles of A-A', B-B' and C-C' are respectively Fig.13 The cross-sectional view in the directions of AA', BB' and CC' after the protrusion 50 is formed in the first doping region 30. The doping concentration of the second epitaxial layer 40 can be 1E16~5E17cm -3 The implantation depth can be 0.01-2 μm. The height of the protrusion 50 is 0.1-3 μm, the width of the protrusion is 0.3-1.5 μm, and the minimum distance between the two protrusions is not less than 0.5 μm.

[0083] In some optional embodiments, the step of forming the first doping region includes: etching the first epitaxial layer and a portion of the first preliminary doping region so that the first preliminary doping region has a plurality of protrusions; epitaxially forming a third epitaxial layer on the first preliminary doping region having the plurality of protrusions, and forming a second preliminary doping region in the third epitaxial layer using an ion implantation process, the first preliminary doping region and the second preliminary doping region form a first doping region, and the doping concentration of the second preliminary doping region is lower than the doping concentration of the first preliminary doping region.

[0084] In the above optional embodiment, the first doping region has a non-uniform doping concentration. The first epitaxial layer and part of the first preliminary doping region are first etched to form a protrusion in the first preliminary doping region, and a third epitaxial layer is formed on the protrusion. The third epitaxial layer covers the first preliminary doping region with the protrusion. Ions are implanted into the third epitaxial layer to form a second preliminary doping region. The first preliminary doping region and the second preliminary doping region are the first doping region as a whole. The doping concentration of the second preliminary doping region is lower than the doping concentration of the first preliminary doping region. The first preliminary doping region and the second preliminary doping region form a first doping region with a non-uniform concentration. A second epitaxial layer is then formed on the second preliminary doping region so that the second epitaxial layer also has the morphology of the protrusion.

[0085] In some optional embodiments, such as Fig.15 As shown, after forming the second epitaxial layer 40, the preparation method also includes: forming a second doping region 90, a JFET region 80 and a third doping region 100 in the first epitaxial layer 20 and the second epitaxial layer 40, the projection of the second doping region 90 on the first surface is located in the projection of the first doping region 30 on the first surface, the second doping region 90 is arranged around the third doping region 100, the second doping region 90 is in contact with the third doping region 100, the combined projection pattern of the third doping region 100 and the second doping region 90 on the first surface is a centrally symmetrical pattern, at least part of the JFET region 80 is located in the spacing region in a one-to-one correspondence, and the third doping region 100 has a second doping type; forming a gate structure 70 on the side of the second epitaxial layer 40 away from the first doping region 30, so that the first part 71 of the gate structure 70 protrudes from the protrusion, and the second part 72 of the gate structure 70 is located between adjacent protrusions.

[0086] In the above optional implementation, the JFET region can be formed by an ion implantation process or an epitaxial growth process, and a thin carbon film is covered on the formed first doping region, the second doping region and the JFET region, and the carbon film is annealed at a temperature of 1600° C. to 1800° C. to activate the doped ions in the second doping region, the third doping region and the JFET region. Fig.15 As shown, the gate oxide layer 73 can be formed by a process of deposition followed by thermal oxidation. The gate oxide layer 73 can adopt SiO2 process and the thickness can be 30~70nm. Polysilicon can be deposited on the gate oxide layer 73 to form a gate 74, wherein the gate 74 can be polysilicon and the thickness can be 400~1000nm. Doping is required to adjust the threshold voltage and gate resistance. The first portion 71 of the gate structure 70 protrudes from the raised portion 50, and the second portion 72 of the gate structure 70 is located between adjacent raised portions 50. At the A-A' viewing angle, the gate oxide layer 73 is located between the gate 74 and the second epitaxial layer 40; at the B-B' viewing angle, part of the first portion 71 is located on the side of the JFET region 80 and the second doped region 90 facing away from the substrate 10, and the second portion (not shown in B-B', blocked by the first doped region 30) is located between the JFET region 80 and the second doped region 90; at the CC' viewing angle, the first portion 71 is located on the side of the second epitaxial layer 40 facing away from the substrate 10, and the second portion 72 is located between the protruding features of adjacent second epitaxial layers 40.

[0087] In the above optional implementation, the doping concentration of the second doping region may be 1E18~5E21cm -3 The implantation depth can be 0.2~1μm. Ions are implanted into the first epitaxial layer to form a JFET region. The doping concentration of the JFET region can be 5E15~1E19cm -3 , the thickness can be 0.3~3μm, and the doping concentration of the third doping region can be 5E17~5E21cm -3 , the injection depth can be 0.2~2μm.

[0088] In some optional embodiments, such as Fig.15 As shown, after the step of forming the gate structure 70, the preparation method further includes: forming an isolation oxide layer (not shown in the figure) on the side of the gate structure 70 facing away from the substrate; patterning the isolation oxide layer located on the side of the second doping region 90 and the third doping region 100 facing away from the substrate 10, so that part of the second doping region 90 and part of the third doping region 100 have a first exposed area; forming a first conductive layer 110 on the side of the isolation oxide layer facing away from the substrate 10, and the first conductive layer 110 covers the first exposed area.

[0089] In the above optional implementation, an isolation oxide layer (not shown) is covered on the MOS device, and holes are opened in the isolation oxide layer on the second doping region 90 and the third doping region 100 so that Fig.15 The first conductive layer 110 formed in the process contacts the second doping region 90 and the third doping region 100, and the first conductive layer 110 is annealed in an inert atmosphere to form an ohmic contact, which serves as the source electrode of the MOS device. The isolation oxide layer can be made of materials such as silicon oxide, silicon dioxide and silicon nitride.

[0090] In some optional embodiments, such as Fig.16 As shown, after the step of forming the isolation oxide layer, the preparation method further includes: patterning the isolation oxide layer located on the side of the JFET region 80 away from the substrate 10 so that part of the JFET region 80 has a second exposed area; forming a second conductive layer 120 on the side of the isolation oxide layer away from the JFET region 80, the second conductive layer 120 covering the second exposed area; and forming a third conductive layer 130 on the side of the isolation oxide layer away from the substrate 10.

[0091] In the above optional implementation, the isolation oxide layer is opened in part of the JFET region, a second conductive layer is deposited, and annealed to form a Schottky electrode, so that a Schottky diode is integrated in the MOS device. The third conductive layer is annealed in an inert atmosphere to form a drain electrode of the MOS device.

[0092] In some optional embodiments, such as Fig.17 As shown, in the case where the second epitaxial layer 40 has a plurality of protrusions 50, the steps of forming the second epitaxial layer 40 include: forming a second preliminary epitaxial layer on the side of the first doping region 30 away from the substrate 10; opening holes in the second preliminary epitaxial layer to obtain a second epitaxial layer 40 having a plurality of groove areas, wherein the second epitaxial layer 40 between adjacent groove areas is the protrusion 50; or etching the second preliminary epitaxial layer to obtain a second epitaxial layer 40 having a plurality of protrusions 50.

[0093] In the above optional implementation, when the second epitaxial layer has a plurality of protrusions, there are two situations in which the protrusions are formed. The first situation is: the other second preliminary epitaxial layers except the protrusions to be retained are etched away so that the retained second epitaxial layer forms the protrusions. Fig.17 The second situation is: the second preliminary epitaxial layer is etched to form a plurality of spaced grooves in the second epitaxial layer, and the second epitaxial layer between adjacent grooves is a convex portion. In this situation, the second epitaxial layer 40 at the A-A' perspective is a flat second epitaxial layer 40, without Fig.17 The bulge in the .

[0094] In the above optional implementation, if Fig.18 As shown, after the second epitaxial layer 40 is formed by etching, the preparation method further includes: forming a JFET region 80 in the first epitaxial layer 20 and the second epitaxial layer 40, forming a second doping region 90 and a third doping region 100 in the second epitaxial layer 40, the projection of the second doping region 90 on the first surface is located in the projection of the first doping region 30 on the first surface, the second doping region 90 is arranged around the third doping region 100, and the second doping region 90 is in contact with the third doping region 100, the combined projection pattern of the third doping region 100 and the second doping region 90 on the first surface is a centrally symmetrical pattern, at least part of the JFET region 80 is located in the spacing region in a one-to-one correspondence, and part of the JFET region 80 will exceed the spacing region and be located on the first doping region 30, and the third doping region 100 has a second doping type; forming a gate structure 70 on the side of the second epitaxial layer 40 away from the first doping region 30, so that the first part 71 of the gate structure 70 protrudes from the protrusion 50, and the second part 72 of the gate structure 70 is located between adjacent protrusions 50.

[0095] In the above optional implementation, if Fig.19 As shown, after the step of forming the gate structure 70, the preparation method also includes: forming an isolation oxide layer on the side of the gate structure 70 away from the substrate 10; patterning the isolation oxide layer located on the side of the second doping region 90 and the third doping region 100 away from the substrate 10, so that part of the second doping region 90 and part of the third doping region 100 have a first exposed area; forming a first conductive layer 110 on the side of the isolation oxide layer away from the substrate 10, and the first conductive layer 110 covers the first exposed area.

[0096] In the above optional implementation, if Fig.19 As shown, after the step of forming the isolation oxide layer, the preparation method further includes: patterning the isolation oxide layer located on the side of the JFET region 80 away from the substrate 10 so that part of the JFET region 80 has a second exposed area; forming a second conductive layer 120 on the side of the isolation oxide layer away from the JFET region 80, the second conductive layer 120 covering the second exposed area; and forming a third conductive layer 130 on the side of the isolation oxide layer away from the substrate 10. Figures 14 to 19 The method used is to etch away the area outside the protruding portion 50 of the first doped region 30 or the second epitaxial layer 40 .

[0097] In some optional embodiments, such as Fig. 20As shown, the step of forming the second epitaxial layer 40 further includes: forming a first sub-prepared epitaxial layer on the side of the first doped region 30 away from the substrate 10; opening the first sub-prepared epitaxial layer to obtain a first sub-epitaxial layer 41 having a plurality of groove regions, wherein the first sub-epitaxial layer 41 between adjacent groove regions is a protrusion 50; or etching the first sub-prepared epitaxial layer to obtain a first sub-epitaxial layer 41 having a plurality of protrusions 50 (this solution Fig. 20 The second sub-epitaxial layer 42 is formed on the surface of the first sub-epitaxial layer 41 away from the substrate 10 by an epitaxial growth process. The first sub-epitaxial layer 41 and the second sub-epitaxial layer 42 constitute the second epitaxial layer 40. The first sub-epitaxial layer 41 and the second sub-epitaxial layer 42 have the second doping type. The doping concentration of the second sub-epitaxial layer 42 is lower than the doping concentration of the first sub-epitaxial layer 41.

[0098] In the above optional implementation, if Fig. 20 As shown in (a), the step of forming the second epitaxial layer 40 further includes: forming a first sub-prepared epitaxial layer on the side of the first doping region 30 away from the substrate 10, and performing a hole opening or etching process on the first sub-prepared epitaxial layer, ( Fig. 20 The schematic diagram shows a scheme of opening holes) to obtain the protrusion 50. The steps of opening holes or etching are the same as the steps of opening holes and etching the second epitaxial layer 40 to form the protrusion 50. The opening of the first sub-prepared epitaxial layer can be referred to. Figure 4 FIG. 4 is a schematic diagram of opening a hole in the second epitaxial layer 40. Fig. 20 As shown in (b), a gate structure 70 is formed on the second epitaxial sub-layer 42, a first conductive layer 110 is formed on the second doping region 90 and the third doping region 100, a second conductive layer 120 is formed on the JFET region 80, and a third conductive layer 130 is formed on the back of the substrate 10. The above steps are consistent with the above description and are not repeated here. The doping concentration of the first epitaxial sub-layer 41 can be 1E16~5E17cm -3 , the thickness is 0.01~0.3μm, and the doping concentration of the second epitaxial layer 42 can be 5E15~2E17cm -3 , thickness is 0.1 ~2μm.

[0099] In some optional embodiments, such as Fig.21As shown, the step of forming the second epitaxial layer 40 also includes: forming a first sub-preparatory epitaxial layer on the side of the above-mentioned first doping region 30 away from the substrate 10; performing ion implantation on the first sub-preparatory epitaxial layer to form a preliminary raised portion region 51; forming a second sub-preparatory epitaxial layer on the side of the first sub-preparatory epitaxial layer away from the substrate 10 by an epitaxial growth process; opening holes in the second sub-preparatory epitaxial layer and the first sub-preparatory epitaxial layer to obtain a second sub-epitaxial layer 42 and a first sub-epitaxial layer 41 having a plurality of groove regions, the first sub-epitaxial layer 41 and the second sub-epitaxial layer 42 constitute the second epitaxial layer 40, and the preliminary raised portion region 51 between adjacent groove regions is a raised portion 50.

[0100] In the above optional implementation, if Fig.21 As shown, the low-concentration second epitaxial layer 40 wraps the high-concentration protrusion 50, the second epitaxial layer 40 forms a channel, and the doping concentration of the second sub-epitaxial layer 42 is the same as the doping concentration of the first sub-epitaxial layer 41 or there is a small concentration difference, so that the channel on the top and side wall of the protrusion 50 can be opened at approximately the same time.

[0101] In the above optional implementation, if Fig. 22 As shown, the step of forming the protrusion 50 in the first sub-epitaxial layer 41 may include: forming a first sub-prepared epitaxial layer on the side of the first doping region 30 away from the substrate 10; ion implanting the first sub-prepared epitaxial layer to form a preparatory protrusion region 51, wherein the doping concentration of the preparatory protrusion region 51 is higher than that of the first sub-prepared epitaxial layer; opening the first sub-prepared epitaxial layer to obtain a plurality of groove regions, wherein the preparatory protrusion region 51 between adjacent groove regions is the protrusion 50. Then, an epitaxial growth process is used to form a second sub-epitaxial layer 42 on the surface of the protrusion 50 and the groove region, wherein the first sub-epitaxial layer 41 and the second sub-epitaxial layer 42 constitute the second epitaxial layer 40; and the second sub-epitaxial layer 42 and the first sub-epitaxial layer 41 have the same or different doping concentrations.

[0102] When the hole is opened, the first preliminary epitaxial sub-layer can be completely etched away, and the second epitaxial sub-layer can be formed on the surface of the protruding portion 50 and the first doping region 30 .

[0103] Fig.21 and Fig. 22 Only the preparation process of the C-C' cross section is shown in the figure. For the formation process of other cross sections, please refer to the description of other figures.

[0104] According to another aspect of the present application, a MOSFET device is provided, including at least one cell structure of the MOSFET device.

[0105] According to another aspect of the present application, a layout of a MOSFET device is provided, such as Fig.23As shown, the cell structure of at least one MOSFET device is included. The figure is only for illustration, and more cell structures may be included. The structure in the red dotted box is the channel of the layout, and the channel structure may also be circular or elliptical, without specific limitation.

[0106] like Fig.24 and Fig.25 As shown, based on the above MOS device, a trench can also be formed in the first doping region 30. In other words, Fig.23 On the basis of the cell structure, a groove is set at the first doping region 30 at the edge of each cell structure, and then a second epitaxial layer is set on the first doping region 30, and ion implantation is performed on the second epitaxial layer to form a JFET region 80, so that part of the JFET region 80 fills the groove of the first doping region 30, and multiple cell structures are formed. Fig.24 and Fig.25 The layout in the circuit increases the width of the device channel and enhances the current conduction capability of the MOS device. Fig.24 The middle one is the layout structure with only MOS devices. Fig.25 The layout structure of a MOS device with an integrated Schottky diode.

[0107] Example 1

[0108] The present application proposes a method for preparing a MOS device, comprising the following steps:

[0109] Provide a substrate, the substrate is silicon carbide, has a thickness of 200 μm, and a doping concentration of 1E19 cm -3 ;

[0110] A buffer layer and a first epitaxial layer are formed on the first surface of the substrate. The buffer layer is made of silicon carbide with a doping concentration of 1E18 cm -3 , with a thickness of 1 μm; the first epitaxial layer is silicon carbide, and the doping concentration can be 1E16cm -3 , thickness is 10 μm;

[0111] Ions are implanted on the surface of the first epitaxial layer away from the substrate to form a patterned first doped region. The first epitaxial layer and part of the first doped region are etched so that the first doped region has a plurality of protrusions. The surface of the first epitaxial layer having the protrusions is called the third surface. The doping concentration of the first doped region is 1E20 cm -3 , the injection depth is 5 μm, the height of the protrusion is 1 μm, the width of the protrusion is 0.3 μm, and the distance between two adjacent protrusions is 0.5 μm;

[0112] A second epitaxial layer is epitaxially grown on the third surface of the first epitaxial layer, wherein the doping concentration of the second epitaxial layer is 1E16 cm -3, thickness is 0.5 μm;

[0113] Ion implantation is performed on the second epitaxial layer to form a JFET region, a second doping region and a third doping region. The second doping region and part of the third doping region are located on the side of the first doping region away from the substrate, and part of the third doping region is located in the second epitaxial layer. Part of the JFET region is located in the first epitaxial layer, and the other part is located in the second epitaxial layer. The doping concentration is 3E16cm -3 , the implantation depth is 1 μm; the doping concentration of the second doping region is 1E21 cm -3 , the implantation depth is 0.5 μm, and the doping concentration of the third doping region is 1E20 cm -3 , the implantation depth is 1 μm;

[0114] Covering the second epitaxial layer, the JFET region, the second doping region and the third doping region with a carbon film, and performing annealing at 1800° C. to activate doping ions;

[0115] A gate oxide layer and a polysilicon layer are formed on the side of the second epitaxial layer away from the substrate by a deposition process, the polysilicon layer is used as the gate electrode of the MOS device, the gate oxide layer is silicon dioxide with a thickness of 50nm, and the gate is polysilicon with a thickness of 800nm;

[0116] Depositing an isolation oxide layer on the gate, wherein the isolation oxide layer covers the JFET region, the second doping region and the third doping region;

[0117] Opening holes in the isolation oxide layer at the second doping region and the third doping region;

[0118] Forming a first conductive layer on the second doping region and the third doping region, performing annealing, so that the first conductive layer forms an ohmic contact with the second doping region and the third doping region to form a source electrode of the MOS device, wherein the material of the first conductive layer is Ti;

[0119] Opening a hole in the isolation oxide layer of the JFET region, forming a second conductive layer on the JFET region, and performing an annealing process, so that the second conductive layer forms a Schottky contact with the JFET region, wherein the material of the second conductive layer is Ti;

[0120] A third conductive layer is formed on a side of the substrate away from the first epitaxial layer, and annealing is performed to form a drain electrode of the MOS device. The material of the third conductive layer is Ti.

[0121] Example 2

[0122] The present application proposes a method for preparing a MOS device, comprising the following steps:

[0123] Provide a substrate, the substrate is silicon carbide, has a thickness of 200 μm, and a doping concentration of E19 cm -3 ;

[0124] A buffer layer and a first epitaxial layer are formed on the first surface of the substrate. The buffer layer is made of silicon oxide with a doping concentration of 1E18 cm -3 , with a thickness of 1 μm; the first epitaxial layer is silicon carbide, and the doping concentration can be 1E16cm -3 , thickness is 10 μm;

[0125] Ion implantation is performed on the surface of the first epitaxial layer away from the substrate to form a first doped region, epitaxial growth is performed on the side of the first doped region away from the first epitaxial layer to form a second epitaxial layer, and ion implantation is performed on the second epitaxial layer to form a JFET region, a second doped region, and a third doped region, wherein the second doped region and a portion of the third doped region are located on the side of the first doped region away from the substrate, and a portion of the third doped region is located in the second epitaxial layer; wherein a portion of the JFET region is located in the first epitaxial layer, and another portion is located in the second epitaxial layer, and the doping concentration is 3E16cm -3 , the implantation depth is 1 μm; the doping concentration of the second doping region is 1E21 cm -3 , the implantation depth is 0.5 μm, and the doping concentration of the third doping region is 1E20 cm -3 , the implantation depth is 1 μm;

[0126] The region of the second epitaxial layer between the JFET region and the second doping region that has not been implanted is opened to obtain a plurality of groove regions, and the second epitaxial layer between adjacent groove regions is a convex portion. The doping concentration of the first doping region is 1E20cm -3 The implantation depth is 5 μm, and the doping concentration of the second epitaxial layer is 1E16 cm -3 , the thickness is 0.5μm, the height of the protrusion is 1um, the width of the protrusion is 0.3μm; the distance between the two protrusions is 0.5μm;

[0127] Covering the second epitaxial layer, the JFET region, the second doping region and the third doping region with a carbon film, and performing annealing at 1800° C. to activate doping ions;

[0128] A gate oxide layer and a polysilicon layer are formed on the side of the second epitaxial layer away from the substrate by a deposition process, the polysilicon layer is used as the gate electrode of the MOS device, the gate oxide layer is silicon dioxide with a thickness of 50nm, and the gate is polysilicon with a thickness of 800nm;

[0129] Depositing an isolation oxide layer on the gate, wherein the isolation oxide layer covers the JFET region, the second doping region and the third doping region;

[0130] Opening holes in the isolation oxide layer at the second doping region and the third doping region;

[0131] Forming a first conductive layer on the second doping region and the third doping region, performing annealing, so that the first conductive layer forms an ohmic contact with the second doping region and the third doping region to form a source electrode of the MOS device, wherein the material of the first conductive layer is Ti;

[0132] Opening a hole in the isolation oxide layer of the JFET region, forming a second conductive layer on the JFET region, and performing an annealing process, so that the second conductive layer forms a Schottky contact with the JFET region, wherein the material of the second conductive layer is Ti;

[0133] A third conductive layer is formed on a side of the substrate away from the first epitaxial layer, and annealing is performed to form a drain electrode of the MOS device. The material of the third conductive layer is Ti.

[0134] Example 3

[0135] The present application proposes a method for preparing a MOS device, comprising the following steps:

[0136] Provide a substrate, the substrate is silicon carbide, has a thickness of 200 μm, and a doping concentration of 1E19 cm -3 ;

[0137] A buffer layer, a first epitaxial layer and a JFET region are formed on the first surface of the substrate, wherein the buffer layer is made of silicon carbide with a doping concentration of 1E18 cm -3 , with a thickness of 1 μm; the first epitaxial layer is silicon carbide, and the doping concentration can be 1E16cm -3 , with a thickness of 10 μm. The JFET region is located on the side of the groove region away from the second doping region. Part of the JFET region is located in the first epitaxial layer, and the other part is located in the second epitaxial layer. The doping concentration is 3E16 cm -3 , the implantation depth is 1 μm;

[0138] Ions are implanted into the first epitaxial layer to form a first doped region, epitaxial growth is performed on the side of the first doped region away from the first epitaxial layer to form a second epitaxial layer, and the second epitaxial layer is etched to obtain a plurality of protrusions, wherein the doping concentration of the first doped region is 1E20 cm -3 The implantation depth is 5 μm, and the doping concentration of the second epitaxial layer is 1E16 cm -3 , the injection depth is 0.5 μm, the height of the protrusion is 1 μm, the width of the protrusion is 0.3 μm, and the distance between two adjacent protrusions is 0.5 μm;

[0139] Ion implantation is performed on the second epitaxial layer to form a second doping region and a third doping region, wherein the second doping region and part of the third doping region are located on the side of the first doping region away from the substrate, and part of the third doping region is located in the second epitaxial layer, wherein the doping concentration of the second doping region is 1E21cm -3, the implantation depth is 0.5 μm, and the doping concentration of the third doping region is 1E20 cm -3 , the implantation depth is 1 μm;

[0140] Covering the second epitaxial layer, the JFET region, the second doping region and the third doping region with a carbon film, and performing annealing at 1800° C. to activate doping ions;

[0141] A gate oxide layer and a polysilicon layer are formed on the side of the second epitaxial layer away from the substrate by a deposition process, the polysilicon layer is used as the gate electrode of the MOS device, the gate oxide layer is silicon dioxide with a thickness of 50nm, and the gate is polysilicon with a thickness of 800nm;

[0142] Depositing an isolation oxide layer on the gate, wherein the isolation oxide layer covers the JFET region, the second doping region and the third doping region;

[0143] Opening holes in the isolation oxide layer at the second doping region and the third doping region;

[0144] Forming a first conductive layer on the second doping region and the third doping region, performing annealing, so that the first conductive layer forms an ohmic contact with the second doping region and the third doping region to form a source electrode of the MOS device, wherein the material of the first conductive layer is Ti;

[0145] Opening a hole in the isolation oxide layer of the JFET region, forming a second conductive layer on the JFET region, and performing an annealing process, so that the second conductive layer forms a Schottky contact with the JFET region, wherein the material of the second conductive layer is Ti;

[0146] A third conductive layer is formed on a side of the substrate away from the first epitaxial layer, and annealing is performed to form a drain electrode of the MOS device. The material of the third conductive layer is Ti.

[0147] Example 4

[0148] The present application proposes a method for preparing a MOS device, comprising the following steps:

[0149] Provide a substrate, the substrate is silicon carbide, has a thickness of 200 μm, and a doping concentration of 1E19 cm -3 ;

[0150] A buffer layer and a first epitaxial layer are formed on the first surface of the substrate. The buffer layer is made of silicon carbide with a doping concentration of 1E18 cm -3 , with a thickness of 1 μm; the first epitaxial layer is silicon carbide, and the doping concentration can be 1E16cm -3 , thickness is 10 μm;

[0151] Ions are implanted on the surface of the first epitaxial layer away from the substrate to form a patterned first doped region, and a first sub-epitaxial layer is formed by epitaxial growth on the side of the first doped region away from the first epitaxial layer. A hole is opened in the region of the second epitaxial layer between the JFET region and the second doped region where no implantation is performed to obtain a plurality of groove regions. The first sub-epitaxial layer between adjacent groove regions is a protrusion. The surface of the first sub-epitaxial layer having the protrusion is called the third surface. The height of the protrusion is 1 um, the width of the protrusion is 0.3 μm, the spacing between two adjacent protrusions is 0.5 μm, the thickness of the first sub-epitaxial layer is 0.3 μm, and the doping concentration is 1E16 cm -3 ;

[0152] A second sub-epitaxial layer is formed on the third surface of the first sub-epitaxial layer to obtain a second epitaxial layer, and ion implantation is performed on the second epitaxial layer and the first sub-epitaxial layer to form a JFET region, a second doping region, and a third doping region, wherein the second doping region and a portion of the third doping region are located on a side of the first doping region away from the substrate, and a portion of the third doping region is located in the second epitaxial layer, wherein a portion of the JFET region is located in the first epitaxial layer, and another portion is located in the second epitaxial layer, and the doping concentration is 3E16cm -3 , the implantation depth is 1 μm, and the doping concentration of the second doping region is 1E21 cm -3 , the implantation depth is 0.5 μm, and the doping concentration of the third doping region is 1E20 cm -3 The implantation depth is 1 μm, and the doping concentration of the first doping region is 1E20 cm -3 The implantation depth is 5 μm, and the doping concentration of the second epitaxial layer is 5E15 cm -3 , the implantation depth is 0.7 μm;

[0153] Covering the second epitaxial layer, the JFET region, the second doping region and the third doping region with a carbon film, and performing annealing at 1800° C. to activate doping ions;

[0154] A gate oxide layer and a polysilicon layer are formed on the side of the second epitaxial layer away from the substrate by a deposition process, the polysilicon layer is used as the gate electrode of the MOS device, the gate oxide layer is silicon dioxide with a thickness of 50nm, and the gate is polysilicon with a thickness of 800nm;

[0155] Depositing an isolation oxide layer on the gate, wherein the isolation oxide layer covers the JFET region, the second doping region and the third doping region;

[0156] Opening holes in the isolation oxide layer at the second doping region and the third doping region;

[0157] Forming a first conductive layer on the second doping region and the third doping region, performing annealing, so that the first conductive layer forms an ohmic contact with the second doping region and the third doping region to form a source electrode of the MOS device, wherein the material of the first conductive layer is Ti;

[0158] Opening a hole in the isolation oxide layer of the JFET region, forming a second conductive layer on the JFET region, and performing an annealing process, so that the second conductive layer forms a Schottky contact with the JFET region, wherein the material of the second conductive layer is Ti;

[0159] A third conductive layer is formed on a side of the substrate away from the first epitaxial layer, and annealing is performed to form a drain electrode of the MOS device. The material of the third conductive layer is Ti.

[0160] Example 5

[0161] The present application discloses a method for preparing a MOS device, comprising the following steps:

[0162] Provide a substrate, the substrate is silicon carbide, has a thickness of 200 μm, and a doping concentration of 1E19 cm -3 ;

[0163] A buffer layer, a first epitaxial layer and a JFET region are formed on the first surface of the substrate, wherein the buffer layer is made of silicon carbide with a doping concentration of 1E18 cm -3 , with a thickness of 1 μm; the first epitaxial layer is silicon carbide, and the doping concentration can be 1E16cm -3 , with a thickness of 10 μm. The JFET region is located on the side of the groove region away from the second doping region, and the doping concentration is 3E16 cm -3 , the implantation depth is 1 μm;

[0164] Ion implantation is performed in the first epitaxial layer to form a first doped region, epitaxial growth is performed on the side of the first doped region away from the first epitaxial layer to form a first sub-epitaxial layer, and the first sub-epitaxial layer is etched to obtain a plurality of protrusions, wherein the doping concentration of the first doped region is 1E20cm -3 The implantation depth is 5 μm, the thickness of the first epitaxial layer is 0.3 μm, and the doping concentration is 1E16 cm -3 , the height of the protrusion is 1um, the width of the protrusion is 0.3μm, and the distance between two adjacent protrusions is 0.5μm;

[0165] A second sub-epitaxial layer is epitaxially grown on the first sub-epitaxial layer, and ion implantation is performed on the second sub-epitaxial layer to form a second doping region and a third doping region, wherein the second doping region and a portion of the third doping region are located on a side of the first doping region away from the substrate, and a portion of the third doping region is located in the second epitaxial layer, wherein the doping concentration of the second doping region is 1E21cm -3, the implantation depth is 0.5 μm, and the doping concentration of the third doping region is 1E20 cm -3 The implantation depth is 1 μm, and the doping concentration of the second epitaxial layer is 5E15 cm -3 , the implantation depth is 0.7 μm;

[0166] Covering the second epitaxial layer, the JFET region, the second doping region and the third doping region with a carbon film, and performing annealing at 1800° C. to activate doping ions;

[0167] A gate oxide layer and a polysilicon layer are formed on the side of the second epitaxial layer away from the substrate by a deposition process, the polysilicon layer is used as the gate electrode of the MOS device, the gate oxide layer is silicon dioxide with a thickness of 50nm, and the gate is polysilicon with a thickness of 800nm;

[0168] Depositing an isolation oxide layer on the gate, wherein the isolation oxide layer covers the JFET region, the second doping region and the third doping region;

[0169] Opening holes in the isolation oxide layer at the second doping region and the third doping region;

[0170] Forming a first conductive layer on the second doping region and the third doping region, performing annealing, so that the first conductive layer forms an ohmic contact with the second doping region and the third doping region to form a source electrode of the MOS device, wherein the material of the first conductive layer is Ti;

[0171] Opening a hole in the isolation oxide layer of the JFET region, forming a second conductive layer on the JFET region, and performing an annealing process, so that the second conductive layer forms a Schottky contact with the JFET region, wherein the material of the second conductive layer is Ti;

[0172] A third conductive layer is formed on a side of the substrate away from the first epitaxial layer, and annealing is performed to form a drain electrode of the MOS device. The material of the third conductive layer is Ti.

[0173] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0174] 1) The cell structure of the MOSFET device of the present application includes a substrate, a first epitaxial layer, a first doped region and a second epitaxial layer, wherein the first doped region and the second epitaxial layer are formed on the first epitaxial layer, ion implantation is performed on the first epitaxial layer to form the first doped region, and then the second epitaxial layer is formed on the first doped region by epitaxy, and the first doped region or the second epitaxial layer has a plurality of protrusions, so that the gate of the MOS device is arranged in the horizontal and vertical directions of the protrusions, thereby increasing the channel width of the MOS device and improving the forward conduction characteristics of the MOS device. The problem of insufficient channel width of the MOS device in the related art and thus poor forward conduction characteristics of the MOS device is solved.

[0175] 2) The first part of the gate structure of the cell structure of the MOSFET device of the present application protrudes from the protrusion, and the second part is located between adjacent protrusions, and the setting area of ​​the first doped region is larger than the setting area of ​​the gate structure, so that the projection of the gate structure on the first surface is located in the first projection, which greatly reduces the gate-drain capacitance and thus improves the switching characteristics of the MOS device; it also improves the electric field distribution at the gate oxide layer and improves the reliability of the gate oxide layer; and the first doped region can also perform field shielding on the gate structure, optimize the potential distribution in the channel region of the MOS device, suppress the short channel effect, and improve the short circuit characteristics.

[0176] 3) The first doping region of the cell structure of the MOSFET device of the present application has a non-uniform doping concentration, wherein the near-channel has a lower, independently controllable doping concentration, which optimizes the doping configuration below the channel, making the channel easy to open and improving the transfer characteristics. The above-mentioned optimized doping distribution avoids the punch-through problem of the bipolar junction transistor (BJT) parasitic in the MOSFET between the JFET region, the second epitaxial layer and the second doping region caused by the second epitaxial layer being too thick.

[0177] 4) The cell structure of the MOSFET device of the present application adopts the epitaxial method to prepare the second epitaxial layer, which avoids the interface state problems caused by ion implantation (surface roughness, hanging parts, carbon clusters, implantation damage, etc.), improves the channel mobility, reduces the carbon vacancy concentration of the second epitaxial layer, and improves the carbon vacancy leakage problem; the second epitaxial layer is prepared by the epitaxial method, the doping of the second epitaxial layer is highly controllable, the doping concentration distribution is uniform, and the threshold value is easy to control. In addition, it provides the possibility for the vertical arrangement of the channel.

[0178] 5) A second conductive layer is deposited on part of the JFET region of the cell structure of the MOSFET device of the present application so that a Schottky diode is integrated in the MOS device. The second conductive layer is annealed to form a Schottky electrode. The MOS device and the Schottky diode share the JFET region resistance, the first epitaxial layer resistance and the substrate resistance, and part of the current path is shared. Since the Schottky diode has a lower forward conduction voltage drop and a fast reverse recovery characteristic, the forward MOS device conduction characteristic and the reverse Schottky diode conduction characteristic are improved.

[0179] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0180] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the claims of the present application.

Claims

1. A cell structure of a MOSFET device, characterized in that: include: a substrate having a first doping type; A first epitaxial layer, located at one side of the substrate, the first epitaxial layer having a first surface on a side away from the substrate, and the first epitaxial layer having a first doping type; A first doped region is located in the first epitaxial layer, the first doped region is formed by ion implantation from the first surface toward the substrate, the first surface has a plurality of spacing regions where the first doped region is not formed, the first doped region is located between any two adjacent spacing regions, and the first doped region has a second doping type; A second epitaxial layer is located on the first surface, the second epitaxial layer at least covers a portion of the first doped region, the second epitaxial layer has a second doping type, the doping concentration of the second epitaxial layer is lower than the doping concentration of the first doped region, and the first doped region or the second epitaxial layer has a plurality of protrusions.

2. The cellular structure according to claim 1, characterized in that: The cell structure further includes a gate structure, which is located on a side of the second epitaxial layer away from the substrate. The gate structure includes a first portion and a second portion, wherein the first portion protrudes from the protrusions, and the second portion is located between adjacent protrusions.

3. The cellular structure according to claim 2, characterized in that: The first doped region has a first projection in the first surface, and the projection of the gate structure on the first surface is located in the first projection.

4. The cellular structure according to claim 2, characterized in that: The cell structure further includes a plurality of JFET regions, at least some of the JFET regions are located in the spacing region in a one-to-one correspondence, and some of the second portions are located on a side of the JFET region away from the first doping region.

5. The cellular structure according to claim 3, characterized in that: The cell structure further includes: a second doping region and at least one third doping region, wherein: At least part of the second doping region and at least part of the third doping region are located in the second epitaxial layer, and at least part of the second doping region and at least part of the third doping region are located on a side of the first doping region away from the substrate; The projection of the second doping region on the first surface is located in the first projection, part of the second part is located on a side of the second doping region away from the first doping region, and the second doping region has a first doping type; The second doping region is disposed around the third doping region, the second doping region is in contact with the third doping region, and the third doping region has a second doping type.

6. The cellular structure according to claim 5, characterized in that: A combined projection pattern of the third doping region and the second doping region on the first surface is a centrally symmetrical pattern.

7. The cellular structure according to claim 5, characterized in that: The cell structure further includes: a first conductive layer, wherein the first conductive layer covers the third doping region and a portion of the second doping region.

8. The cellular structure according to claim 4, characterized in that: The cell structure further includes: a plurality of second conductive layers, wherein the second conductive layers cover a partial area of ​​each of the plurality of JFET regions in a one-to-one correspondence.

9. The cellular structure according to claim 5, characterized in that: The first doping region has a non-uniform doping concentration.

10. A method for preparing a cell structure of a MOSFET device, characterized in that: The preparation method is used to prepare the cellular structure according to any one of claims 1 to 9, and the preparation method comprises: providing a substrate, the substrate having a first doping type; forming a first epitaxial layer on one side of the substrate, wherein the first epitaxial layer has a first surface on a side facing away from the substrate, and the first epitaxial layer has a first doping type; Ion implantation is performed in the first epitaxial layer to form a first doped region, the first surface has a plurality of spacing regions where the first doped region is not formed, the first doped region is located between any two adjacent spacing regions, and the first doped region has a second doping type; A second epitaxial layer is formed on the first surface, the second epitaxial layer at least covers a portion of the first doped region, the second epitaxial layer has a second doping type, the doping concentration of the second epitaxial layer is lower than the doping concentration of the first doped region, and the first doped region or the second epitaxial layer has a plurality of protrusions.

11. The preparation method according to claim 10, characterized in that: In the case where the first doped region has a plurality of protrusions, the step of forming the second epitaxial layer includes: forming a first preliminary doping region in the first epitaxial layer by an ion implantation process; Etching the first epitaxial layer and a portion of the first preliminary doping region so that the first preliminary doping region has a plurality of the protrusions to form a first doping region, wherein the first doping region has a non-uniform doping concentration; The second epitaxial layer is formed on the first surface, and the second epitaxial layer covers the protrusion.

12. The preparation method according to claim 10, characterized in that: In the case where the first doped region has a plurality of protrusions, the step of forming the second epitaxial layer includes: forming a first preliminary doping region in the first epitaxial layer by an ion implantation process; Etching the first epitaxial layer and a portion of the first preliminary doping region so that the first preliminary doping region has a plurality of the protrusions; epitaxially forming a third epitaxial layer on the first preliminary doping region having a plurality of protrusions, and forming a second preliminary doping region in the third epitaxial layer by an ion implantation process, wherein the first preliminary doping region and the second preliminary doping region form the first doping region, and the doping concentration of the second preliminary doping region is lower than the doping concentration of the first preliminary doping region; The second epitaxial layer is formed on the first surface.

13. The preparation method according to claim 10, characterized in that: In the case where the second epitaxial layer has a plurality of protrusions, the step of forming the second epitaxial layer includes: forming a second preliminary epitaxial layer on a side of the first doped region away from the substrate; Opening holes in the second preliminary epitaxial layer to obtain a second epitaxial layer having a plurality of groove regions, wherein the second epitaxial layer between adjacent groove regions is a protrusion; or The second preliminary epitaxial layer is etched to obtain the second epitaxial layer having a plurality of protrusions.

14. The preparation method according to claim 10, characterized in that: In the case where the second epitaxial layer has a plurality of protrusions, the step of forming the second epitaxial layer includes: forming a first sub-preparation epitaxial layer on a side of the first doped region away from the substrate; Opening holes in the first preliminary sub-epitaxial layer to obtain a first sub-epitaxial layer having a plurality of groove regions, wherein the first sub-epitaxial layer between adjacent groove regions is a convex portion; or Etching the first preliminary epitaxial sub-layer to obtain a first epitaxial sub-layer having a plurality of protrusions; A second sub-epitaxial layer is formed on a surface of the first sub-epitaxial layer away from the substrate by an epitaxial growth process, the first sub-epitaxial layer and the second sub-epitaxial layer constitute the second epitaxial layer, the first sub-epitaxial layer and the second sub-epitaxial layer have a second doping type, and the doping concentration of the second sub-epitaxial layer is lower than the doping concentration of the first sub-epitaxial layer.

15. The preparation method according to claim 10, characterized in that: In the case where the second epitaxial layer has a plurality of protrusions, the step of forming the second epitaxial layer includes: forming a first sub-preparation epitaxial layer on a side of the first doped region away from the substrate; Performing ion implantation on the first preliminary epitaxial layer to form a preliminary raised portion region; Forming a second sub-preparation epitaxial layer on a side of the first sub-preparation epitaxial layer away from the substrate by using an epitaxial growth process; The second sub-prepared epitaxial layer and the first sub-prepared epitaxial layer are opened to obtain a second sub-epitaxial layer and a first sub-epitaxial layer having a plurality of groove areas. The first sub-epitaxial layer and the second sub-epitaxial layer constitute the second epitaxial layer, and the prepared raised portion area between adjacent groove areas is the raised portion.

16. The preparation method according to any one of claims 11 to 15, characterized in that: After forming the second epitaxial layer, the preparation method further includes: A second doping region, a JFET region and a third doping region are formed in the first epitaxial layer and the second epitaxial layer, the projection of the second doping region on the first surface is located in the projection of the first doping region on the first surface, the second doping region is arranged around the third doping region, the second doping region is in contact with the third doping region, the combined projection pattern of the third doping region and the second doping region on the first surface is a central symmetrical pattern, at least part of the JFET region is located in the spacing region in a one-to-one correspondence, and the third doping region has a second doping type; A gate structure is formed on a side of the second epitaxial layer away from the first doping region, so that a first portion of the gate structure protrudes from the protrusions, and a second portion of the gate structure is located between adjacent protrusions.

17. The preparation method according to claim 16, characterized in that: After the step of forming the gate structure, the preparation method further comprises: forming an isolation oxide layer on a side of the gate structure facing away from the substrate; Performing patterning on the isolation oxide layer located at a side of the second doping region and the third doping region facing away from the substrate, so that a portion of the second doping region and a portion of the third doping region have a first exposed area; A first conductive layer is formed on a side of the isolation oxide layer facing away from the substrate, and the first conductive layer covers the first exposed area.

18. The preparation method according to claim 17, characterized in that: After the step of forming the isolation oxide layer, the preparation method further comprises: Performing patterning on the isolation oxide layer located at a side of the JFET region away from the substrate so that a portion of the JFET region has a second exposed area; forming a second conductive layer on a side of the isolation oxide layer away from the JFET region, wherein the second conductive layer covers the second exposed area; A third conductive layer is formed on a side of the isolation oxide layer facing away from the substrate.

19. A MOSFET device, characterized in that: A cell structure comprising at least one MOSFET device according to any one of claims 1 to 9.

20. A layout of a MOSFET device, characterized in that: A cell structure comprising at least one MOSFET device according to any one of claims 1 to 9.

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