MOSFET device and method for manufacturing the same

Abstract

The present application discloses a MOSFET device and a preparation method thereof, wherein the MOSFET device comprises: a substrate; a drift layer; a first JFET region extending along a first direction; a first well region located in the drift layer, and the first well region is located on one side of the first JFET region in the first direction; a first doped region located in the first well region, and a portion of the first well region is provided between the first doped region and the first JFET region; a conductive layer at least covers a portion of the first JFET region; and a gate structure at least covers a portion of the first doped region and a portion of the first JFET region. When the MOSFET device is forward-conducted, the current can smoothly flow through the first doped region to the first JFET region, participating in forward conduction; when the current is reversely conducted, the current passes through the conductive layer and enters the first JFET region covered by the conductive layer. By adjusting the first JFET region to have a higher doping concentration, the current can be rapidly expanded, showing the excellent reverse characteristic capability of the MOSFET device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor devices, and in particular, to a MOSFET device and a method for preparing the same. Background Art

[0002] Traditional junction barrier Schottky diode integrated MOSFET devices (JBSFET, Junction Barrier Schottky Diode MOSFET) need to use part of the chip area for Schottky structure because Schottky is integrated inside the chip, which leads to a decrease in the channel density of the device and reduces the power density of the device. There are currently two main types of MOSFET devices with discontinuous structures, one is the conventional non-integrated SiC MOSFET device (CMOS, Conventional Metal Oxide Semiconductor), and the other is the discontinuous SiC integrated Schottky diode SiC MOSFET (JBSFET, Junction Barrier Schottky MOSFET) device. The structural advantage of CMOS is that the well region and the JFET region can conduct electricity, so the current density can be increased, but its structure does not contain Schottky, so the reverse characteristics are poor; the advantage of CJBSFET is that it integrates Schottky diodes and has excellent reverse characteristics, but the JFET region is only used for reverse conduction, and there is little current involved in conduction in the forward direction, which wastes area. Summary of the invention

[0003] The present application provides a MOSFET device and a preparation method thereof, so as to solve the problem in the related art that the MOSFET device cannot have good reverse characteristics and participate in forward conduction at the same time.

[0004] According to one aspect of the present application, a MOSFET device is provided, comprising: a substrate; a drift layer, located on one side of the substrate; a first JFET region, located in the drift layer, the first JFET region extending along a first direction, the first direction being perpendicular to a direction from the substrate to the drift layer; a first well region, located in the drift layer, the first well region being located on one side of the first JFET region in the first direction; a first doped region, located in the first well region, a portion of the first well region being provided between the first doped region and the first JFET region; a conductive layer, covering at least a portion of the first JFET region; and a gate structure, covering at least a portion of the first doped region and the first JFET region.

[0005] Optionally, the MOSFET device also includes a second well region, the second well region is located in the drift layer, the second well region is located on the side of the first JFET region away from the first well region, a portion of the second well region is located on a side of the conductive layer close to the substrate, and the first well region and the second well region have the same doping type.

[0006] Optionally, the MOSFET device also includes a second JFET region, which is located in the drift layer and extends along a second direction, with a portion of the first well region between the first doped region and the second JFET region, the second direction is perpendicular to the first direction and parallel to a surface of the substrate close to the drift layer, and the second JFET region is in contact with the first JFET region.

[0007] Optionally, the MOSFET device further includes a second doped region, a portion of the second doped region is located on a side of the first doped region away from the second JFET region, another portion of the second doped region is located on a side of the first doped region away from the first JFET region, and the second doped region has a second doping type.

[0008] Optionally, the MOSFET device further includes: a third doping region and a fourth doping region, wherein: the third doping region is located in the second well region, a portion of the second well region is between the third doping region and the second JFET region, and the third doping region has a first doping type; the fourth doping region is located in the second well region, a portion of the fourth doping region and the second JFET region have a portion of the second well region between a portion of the fourth doping region and the first JFET region, and another portion of the fourth doping region and the first JFET region have a portion of the second well region between; the third doping region is located on a side of a portion of the fourth doping region away from the first JFET region, and the fourth doping region has a second doping type.

[0009] Optionally, the gate structure includes a first sub-gate structure and a second sub-gate structure, wherein: the first sub-gate structure covers at least another part of the first JFET region and the first well region between the first doped region and the first JFET region, and the first sub-gate structure extends along the first direction; the second sub-gate structure covers at least the second JFET region, the first well region between the first doped region and the second JFET region, and the second well region between the third doped region and the second JFET region, the extension direction of the second sub-gate structure is the same as the extension direction of the second JFET region, and the first sub-gate structure is in contact with the second sub-gate structure.

[0010] Optionally, the MOSFET device further includes a first electrode, a second electrode and a third electrode, wherein: the first electrode is located on a side of the first JFET region away from the conductive layer; the second electrode is located on a side of the conductive layer away from the first JFET region; and the third electrode is located on a side of the substrate away from the drift layer.

[0011] Optionally, the MOSFET device further includes a first electrode, a second electrode and a third electrode, wherein: the first electrode is located on a side of the first JFET region away from the conductive layer; the second electrode is located on a side of the conductive layer away from the first JFET region; and the third electrode is located on a side of the substrate away from the drift layer.

[0012] According to another aspect of the present application, a method for preparing a MOSFET device is provided, comprising: providing a substrate and forming a drift layer on one side of the substrate; forming a first JFET region in the drift layer, the first JFET region extending along a first direction, the first direction being perpendicular to a direction from the substrate to the drift layer; forming a first well region in the drift layer, the first well region being located on one side of the first JFET region in the first direction; forming a first doped region in the first well region, a portion of the first well region being between the first doped region and the first JFET region; and forming a conductive layer on at least a portion of the first JFET region on a side facing away from the substrate.

[0013] Optionally, the preparation method further includes: forming a second JFET region in the drift layer, wherein an extension direction of the second JFET region is perpendicular to the first direction, and the second JFET region is in contact with the first JFET region.

[0014] Optionally, the step of forming a first well region in the drift layer includes: forming a first preparatory well region in the drift layer by an ion implantation process; forming a first doped region in the first preparatory well region by an ion implantation process, a portion of the first doped region has a portion of the first preparatory well region between the second JFET region, and another portion of the first doped region has a portion of the first preparatory well region between the first JFET region, and the first doped region has a first doping type; forming a second doped region in the first preparatory well region by an ion implantation process, a portion of the second doped region is located on a side of the first doped region away from the second JFET region, and another portion is located on a side of the first doped region away from the first JFET region, and the second doped region has a second doping type, and the first preparatory well region after forming the first doped region and the second doped region is the first well region.

[0015] Optionally, the preparation method also includes: forming a second preliminary well region in the drift layer, the second preliminary well region is located on the side of the first JFET region away from the first well region, and the first well region and the second preliminary well region have the same doping type; forming a third doping region in the second preliminary well region by using an ion implantation process, a portion of the second preliminary well region is between the third doping region and the second JFET region, and the third doping region has the first doping type; forming a fourth doping region in the second preliminary well region by using an ion implantation process, a portion of the fourth doping region has a portion of the second preliminary well region between a portion of the fourth doping region and the second JFET region, and another portion of the second preliminary well region has a portion of the first JFET region, the third doping region is located on the side of a portion of the fourth doping region away from the first JFET region, the fourth doping region has the second doping type, and the second preliminary well region after forming the third doping region and the fourth doping region is the second well region.

[0016] A MOSFET device provided by the present application includes a substrate, a drift layer, a first JFET region, a first well region, a first doped region, a conductive layer and a gate structure, wherein a portion of the first well region is provided between the first doped region and the first JFET region, the conductive layer covers a portion of the first JFET region, and the gate structure covers a portion of the first JFET region. When the MOSFET device is forward-conducted, the region covered with the gate structure is a CMOS structure, so that the current can smoothly flow through the first doped region to the first JFET region, thereby suppressing the degradation of the on-resistance and participating in the forward conduction; when the MOSFET device is reverse-conducted, the region covered with the conductive layer is a CJBSFET structure, and the current passes through the conductive layer and enters the first JFET region covered by the conductive layer. Then, by adjusting the first JFET region to have a higher doping concentration, the current can expand more rapidly, showing the excellent reverse characteristic capability of the MOSFET device. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings constituting a part of the present application are used to provide a further understanding of the present application. The illustrative embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0018] Figure 1 is a schematic diagram of a three-dimensional structure of a MOSFET device provided according to an embodiment of the present application;

[0019] Figure 2 is a schematic diagram of a three-dimensional structure of another MOSFET device provided according to an embodiment of the present application;

[0020] Figure 3 is a schematic diagram of a top view of a MOSFET device provided according to an embodiment of the present application;

[0021] Figure 4 yes Figure 2 A top view perspective structural diagram of a three-dimensional schematic diagram of a MOSFET device;

[0022] Figure 5 It is a schematic flow chart of a method for preparing a MOSFET device according to an embodiment of the present application;

[0023] Figure 6 It is a cross-sectional schematic diagram of a base body after providing a substrate and forming a drift layer on the substrate in a method for preparing a MOSFET device provided in an embodiment of the present application;

[0024] Figure 7 is Figure 6 A schematic cross-sectional view of a substrate after a first JFET region and a second JFET region are formed in a drift layer formed in FIG.

[0025] The above drawings include the following reference numerals:

[0026] 10. Substrate; 20. Drift layer; 31. First JFET region; 32. Second JFET region; 41. First well region; 42. Second well region; 51. First doped region; 52. Second doped region; 53. Third doped region; 54. Fourth doped region; 60. Conductive layer; 70. Gate structure; 71. First sub-gate structure; 72. Second sub-gate structure; 73. Gate; 74. Gate oxide layer; 81. First electrode; 82. Second electrode; 83. Third electrode. DETAILED DESCRIPTION

[0027] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0028] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0029] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0030] As mentioned in the background technology, there are two main types of discontinuous structure MOSFET devices in the prior art, one is the conventional non-integrated SiC MOSFET device (CMOS, Conventional Metal Oxide Semiconductor), and the other is the discontinuous SiC integrated Schottky diode SiC MOSFET (JBSFET, Junction Barrier SchottkyMOSFET) device. The structural advantage of CMOS is that the well region and the JFET region can be conductive, so the current density can be increased, but its structure does not contain Schottky, so the reverse characteristics are poor; the advantage of JBSFET is that it integrates Schottky diodes and has excellent reverse characteristics, but the JFET region is only used for reverse conduction, and very little current is involved in conduction in the forward direction, wasting the device area.

[0031] In order to solve the above technical problems, according to an embodiment of the present application, a MOSFET device is provided. Figures 1 to 3 is a cross-sectional schematic diagram of a MOSFET device according to an embodiment of the present application. Figures 1 to 3 As shown, a substrate 10; a drift layer 20, located on one side of the substrate 10; a first JFET region 31, located in the drift layer 20, the first JFET region 31 extends along a first direction X, and the first direction X is perpendicular to the direction from the substrate 10 to the drift layer 20; a first well region 41, located in the drift layer 20, and the first well region 41 is located on one side of the first JFET region 31 in the first direction X; a first doped region 51, located in the first well region 41, with a portion of the first well region 41 between the first doped region 51 and the first JFET region 31; a conductive layer 60, at least covering a portion of the first JFET region 31; a gate structure 70, at least covering a portion of the first doped region 51 and the first JFET region 31.

[0032] By having a part of the first well region between the first doped region and the first JFET region of the above-mentioned MOSFET device, and the conductive layer covering part of the first JFET region, when the MOSFET device is forward-conducted, the current can smoothly flow through the first doped region of the CMOS structure region of the device to the first JFET region, suppressing the degradation of the on-resistance and participating in the forward conduction; when reverse-conducted, the current passes through the conductive layer of the CJBSFET structure region of the device and enters the first JFET region covered by the conductive layer, and the conductive layer is a Schottky metal that contacts the first JFET region to form a Schottky contact, and then by adjusting the first JFET region to have a higher doping concentration, the current can be expanded more rapidly, showing the excellent reverse characteristic capability of the MOSFET device. The problem that the MOSFET device in the related art cannot take into account both having good reverse characteristics and participating in forward conduction is solved.

[0033] In some optional embodiments, such as Figures 1 to 4 As shown, the MOSFET device also includes a second well region 42, which is located in the drift layer 20, and the second well region 42 is located on the side of the first JFET region 31 away from the first well region 41, and part of the second well region 42 is located on the side of the conductive layer 60 close to the substrate 10, and the first well region 41 and the second well region 42 have the same doping type.

[0034] In the above optional implementation, if Figures 1 to 4 As shown, the doping type of the drift layer 20 may be N-type, the doping type of the first doping region 51 may be N-type, the doping type of the first JFET region 31 may be N-type, the doping type of the first well region 41 may be P-type, and the doping type of the second well region 42 may be P-type. Figure 4 As shown, the conductive layer 60 covers a portion of the first JFET region and a portion of the second well region, a Schottky contact is formed between the conductive layer 60 and the first JFET region, and the work function of the conductive layer 60 may be 4.3 eV to 5.5 eV.

[0035] In some optional embodiments, such as Figure 1 As shown, the MOSFET device also includes a second JFET region 32, which is located in the drift layer 20 and extends along the second direction Y. A portion of the first well region 41 is provided between the first doped region 51 and the second JFET region 32. The second direction Y is perpendicular to the first direction X and parallel to a surface of the substrate 10 close to the drift layer 20. The second JFET region 32 is in contact with the first JFET region 31.

[0036] In the above optional implementation, if Figure 1As shown, the second JFET region 32 is connected to the first JFET region 31, and the extension direction of the second JFET region 32 is perpendicular to the extension direction of the first JFET region 31. A portion of the first well region 41 is located between the first JFET region 31 and the first doping region 51, and a portion of the first well region 41 is located between the second JFET region 32 and the first doping region 51. Current flows into the first JFET region 31 and the second JFET region 32 through the first doping region 51 and the first well region 41, and by adjusting the doping concentration of the first JFET region 31, the current can be conducted to the drift layer 20, thereby suppressing the degradation of the on-resistance.

[0037] In some optional embodiments, such as Figure 1 and Figure 2 As shown, the MOSFET device further includes a second doping region 52 , a portion of which is located on a side of the first doping region 51 away from the second JFET region 32 , and another portion of which is located on a side of the first doping region 51 away from the first JFET region 31 , and the second doping region 52 has a second doping type.

[0038] In the above optional implementation, if Figure 1 and Figure 2 As shown, the doping type of the second doping region 52 can be P type, and the second doping region 52 is semi-surrounded by the first doping region 51. The first doping region 51 is arranged on the side of the first well region 41 away from the first JFET region 31, so that when the device is forwardly conducted, the current enters the first JFET region 31 through the first doping region 51 and the first well region 41 located between the first doping region 51 and the first JFET region 31, and the current enters the second JFET region 32 through the first doping region 51 and the first well region 41 located between the first doping region 51 and the second JFET region 32.

[0039] In some optional embodiments, such as Figure 1 and Figure 3 As shown, the MOSFET device also includes: a third doping region 53 and a fourth doping region 54, wherein: the third doping region 53 is located in the second well region 42, a portion of the second well region 42 is provided between the third doping region 53 and the second JFET region 32, and the third doping region 53 has a first doping type; the fourth doping region 54 is located in the second well region 42, a portion of the fourth doping region 54 and the second JFET region 32 have a portion of the second well region 42, and another portion and the first JFET region 31 have a portion of the second well region 42; the third doping region 53 is located on a side of the portion of the fourth doping region 54 away from the first JFET region 31, and the fourth doping region 54 has a second doping type.

[0040] In the above optional implementation, if Figure 1 and Figure 3As shown, the doping type of the third doping region 53 can be N-type, and the doping type of the fourth doping region 54 can be P-type. In the second well region 42, the third doping region 53 is arranged on the side of the fourth doping region 54 away from the first JFET region 31, so that when the device is forward-conducted, the current will not enter the first JFET region 31 through the third doping region 53 and the second well region 42, and then the active region composed of the second well region 42, the third doping region 53 and the fourth doping region 54 is applied to the reverse conduction of the device. Part of the second well region 42 is located between the third doping region 53 and the second JFET region 32, and part of the second well region 42 is located between the fourth doping region 54 and the first JFET region 31.

[0041] It should be noted that Figure 4 Zhongwei Figure 2 , wherein the first well region 41 and the second well region 42 are areas circled by green dashed lines, the first doped region 51 and the fourth doped region 54 are areas filled in red, the second doped region 52 and the third doped region 53 are areas circled by blue frames, and the first JFET region (not shown in the figure) is located between the first well region 41 and the second well region 42, and the first JFET region (not shown in the figure) is covered by the second sub-gate structure (including the gate 73 and the gate oxide layer 74).

[0042] In some optional embodiments, such as Figure 1 , Figure 2 and Figure 4 As shown, the gate structure 70 includes a first sub-gate structure 71 and a second sub-gate structure 72, wherein: the first sub-gate structure 71 at least covers another part of the first JFET region 31 and the first well region 41 located between the first doping region 51 and the first JFET region 31, and the first sub-gate structure 71 extends along the first direction X; the second sub-gate structure 72 at least covers the second JFET region 32, the first well region 41 located between the first doping region 51 and the second JFET region 32, and the second well region 42 located between the third doping region 53 and the second JFET region 32, the extension direction of the second sub-gate structure 72 is the same as the extension direction of the second JFET region 32, and the first sub-gate structure 71 and the second sub-gate structure 72 are in contact.

[0043] In the above optional implementation, if Figure 1 , Figure 2 and Figure 4As shown, a first sub-gate structure 71 covers part of the first JFET region 31, part of the first well region 41 and part of the first doping region 51. More specifically, the structures covered by the first sub-gate structure 71 include: the first JFET region 31, the first well region 41 between the first JFET region 31 and the first doping region 51, the first well region 41 between the second JFET region 32 and the first doping region 51, the first well region 41 between the second JFET region 32 and the third doping region 53, the second well region 42 between the first JFET region 31 and the fourth doping region 54, part of the first doping region 51 and part of the third doping region 53. The extension direction of the first sub-gate structure 71 is consistent with the extension direction of the first JFET region 31, and the second sub-gate structure 72 covers part of the first well region 41, part of the second well region 42, the first doping region 51, the third doping region 53, the fourth doping region 54 and the second JFET region 32. The extension direction of the second sub-gate structure 72 is consistent with the extension direction of the second JFET region 32. The current of the MOS device should flow through the first doped region 51, through the first well region 41, and finally enter the first JFET region 31 and the second JFET region 32, wherein the second JFET region 32 is fully covered by the second sub-gate structure 72 and has excellent forward conductivity, a portion of the top of the first JFET region 31 is covered by the first sub-gate structure 71, and the other portion is covered by the conductive layer 60, and the area of ​​the first JFET region 31 covered by the conductive layer 60 makes up for the defect of the MOS device having a degraded on-resistance.

[0044] In some optional embodiments, such as Figures 2 to 4 As shown, the MOSFET device also includes a first electrode 81, a second electrode 82 and a third electrode 83, wherein: the first electrode 81 is located on the side of the first JFET region 31 away from the conductive layer 60; the second electrode 82 is located on the side of the conductive layer 60 away from the first JFET region 31; the third electrode 83 is located on the side of the substrate 10 away from the drift layer 20.

[0045] In the above optional implementation, if Figures 2 to 4As shown, the first electrode 81 covers the first doping region 51 and the second doping region 52 not covered by the gate structure 70, and the second electrode 82 covers the third doping region 53 and the fourth doping region 54 not covered by the gate structure 70. The third electrode 83 is located on the side of the substrate 10 away from the drift layer 20. When the device is in forward conduction, the current flows into the first doping region 51 through the first electrode 81, and flows through the first well region 41, the first JFET region 31 and the drift layer 20 to the back of the device. The current can also flow through the second electrode 82 into the third doping region 53, the second well region 42, the second JFET region 32 and the drift layer 20 to the back of the device, thereby suppressing the degradation of the on-resistance. When the device is in reverse conduction, the current enters the first JFET region 31 through the conductive layer 60 for reverse conduction, and the first JFET region 31 has high doping, so the current can expand rapidly, thereby showing the excellent reverse characteristic capability of the device.

[0046] When the device is in a reverse bias state, the first well region 41, the first JFET region 31 and the second well region 42 correspond to the first electrode 81, the gate structure 70 (including the gate oxide layer 74 and the gate 73), the conductive layer 60 and the second electrode 82 respectively. In the reverse bias state, the electrodes of the three parts are all 0V, so the first JFET region 31 between the first well region 41 and the second well region 42 can be completely depleted, and the Schottky withstand voltage characteristics of the device are retained. The gate oxide layer 74 includes two parts. The gate oxide layer 74 of the first part is located on the side of the gate 73 close to the substrate 10 (that is, the bottom surface of the gate structure 70), and the gate oxide layer 74 of the second part is the remaining gate oxide layer 74. The thickness of the gate oxide layer 74 of the first part can be 40nm~60nm, and the thickness of the gate oxide layer 74 of the second part can be 0.2μm~1μm. The material of the gate 73 can be N-type doped polysilicon, the thickness can be 0.5μm~1.5μm, and the doping concentration can be 1e 19 ~5e 20 cm -3 .

[0047] According to another aspect of the present application, a method for preparing a MOSFET device is provided, such as Figure 5 As shown, including:

[0048] Step S101: providing a substrate, and forming a drift layer on one side of the substrate;

[0049] Step S102: forming a first JFET region in the drift layer, wherein the first JFET region extends along a first direction, and the first direction is perpendicular to a direction from the substrate to the drift layer;

[0050] Step S103: forming a first well region in the drift layer, wherein the first well region is located at one side of the first JFET region in the first direction;

[0051] Step S104: forming a first doped region in the first well region, with a portion of the first well region between the first doped region and the first JFET region;

[0052] Step S105: forming a conductive layer on at least a portion of the first JFET region on a side facing away from the substrate, and forming a gate structure on at least a first doped region and a portion of the first JFET region on a side facing away from the substrate.

[0053] The MOSFET device prepared by the preparation method has a portion of the first well region between the first doped region and the first JFET region, and the conductive layer covers a portion of the first JFET region. When the MOSFET device is forward-conducted, the current can smoothly flow through the first doped region of the CMOS structure region of the device to the first JFET region, thereby suppressing the degradation of the on-resistance and participating in the forward conduction; when reverse-conducted, the current passes through the conductive layer of the CJBSFET structure region of the device and enters the first JFET region covered by the conductive layer, and then by adjusting the first JFET region to have a higher doping concentration, the current can expand rapidly, showing the excellent reverse characteristic capability of the MOSFET device.

[0054] The exemplary embodiments of the method for preparing a MOSFET device provided according to the present invention will be described in more detail below in conjunction with the accompanying drawings. However, these exemplary embodiments can be implemented in a variety of different forms and should not be interpreted as being limited to the embodiments described herein. It should be understood that these embodiments are provided to make the disclosure of this application thorough and complete, and to fully convey the concepts of these exemplary embodiments to those of ordinary skill in the art.

[0055] First, if Figure 6 As shown, step S101 is performed: providing a substrate 10 , and forming a drift layer 20 on one side of the substrate 10 .

[0056] Specifically, the substrate 10 may be silicon carbide, specifically 4H-SiC. The substrate 10 has a relatively high doping concentration, which may be 5e 18 ~1e 21 cm -3 The thickness of the drift layer 20 is 50-500 μm. The thickness and doping concentration of the drift layer 20 can be changed according to the withstand voltage specification of the device.

[0057] After the step of providing a substrate, as Figure 7 As shown, step S102 is performed: a first JFET region 31 is formed in the drift layer 20 , and the first JFET region 31 extends along a first direction X, and the first direction X is perpendicular to a direction from the substrate 10 to the drift layer 20 .

[0058] In some optional embodiments, such as Figure 7As shown, the preparation method further includes: forming a second JFET region 32 in the drift layer 20 , wherein an extension direction of the second JFET region 32 is perpendicular to the first direction X, and the second JFET region 32 is in contact with the first JFET region 31 .

[0059] In the above optional implementation, if Figure 7 As shown, a photomask and N-type ion implantation may be used to form the first JFET region 31 and the second JFET region 32. The doping concentration of the first JFET region 31 and the second JFET region 32 may be 1e 16 cm -3 ~2e 17 cm -3 , and can be changed according to the actual needs of the device.

[0060] After the steps of forming the first JFET region and the second JFET region in the drift layer are completed, as shown in FIG. Figure 7 , Figure 1 and Figure 2 As shown, step S103 is performed: a first well region 41 is formed in the drift layer 20, and the first well region 41 is located on one side of the first JFET region 31 in the first direction X; a first doped region 51 is formed in the first well region 41, and a portion of the first well region 41 is between the first doped region 51 and the first JFET region 31; and a conductive layer 60 is formed on at least a portion of the first JFET region 31 on a side facing away from the substrate 10.

[0061] After the step of forming the first well region in the drift layer is performed, Figure 1 As shown, step S104 is performed: a first doping region 51 is formed in the first well region 41 , and a portion of the first well region 41 is provided between the first doping region 51 and the first JFET region 31 .

[0062] Specifically, the second doping region 52 is formed in the first well region 41 away from the first JFET region 31 in the first doping region 51, such as Figure 1 As shown, a photomask and N-type ions may be used to implant a first doping region 51 in the first well region 41. The doping concentration of the first doping region 51 may be 1e 19 cm -3 ~1e 20 cm -3 The second doping region 52 can be formed by using a photomask and Al ion implantation. The doping concentration of the second doping region 52 can be 1e 18 cm -3 ~5e 19 cm -3 .

[0063] Specifically, Figure 7 and Figure 1As shown, while the active region formed by the first well region 41, the first doping region 51 and the second doping region 52 is formed, the second well region 42 is also formed on the side of the first JFET region 31 away from the first well region 41, and the third doping region 53 and the fourth doping region 54 are formed in the second well region 42. After the first JFET region 31 and the second JFET region 32 are formed, the first well region 41 and the second well region 42 can be formed simultaneously by using a photomask and Al ion implantation.

[0064] The specific steps of forming the active area formed by the first well region, the first doped region, the second doped region, the second well region, the third doped region and the fourth doped region include: forming the first preparatory well region and the second preparatory well region by using an ion implantation process in the drift layer; forming the first doped region and the third doped region by using an ion implantation process in the first preparatory well region and the second preparatory well region, a part of the first doped region and the second JFET region have a part of the first preparatory well region between a part of the third doped region and the second JFET region, a part of the first doped region and the first JFET region have a part of the first preparatory well region between another part of the first doped region and the first JFET region, and a part of the second preparatory well region between another part of the third doped region and the first JFET region The well region, the first doping region and the third doping region have the first doping type; at the same time, the second doping region is formed in the first prepared well region by an ion implantation process, and the fourth doping region is formed in the second prepared well region by an ion implantation process, a part of the second doping region is located on the side of the first doping region away from the second JFET region, another part of the second doping region is located on the side of the first doping region away from the first JFET region, a part of the fourth doping region is located on the side of the third doping region close to the first JFET region, the second doping region and the fourth doping region have the second doping type, the first prepared well region after the first doping region and the second doping region are formed is the first well region, and the second prepared well region after the third doping region and the fourth doping region are formed is the second well region.

[0065] Specifically, the doping concentration of the first well region and the second well region can be 1e 16 cm -3 ~5e 18 cm -3 , and the top view pattern of the first well region and the second well region can be determined according to actual needs. The second doping region can be formed by using a photomask and Al ion implantation, and the doping concentration of the second doping region can be 1e 18 cm -3 ~5e 19 cm -3 In the second well region, a third doping region can be implanted by using a photomask and N-type ions, and the doping concentration of the third doping region can be 1e 19 cm -3 ~1e 20 cm -3, a fourth doping region can be formed by using a photomask and Al ion implantation, and the doping concentration of the fourth doping region can be 1e 18 cm -3 ~5e 19 cm -3 , wherein the doping concentration and morphology pattern of the first doping region, the second doping region, the third doping region and the fourth doping region can be determined according to specific parameter requirements.

[0066] After forming various doping regions, the device is annealed, and a high temperature of 1700° C. can be used for annealing activation.

[0067] After the step of forming the first doping region in the first well region, Figure 2 As shown, step S105 is performed: a conductive layer 60 is formed on at least a side of a portion of the first JFET region facing away from the substrate 10 , and a gate structure 70 is formed on at least a side of the first doped region 51 and a portion of the first JFET region 31 facing away from the substrate 10 .

[0068] Specifically, Figure 2 As shown, a conductive layer 60 is formed on a portion of the first JFET region 31 close to one side of the second direction Y, so that a portion of the first JFET region 31 is used for forward conduction and the other portion is used for reverse conduction.

[0069] like Figure 2 As shown, after forming various doping regions and before forming the conductive layer 60, a gate structure 70 is formed on the first JFET region and the second JFET region. The gate structure 70 includes a gate oxide layer 74 and a gate 73. A first portion of the gate oxide layer 74 with a relatively thin thickness is first formed on the first JFET region and the second JFET region, and a gate 73 is formed on the first portion of the gate oxide layer 74. A second portion of the gate oxide layer 74 is formed on the top and sidewall of the gate 73. The thickness of the second portion of the gate oxide layer 74 is greater than that of the first portion of the gate oxide layer 74, so that the resistance from the bottom of the gate 73 to the drift layer 20 is small, thereby reducing the loss of current. A first electrode 81 and a second electrode 82 are formed on the first well region 41 and the second well region 42, respectively, and a third electrode 83 is formed on the side of the substrate 10 away from the drift layer 20. The thickness of the upper surface of the gate oxide layer 74 may be 0.2 μm to 1 μm, the thickness of the gate 73 may be 0.5 μm to 1.5 μm, the doping type may be N-type, and the doping concentration may be 1e 19 ~5e 20 cm -3 The thickness of the gate oxide layer 74 between the gate 73 and other structures can be 40nm~60nm.

[0070] It should be noted that the preparation method is a preparation method of the present application, and after forming the drift layer, the first well region and the second well region may be formed first, the first doping region, the second doping region, the third doping region and the fourth doping region may be formed in the first well region and the second well region, and then the first JFET region and the second JFET region may be formed in the drift layer. The specific process sequence may be reasonably adjusted according to actual conditions.

[0071] Example 1

[0072] The present application proposes a MOSFET device, which comprises:

[0073] SiC substrate, 100 μm thick, 5e doping concentration 18 cm -3 ;

[0074] The drift layer is located on one side of the substrate. The drift layer thickness is 200 μm and the doping concentration is 5e 16 cm -3 ;

[0075] The first JFET region is located in the drift layer. The doping type of the first JFET region is N-type, the thickness is 100 μm, and the doping concentration is 1e 16 cm -3 , extending in a direction perpendicular to the direction in which the drift layer points to the substrate;

[0076] The second JFET region is located in the drift layer. The doping type of the second JFET region is N-type, the thickness is 100μm, and the doping concentration is 1e 16 cm -3 , extending in a direction perpendicular to an extending direction of the first JFET region and contacting the first JFET region;

[0077] The first active region is located on one side of the first JFET region in the extension direction, and includes a first well region, a first doping region, and a second doping region, wherein the doping type of the first well region is P type, and the doping concentration is 1e 16 cm -3 The doping type of the first doping region is N-type, and the doping concentration of the first doping region can be 1e 19 cm -3 The doping type of the second doping region is P type, and the doping concentration of the second doping region can be 1e 18 cm -3 ;

[0078] The second active region is located on the other side of the first JFET region in the extension direction, and includes a second well region, a third doping region and a fourth doping region, wherein the doping type of the second well region is P type, and the doping concentration is 1e 16 cm -3The doping type of the third doping region is N-type, and the doping concentration can be 1e 19 cm -3 The doping type of the fourth doping region is P type, and the doping concentration can be 1e 18 cm -3 ;

[0079] The gate structure includes a gate oxide layer and a gate, the gate structure covers a first JFET region, a second JFET region, a portion of a first well region, a portion of a second well region, a portion of a first doping region, a portion of a third doping region, and a portion of a fourth doping region, the gate oxide layer on a side of the gate close to the substrate has a thickness of 50 nm, the gate oxide layer on a side of the gate away from the substrate has a thickness of 0.5 μm, the material of the gate oxide layer is silicon oxide, the material of the gate is N-type polysilicon, the thickness is 1 μm, and the doping concentration is 3e 20 cm -3 .

[0080] A first electrode, covering the first doping region and the second doping region, and made of Ag;

[0081] A second electrode, covering the third doping region and the fourth doping region, and made of Ag;

[0082] The third electrode is located on the side of the substrate away from the drift layer and is made of Ag;

[0083] The conductive layer covers a portion of the first JFET region and a portion of the second well region, and the material is Cu.

[0084] Example 2

[0085] The present application provides a method for preparing a MOSFET device, comprising:

[0086] A substrate is provided, and a drift layer is formed on one side of the substrate, the thickness of the substrate is 100 μm, and the doping concentration is 5e 18 cm -3 , the drift layer thickness is 200μm and the doping concentration is 5e 16 cm -3 ;

[0087] Ion implantation is used to form a first JFET region and a second JFET region in the drift layer. The first JFET region extends along a first direction, and the second JFET region extends along a second direction. The first direction is perpendicular to the direction of the substrate pointing to the drift layer, and the second direction is perpendicular to the first direction. The thickness of the first JFET region and the second JFET region is 100 μm, and the doping concentration is 1e 16 cm -3 ;

[0088] Ion implantation is used to form a first well region and a second well region in the drift layer. The first well region is located on one side of the first JFET region in the first direction, and the second well region is located on the other side of the first JFET region in the first direction. The first well region and the second well region are P-type, and the doping concentration is 1e 16 cm -3 ;

[0089] Ion implantation is used to form a first doping region and a third doping region in the first well region. A portion of the first well region is provided between the first doping region and the first JFET region, and a portion of the second well region is provided between the third doping region and the second JFET region. The doping type of the first doping region and the third doping region is N-type, and the doping concentration can be 1e 19 cm -3 ;

[0090] Ion implantation is used to form a second doping region and a fourth doping region in the second well region. The first doping region surrounds the second doping region, the fourth doping region surrounds the third doping region, and part of the fourth doping region is located between the third doping region and the first JFET region. The doping type of the second doping region and the fourth doping region is P type, and the doping concentration can be 1e 18 cm -3 ;

[0091] A first gate oxide layer is deposited on a portion of the first JFET region, the first JFET region, a portion of the first well region, a portion of the second well region, a portion of the first doped region, a portion of the third doped region and a portion of the fourth doped region, a gate is formed on the first gate oxide layer, a second gate oxide layer is formed on the gate, and finally a gate structure is formed, the thickness of the first gate oxide layer is 50nm, the thickness of the second gate oxide layer is 0.5μm, the material of the gate oxide layer is silicon oxide, the material of the gate is N-type polysilicon, the thickness is 1μm, and the doping concentration is 3e 20 cm -3 ;

[0092] Depositing a first electrode on the first doping region and the second doping region, wherein the material is Ag;

[0093] Depositing a second electrode on the third doping region and the fourth doping region, wherein the material is Ag;

[0094] A third electrode is formed by depositing Ag on the side of the substrate away from the drift layer;

[0095] A conductive layer is deposited on another portion of the first JFET region and a portion of the second well region on a side facing away from the substrate, and the material of the conductive layer is Cu.

[0096] Example 3

[0097] The present application provides a method for preparing a MOSFET device, comprising:

[0098] A substrate is provided, and a drift layer is formed on one side of the substrate, with a thickness of 100 μm and a doping concentration of 5e 18 cm -3 , the drift layer thickness is 200μm and the doping concentration is 5e 16 cm -3 ;

[0099] Ion implantation is used to form a first well region and a second well region in the drift layer. There is a portion of the drift layer between the first well region and the second well region. The first well region and the second well region are P-type with a doping concentration of 1e 16 cm -3 ;

[0100] Ion implantation is used to form a first doping region and a third doping region in the first well region. A portion of the first well region is provided between the first doping region and the drift layer. A portion of the second well region is provided between the third doping region and the drift layer. The doping type of the first doping region and the third doping region is N-type, and the doping concentration can be 1e 19 cm -3 ;

[0101] Ion implantation is used to form a second doping region and a fourth doping region in the second well region. The fourth doping region surrounds the third doping region, and a portion of the fourth doping region is located between the third doping region and the drift layer. The first doping region surrounds the second doping region. The doping type of the second doping region and the fourth doping region is P type, and the doping concentration can be 1e 18 cm -3 ;

[0102] Ion implantation is used to form a first JFET region and a second JFET region in the drift layer. The first JFET region extends along a first direction and is located between the first well region and the second well region. The second JFET region extends along a second direction. The first direction is perpendicular to the direction of the substrate pointing to the drift layer, and the second direction is perpendicular to the first direction. The thickness of the first JFET region and the second JFET region is 100 μm, and the doping concentration is 1e 16 cm -3 ;

[0103] A first gate oxide layer is deposited on part of the first JFET region, the first JFET region, part of the first well region, part of the second well region, part of the first doped region, part of the third doped region and part of the fourth doped region, a gate is formed on the first gate oxide layer, a second gate oxide layer is formed on the gate, and finally a gate structure is formed, the thickness of the first gate oxide layer is 50nm, the thickness of the second gate oxide layer is 0.5μm, the material of the gate oxide layer is silicon oxide, the material of the gate is N-type polysilicon, the thickness is 1μm, and the doping concentration is 3e 20 cm -3 ;

[0104] Depositing a first electrode on the first doping region and the second doping region, wherein the material is Ag;

[0105] Depositing a second electrode on the third doping region and the fourth doping region, wherein the material is Ag;

[0106] A third electrode is formed by depositing Ag on the side of the substrate away from the drift layer;

[0107] A conductive layer is deposited on another portion of the first JFET region and a portion of the second well region on a side facing away from the substrate, and the material of the conductive layer is Cu.

[0108] From the above description, it can be seen that the embodiments of the present application achieve the following technical effects:

[0109] 1) When the MOSFET device of the present application is forward-conducted, the current can smoothly flow through the first doped region of the CMOS structure region of the device to the first JFET region, thereby suppressing the degradation of the on-resistance and participating in the forward conduction; when reverse-conducted, the current passes through the conductive layer of the CJBSFET structure region of the device and enters the first JFET region covered by the conductive layer. By regulating the first JFET region to have a higher doping concentration, the current can be rapidly expanded, demonstrating the excellent reverse characteristic capability of the MOSFET device.

[0110] 2) When the device is in a reverse bias state, the first well region, the first JFET region and the second well region correspond to the first electrode, the gate structure (including the gate oxide layer and the gate) and the conductive layer and the second electrode respectively. In the reverse bias state, the electrodes of the three parts are all 0V, so the first JFET region between the first well region and the second well region can be completely depleted, retaining the Schottky withstand voltage characteristics of the device.

[0111] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0112] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the claims of the present application.

Claims

1. A MOSFET device, characterized in that: include: substrate; A drift layer, located on one side of the substrate; A first JFET region is located in the drift layer, the first JFET region extends along a first direction, the first direction is perpendicular to a direction from the substrate to the drift layer, and the doping concentration of the first JFET region is 1e 16 cm -3 ~2e 17 cm -3 ; A first well region is located in the drift layer, and the first well region is located on one side of the first JFET region in the first direction; A first doped region, located in the first well region, with a portion of the first well region between the first doped region and the first JFET region; a conductive layer, covering at least a portion of the first JFET region, wherein a Schottky contact is formed between the conductive layer and the first JFET region; The gate structure at least covers a portion of the first doped region and a portion of the first JFET region.

2. The MOSFET device according to claim 1, characterized in that The MOSFET device also includes a second well region, which is located in the drift layer, the second well region is located on a side of the first JFET region away from the first well region, a portion of the second well region is located on a side of the conductive layer close to the substrate, and the first well region and the second well region have the same doping type.

3. The MOSFET device according to claim 2, characterized in that: The MOSFET device also includes a second JFET region, which is located in the drift layer and extends along a second direction. A portion of the first well region is provided between the first doped region and the second JFET region. The second direction is perpendicular to the first direction and parallel to a surface of the substrate on one side close to the drift layer, and the second JFET region is in contact with the first JFET region.

4. The MOSFET device according to claim 3, characterized in that: The MOSFET device further includes a second doping region, a portion of the second doping region is located on a side of the first doping region away from the second JFET region, another portion of the second doping region is located on a side of the first doping region away from the first JFET region, and the second doping region has a second doping type.

5. The MOSFET device according to claim 3, characterized in that: The MOSFET device further comprises: a third doping region and a fourth doping region, wherein: The third doping region is located in the second well region, a portion of the second well region is between the third doping region and the second JFET region, and the third doping region has a first doping type; The fourth doped region is located in the second well region, a portion of the fourth doped region has a portion of the second well region between a portion of the fourth doped region and the second JFET region, and a portion of the second well region has a portion of the fourth doped region between the other portion of the fourth doped region and the first JFET region; The third doping region is located on a side of a portion of the fourth doping region away from the first JFET region, and the fourth doping region has a second doping type.

6. The MOSFET device according to claim 5, characterized in that: The gate structure comprises a first sub-gate structure and a second sub-gate structure, wherein: The first sub-gate structure at least covers another portion of the first JFET region and the first well region between the first doped region and the first JFET region, and the first sub-gate structure extends along the first direction; The second sub-gate structure at least covers the second JFET region, the first well region between the first doping region and the second JFET region, and the second well region between the third doping region and the second JFET region. The extension direction of the second sub-gate structure is the same as the extension direction of the second JFET region, and the first sub-gate structure is in contact with the second sub-gate structure.

7. The MOSFET device according to claim 1, characterized in that: The MOSFET device further comprises a first electrode, a second electrode and a third electrode, wherein: The first electrode is located at a side of the first JFET region away from the conductive layer; The second electrode is located at a side of the conductive layer away from the first JFET region; The third electrode is located on a side of the substrate facing away from the drift layer.

8. A method for preparing a MOSFET device, characterized in that: For preparing a MOSFET device according to any one of claims 1 to 7, comprising: providing a substrate, and forming a drift layer on one side of the substrate; A first JFET region is formed in the drift layer, the first JFET region extends along a first direction, the first direction is perpendicular to a direction from the substrate to the drift layer, and the doping concentration of the first JFET region is 1e 16 cm -3 ~2e 17 cm -3 ; forming a first well region in the drift layer, wherein the first well region is located on one side of the first JFET region in the first direction; forming a first doped region in the first well region, wherein a portion of the first well region is between the first doped region and the first JFET region; A conductive layer is formed on at least a portion of the first JFET region on a side facing away from the substrate, and a Schottky contact is formed between the conductive layer and the first JFET region.

9. The preparation method according to claim 8, characterized in that: The preparation method further comprises: A second JFET region is formed in the drift layer, wherein an extension direction of the second JFET region is perpendicular to the first direction, and the second JFET region is in contact with the first JFET region.

10. The preparation method according to claim 9, characterized in that: The step of forming a first well region in the drift layer comprises: forming a first preliminary well region in the drift layer by using an ion implantation process; forming a first doped region in the first prepared well region by an ion implantation process, wherein a portion of the first doped region has a portion of the first prepared well region between the first portion and the second JFET region, and a portion of the first prepared well region has a portion of the first doped region between the other portion and the first JFET region, and the first doped region has a first doping type; An ion implantation process is used to form a second doped region in the first preparatory well region, a portion of the second doped region is located on a side of the first doped region away from the second JFET region, and another portion of the second doped region is located on a side of the first doped region away from the first JFET region, the second doped region has a second doping type, and the first preparatory well region after forming the first doped region and the second doped region is the first well region.

11. The preparation method according to claim 9, characterized in that: The preparation method further comprises: forming a second prepared well region in the drift layer, the second prepared well region being located at a side of the first JFET region away from the first well region, and the first well region and the second prepared well region having the same doping type; forming a third doping region in the second preparatory well region by an ion implantation process, wherein a portion of the second preparatory well region is provided between the third doping region and the second JFET region, and the third doping region has a first doping type; An ion implantation process is used to form a fourth doped region in the second preparatory well region, a portion of the fourth doped region has a portion of the second preparatory well region between it and the second JFET region, and another portion of the fourth doped region has a portion of the second preparatory well region between it and the first JFET region, the third doped region is located on a side of the portion of the fourth doped region away from the first JFET region, the fourth doped region has a second doping type, and the second preparatory well region after the third doped region and the fourth doped region are formed is a second well region.

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