Normally-off silicon carbide high-voltage jfet device based on extended conductive channel and preparation method

Abstract

A normally-off silicon carbide high-voltage JFET device based on an extended conductive channel and a preparation method thereof. The device comprises a P-type epitaxial layer grown on an N-type substrate and an N-type drift region, a P-type buried layer in the N-type drift region, a first and a second P-type well-doped region, a first N-type well-doped region, a first and a second N-type high-doped region, a first and a second P-type high-doped region, an oxide layer and an auxiliary inversion metal in the second P-type high-doped region, an oxide layer dielectric provided above the N-type drift region, and etching of the oxide layer dielectric to lead out source, drain and gate metal electrodes. The preparation method comprises obtaining a substrate, growing an epitaxial layer on the substrate, growing a drift region on the epitaxial layer, high-energy ion implantation to form a P-type buried layer, ion implantation in the drift region to form different types of doped well and high-doped region, etching of the second P-type well-doped region to grow an oxide layer and deposit an auxiliary inversion metal electrode and form an extended conductive structure, growing an interlayer dielectric, etching, and depositing metal to form source, drain and gate electrodes.

Description

Technical Field

[0001] The present application relates to the field of semiconductor devices and their manufacturing, and in particular to a normally-off silicon carbide high-voltage JFET device based on an extended conductive channel and a preparation method thereof. Background Art

[0002] The semiconductor industry is placing increasing demands on power devices. Currently, power semiconductor devices are dominated by silicon. As power electronics technology evolves toward higher blocking voltages, faster switching speeds, and higher operating temperatures, the limitations of silicon-based power devices are becoming increasingly apparent. The performance of traditional silicon-based power devices has already approached the theoretical limits of their materials, failing to meet the requirements of next-generation power electronics systems under high-temperature and high-pressure environments. Silicon carbide, a wide-bandgap semiconductor material, offers advantages over traditional silicon materials, such as a wide bandgap, a high critical breakdown electric field, a high electron saturation drift velocity, and high thermal conductivity. This makes it an ideal semiconductor material for high-power, high-temperature, high-frequency, and radiation-resistant applications.

[0003] The Junction-Field-Effect-Transistor (JFET) is a voltage-controlled device. By integrating lateral JFET devices with passive components such as resistors, various analog and digital integrated circuits can be implemented. JFET power devices achieve gate voltage control solely through the PN junction, eliminating the SiO2 / SiC interface state issue. This offers significant reliability advantages over silicon carbide (LDOMS). Furthermore, compared to MOS control, the turn-on voltage of the PN junction gate structure varies less with temperature, reducing the possibility of false triggering in high-temperature environments.

[0004] Compared to MOSFETs, silicon carbide JFET devices are relatively easy to turn on, lack a low-reliability gate oxide layer, have higher input resistance, and exhibit less noise. Existing silicon carbide JFET devices are divided into two categories: normally-on and normally-off. Normally-on devices have better current capabilities than normally-off devices, but when normally-on silicon carbide JFET devices are turned off, a negative voltage must be applied to the gate to deplete the conduction channel, resulting in significant energy loss and increased circuit design difficulty. Normally-off devices have a higher voltage resistance than normally-on devices. When in use, normally-off silicon carbide JFETs only require a gate voltage when turned on; in the off state, the channel automatically pinches off without the need for a gate voltage, resulting in lower energy consumption but lower current capabilities. Summary of the Invention

[0005] The present invention provides a normally-off silicon carbide high-voltage JFET device based on an extended conductive channel, which can improve the current capability of the normally-off device.

[0006] In view of the above problems, the present invention adopts the following technical solutions:

[0007] The present invention provides a silicon carbide high-voltage JFET device based on an extended conductive channel, comprising:

[0008] An N-type substrate is provided, a P-type epitaxial growth is grown on the N-type substrate, an N-drift region is grown on the P-type epitaxial growth, a P-type buried layer, a first P-type well doped region, a second P-type well doped region, a first N-type well doped region and a first N-type highly doped region are provided in the N-type drift region, the first P-type well doped region touches the P-type buried layer,

[0009] The bottom of the second P-type well doped region is higher than the upper surface of the P-type buried layer. When the device is turned on, a first conductive channel is formed by the N-type drift region between the second P-type well doped region and the P-type buried layer. The first N-type highly doped region is located between the first P-type well doped region and the second P-type well doped region, and the first N-type highly doped region is in contact with the first P-type well doped region.

[0010] A first P-type high-doping region is provided in the first P-type well-doping region, a second P-type high-doping region is provided in the second P-type well-doping region, and a second N-type high-doping region is provided in the first N-type well-doping region; an oxide layer dielectric is provided on the surfaces of the first P-type well-doping region, the first P-type high-doping region, the first N-type high-doping region, the second P-type well-doping region, the second P-type high-doping region, the first N-type well-doping region, the second N-type high-doping region and the N-type drift region.

[0011] A source metal electrode is drawn out from the first P-type highly doped region and the first N-type highly doped region to form a source of the device, a gate metal electrode is drawn out from the second P-type highly doped region to form a gate of the device, and a drain metal electrode is drawn out from the second N-type highly doped region to form a drain of the device.

[0012] The second P-type highly doped region includes two or more second P-type highly doped units arranged in the same direction and in a straight line as the first P-type highly doped region, and adjacent second P-type highly doped units are separated; a groove is provided between adjacent second P-type highly doped units, and the two side surfaces of the groove are respectively in conflict with the adjacent second P-type highly doped units, an extended conductive structure is provided in the groove, and a second conductive channel is formed by the extended conductive structure, which is connected to the second P-type highly doped region and has the same potential.

[0013] When the device of the present invention is in the off state, the source is connected to a zero potential voltage, the gate is connected to a zero potential voltage, the P-type buried layer, the second P-type well doped region and the N-type drift region are depleted respectively. When no voltage is applied to the drain, the P-type buried layer, the second P-type well doped region and the portion of the N-type drift region located therein are just depleted, so that the depletion layer formed by the conductive channel is just pinched off. The above-mentioned depletion region expands as the voltage applied to the drain increases, thereby realizing the off state and reverse withstand voltage process of the normally-off silicon carbide high-voltage JFET device;

[0014] When the device described in the present invention is in the on state, the source is connected to a zero potential voltage and the gate is connected to a voltage range of 0~2.7V. When the gate is connected to a non-zero potential voltage, the depletion area of ​​the P-type buried layer, the second P-type well doped region and the part of the N-type drift region located therein is reduced, so that the conduction channel originally pinched off by the depletion layer is opened. As the voltage applied to the gate increases, the part of the second P-type well doped region immediately below the auxiliary inversion electrode is inverted to form a special second conduction channel, thereby increasing the current capacity of the silicon carbide normally-off high-voltage JFET device during forward conduction, so that the saturation current of the silicon carbide normally-off high-voltage JFET device is effectively improved when it is in the on state.

[0015] The present invention provides a method for preparing a normally-off silicon carbide high-voltage JFET device based on an extended conductive channel.

[0016] forming an N-type substrate on a silicon carbide substrate; epitaxially growing a P-type epitaxial region on the N-type substrate; and epitaxially growing an N-type drift region on the P-type epitaxial region;

[0017] forming a P-type buried layer in the N-type drift region by high-energy ion implantation;

[0018] Performing P-type ion implantation on the N-type drift region to form a first P-type well doping region and a second P-type well doping region; performing N-type ion implantation on the N-type drift region to form a first N-type well doping region; performing highly doped N-type ion implantation on the N-type drift region and the first N-type well doping region to form a first N-type highly doped region and a second N-type highly doped region, respectively;

[0019] Performing highly doped P-type ion implantation on the first P-type well doping region and the second P-type well doping region and forming a first P-type well doping region and a separated second P-type highly doped unit on the N-type drift region and the first N-type well doping region respectively;

[0020] After the thermal annealing treatment, etching the second P-type well doped region between adjacent second P-type highly doped units to form a trench, growing an oxide layer on the bottom and inner wall of the trench, and then depositing metal in the oxide layer to form an extended conductive structure;

[0021] Depositing a layer of oxide dielectric on the surfaces of the N-type drift region, the first P-type highly doped region, the second P-type highly doped region, the first N-type highly doped region, the second P-type well doped region, the second P-type highly doped region, the extended conductive structure, the first N-type well doped region and the second N-type highly doped region;

[0022] The first P-type highly doped region, the first N-type highly doped region, the second P-type highly doped region and the extended conductive structure, as well as a local area of ​​the oxide layer dielectric above the second N-type highly doped region are etched to form a through hole, and then a metal layer is deposited on the oxide layer dielectric. Finally, the metal layer is etched to form a source, a gate and a drain.

[0023] Compared with the prior art, the present invention has the following advantages:

[0024] This invention provides a normally-off silicon carbide high-voltage JFET device based on an extended conductive channel and its fabrication method. Compared with traditional silicon-based JFET devices, SiC devices surpass the limits of traditional silicon-based devices in terms of withstand voltage and operating temperature, offering significant advantages in high-voltage, high-power, and high-temperature environments. Because the device's partially conductive channel lacks a SiC-SiO2 interface, the equivalent mobility of channel carriers is higher, and the turn-on voltage of the PN junction gate structure varies less with temperature, reducing the possibility of false triggering in high-temperature environments.

[0025] The normally-off silicon carbide high-voltage JFET device described in the present invention has the advantage of high on-state current capability. This invention forms multiple extended conductive structures by etching trenches and growing oxide layers within adjacent P-well doped regions. These extended conductive structures are then connected to the gate electrode of the entire JFET device. While the device's conductive channel is turned on via a conventional gate electrode, the extended conductive structures, or the adjacent region of the second P-type well doped region below the auxiliary inversion electrode, are inverted to form a second conductive channel of the device, participating in the device's on-state current conduction process. This solves the low current capability issue of conventional normally-off silicon carbide high-voltage JFET devices while maintaining their off-state withstand voltage capability, thereby improving the device's on-state current capability. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more of the accompanying drawings. The additional details or examples used to describe the accompanying drawings should not be considered to limit the scope of the disclosed inventions, the presently described embodiments and / or examples, and any of the best modes currently understood for these inventions.

[0027] Figure 1 This is a 3D schematic diagram of the interior of a normally-off silicon carbide high-voltage JFET device with an extended conductive structure invented by the present application without metal deposition.

[0028] Figure 2 This is a local 3D schematic diagram of a normally-off silicon carbide high-voltage JFET device with an extended conductive structure after metal deposition, according to the present invention.

[0029] Figure 3 It is along Figure 2 Schematic diagram of the relative positions of the P-WELL and the extended conductive structure in the CC' section.

[0030] Figure 4 It is along Figure 2Middle AA' section.

[0031] Figure 5 It is along Figure 2 Middle BB' cross-section.

[0032] Figure 6 This is a schematic diagram of the steps for preparing a silicon carbide normally-off high-voltage JFET device with an extended conductive structure according to the present invention.

[0033] Figure 7(a)-Figure 7(i) This invention is a silicon carbide normally-off high-voltage JFET device with an extended conductive structure, wherein Figures 7(a) to 7(i) are schematic diagrams of the various steps of the preparation process.

[0034] Figure 8 This is a schematic diagram of the mask structure during ion implantation in the P-type highly doped region. DETAILED DESCRIPTION

[0035] To facilitate understanding of the present invention, the present invention will be described more fully below with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. However, the present invention may be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive disclosure of the present invention.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one skilled in the art to which this invention pertains. The terms used in this specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0037] The semiconductor terminology used herein is commonly used by those skilled in the art. For example, to distinguish between P-type and N-type impurities, the doping concentrations are described as follows: the first P-type highly doped region, the second P-type highly doped region, and the P-type buried layer are all heavily doped with P-type impurities; the first P-type doped region, the second P-type doped region, and the P-type epitaxial layer are all lightly doped with P-type impurities; the first N-type highly doped region and the second N-type highly doped region are all heavily doped with N-type impurities; and the first N-type well-doped region, the N-type drift region, and the N-type substrate are all lightly doped with N-type impurities. To distinguish between doping locations, the terms "first type" and "second type" are used. To distinguish the channel location of a normally-off device, the terms "conduction channel" and "characteristic conduction channel" are used. The extended conductive channel underlying the normally-off silicon carbide high-voltage JFET device is referred to herein as the trench portion and the oxide layer portion.

[0038] In order to solve the problems of poor current capability and insufficient voltage resistance of traditional normally-off silicon carbide high-voltage JFET devices, the present application proposes a normally-off silicon carbide high-voltage JFET device based on an extended conductive channel. Example 1

[0039] A silicon carbide high-voltage JFET device based on an extended conductive channel, comprising:

[0040] An N-type substrate 005 is provided. A P-type epitaxial layer 006 is grown on the N-type substrate 005. An N-drift region 007 is grown on the P-type epitaxial layer 006. A P-type buried layer 003, a first P-type well doping region 001, a second P-type well doping region 002, a first N-type well doping region 004, and a first N-type highly doped region 012 are provided in the N-type drift region 007. The first P-type well doping region 001 touches the P-type buried layer 003.

[0041] The bottom of the second P-type well doped region 002 is higher than the upper surface of the P-type buried layer 003. When the device is turned on, the first conduction channel 111 is formed by the N-type drift region 007 between the second P-type well doped region 002 and the P-type buried layer 003. The first N-type highly doped region 012 is located between the first P-type well doped region 001 and the second P-type well doped region 002, and the first N-type highly doped region 012 is in contact with the first P-type well doped region 001.

[0042] A first P-type highly doped region 011 is provided in the first P-type well doping region 001, a second P-type highly doped region 021 is provided in the second P-type well doping region 002, and a second N-type highly doped region 041 is provided in the first N-type well doping region 004; an oxide layer dielectric 041 is provided on the surfaces of the first P-type well doping region 001, the first P-type highly doped region 011, the first N-type highly doped region 012, the second P-type well doping region 002, the second P-type highly doped region 021, the first N-type well doping region 004, the second N-type highly doped region 041 and the N-type drift region 007.

[0043] A source metal electrode is drawn out from the first P-type highly doped region 011 and the first N-type highly doped region 012 to form a device source 01S, a gate metal electrode is drawn out from the second P-type highly doped region 021 to form a device gate 02G, and a drain metal electrode is drawn out from the second N-type highly doped region 041 to form a device drain 03D.

[0044] The second P-type highly doped region 021 includes two or more second P-type highly doped units arranged in a straight line in the same direction as the first P-type highly doped region 011, and adjacent second P-type highly doped units are separated; a trench is provided between adjacent second P-type highly doped units, and the two sides of the trench are respectively in contact with the adjacent second P-type highly doped units, and an extended conductive structure 023 is provided in the trench and a second conductive channel 222 is formed by the extended conductive structure 023, which is connected to the second P-type highly doped region 021 and has the same potential. In this embodiment,

[0045] The extended conductive structure 023 includes an oxide layer 022 disposed at the bottom and inner wall of the trench. Metal is filled within the oxide layer 022 to form an auxiliary inversion electrode 024, which is connected to the gate metal electrode. The number of extended conductive structures 023 is 3-6. Furthermore, the doping concentration of each type of high-doped region is greater than the doping concentration of the well doping region, epitaxy, and substrate, with the concentration range of the substrate being 1e8-5e8, the epitaxy being 1e9-5e9, the doping region being 1e10-5e10, and the high-doped region being 1e11-5e11.

[0046] In the normally-off silicon carbide high-voltage JFET device structure of the present invention, an extended conductive structure 023 is added. Specifically, the extended conductive structure 023 includes an oxide layer 022 provided on the bottom and inner wall of the trench, and metal is filled in the oxide layer 022 to form an auxiliary inversion electrode 024. The auxiliary inversion electrode 024 is connected to the gate metal electrode. When the first conduction channel 111 formed in the N-type drift region 007 between the second P-type well-doped region 002 and the P-type buried layer 003 is turned on, the second conduction channel 222 formed by inversion in the second P-type well-doped region 002 and in the adjacent region of the second P-type well-doped region 002 below the extended conductive channel 023 and the auxiliary inversion electrode 024 is turned on at the same time. Example 2

[0047] A method for preparing a normally-off silicon carbide high-voltage JFET device based on an extended conductive channel.

[0048] An N-type substrate 005 is formed on a silicon carbide substrate; a P-type epitaxial region 006 is epitaxially grown on the N-type substrate 005; and an N-type drift region 007 is epitaxially grown on the P-type epitaxial region 006.

[0049] A P-type buried layer 003 is formed in the N-type drift region 007 by high-energy ion implantation;

[0050] Performing P-type ion implantation on the N-type drift region 007 to form a first P-type well doping region 001 and a second P-type well doping region 002; performing N-type ion implantation on the N-type drift region 007 to form a first N-type well doping region 004; performing highly doped N-type ion implantation on the N-type drift region 007 and the first N-type well doping region 004 to form a first N-type highly doped region 012 and a second N-type highly doped region 041, respectively;

[0051] Highly doped P-type ion implantation is performed on the first P-type well doping region 001 and the second P-type well doping region 002, and the first P-type well doping region 001 and the separated second P-type highly doped unit are formed on the N-type drift region 007 and the first N-type well doping region 004 respectively. As is known to all, ion implantation requires the use of a mask. Figure 8 The mask structure in this step is as follows Figure 8 shown.

[0052] After thermal annealing, the second P-type well doped region 002 between adjacent second P-type high-doped units is etched to form a trench, an oxide layer 022 is grown on the bottom and inner wall of the trench, and metal is deposited in the oxide layer 022 to form an extended conductive structure 023. Figure 3 , the trenches are respectively offset against the adjacent second P-type highly doped units, and the trenches extend from one side of the second P-type well doped region 002 to the other side thereof;

[0053] Depositing a layer of oxide dielectric 04F on the surfaces of the N-type drift region 007, the first P-type highly doped region 011, the second P-type highly doped region 021, the first N-type highly doped region 012, the second P-type well doped region 002, the second P-type highly doped region 021, the extended conductive structure 023, the first N-type well doped region 004 and the second N-type highly doped region 041;

[0054] The oxide layer dielectric local area above the first P-type highly doped region 011, the first N-type highly doped region 012, the second P-type highly doped region 021, the extended conductive structure 023, and the second N-type highly doped region 041 is etched to form a through hole, and then a metal layer is deposited on the oxide layer dielectric. Finally, the metal layer is etched to form the source 01S, the gate 02G, and the drain 03D. In this embodiment,

[0055] The high-energy ion implantation used to form the P-type buried layer 003 is Al doped with a doping dose of 1e10~5e10cm -3 , the energy is 1.2MeV~10MeV. P-type ion implantation, the doping impurity is Al, the doping dose is 1e10~5e10 cm -3, energy is 10keV~1MeV, N-type ion implantation, the doping impurity is N, the doping dose is 1e10~5e10 cm -3 , the energy is 1.2MeV~10MeV; the high-doped N-type ion implantation, the doping impurity is N, the doping dose is 1e11~5e11 cm -3 , the energy is 1.2MeV~10MeV. Highly doped P-type ion implantation, the doping impurity is Al, the doping dose is 1e11~5e11 cm -3 , energy is 1.2MeV~10MeV.

[0056] Refer to the following Figures 1 to 6 , further illustrating the device structure of the present invention:

[0057] Figure 1 This is a 3D schematic diagram of the interior of a normally-off silicon carbide high-voltage JFET device based on an extended conductive channel invented by the present application. A conductive channel is formed by the first P-type well-doped region 001, the first N-type highly doped region 012, the region above the P-type buried layer 003, and the second P-type well-doped region 002. In the area adjacent to the second P-type well-doped region below the multiple trench-formed oxide layer 022, the auxiliary inversion metal electrode 024 in the extended conductive structure is connected to a positive potential voltage to make the P-type semiconductor inverted, forming a characteristic conductive channel 222 of the device, and participating in the device current conduction process together with the conductive channel.

[0058] Figure 4 along Figure 2 Schematic diagram of the overall channel of the device at section AA'. In the off state, the P-type buried layer 003, the second P-type well doped region 002 and the N-type drift region 007 are depleted respectively. The N-type drift region 007 is depleted internally and depleted together with the P-type substrate 006, sharing the withstand voltage. When turned on, the depletion area decreases, the conduction channel opens, and electrons flow from the first N-type highly doped region 012 through the conduction channel 111 formed by the P-type buried layer 003, the second P-type well doped region 002 and the N-type drift region 007, from the N-type drift region 007 to the first N-type well doped region 004, and finally reach the second N-type highly doped region 041.

[0059] Figure 5 along Figure 2Schematic diagram of the overall channel of the device at section BB'. In the off state, the P-type buried layer 003, the second P-type well-doped region 002 and the N-type drift region 007 are depleted respectively. The N-type drift region 007 is depleted internally and depleted together with the P-type substrate 006, sharing the withstand voltage. When turned on, the auxiliary inversion metal electrode 024 in the extended conductive structure is connected to a positive voltage, so that the second P-type well-doped region 002 below the gate oxide layer is inverted to form a characteristic conduction channel 222. In addition to flowing through the above path, electrons can also flow from the first N-type highly doped region 012 through the adjacent N-type drift region 007, through the characteristic conduction channel 222 in the second P-type well-doped region 002, and finally reach the first N-type well-doped region 004 and the second N-type highly doped region 041.

Claims

1. A silicon carbide high-voltage JFET device based on an extended conductive channel, comprising: An N-type substrate (005) is provided, a P-type epitaxial layer (006) is grown on the N-type substrate (005), an N-type drift region (007) is grown on the P-type epitaxial layer (006), a P-type buried layer (003), a first P-type well doping region (001), a second P-type well doping region (002), a first N-type well doping region (004) and a first N-type high-doping region (012) are provided in the N-type drift region (007), the first P-type well doping region (001) touches the P-type buried layer (003), The bottom of the second P-type well doping region (002) is higher than the upper surface of the P-type buried layer (003); when the device is turned on, a first conduction channel (111) is formed by the N-type drift region (007) between the second P-type well doping region (002) and the P-type buried layer (003); the first N-type high-doping region (012) is located between the first P-type well doping region (001) and the second P-type well doping region (002), and the first N-type high-doping region (012) is in contact with the first P-type well doping region (001). A first P-type high-doping region (011) is provided in the first P-type well doping region (001), a second P-type high-doping region (021) is provided in the second P-type well doping region (002), and a second N-type high-doping region (041) is provided in the first N-type well doping region (004); an oxide layer medium (04F) is provided on the surfaces of the first P-type well doping region (001), the first P-type high-doping region (011), the first N-type high-doping region (012), the second P-type well doping region (002), the second P-type high-doping region (021), the first N-type well doping region (004), the second N-type high-doping region (041), and the N-type drift region (007). A source metal electrode is drawn out from the first P-type highly doped region (011) and the first N-type highly doped region (012) to form a device source (01S), a gate metal electrode is drawn out from the second P-type highly doped region (021) to form a device gate (02G), and a drain metal electrode is drawn out from the second N-type highly doped region (041) to form a device drain (03D), It is characterized by: The second P-type highly doped region (021) includes two or more second P-type highly doped units arranged in a straight line in the same direction as the first P-type highly doped region (011), and adjacent second P-type highly doped units are separated; a groove is provided between adjacent second P-type highly doped units, and two side surfaces of the groove respectively contact the adjacent second P-type highly doped units; an extended conductive structure (023) is provided in the groove, and a second conductive channel (222) is formed by the extended conductive structure (023), which is connected to the second P-type highly doped region (021) and has an equipotential.

2. The silicon carbide high voltage JFET device based on extended conductive channel according to claim 1, characterized in that: The extended conductive structure (023) comprises an oxide layer (022) provided on the bottom and inner wall of the trench, metal is filled in the oxide layer (022) to form an auxiliary inversion electrode (024), and the auxiliary inversion electrode (024) is connected to the gate metal electrode.

3. The silicon carbide high voltage JFET device based on extended conductive channel according to claim 1 or 2, characterized in that: The number of the extended conductive structures (023) is 3-6.

4. A method for preparing a normally-off silicon carbide high-voltage JFET device based on an extended conductive channel, characterized in that: An N-type substrate (005) is formed on a silicon carbide substrate; a P-type epitaxial layer (006) is epitaxially grown on the N-type substrate (005); and an N-type drift region (007) is epitaxially grown on the P-type epitaxial layer (006); forming a P-type buried layer (003) in the N-type drift region (007) by high-energy ion implantation; Performing P-type ion implantation on the N-type drift region (007) to form a first P-type well doping region (001) and a second P-type well doping region (002); performing N-type ion implantation on the N-type drift region (007) to form a first N-type well doping region (004); performing highly doped N-type ion implantation on the N-type drift region (007) and the first N-type well doping region (004) to form a first N-type highly doped region (012) and a second N-type highly doped region (041), respectively; Performing high-doped P-type ion implantation on the first P-type well doping region (001) and the second P-type well doping region (002) and forming the first P-type well doping region (001) and the separated second P-type high-doping unit on the N-type drift region (007) and the first N-type well doping region (004); After thermal annealing, etching the second P-type well doping region (002) between adjacent second P-type high-doping units to form a trench, growing an oxide layer (022) on the bottom and inner wall of the trench, and then depositing metal in the oxide layer (022) to form an extended conductive structure (023); Depositing a layer of oxide layer dielectric (041) on the surfaces of the N-type drift region (007), the first P-type highly doped region (011), the second P-type highly doped region (021), the first N-type highly doped region (012), the second P-type well doped region (002), the second P-type highly doped region (021), the extended conductive structure (023), the first N-type well doped region (004) and the second N-type highly doped region (041); The first P-type highly doped region (011), the first N-type highly doped region (012), the second P-type highly doped region (021), the extended conductive structure (023), and a local area of ​​the oxide layer medium (041) above the second N-type highly doped region (041) are etched to form a through hole, and then a metal layer is deposited on the oxide layer medium. Finally, the metal layer is etched to form a source (01S), a gate (02G), and a drain (03D).

5. The method for preparing a normally-off silicon carbide high-voltage JFET device based on an extended conductive channel according to claim 4, characterized in that: High-energy ion implantation is used to form a P-type buried layer (003), with Al doping impurities and a doping dose of 1e10 ~5e10 cm -3 , energy is 1.2MeV~10MeV.

6. The method for preparing a normally-off silicon carbide high-voltage JFET device based on an extended conductive channel according to claim 4, wherein: P-type ion implantation, the doping impurity is Al, the doping dose is 1e10 ~5e10 cm -3 , energy is 10keV~1MeV, N-type ion implantation, the doping impurity is N, the doping dose is 1e10~5e10 cm -3 , energy is 1.2MeV~10MeV.

7. The method for preparing a normally-off silicon carbide high-voltage JFET device based on an extended conductive channel according to claim 4, wherein: Highly doped N-type ion implantation, where the doping impurity is N and the doping dose is 1e11 ~5e11 cm -3 , the energy is 1.2MeV~10MeV; the highly doped P-type ion implantation, the doping impurity is Al, the doping dose is 1e11~5e11 cm -3 , energy is 1.2MeV~10MeV.

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