Display substrate, display panel and display device

Abstract

The invention discloses a display substrate, a display panel and a display device. The display substrate comprises a substrate (10); a plurality of data lines (DL) on the substrate (10), the data lines (DL) extending in a first direction; the touch control layer is located on the side, away from the substrate (10), of the layer where the data lines (DL) are located, the touch control layer comprises a plurality of touch control electrodes (20) which are configured to be multiplexed as common electrodes, and each touch control electrode (20) comprises a plurality of touch control sub-electrodes (21) which are electrically connected with one another; wherein the touch sub-electrodes (21) are arranged in an array mode in the first direction and the second direction, a first slit (20a) is formed between every two adjacent touch sub-electrodes (21) in the second direction, and the orthographic projection of the first slits (20a) on the substrate (10) and the orthographic projection of the data lines (DL) on the substrate (10) are overlapped; the first direction intersects with the second direction; the touch control signal lines (TL) are located on the side, away from the substrate (10), of the touch control layer, the touch control signal lines (TL) are connected with the touch control electrodes (20), and the orthographic projection of at least one touch control signal line (TL) on the substrate (10) covers the orthographic projection of the first slit (20a) on the substrate (10).

Description

Display substrate, display panel, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate, a display panel, and a display device. Background Art

[0002] A liquid crystal display panel consists of a display substrate and a counter substrate positioned opposite each other, with a liquid crystal layer located between them. The liquid crystal layer is deflected by the electric field between the pixel electrode and the common electrode, allowing light to pass through. In some products, touchscreen functionality can also be integrated into the LCD panel, enabling simultaneous touch control and display.

[0003] Summary of the Invention

[0004] The present disclosure provides a display substrate, a display panel, and a display device.

[0005] The present disclosure provides a display substrate, comprising:

[0006] substrate;

[0007] a plurality of data lines located on the substrate, the data lines extending along a first direction;

[0008] a touch layer located on a side of the layer containing the data lines away from the substrate, the touch layer comprising a plurality of touch electrodes configured to function as common electrodes, the touch electrodes comprising a plurality of touch sub-electrodes electrically connected to each other; wherein the touch sub-electrodes are arranged in an array along the first direction and the second direction, a first slit is defined between two adjacent touch sub-electrodes along the second direction, an orthographic projection of the first slit on the substrate overlaps an orthographic projection of the data lines on the substrate; and the first direction intersects the second direction.

[0009] A plurality of touch signal lines are located on a side of the touch layer away from the substrate, the touch signal lines are connected to the touch electrodes, and the orthographic projection of at least one touch signal line on the substrate covers the orthographic projection of the first slit on the substrate.

[0010] In some embodiments, at least one of the touch signal lines overlaps with the orthographic projections of the touch sub-electrodes on both sides of the first slit on the substrate.

[0011] In some embodiments, an overlapping width along the second direction between the orthographic projection of the touch signal line on the substrate and the orthographic projection of the touch sub-electrodes on both sides of the first slit on the substrate is a first width, and the first width is 1 to 1.2 times the first preset width D.

[0012] Among them, D1 is the maximum displacement fluctuation value in the touch signal line manufacturing process; D2 is the maximum unilateral size fluctuation value in the touch signal line manufacturing process; D3 is the maximum unilateral size fluctuation value in the touch sub-electrode manufacturing process.

[0013] In some embodiments, the first width is equal to D.

[0014] In some embodiments, the first width is between 1.69 μm and 2.0 μm.

[0015] In some embodiments, the orthographic projection of each touch signal line on the substrate covers the orthographic projection of the first slit on the substrate, and overlaps with the orthographic projections of the touch sub-electrodes on both sides of the first slit on the substrate.

[0016] In some embodiments, the display substrate has a display area, at least a portion of the data line and the touch layer are located in the display area, and a plurality of gate lines are further provided in the display area. The plurality of gate lines and the plurality of data lines divide the display area into a plurality of pixel areas, and pixel electrodes are provided in the pixel areas. The pixel electrodes are located on a side of the touch layer away from the substrate, and a second slit is provided on the pixel electrode.

[0017] In some embodiments, a first passivation layer is provided between the touch layer and the touch signal line, a second passivation layer is provided on the side of the touch signal line layer away from the substrate, and the pixel electrode is provided on the side of the second passivation layer away from the substrate.

[0018] In some embodiments, the display substrate further comprises a peripheral region surrounding the display region, and the display substrate further comprises:

[0019] A first signal transmission component is provided on the same layer as the gate line;

[0020] a second signal transmission component, disposed on the same layer as the data line;

[0021] A connecting member is provided in the same layer as the pixel electrode, and the connecting member is connected to the first signal transmission member through a first via hole, and is connected to the second signal transmission member through a second via hole.

[0022] In some embodiments, a passivation layer is provided on the side of the touch layer away from the substrate, and the touch signal line and the pixel electrode are both located on the side of the passivation layer away from the substrate; a protective layer is also provided on the side of the touch signal line away from the substrate, and the protective layer covers the touch signal line and is provided on the same layer as the pixel electrode.

[0023] In some embodiments, the orthographic projection of the protective layer on the substrate exceeds the orthographic projection of the touch signal line on the substrate, and the width of the exceeding portion is 1 to 1.2 times the second preset width D'.

[0024] Among them, D1 is the maximum displacement fluctuation value in the touch signal line manufacturing process; D2 is the maximum unilateral size fluctuation value in the touch signal line manufacturing process; D4 is the maximum displacement fluctuation value in the protective layer manufacturing process; D5 is the maximum unilateral size fluctuation value in the protective layer manufacturing process.

[0025] In some embodiments, the display substrate further comprises a peripheral region surrounding the display region, and the display substrate further comprises:

[0026] A first signal transmission component is provided on the same layer as the gate line;

[0027] a second signal transmission component, disposed on the same layer as the data line;

[0028] A first connector and a second connector are stacked and connected, wherein the first connector is arranged on the same layer as the touch line, the first connector is connected to the first signal transmission component through a first via, and is connected to the second signal transmission component through a second via; the second connector is located on a side of the first connection layer away from the substrate, and the second connector is arranged on the same layer as the pixel electrode.

[0029] In some embodiments, the first conductive layer and the second conductive layer coincide with each other in orthographic projection on the substrate.

[0030] In some embodiments, the display substrate further includes: a plurality of common electrode lines, the common electrode lines are located between the touch layer and the substrate, and the touch electrodes are electrically connected to the common electrode lines.

[0031] In some embodiments, the touch signal line includes: a plurality of first line segments arranged along a first direction and a second line segment connected between two adjacent first line segments, wherein the orthographic projections of the first line segments on the substrate overlap with the orthographic projections of the first slits on the substrate, and the orthographic projections of at least a portion of the second line segments on the substrate do not overlap with the orthographic projections of the first slits on the substrate;

[0032] Each of the touch electrodes is connected to the second line segment of a corresponding touch signal line.

[0033] In some embodiments, each of the touch electrodes is connected to a plurality of second line segments of a corresponding touch signal line.

[0034] In some embodiments, in the same touch electrode, one of the touch sub-electrodes in each row is connected to the touch signal line; two adjacent touch sub-electrodes in the same row are connected by a connecting portion, and the connecting portion and the touch sub-electrode are an integrated structure.

[0035] In some embodiments, the display substrate further includes a plurality of gate lines, and an orthographic projection of the second line segment on the substrate overlaps with an orthographic projection of the gate line on the substrate.

[0036] In a second aspect, the present disclosure provides a display panel comprising the above-mentioned display substrate and a color filter substrate arranged opposite to each other.

[0037] In a third aspect, the present disclosure provides a display device comprising the above-mentioned display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following detailed description, they are used to explain the present disclosure but do not constitute a limitation of the present disclosure. In the accompanying drawings:

[0039] FIG. 1 is a schematic diagram of a display substrate provided in some embodiments.

[0040] FIG. 2 is a plan view showing touch electrodes, pixel electrodes, touch signal lines, and data lines in a local area of ​​the display substrate in FIG. 1 .

[0041] FIG3 is a cross-sectional view taken along line AA' in FIG2.

[0042] FIG. 4 is a schematic diagram of area division of a display substrate provided in some embodiments of the present disclosure.

[0043] FIG5 is a partial schematic diagram of a display substrate provided in some embodiments of the present disclosure.

[0044] FIG. 6 is a schematic diagram of the touch electrode in FIG. 5 .

[0045] FIG. 7 is a schematic diagram of the touch electrodes, touch signal lines, and common electrode lines in FIG. 5 .

[0046] FIG8 is a cross-sectional view along line BB′ in FIG5 provided in some embodiments of the present disclosure.

[0047] FIG. 9 is a schematic diagram showing the connection between the pixel electrode and the thin film transistor in FIG. 5 .

[0048] FIG10 is a schematic diagram of a partial structure of the peripheral region and the display region of a display substrate provided in some embodiments of the present disclosure.

[0049] FIG11 is a plan view showing the connection between a first signal transmission member and a second signal transmission member provided in some embodiments of the present disclosure.

[0050] FIG. 12 is a cross-sectional view along line BB′ in FIG. 5 provided in some other embodiments of the present disclosure.

[0051] FIG13 is a schematic diagram of a partial structure of the peripheral area and the display area provided in some other embodiments of the present disclosure.

[0052] FIG14 is a schematic diagram of a display panel provided in some embodiments of the present disclosure. DETAILED DESCRIPTION

[0053] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0054] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0055] It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity. It is also understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intervening layer. It is also understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be one or more intervening layers or elements. It is also understood that when a layer or element is referred to as being "between" two layers or elements, it may be the only layer between the two layers or elements, or there may be one or more intervening layers or elements.

[0056] It should also be noted that the "same-layer arrangement" in the embodiment of the present disclosure means that the two structures are formed by the same material layer through a composition process, so the two are in the same layer in terms of the stacking relationship; but this does not mean that the distance between the two and the substrate must be the same.

[0057] The liquid crystal display panel includes a display substrate and a counter substrate that are arranged opposite to each other, and a liquid crystal layer located therebetween. FIG1 is a schematic diagram of a display substrate provided in some embodiments, FIG2 is a plan view of a touch electrode, a pixel electrode, a touch signal line, and a data line in a local area of ​​the display substrate in FIG1 , and FIG3 is a cross-sectional view along line A-A' in FIG2 . As shown in FIG1 to FIG3 , the display substrate includes a plurality of gate lines GL and a plurality of data lines DL (not shown) arranged on a substrate 10. The plurality of gate lines GL and the plurality of data lines DL are arranged to cross each other to define a plurality of pixel areas PA, and a pixel electrode 30 is provided in each pixel area PA. In addition, the display substrate may further include a common electrode. When the liquid crystal display panel is displaying, the common electrode line (not shown) provides a common voltage to the common electrode, and the data line DL provides a pixel voltage to the pixel electrode 30, thereby generating an electric field between the common electrode and the pixel electrode 30 to drive the liquid crystal to deflect.

[0058] In addition, a touch-sensitive structure can be integrated into the LCD panel, enabling touch control and improving product integration. As shown in Figure 1, the display substrate also includes touch signal lines TL. Common electrodes can be reused as touch electrodes 20, with each touch electrode 20 connected to a touch signal line TL. In this case, the LCD panel implements touch control and display in a time-sharing manner. During the display phase, the common electrode lines provide common voltage signals to the common electrodes; during the touch phase, the touch signal lines TL provide touch drive signals to the common electrodes (i.e., touch electrodes 20).

[0059] As shown in Figures 2 and 3, the orthographic projection of the touch signal line TL on the substrate 10 overlaps with the orthographic projection of the data line DL on the substrate 10. The orthographic projection of each touch electrode 20 on the substrate 10 overlaps with multiple pixel areas PA. For example, each touch electrode 20 includes multiple touch sub-electrodes 21 arranged in an array, and the orthographic projection of each touch sub-electrode 21 on the substrate 10 overlaps with the orthographic projection of a pixel electrode 30 on the substrate 10. In the same touch electrode 20, two adjacent touch sub-electrodes 21 in the same row are connected by a connecting portion, and each row of touch sub-electrodes 21 is connected to the touch signal line TL corresponding to the touch electrode 20 through a fourth via V4.

[0060] As shown in FIG3 , on the entire display substrate, there is a first slit 20a between two adjacent touch sub-electrodes 21 in the same row (for example, a slit between two adjacent touch sub-electrodes 21 in the same row in the same touch electrode 20, or a slit between two adjacent touch electrodes 20 in the same row). The orthographic projections of the touch signal line TL and the data line DL on the substrate 10 overlap with the orthographic projections of the first slit 20a on the substrate 10. In some embodiments, the width of the touch signal line TL is smaller than the width of the first slit 20a. However, since the voltage on the data line DL is the same as that on the pixel electrode 30, for the structures shown in FIG2 and FIG3 , a lateral electric field is generated between the data line DL and the touch sub-electrode 21, thereby causing the liquid crystal deflection in the pixel area PA near the data line DL position (such as the A1 and A2 areas in FIG3 ) to be disordered, thereby causing pixel light leakage.

[0061] Figure 4 is a schematic diagram of the regional division of a display substrate provided in some embodiments of the present disclosure. Figure 5 is a partial schematic diagram of a display substrate provided in some embodiments of the present disclosure. Figure 6 is a schematic diagram of the touch electrodes in Figure 5. Figure 7 is a schematic diagram of the touch electrodes, touch signal lines, and common electrode lines in Figure 5. Figure 8 is a cross-sectional view taken along line BB' in Figure 5 provided in some embodiments of the present disclosure. As shown in Figures 4 to 8, the display substrate includes a substrate 10 and, disposed on the substrate 10, a plurality of gate lines GL, a plurality of data lines DL, a plurality of touch signal lines TL, and a touch layer. The display substrate has a display area AA and a peripheral area WA surrounding the display area AA. At least a portion of the gate lines GL and at least a portion of the data lines DL are located in the display area AA. The data lines DL extend along a first direction, and the gate lines GL extend along a second direction. The plurality of gate lines GL and the plurality of data lines DL define a plurality of pixel areas PA in the display area AA. The first direction intersects the second direction, for example, the two are perpendicular.

[0062] It should be noted that the data line DL extending along the first direction does not necessarily mean that the data line DL is a straight line extending along the first direction; it may also have some bends, as long as the data line DL has a tendency to extend along the first direction as a whole. Similarly, the gate line GL extending along the second direction means that the gate line GL has a tendency to extend along the first direction as a whole.

[0063] The touch layer is located on the side of the layer containing the data lines DL, away from the substrate 10. The touch layer includes multiple touch electrodes 20, which are reused as common electrodes. Each touch electrode 20 may include multiple electrically connected touch sub-electrodes 21. The multiple touch sub-electrodes 21 in the touch layer are arranged in an array along a first direction and a second direction. Specifically, the multiple touch sub-electrodes 21 in the touch layer are arranged in multiple rows along the first direction, and each row includes multiple touch sub-electrodes 21 arranged along the second direction. As shown in Figures 6 and 8, a first slit 20a is defined along the second direction between two adjacent touch sub-electrodes 21. That is, a first slit 20a is defined between two adjacent touch sub-electrodes 21 in the same row. The orthographic projection of the first slit 20a on the substrate 10 overlaps with the orthographic projection of the data lines DL on the substrate 10.

[0064] It should be understood that the so-called "two adjacent touch sub-electrodes 21 in the same row" can be two adjacent touch sub-electrodes 21 arranged along the second direction in the same touch electrode 20, or two adjacent touch sub-electrodes 21 located in two touch electrodes 20 and arranged along the second direction.

[0065] Among them, the first slit 20a can be a strip structure extending along the first direction. It should be noted that the first slit 20a can be a straight strip structure extending along the first direction, or a bent strip structure, as long as the first slit 20a has a tendency to extend along the first direction as a whole.

[0066] Multiple touch signal lines TL are located on a side of the touch layer away from the substrate 10. The touch signal lines TL are connected to the touch electrodes 20. The orthographic projection of at least one touch signal line TL on the substrate 10 overlaps the orthographic projection of the first slit 20a on the substrate 10. The orthographic projection of at least one touch signal line TL on the substrate 10 completely covers the orthographic projection of the first slit 20a. Specifically, the width of the touch signal line TL in the second direction is greater than the width of the first slit 20a in the second direction. For example, the first slit 20a has two first edges arranged in the second direction. The orthographic projections of the edges of the touch signal line TL on the substrate 10 may contact the edges of the first edges on the substrate 10. Alternatively, the orthographic projection of the touch signal line TL on the substrate 10 may extend beyond the orthographic projection of the first slit 20a on the substrate 10 and overlap with the orthographic projection of the touch sub-electrode 21 on the substrate 10.

[0067] During the display stage, the touch sub-electrode 21 and the touch signal line TL will receive a common voltage signal. Since in the embodiment of the present disclosure, the orthographic projection of the touch signal line TL on the substrate 10 covers the orthographic projection of the first slit 20a on the substrate 10, the touch signal line TL can shield the electric field formed between the data line DL and the touch sub-electrode 21, preventing the electric field from affecting the deflection of the liquid crystal and causing light leakage, thereby ensuring the display effect.

[0068] In some embodiments, as shown in Figure 8, the orthographic projection of at least one touch signal line TL on the substrate 10 covers the orthographic projection of the first slit 20a on the substrate 10, and overlaps with the orthographic projections of the touch sub-electrodes 21 on both sides of the first slit 20a on the substrate 10, thereby further ensuring the shielding effect of the touch signal line TL on the electric field between the data line DL and the touch sub-electrode 21.

[0069] It should be noted that the touch sub-electrodes 21 on both sides of the first slit 20 a refer to both sides of the first slit 20 a along the second direction.

[0070] In some embodiments, the orthographic projection of each touch signal line TL on the substrate 10 covers the orthographic projection of the first slit 20a on the substrate 10, and overlaps with the orthographic projections of the touch sub-electrodes 21 on both sides of the first slit 20a on the substrate 10, so as to ensure that light leakage does not occur in the adjacent positions of each touch signal line TL.

[0071] In some embodiments, a data driver chip 71 is disposed on one side of the display area AA to provide data signals to the data lines DL. Touch signal lines TL extend from one end of the display area AA closest to the data driver chip 71 to the other end farther from the data driver chip 71. This ensures that the orthographic projection of each first slit 20a on the substrate 10 is covered by the orthographic projection of the touch signal line TL on the substrate 10, thereby improving light leakage prevention.

[0072] In some embodiments, the overlap width between the orthographic projection of the touch signal line TL on the substrate 10 and the orthographic projection of the touch sub-electrodes 21 on both sides of the first slit 20a on the substrate 10 is a first width W. It should be noted that the overlap width refers to the width of the overlapping area in the second direction. The first width W can be set according to a first preset width D, which is a parameter related to the manufacturing process. Specifically,

[0073] Wherein, D1 is the maximum displacement fluctuation value in the touch signal line TL manufacturing process. The maximum position fluctuation value of a device in the manufacturing process refers to the distance between the actual position and the target position of the center of the device on the substrate 10 due to the accuracy of the manufacturing process. D2 is the maximum unilateral dimension fluctuation value in the touch signal line TL manufacturing process. Specifically, if the target width of the touch signal line TL is W1 and the actual width is W2, then |W1-W2| / 2 is the unilateral dimension fluctuation value, and the maximum value of |W1-W2| / 2 is D2. D3 is the maximum dimension fluctuation value in the touch sub-electrode 21 manufacturing process. D3 refers to the maximum unilateral dimension fluctuation value of the touch sub-electrode 21. Specifically, if the target width of the touch sub-electrode 21 is W3 and the actual width is W4, then the maximum value of |W3-W4| / 2 is D2.

[0074] In some embodiments, the first width W is 1 to 1.2 times of D. In this case, even if process fluctuations occur during the manufacturing process, the orthographic projection of the touch signal line TL on the substrate 10 can still cover the orthographic projection of the first slit 20 a on the substrate 10 .

[0075] Preferably, the first width is D, so as to ensure that when process fluctuations occur, the orthographic projection of the touch signal line TL on the substrate 10 covers the orthographic projection of the first slit 20a on the substrate 10, and the overlapping area between the touch signal line TL and the touch electrode 20 is not too large to prevent the generation of large parasitic capacitance and affect the touch effect.

[0076] In one example, D1=1.5μm, D2=0.6μm, D3=0.5μm, and D=1.69. At this time, the first width W can be set between 1.69 and 2.0μm. For example, W is set to 1.69μm, 1.7μm, 1.8μm, 1.9μm, or 2.0μm.

[0077] Among them, in the display panel, the cell substrate arranged opposite to the display substrate includes a black matrix. The orthographic projection of the black matrix on the substrate 10 covers the orthographic projection of the data line DL, the gate line GL, and the touch signal line TL on the substrate 10. In order to increase the effective light-emitting area of ​​the pixel area, the touch signal line CL and the data line DL can be set to a smaller width. In one example, the width of the first slit 20a is between 3 and 7 μm, W is between 1.69 and 2.0 μm, and the width of the data line DL is between 4 and 6 μm, so that the touch signal line TL and the data line DL have a smaller width, and thus the black matrix has a smaller width to increase the effective light-emitting area of ​​the pixel area. For example, in the structure of Figure 8, the width of the data line DL is 5 μm, the width of the touch signal line TL is 7 μm, the width of the first slit 20a is 3.6 μm, and W is set to 1.7 μm.

[0078] As shown in Figures 5 and 8, a pixel electrode 30 is provided in each pixel area PA. The pixel electrode 30 is located on the side of the touch layer away from the substrate 10, and a second slit 30a is provided on the pixel electrode 30. The second slit 30a can be a zigzag shape. It should be noted that Figure 8 only shows the structure of the data line DL and the film layer above it. The structure between the data line DL and the substrate 10 can be seen in Figure 9. Figure 9 is a schematic diagram of the connection between the pixel electrode and the thin film transistor in Figure 5. As shown in Figures 5 and 9, each pixel area PA corresponds to a thin film transistor 50, and the thin film transistor 50 includes a gate 51, an active layer 52, a source 53, and a drain 54.

[0079] The gate 51 of the thin film transistor 50 and the gate line GL are formed as an integral structure, and a gate insulating layer GI is provided on the side of the layer where the gate line GL is located away from the substrate 10. The materials of the gate 51 and the gate line GL may include metal, metal alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. For example, the gate electrode 51 and the gate line GL may include gold (Au), a gold alloy, silver (Ag), a silver alloy, aluminum (Al), an aluminum alloy, aluminum nitride (AlNx), tungsten (W), tungsten nitride (WNx), copper (Cu), a copper alloy, nickel (Ni), chromium (Cr), chromium nitride (CrNx), molybdenum (Mo), a molybdenum alloy, titanium (Ti), titanium nitride (TiNx), platinum (Pt), tantalum (Ta), tantalum nitride (TaNx), neodymium (Nd), scandium (Sc), strontium ruthenium oxide (SRO), zinc oxide (ZnOx), tin oxide (SnOx), indium oxide (InOx), gallium oxide (GaOx), indium tin oxide (ITO), indium zinc oxide (IZO), etc. The gate electrode 51 and the gate line GL may have a single layer or multiple layers.

[0080] The gate insulating layer GI may include, for example, a silicon compound or a metal oxide. For example, the gate insulating layer GI may include silicon oxynitride (SiON), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxycarbide (SiOxCy), silicon carbide nitride (SiCxNy), aluminum oxide (AlOx), aluminum nitride (AlNx), tantalum oxide (TaOx), hafnium oxide (HfOx), zirconium oxide (ZrOx), titanium oxide (TiOx), etc. The gate insulating layer GI may be formed as a single layer or multiple layers.

[0081] The active layer 52 is located on the side of the gate insulating layer GI away from the substrate 10. The active layer 52 may include, for example, an inorganic semiconductor material (e.g., polycrystalline silicon, amorphous silicon, etc.), an organic semiconductor material, or an oxide semiconductor material. The active layer 52 includes a source contact region, a drain contact region, and a channel region located therebetween. The gate electrode and the channel region are disposed opposite each other. The source contact region and the drain contact region may each include impurities with a higher impurity concentration than the channel region. The impurities may include N-type impurities or P-type impurities.

[0082] The source electrode 53 and the drain electrode 54 are located on the side of the active layer 52 away from the substrate 10. The source electrode 53 is connected to the source contact region, and the drain electrode 54 is connected to the drain contact region. The source electrode 53 and the data line DL form an integral structure. The source electrode 53 and the drain electrode 54 are arranged in the same layer. The materials of the source electrode 53 and the drain electrode 54 can include metals, alloys, metal nitrides, conductive metal oxides, transparent conductive materials, etc., and the source electrode 53 and the drain electrode 54 can both be a single layer or multiple layers of metal. For example, the source electrode 53 and the drain electrode 54 are Mo / Al / Mo or Ti / Al / Ti.

[0083] As shown in Figures 5 and 9, the pixel electrode 30 is connected to the drain 54 of the thin film transistor 50 through the fifth via V5. For example, the pixel electrode 30 includes an electrode main body 31 and an electrode connecting portion 32 that are connected to each other, and the electrode connecting portion 32 and the electrode main body 31 can be an integral structure. A second slit 30a is provided on the electrode main body 31, and the electrode main body 31 is located on one side of the electrode main body 31 and is connected to the drain 54 of the thin film transistor 50 through the fifth via V5. The fifth via V5 penetrates the film layers between the layer where the pixel electrode 30 is located and the drain 54. Among them, the pixel electrode 30 and the touch electrode 20 can be made of transparent conductive materials such as indium tin oxide (ITO).

[0084] As shown in FIG5 , the display substrate further includes a plurality of common electrode lines CL. The common electrode lines CL are located between the touch layer and the substrate 10, and the touch electrodes 20 are electrically connected to the common electrode lines CL. The common electrode lines CL can be provided on the same layer as the gate lines GL, and the touch layer is connected to the common electrode lines CL via third vias V3 that penetrate the gate insulating layer GI and the planarization layer PLN.

[0085] The multiple pixel areas PA in the display area AA can be organized into multiple repeating units, each of which includes multiple pixel areas PA, for example, three pixel areas PA (respectively, a red pixel area, a green pixel area, and a blue pixel area). In one example, the orthographic projection of the touch electrode 20 on the substrate 10 overlaps with the multiple repeating units, and each repeating unit is provided with a third via V3, so that the touch electrode 20 is connected to the common electrode line CL through the multiple third vias V3, so that the common voltage received by different positions on the touch electrode 20 is more evenly distributed. For example, each repeating unit is provided with one third via V3.

[0086] Continuing with reference to FIG8 and FIG9 , a planarization layer PLN is provided on the side of the layer where the source electrode 53 and the drain electrode 54 are located away from the substrate 10. The planarization layer PLN may include an organic insulating material, such as a resin material such as polyimide, epoxy resin, acrylic, polyester, photoresist, polyacrylate, polyamide, or silicone. For another example, the organic insulating material may include an elastic material such as urethane or thermoplastic polyurethane (TPU).

[0087] The touch layer is located on the side of the planarization layer PLN away from the substrate 10. A passivation layer PVX is provided on the side of the touch layer away from the substrate 10, and the touch signal line TL and the pixel electrode 30 are both located on the side of the passivation layer PVX away from the substrate 10. The passivation layer PVX may include, for example, a silicon compound or a metal oxide. For example, the passivation layer PVX may include silicon oxynitride (SiON), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxycarbide (SiOxCy), silicon carbide nitride (SiCxNy), aluminum oxide (AlOx), aluminum nitride (AlNx), tantalum oxide (TaOx), hafnium oxide (HfOx), zirconium oxide (ZrOx), titanium oxide (TiOx), etc. The passivation layer PVX may be formed as a single layer or multiple layers.

[0088] In some embodiments, a protective layer 60 is further provided on the side of the touch signal line TL away from the substrate 10. The protective layer 60 is provided in the same layer as the pixel electrode 30. The touch signal line TL can be made of a metal material, and the protective layer 60 can be made of a transparent conductive material such as indium tin oxide (ITO). The protective layer 60 can cover the touch signal line TL, thereby protecting the touch signal line TL from corrosion. The overall resistance of the touch signal line TL and the protective layer 60 is lower than the resistance of the touch signal line TL itself, thereby facilitating the transmission of touch signals. The touch signal line TL has an upper surface away from the substrate 10, a lower surface facing the substrate 10, and a side surface connected between the upper and lower surfaces. The protective layer 60 covering the touch signal line TL can mean that the protective layer 60 covers the upper surface and the side surface of the touch signal line TL.

[0089] In some embodiments, the orthographic projection of the protective layer 60 on the substrate 10 exceeds the orthographic projection of the touch signal line TL on the substrate 10, and the width W' of the exceeding portion is greater than or equal to the second preset width D'. D' is a parameter related to the manufacturing process. Specifically,

[0090] As mentioned above, D1 is the maximum displacement fluctuation during the touch signal line TL manufacturing process; D2 is the maximum unilateral dimensional fluctuation during the touch signal line TL manufacturing process. Furthermore, D4 ​​is the maximum displacement fluctuation during the protective layer 60 manufacturing process; and D5 is the maximum unilateral dimensional fluctuation during the protective layer 60 manufacturing process.

[0091] Setting W' to be greater than or equal to the second preset width D' can ensure that even if process fluctuations occur, the orthographic projection of the protection layer 60 on the substrate 10 can cover the orthographic projection of the touch signal line TL on the substrate 10, thereby ensuring the protection effect of the protection layer 60 on the touch signal line TL.

[0092] In one example, D1 = 1.5 μm, D2 = 0.6 μm, D4 = 1.5 μm, and D5 = 0.5 μm. In this case, W' can be set between 2.26 μm and 2.8 μm, for example, W' is set to 2.26 μm, or 2.3 μm, or 2.45 μm, or 2.5 μm.

[0093] In some embodiments, the touch signal line TL is connected to the touch electrode 20 via a fourth via V4 that penetrates the passivation layer PVX. As shown in Figures 5 to 7 , the touch signal line TL includes a plurality of first line segments TL1 arranged along a first direction and a second line segment TL2 connected between two adjacent first line segments TL1. The orthographic projections of the first line segments TL1 on the substrate 10 overlap with the orthographic projections of the first slits 20a on the substrate 10 and also overlap with the orthographic projections of the data lines DL on the substrate 10. The second line segments TL2 bend toward one side of the data lines DL along their width. The orthographic projections of at least a portion of the second line segments TL2 on the substrate 10 do not overlap with either the orthographic projections of the data lines DL or the first slits 20a on the substrate 10. The orthographic projections of the second line segments TL2 on the substrate 10 overlap with the orthographic projections of the gate lines GL on the substrate 10. Each touch electrode 20 is connected to the second line segment TL2 of a corresponding touch signal line TL.

[0094] In some embodiments, each touch electrode 20 is connected to multiple second line segments TL2 of a corresponding touch signal line TL. For example, each touch electrode 20 includes multiple rows of touch sub-electrodes 21. As shown in FIG6 , in a touch electrode 20, two adjacent touch sub-electrodes 21 in the same row are connected by a connecting portion 20 b, and the connecting portion 20 b and the touch sub-electrode 21 are integrally formed. For example, two adjacent touch sub-electrodes 21 are connected by two connecting portions 20 b, and the gap between the two connecting portions 20 b and the two touch sub-electrodes 21 can serve as a first slit 20 a. In a touch electrode 20, one touch sub-electrode 21 in each row is connected to the second line segment TL2 of the touch signal line TL.

[0095] In some embodiments, as shown in Figures 5 and 7 , the touch sub-electrode 21 includes a first portion 21a and a second portion 21b, which are connected to form an integral structure. The orthographic projection of the first portion 21a on the substrate 10 overlaps with the orthographic projection of the pixel electrode 30 on the substrate 10. The second portion 21b is located to one side of the first portion 21a and is connected to the touch signal line TL through a fourth via V4. The fourth via V4 corresponding to the touch sub-electrode 21 and the first portion 21a of the touch sub-electrode 21 can be located on opposite sides of the gate line GL, respectively.

[0096] Figure 10 is a schematic diagram of a portion of the structure of the peripheral region and display region of a display substrate provided in some embodiments of the present disclosure. Figure 11 is a plan view of the connection between the first signal transmission member and the second signal transmission member provided in some embodiments of the present disclosure. As shown in Figure 10, the display substrate further includes: a first signal transmission member 91, a second signal transmission member 92, a first connector 81, and a second connector 82 located in the peripheral region WA. The first connector 81 and the second connector 82 are stacked and contact each other. The first signal transmission member 91 is disposed on the same layer as the gate line GL, and the second signal transmission member 92 is disposed on the same layer as the data line DL. The first connector 81 is disposed on the same layer as the touch signal line TL. As shown in Figures 10 and 11, the first connector 81 is connected to the first signal transmission member 91 through a first via V1 and to the second signal transmission member 92 through a second via V2. The number of the first via V1 and the second via V2 can be one or more. The second connector 82 is located on the side of the first connector 81 away from the substrate 10 and is disposed on the same layer as the pixel electrode 30.

[0097] In some embodiments, the first signal transmission member 91, the second signal transmission member 92, and the touch signal line TL contain the same metal component. In this case, disposing the first connector 81 in the same layer as the touch signal line TL can prevent the first and second signal transmission members 91 and 92 from being corroded during the etching process of the touch signal line TL without increasing the number of process steps. The specific reason is as follows: For example, if the touch signal line TL and the second signal transmission line are both Mo / Al / Mo stacked layers, and the first signal transmission line is MoNb / Cu (all three contain the same metal component Mo), if the first connector 81 is not provided and the first signal transmission member 91 and the second signal transmission member 92 are connected only by the second connector 82 in the same layer as the pixel electrode 30, then after the first via hole V1 and the second via hole V2 are formed, during the patterning process of the touch signal line TL, the etching solution will enter the first via hole V1 and the second via hole V2, thereby corroding the first and second signal transmission members 91 and 92. If the first connecting member 81 is provided, it is not necessary to etch away the metal material above the first via hole V1 and the second via hole V2 during the patterning process of the touch signal line TL, and the etching liquid will not enter the first via hole V1 and the second via hole V2 and corrode the first signal transmission member 91 and the second signal transmission member 92.

[0098] In some embodiments, the first signal transmission element 91 and the second signal transmission element 92 can be used to realize the connection between the gate drive circuit and the gate line GL. As shown in Figure 4, the peripheral area WA is provided with a gate drive circuit 72, and the gate drive circuit 72 includes a plurality of shift register units, each shift register unit corresponding to a gate line GL, and is used to provide a scanning signal for the corresponding gate line GL. Among them, the peripheral area WA is provided with a gate line lead-out portion GL1 corresponding to the gate line GL one by one, and the gate line lead-out portion GL1 is an integral structure with the gate line GL and is connected to the signal output portion of the shift register unit. Among them, the first signal transmission element 81 can be used as the gate line lead-out portion GL1, and the second signal transmission element 82 can be used as the signal output portion of the shift register unit.

[0099] In other embodiments, the first signal transmission member 91 and the second signal transmission member 92 can also be used to realize the electrical connection between the data driver chip 71 and the data line DL. As shown in Figure 4, the peripheral area WA includes a transfer area DA located on one side of the display area AA. A plurality of data line lead portions DL1 are provided in the transfer area DA. The data line lead portions DL1 are connected to the data lines DL in a one-to-one correspondence. For example, the data line lead portions DL1 and the data lines DL form an integral structure. The fan-out line 202 is connected to the data line lead portions DL1 in a one-to-one correspondence. The fan-out line 202 is used to transmit the data signal provided by the data driver chip 71 to the corresponding data line DL. Among them, the first signal transmission member 91 can be used as the fan-out line 202, and the second signal transmission member 92 can be used as the data line lead portion DL1.

[0100] Alternatively, a portion of the first signal transmission components 91 and the second signal transmission components 92 are used to realize the electrical connection between the data driver chip 71 and the data line DL, and another portion of the first signal transmission components 91 and the second signal transmission components 92 are used to realize the connection between the gate driver circuit 72 and the gate line GL.

[0101] Of course, the first signal transmission component 91 and the second signal transmission component 92 can also be used as other signal transmission structures, which are not listed here one by one.

[0102] FIG12 is a cross-sectional view taken along line BB' in FIG5 , provided in some other embodiments of the present disclosure. FIG12 is similar to FIG8 , except that, in FIG12 , a first passivation layer PVX1 and a second passivation layer PVX2 are provided on the side of the touch layer away from the substrate 10. The second passivation layer PVX2 is located on the side of the first passivation layer PVX1 away from the substrate 10. The touch signal line TL is located between the first passivation layer PVX1 and the second passivation layer PVX2. The pixel electrode 30 is located on the side of the second passivation layer PVX2 away from the substrate 10. In this case, a fourth via hole V4 for connecting the touch signal line TL and the touch electrode 20 passes through the first passivation layer PVX1, and a third via hole V3 for connecting the touch electrode 20 and the common electrode line CL passes through the first passivation layer PVX1, the second passivation layer PVX2, the planarization layer PLN, and the gate insulating layer GI.

[0103] The materials of the first passivation layer PVX1 and the second passivation layer PVX2 can both be selected from the materials of the passivation layer PVX listed above.

[0104] Compared with FIG8 , FIG12 shows a display substrate in which two passivation layers are provided, while FIG8 shows a display substrate in which only one passivation layer PVX is provided, thereby reducing the film layer structure and simplifying the manufacturing process.

[0105] In Figure 12 , the orthographic projection of the touch signal line TL on the substrate 10 can also overlap with the orthographic projections of the touch sub-electrodes 21 on both sides of the first slit 20a. The width of the overlapping area is between D and 1.2D. For example, the first width is between 1.69 μm and 2.0 μm. In one example, the width of the first slit 20a is 6.6 μm, the width of the touch signal line TL is 10.0 μm, the first width is 1.7 μm, and the width of the data line DL is 4.2 μm.

[0106] Figure 13 is a partial structural schematic diagram of the peripheral area and the display area provided in some other embodiments of the present disclosure. As shown in Figure 13, when the display substrate includes a first passivation layer PVX1 and a second passivation layer PVX2, and the touch signal line TL is located between the first passivation layer PVX1 and the second passivation layer PVX2, and the pixel electrode 30 is located on the side of the second passivation layer PVX2 away from the substrate 10, the first signal transmission element 91 and the second signal transmission element 92 in the peripheral area WA can be connected through a connector 80, wherein the connector 80 is arranged on the same layer as the pixel electrode 30, and the connector 80 is connected to the first signal transmission element 91 through a first via V1, and is connected to the second signal transmission element 92 through a second via V2. For the display substrate shown in Figure 13, during the manufacturing process, the first via hole V1 and the second via hole V2 can be formed after the second passivation layer PVX2 is formed, and the composition process of the touch signal line TL is completed after the first passivation layer PVX1 is formed. Therefore, during the composition process of the touch signal line TL, the etching liquid will not contact the first signal transmission component 91 and the second signal transmission component 92.

[0107] The present disclosure also provides a display panel. FIG14 is a schematic diagram of a display panel provided in some embodiments of the present disclosure. As shown in FIG14 , the display panel includes the display substrate described in the above embodiments and a cell substrate 100. The display substrate and the cell substrate 100 are disposed opposite each other. In addition, the display panel may further include a liquid crystal layer 200 located between the display substrate and the cell substrate 100. The cell substrate 100 may be a color filter substrate, which includes a color filter layer and a black matrix 102 disposed on a base 101. The color filter layer includes multiple color filter portions 103, such as a red filter portion, a green filter portion, and a blue filter portion. Each pixel region is disposed opposite each color filter portion 103. The red pixel region herein refers to a pixel region opposite a red filter portion, the green pixel region refers to a pixel region opposite a green filter portion, and the blue pixel region refers to a pixel region opposite a blue filter portion. The orthographic projection of the black matrix 102 on the substrate 10 covers the orthographic projections of the gate lines, data lines DL, touch signal lines TL, and thin film transistors on the substrate 10.

[0108] In one example, the width of the first slit 20a is between 3 and 7 μm, the overlapping width of the orthographic projection of the touch signal line TL on the substrate 10 and the orthographic projection of the touch sub-electrode 21 on the substrate 10 is between 1.69 and 2.0 μm, and the width of the data line DL is between 4 and 6 μm. Because the touch signal line TL in the disclosed embodiment can shield the electric field formed between the data line DL and the touch sub-electrode 21, preventing the electric field from affecting the deflection of the liquid crystal and causing light leakage, the width of the black matrix 102 does not need to be set larger. For example, the width of the black matrix 102 can be smaller than the width of the touch signal line TL.

[0109] The present disclosure also provides a display device comprising the display panel of the above embodiment. The display device can be any product or component with a display function, such as electronic paper, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system.

[0110] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing the disclosure herein. This disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the following claims.

[0111] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes can be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A display substrate, comprising: substrate; A plurality of data lines located on the substrate, the data lines extending along a first direction; A touch layer is located on a side of the layer where the data line is located away from the substrate, the touch layer includes a plurality of touch electrodes configured to be multiplexed as a common electrode, the touch electrodes include a plurality of touch sub-electrodes electrically connected to each other; wherein the touch sub-electrodes are arranged in an array along the first direction and the second direction, a first slit is provided between two adjacent touch sub-electrodes along the second direction, and an orthographic projection of the first slit on the substrate overlaps with an orthographic projection of the data line on the substrate; and the first direction intersects with the second direction; A plurality of touch signal lines are located on a side of the touch layer away from the substrate, the touch signal lines are connected to the touch electrodes, and an orthographic projection of at least one of the touch signal lines on the substrate covers an orthographic projection of the first slit on the substrate.

2. The display substrate according to claim 1, characterized in that: At least one of the touch signal lines overlaps with the orthographic projections of the touch sub-electrodes on both sides of the first slit on the substrate.

3. The display substrate according to claim 2, wherein: The overlap width of the orthographic projection of the touch signal line on the substrate and the orthographic projection of the touch sub-electrodes on both sides of the first slit on the substrate along the second direction is a first width, and the first width is 1 to 1.2 times the first preset width D. Among them, D1 is the maximum displacement fluctuation value in the touch signal line manufacturing process; D2 is the maximum single-side size fluctuation value in the touch signal line manufacturing process; D3 is the maximum single-side size fluctuation value in the touch sub-electrode manufacturing process.

4. The display substrate according to claim 3, wherein: The first width is equal to D.

5. The display substrate according to claim 3, wherein: The first width is between 1.69 μm and 2.0 μm.

6. The display substrate according to any one of claims 2 to 5, wherein: The orthographic projection of each of the touch signal lines on the substrate covers the orthographic projection of the first slit on the substrate, and overlaps with the orthographic projections of the touch sub-electrodes on both sides of the first slit on the substrate.

7. The display substrate according to any one of claims 1 to 6, wherein: The display substrate has a display area, at least a portion of the data lines and the touch layer are located in the display area, a plurality of gate lines are also arranged in the display area, the plurality of gate lines and the plurality of data lines divide the display area into a plurality of pixel areas, a pixel electrode is arranged in the pixel area, the pixel electrode is located on a side of the touch layer away from the substrate, and a second slit is arranged on the pixel electrode.

8. The display substrate according to claim 7, wherein: A first passivation layer is arranged between the touch layer and the touch signal line, a second passivation layer is arranged on a side of the layer where the touch signal line is located away from the substrate, and the pixel electrode is arranged on a side of the second passivation layer away from the substrate.

9. The display substrate according to claim 8, wherein: The display substrate further comprises a peripheral area surrounding the display area, and the display substrate further comprises: A first signal transmission element is arranged in the same layer as the gate line; A second signal transmission element is arranged on the same layer as the data line; A connecting member is arranged in the same layer as the pixel electrode, and the connecting member is connected to the first signal transmission member through a first via hole, and is connected to the second signal transmission member through a second via hole.

10. The display substrate according to claim 7, wherein: A passivation layer is arranged on the side of the touch layer away from the substrate, and the touch signal line and the pixel electrode are both located on the side of the passivation layer away from the substrate; a protective layer is also arranged on the side of the touch signal line away from the substrate, and the protective layer covers the touch signal line and is arranged on the same layer as the pixel electrode.

11. The display substrate according to claim 11, wherein: The orthographic projection of the protection layer on the substrate exceeds the orthographic projection of the touch signal line on the substrate, and the width of the exceeding portion is 1 to 1.2 times of the second preset width D'. Among them, D1 is the maximum displacement fluctuation value in the touch signal line manufacturing process; D2 is the maximum unilateral size fluctuation value in the touch signal line manufacturing process; D4 is the maximum displacement fluctuation value in the protective layer manufacturing process; D5 is the maximum unilateral size fluctuation value in the protective layer manufacturing process.

12. The display substrate according to claim 7, wherein: The display substrate further comprises a peripheral area surrounding the display area, and the display substrate further comprises: A first signal transmission element is arranged in the same layer as the gate line; A second signal transmission element is arranged on the same layer as the data line; A first connector and a second connector are stacked and connected, wherein the first connector is arranged in the same layer as the touch line, the first connector is connected to the first signal transmission component through a first via hole, and is connected to the second signal transmission component through a second via hole; the second connector is located on a side of the first connection layer away from the substrate, and the second connector is arranged in the same layer as the pixel electrode.

13. The display substrate according to claim 12, wherein: The orthographic projections of the first conductive layer and the second conductive layer on the substrate coincide with each other.

14. The display substrate according to any one of claims 1 to 13, wherein: The display substrate further includes: a plurality of common electrode lines, wherein the common electrode lines are located between the touch layer and the substrate, and the touch electrodes are electrically connected to the common electrode lines.

15. The display substrate according to any one of claims 1 to 14, wherein: The touch signal line includes: a plurality of first line segments arranged along a first direction and a second line segment connected between two adjacent first line segments, the orthographic projections of the first line segments on the substrate overlap with the orthographic projections of the first slits on the substrate, and the orthographic projections of at least a portion of the second line segments on the substrate do not overlap with the orthographic projections of the first slits on the substrate; Each of the touch electrodes is connected to the second line segment of a corresponding touch signal line.

16. The display substrate according to claim 15, wherein: Each of the touch electrodes is connected to a plurality of second line segments of a corresponding touch signal line.

17. The display substrate according to claim 15, wherein: In the same touch electrode, one of the touch sub-electrodes in each row is connected to the touch signal line; two adjacent touch sub-electrodes in the same row are connected via a connecting portion, and the connecting portion and the touch sub-electrode are an integral structure.

18. The display substrate according to claim 15, wherein: The display substrate further includes a plurality of gate lines, and an orthographic projection of the second line segment on the substrate overlaps with an orthographic projection of the gate line on the substrate.

19. A display panel, comprising the display substrate and the color film substrate according to any one of claims 1 to 18 arranged opposite to each other.

20. A display device comprising the display panel according to claim 19.

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