Channel sharing data gating

Abstract

A shared data strobe signal is simultaneously applied to temporal data reception in two or more transactional independent memory channels, the strobe signaling overhead being reduced by at least half compared to a conventional per-channel strobe solution.

Description

Technical Field

[0001] The disclosure herein relates to synchronous memory components and systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Various embodiments disclosed herein are illustrated by way of example and not limitation in the accompanying drawings in which like reference numerals represent similar elements and in which:

[0003] Figure 1 An embodiment of a strobe-sharing dual channel memory system having a dual channel dynamic random access memory (DRAM) component and a dual channel memory control component is illustrated;

[0004] Figure 2 Pictured Figure 1 An example sequence of memory read operations within a shared gate memory system;

[0005] Figure 3 illustrates an exemplary shared data strobe transmission from a control component to a memory component in conjunction with overlapping channel A and channel B column write requests;

[0006] Figure 4 illustrates another shared data strobe example, in this case a time offset sequence of column read transactions for both the A and B memory channels;

[0007] Figure 5 The diagram shows Figure 1 An exemplary shared strobe conflict resolution scheduling circuit device implemented in the control component of the embodiment of the present invention reorders and retimes the column access commands to ensure the same direction transmission of any concurrent data bursts on the A and B memory channels;

[0008] Figure 6 illustrates a more detailed embodiment of a shared gated DRAM component, which explicitly shows the channel A and channel B command / address interfaces and command execution state machines for the A and B memory channels;

[0009] Figure 7 illustrates an alternative shared gate multi-channel memory component in which different A and B memory channels are implemented in counterpart package integrated DRAM dies; and

[0010] Figure 8 Illustrated is an exemplary implementation of at least a portion of a data PHY (physical signaling interface) controller, a data strobe controller, a data PHY, a strobe PHY, and a strobe input / output interface, which may be instantiated Figure 7 The component of the same name within a DRAM die. DETAILED DESCRIPTION

[0011] In various embodiments herein, a shared data strobe signal is simultaneously applied to time data reception in two or more transaction-independent memory channels, and the strobe overhead is reduced by at least half compared to conventional per-channel strobe solutions. In multiple embodiments, a single integrated circuit memory die is implemented with multiple memory channels having corresponding / different command interfaces and memory cores to enable concurrent execution of independent channel-specific memory read and write command streams. The corresponding channel-specific read data and write data streams are sent / received by corresponding channel-specific on-die data transceiver sets, and the synchronous operation of these transceivers is timed by channel-shared data strobe signals instead of conventional per-channel strobe signals. In this way, a relatively narrow per-channel data interface (e.g., ×2 (two data lines) or even ×1 (single data line)) can be achieved without the need to add a super-large strobe line overhead, especially when single-ended data signaling (one data line per data signal) is timed by differential strobe (two strobe lines per strobe signal). In other embodiments, similar strobe overhead reduction is achieved in a multi-die integrated circuit package, where a strobe signal received via one die is transmitted and applied to time data signal reception in one or more other dies. These and other features and embodiments are discussed in greater detail below.

[0012] Figure 1 One embodiment of a gated shared dual channel memory system 100 having a dual channel dynamic random access memory (DRAM) unit 101 and a dual channel memory control unit 103 ("controller") is illustrated. Each of the two memory channels 'A' and 'B' within the DRAM unit 101 includes a respective synchronous data interface (105, 107), physical interface control circuitry (109, 111), data path circuitry (113, 115), DRAM core (117, 119) and command / address interface (the latter not specifically shown), arranged so that independent memory accesses can be transacted in each of the two channels (e.g., two different command / address streams directed to and executed in different / independent same die memory channels A and B). The memory control unit 103 ("controller") also includes per-channel command / address queues (not specifically shown) for supplying separate command / address value streams to the A and B memory channels, as well as channel-specific synchronous data interfaces 135, 137, physical interface controllers 139, 141, and read / write data queues 143, 145.

[0013] exist Figure 1In the embodiment of the invention, a synchronous and bidirectional data interface (DQ) is implemented in both the DRAM and control components (105 / 107 and 135 / 137) with a relatively narrow 2-bit (×2) width (i.e., each channel supports two bidirectional single-ended data links), and data reception in the destination component (DRAM 101 for writing data, controller 103 for reading data) is timed by a data strobe signal sent by the data source component concurrently with a read or write data burst. However, the two memory channels do not require a conventional per-channel data strobe, but instead share a single differential data strobe (sDQS), which cuts the strobe signaling overhead (contacts in the controller and DRAM die, chip-to-chip conductors / traces, strobe receive / transmit circuitry, etc.) in half, and thereby avoids the heavy strobe to data line ratios that are produced in narrow width data interfaces (i.e., one-to-one differential strobe per channel in a ×2 data interface, requiring two strobe lines DQS+ and DQS- for every two DQ lines). As shown, a channel-shared strobe link ("sDQS link") is coupled between a memory-side strobe interface 151 and a controller-side strobe interface 153, which in turn are coupled to respective strobe controller circuits 155, 157. As described below, the strobe controllers transmit shared incoming strobe signals (write data strobes inbound to the DRAM component and read data strobes inbound to the controller component) to the physical signaling controllers for the two memory channels, where a single channel-shared strobe is used to time data reception for both memory channels.

[0014] refer to Figure 1170, a dual channel DRAM component 101 may be mounted to a face of a memory module 175 (e.g., implementing two rows of such DRAM components on respective faces of a module substrate to form a dual in-line memory module or DIMM) along with a plurality of other identical DRAM components and a dual channel registered clock driver 173 (RCD) having per-DRAM data contacts (two channel A data contacts and two channel B data contacts per memory component), per-DRAM channel shared data strobe contacts (sDQS), and respective command / address contacts for the A and B memory channels. Although not specifically shown, incoming chip select and / or chip ID signals are supplied to the RCD 173, which in turn enables a specified one of a plurality of columns of memory dies (i.e., a subset of the memory dies hosted on the memory module 175, each column constituent memory die coupled to a respective set of module DQ links) to respond to incoming commands. More specifically, in the event of command / address values ​​(CA) arriving via the RCD command / address interface of channel A (i.e., "CA A"), the RCD 173 issues corresponding on-module command / address values ​​(QCA A) to the channel A command / address interface within the module-mounted memory component, and issues corresponding RCD chip select / chip ID signals to enable specific memory ranks (i.e., a subset of the module-mounted DRAM components 101) to respond to these commands - sending or receiving data via their corresponding data interfaces in the case of memory read / write commands, with data reception sampling being timed by a strobe signal transmitted on a channel-shared strobe line coupled to a given memory component within the selected rank. The same is true for command / address values ​​arriving via the RCD command / address interface of channel B - the RCD 173 issues corresponding on-module command / address values ​​(QCA B) to the channel B interface within the memory component (again, in the case of memory read / write commands, enabling the selected rank to send or receive data via its corresponding data interface in response to these command / address values).

[0015] Although Figure 1 In the embodiments shown and described herein, a gated shared DRAM component is shown (and described), but in all such embodiments, integrated circuit memory components implemented with various memory technologies may be deployed to replace or supplement DRAM, including but not limited to static random access memory (SRAM), magnetoresistive random access memory (MRAM), resistive random access memory (RRAM), flash memory, conductive bridging random access memory (CBRAM), etc. In addition, two or more gated shared integrated circuit memory dies may be co-packaged side-by-side or stacked on top of each other.

[0016] Figure 2 Pictured Figure 1An example sequence of memory read operations within a shared gating memory system of the present invention is illustrated, and more specifically, a DRAM "column read" is illustrated when a column address specifies a column of data (after the data page is sent from a row address selected row within a bank address selected memory cell group in a row command triggered activation operation) when a column address is retrieved from a page buffer within the subject DRAM component. As shown, at 191, a column read command (RD) directed to memory channel A is received within the channel A command / address interface ("Com A") of a given DRAM component, for example, a grouped column command and address received / sampled within a two clock cycle interval (2*tck, where tck is the clock cycle supplied to the memory component on the module, and '*' indicates multiplication), which interval corresponds to four consecutive data bit intervals (tbit, also called unit interval) in this double data rate example (i.e., tbit=tck / 2). Three clock cycles later, another column read command 193 directed to memory channel B is received within the channel B command / address interface ("Com B") of the DRAM component. The DRAM component independently executes memory read commands within the A and B memory channels, in each case sending the read data back to the control component along with the channel shared data strobe signal after a predetermined column read delay has occurred. More specifically, at 195, the DRAM component begins sending the shared data strobe signal concurrently with the start of the channel A read data burst (i.e., the active edge of the shared data strobe), and continues sending the shared strobe signal until the end of the channel B read data burst at 197 (the strobe preamble and postamble are not shown). Thus, the shared data strobe transmissions continue across the initial portion of the channel A read data burst (shown with shading to match the channel A read data request), the overlapping portion of the channel A and channel B read data bursts (shaded by channel A column read request and hashed by column B column read request), and then the last portion of the channel B read data burst that extends beyond the conclusion of the channel A read data burst (shown by non-shading and hashed by column read request of channel B).

[0017] Figure 3 An exemplary shared data strobe transmission from the control component to the memory component in conjunction with overlapping (but time offset) channel A and channel B column write requests (205, 207) is illustrated. As shown, the shared data strobe begins with the channel A write data burst at 211 (i.e., the start of the active strobe edge) and continues to the end of the channel B write data burst at 215 - spanning a net interval longer than either the channel A or channel B write data burst alone, the total interval being the write data burst length plus the offset between the channel A and channel B data burst start times (and therefore the offset between the channel A and channel B column write requests, at 216). Figure 3 In the example shown, the offset is established over one clock cycle (1*tck). Figure 3 Not specifically shown in the drawings, but in various embodiments presented herein, strobe preamble and postamble waveforms (leading and trailing active strobe edges) are typically communicated between the controller and the memory components.

[0018] Figure 4 Another shared data strobe example is illustrated, in this case, a time-shifted sequence of column read transactions for both the A and B memory channels - back-to-back column reads via memory channel A (231, 233) and back-to-back column reads in memory channel B (241, 243), the latter (channel B read request) starting three clock cycles later than the former. As shown, the shared data strobe signal starts from the initial channel A read data burst (indicated by light shading) and continues until the end of the final channel B read data burst, thus spanning a continuous interval that is longer than the collective duration of the back-to-back read data bursts on either memory channel alone (i.e., n*t burst + L interval, where 'n' is the maximum number of back-to-back reads on any one channel, t burst is the data burst interval for a given column read, 'L' is the time offset between the start of the initial channel A and channel B read data bursts - applicable as long as the longest read data burst in the collective channel A and B read data bursts does not completely obscure the read data burst on the other channel. As shown, the shared data strobe is initially applied only to the timing read data reception (within the memory control unit) of the channel A read data burst, followed by the shared strobe (sDQS) timing of the read data reception of the two initial column read transactions on both the A and B channels (indicated by shading and scattered dots to match the initial channel A and channel B column read commands), after the end of the initial channel A read data burst and the start of the subsequent channel A read data burst (indicated by darker shading), the sDQS timing of the read data reception of both the initial row read transaction on memory channel B and the last column read transaction on memory channel B, followed by the read data reception timing of the latter transaction data burst for both channels A and B, and finally the read data reception timing of the individual latter channel B data burst.

[0019] exist Figure 1 In various embodiments, the shared data strobe line can only carry data strobes in one direction at a time, thereby prohibiting data from being sent in opposite directions simultaneously on the A and B memory channels - imposing time constraints on the transaction timing of the A and B memory channels to avoid resource contention / conflicts. In various embodiments, the scheduling circuitry within the control component 103 resolves any possible conflicts by reordering and occasionally retiming column access commands within the channel A and / or channel B command queues (not specifically shown) and data queues 143 and 145 to ensure that any concurrent data bursts on the A and B memory channels are sent in the same direction. Figure 5Such operation is illustrated in the context of an exemplary host request sequence (e.g., from one or more CPUs or other transaction requesters) issued to the A and B memory channels. In the depicted example, the command arbiter 251 for channel A receives a write command sequence (W1, then W2) (followed by a read command sequence (R1, then R2)) within the same time interval as the command arbiter 253 for memory channel B receives a read command sequence (R1, R2, R3) (followed by a write command W1). If issued concurrently in the order received, the channel A write command and the initial channel B read command (R1, R2) would generate a conflict with the shared strobe line. In this case, the channel A arbiter 251 avoids this contention by giving priority to the channel A read command over the channel A write command, which is an operation performed to achieve read data delivery as quickly as possible in any case that is not limited by consistency / data dependency issues. As shown, in the revised (after prioritizing reads over writes) command sequence at 261 and 263, there is still a potential shared strobe conflict with respect to the final Channel B memory read command (R3) and the initial Channel A write command (W1) - these commands are shown shaded for emphasis in the sequence 261, 263. To resolve this conflict, the Channel A arbiter 251 (an arbiter with lower priority among other competing / conflicting write and read commands) inserts a delay interval (or timing bubble) into the Channel A command queue to delay the issuance of the initial memory write command (and all subsequent commands) by an interval sufficient to avoid a shared data strobe conflict, e.g., delaying write data transmission until at least a bit interval after receipt of the last bit of the R3 read data burst. The final command queue arrangement is conceptually depicted at 271 and 273, which shows the initially received queued Channel B commands, with the Channel A commands reordered (read before write) and delayed (bubble between R2 and W1) to avoid a shared strobe conflict. Corresponding commands in the two command queues are marked by "×2", where a shared strobe is to be applied bidirectionally (jointly) to time data reception in both A and B memory channels (as appropriate, within the controller or memory component); and by "×1", where a shared strobe is to be applied unidirectionally to dedicated time data reception in one channel or the other. Although the command queues are conceptually depicted as first-in, first-out (FIFO) buffers (e.g., through which command / address values ​​are moved), in actual implementations, the arbiters 251 and 253 may implement such FIFO operations through pointer manipulation (e.g., dynamically selecting which of a set of command / address storage elements is used next to drive the channel A CA PHY 281 / channel B CA PHY 283).

[0020] Figure 6A more detailed embodiment of a shared gating DRAM component 301 is illustrated, which explicitly shows the channel A and channel B command / address interfaces 303 and 305 (various other control signals may be received within the DRAM 301 and in some cases shared between channels, such as clock enable) and the command execution state machines 307 and 309 (or sequencers, command decoders, etc.) for the A and B memory channels. As shown, the shared portion of the channel command / address interfaces 303, 305 (conceptually represented by gray shading) generates an internal clock signal (iCK) in response to the incoming clock signal CK, which is supplied to the shared gating controller 155 and data PHY controllers 109 and 111 of the A and B memory channels - a circuit device collectively referred to herein as a data input / output (IO) controller 310. The internal clock signal may be supplied to the channel A and B state machines (307, 309) and other circuit blocks within the memory component in a divided form or otherwise to achieve clock synchronous operation.

[0021] Referring to the detailed view 350 of the data I / O controller, channel A and B data interfaces (105, 107), and shared data strobe interface 151, the channel A and channel B state machines output (in response to incoming column read and column write commands) read and write enable signals and read strobe and write strobe enable signals to selectively enable the shared strobe data I / O of the A and B memory channels. More specifically, in response to a channel A column write request, the channel A state machine (i) asserts read enable (RdEn A) and read strobe enable (RdStTen A) to the channel A physical interface controller ("PHY Cntrl A") and shared DQS controller ("DQS Cntrl"), respectively, and (ii) asserts write enable (WrEn A) and write strobe enable (WrStEn A) to the channel A PHY controller and shared DQS controller, respectively, the control signals being collectively referred to as "ctA". The channel B state machine likewise asserts RdEn B / RdStEn B and WrEn B / WrStEn B to the channel B PHY controller (“PHY Cntrl B”) and shared DQS controller (ie, “ctB”) in response to channel B column read and column write commands.

[0022] Still referring to the detailed view 350, the read strobe enable assertion of either or both memory channels drives the output of the OR gate 361 within the DQS controller high to enable iCK (internal clock) to propagate through the AND gate 363 and the offset delay element 365 to be output as an outbound read data strobe (via the output driver 367 within the sDQS PHY). The read enable assertion for memory channel A and / or memory channel B (i.e., RdEnA and / or RdEnB) likewise enables iCK to propagate (via the AND gate 371 or 373, followed by the offset delay element 375 or 377) to the timing input of the output flip-flop stage 381 or 383 within the channel A or channel B data PHY, thereby enabling the read data of the corresponding channel (RdD A and / or RdD B) to be clocked into the output flip-flop stage for transmission to the controller component via the output drivers 385 and / or 387 in synchronization with the read data flip-flops. During initial and possibly occasional / periodic training operations, the offset delay elements 365, 377, and 375 are programmed (e.g., digital delay settings corresponding to desired time delays are established) to align data and strobe transmissions to achieve desired controller-side signal arrival. In alternative embodiments, one or more offset delay elements may be omitted to facilitate controller-side sampling time alignment circuitry.

[0023] The assertion of the write strobe enable of either memory channel (WrStEn A and / or WrStEn B) drives the output of OR gate 391 high, which in turn enables the incoming shared data strobe signal (i.e., arriving with the incoming write data) to propagate through AND gate 393 and thereby pass the internal data strobe signal (iDQS) to the inputs of AND gates 395 and 397 within the Channel A and Channel B PHY controllers. When enabled by the assertion of the write enable signal of the corresponding memory channel (WrEn A and / or WrEn B), these AND gates pass the internal data strobe signal through offset delay elements (401, 403) to the timing inputs of input flip-flop stages 405 or 407 to sample the incoming data signal (conditioned within amplifier / buffer 411, 413) to produce the digital write data stream for the subject memory channel (WrD A or WrD B). Thus, when both memory channels are receiving write data concurrently (e.g., simultaneous or at least overlapping incoming write data bursts), the internal data strobe is applied to jointly (bidirectionally) sample the respective data streams of memory channels A and B. In the event that write data is received in only one channel (e.g., during the beginning or end of a write data burst, when the write data stream in one channel leads or lags the write data stream in the other channel, or during intervals when one memory channel is idle), only the active channel write enable (WrEn A or WrEn B) will be asserted, thereby unilaterally strobing the data of only that active channel into the write data register (405 or 407).

[0024] Figure 7 An alternative shared-strobe multi-channel memory component 450 is illustrated, wherein different A and B memory channels are implemented in corresponding packaged integrated DRAM die 451, 453, each die being capable of optionally (according to a programmed configuration) receiving / sending data associated with a strobe received from / sent by the other die, and thus referred to as a remote strobe option (RSO) DRAM die. In the depicted example, each RSO DRAM die (451 and 453) includes a DRAM core 461, a data path circuit device 463, a data PHY controller 465, a data PHY 467, a strobe PHY controller 469, a strobe PHY 471, a command / address interface 473, and a state machine 475, which are generally described in reference to FIG. Figure 1 and Figure 6As shown, the physical data strobe interface is enabled (and connected to external routing within IC package 455) for only one of the two DRAM dies - in this example, Channel A DRAM die 451 is the strobe-enabled die - and is passed through strobe IO interface 477 to the corresponding strobe PHY controller of the other DRAM die 453 (the "auxiliary strobe" die). More specifically, in the event that a memory read or write is commanded within the Channel B memory die (453), the strobe I / O circuitry within that die coordinates (issues a control signal ('C') with the strobe input / output circuitry (477) of the Channel A DRAM die 451 to notify the DQS PHY controller 469 within the die 451 of an impending read data burst transmission or write data burst reception. In the event that the strobe I / O control signal indicates a Channel B read data transmission, the DQS PHY controller 469 for the Channel A memory die responds by enabling data strobe transmission via the Channel A strobe PHY 471 to output a strobe signal from the Channel A DRAM die to the memory control unit to enable strobe-timed reception of read data transmitted by the Channel B memory die (within the memory control unit). In the event that the strobe I / O control signal indicates a Channel B write data reception, the Channel A DQS PHY controller 469 receives the incoming data strobe and routes the strobe to the Channel B DRAM die via the corresponding strobe I / O circuitry 477. PHY controller, at the channel BPHY controller, strobe is applied to the time of reception of incoming write data. Figure 7 In an embodiment, DRAM die 451, 453 include corresponding configuration registers (e.g., "reg" elements within state machine 475) that are programmed to establish the operating mode of the DRAM die as either strobe shared or strobe independent, and if the former (shared strobe), as a strobe enabled die or an auxiliary strobe die (strobe disabled die).

[0025] Figure 8 1 and 2 illustrate exemplary implementations of a PHY controller 501, a DQS controller 503, a data PHY 505, a strobe PHY 507, and a strobe I / O interface 509, which may be instantiated. Figure 7 Components of the same name within each RSO DRAM die shown. In the depicted example, each die (only one of which is shown) can be configured (e.g., by Figure 7The configuration register "reg" shown is programmed for strobe sharing operation (SSen=1) or strobe independent operation (SSen=0), and if strobe sharing is enabled, it can be configured as a strobe enable die (StrEn=1) or a strobe disable die (StrEn=0). When configured for strobe independent operation (no strobe sharing), a logic low SSen signal (i) disables strobe signal reception / transmission and control signal reception / transmission within the strobe I / O interface 509, (ii) enables read strobe reception within the signal receiver 533 via operation of the enable logic 512, and (iii) enables the read strobe enable and write strobe enable signals (from Figure 7 The two local control signals ctL of the local state machine 477 are passed to the logic OR gates 361 and 391 through the corresponding strobe circuits 514 and 516, and thereby enable the read data strobe transmission and the write data strobe distribution, as shown in reference Figure 6 As described above, and (iv) enabling iDQS (an internal write data strobe that propagates through AND gate 395 when WrEn L is asserted), bypassing replica delay element 522 via multiplexer 523 (used to explain the strobe sharing delay discussed below), timing the inbound write data sampling, as described with reference to Figure 6 discussed.

[0026] When the corresponding RSO DRAM die is configured for strobe sharing operation (SSen=1), the control signal drivers 531 and 533 and the write strobe receiver 535 receiver within the strobe I / O interface 509 of one of the strobe-disabled die (StrEn=0) of these dies are enabled to send the locally generated read and write strobe enable signals (RdStEn L and WrStEn L) to the corresponding strobe-enabled die (StrEn=1) and receive the inbound write strobe signal (DQS-In) from the strobe-enabled die. The control signal receivers 541, 543 and the write strobe driver 545 are correspondingly enabled within the strobe-enabled die to receive the inbound remote strobe enable signals (WrStEn R, RdStEn R) and output the locally received write data strobe to the strobe-disabled die (i.e., DQS Out). Although not specifically shown (because only one of the two RSO dies is shown), the drivers 531, 533 and receivers 535 within the gate disable die are coupled to the receivers 541, 543 and drivers 545 within the gate enable die, respectively, via chip-to-chip signaling conductors. The control signal drivers 531, 533 and gate signal receivers 535 are disabled within the gate enable die, while the corresponding control signal receivers 541, 543 and gate signal drivers 545 are disabled within the gate disable die. Thus, the chip-to-chip connection between the signal drivers 531, 533 and receivers 535 within the gate enable die and the signal receivers 541, 543 and drivers 545 within the gate disable die is optional, although when present, enables either of the RSO DRAM dies to be programmed as a gate enable die while the other is programmed as a gate disable die.

[0027] When operating in a strobe sharing configuration (SSen=1), the local and remote strobe enable signals (RdStEn L, WrStEn L, RdStEn R, WrStEn R) within the strobe enable die act similarly to the strobe signal transmission and reception. Figure 6 The channel A and channel B strobe enable signals are shown to be substantially identical. More specifically, the local and remote read strobe enable signals (the former propagating through the gating circuit 514, for example, as shown in detail view 550) are ORed in logic gate 361 to implement shared data strobe transmission via DQSPHY 107, as shown in reference Figure 6 Similarly, the local and remote write strobe enable signals (the former passing through gating circuit 516, which may be implemented identically to circuit 514) are ORed in logic gate 391 to effectuate the distribution of the internal DQS signal (iDQS), generally as described above (with respect to Figure 6), iDQS is also sent to the remote (strobe disabled) die via driver 545 (and received therein via corresponding receiver 535).

[0028] In various embodiments, a host control component (e.g., Figure 1 The controller 103 of the RSO DRAM die is additionally programmed to enable shared strobe operation across multiple RSO DRAM dies, or alternatively, to operate the dies independently (issuing separate strobe signals to each die, rather than issuing a shared strobe signal to only one RSO DRAM die). When programmed for strobe sharing operation, the control component enforces a timing offset between the sending of a write strobe and the sending of write data - sending a write strobe before sending the corresponding write data, and then enforcing a strobe sharing delay (t as shown at 560). strobe-share ), which strobe-shared delay corresponds to the time required (due to initial and possibly ongoing timing alignment operations) for a write strobe signal received via the strobe-enabled die to propagate through the corresponding strobe I / O interface 509 to the DQ PHY 505 of the strobe-disable die. By this operation, the edge of the write strobe signal inbound within the strobe-disable die (i.e., the transition of the DQS In signal received via receiver 535 and propagated via the locally enabled AND gate 561, multiplexers 563 and 623, and optional delay element 401) arrives at the trigger input of the sampling circuit 405 with the desired phase relationship with the write data signal arriving via the signal receiver 411 (e.g., the active edge of the write strobe is aligned with the midpoint of the consecutive write data eyes).

[0029] In various embodiments, the control unit applies the strobe write data offset (i.e., in t) as shown at 560 in write operations directed concurrently to the strobe-enabled die and the strobe-disabled die (bilateral strobe-shared write operations) and in write operations directed exclusively / unilaterally to the strobe-enabled die. strobe-share Therefore, in order to take into account the early arrival of the write strobe in the strobe-sharing / strobe-enabled die (i.e., the time t strobe-share Earlier than writing data), iDQS is routed through replica delay element 522 via the operation of multiplexers 563 and 523 to t strobe-share The propagation of iDQS to the sampling circuit 405 is delayed to achieve the desired strobe / data alignment within the strobe enabled die.

[0030] In an alternative embodiment, the control component can selectively apply t strobe-shareDelay is provided to reduce the latency of write operations specifically to the strobe-enabled die (i.e., without overlapping write data transmissions to the strobe-enabled die and the strobe-disabled die). For example, in one implementation, in response to detecting an interval in which write data is to be transmitted unilaterally to the strobe-enabled component (without transmitting write data to the strobe-disabled die), the control component issues a dedicated "low latency" write command to the strobe-enabled die to instruct the replica delay to be bypassed within the DQ PHY controller 501 to transmit the write data and write strobe with nominally the same timing relationship as in the strobe-disabled DRAM die configuration. The strobe-enabled DRAM die responds to the low latency write command by gating the SSen input of the multiplexer 523 for the duration of the write data burst, bypassing the replica delay element 522 to achieve strobe-timed write data reception at an earlier point in time (less latency) than bilateral write data transmission (i.e., concurrent write data transmission to both the strobe-enabled die and the strobe-disabled die). During bidirectional write data transmission (one or more edges of a shared select signal applied to time write data sampling in the two RSO DRAM dies), the control component issues the same write command (neither is a low latency write command) to both DRAM dies (although with optional time staggering and arbitrarily different address values ​​as described above) so that the select-enabled DRAM dies enforce the replication delay as described above.

[0031] The various systems, integrated circuit components, circuit architectures, circuit operations, calibration operations, etc. disclosed herein may be described using computer-aided design tools and expressed (or represented) as data and / or instructions embodied in various computer-readable media in terms of their behavior, register routing, logic components, transistors, layout geometry, and / or other characteristics. The formats of files and other objects in which such circuit, layout, and architecture expressions may be implemented include, but are not limited to, formats that support behavioral languages ​​such as C, Verilog, and VHDL, formats that support register-level description languages ​​such as RTL, and formats that support geometric description languages ​​such as GDSII, GDSIII, GDSIV, CIF, MEBES, and any other suitable formats and languages. The computer-readable media in which such formatted data and / or instructions may be embodied include, but are not limited to, various forms of computer storage media (e.g., optical, magnetic, or semiconductor storage media, whether distributed independently in this manner or stored "in situ" in an operating system).

[0032] When received within a computer system via one or more computer-readable media, such data and / or instruction-based representations of the above-described circuits and device architectures can be processed by a processing entity (e.g., one or more processors) within the computer system in conjunction with the execution of one or more other computer programs, including but not limited to netlist generation programs, placement and routing programs, etc., to generate representations or images of the physical manifestations of such circuits and architectures. Thereafter, such representations or images can be used for device fabrication, for example, by generating one or more masks that are used to form various components of the circuit during device fabrication.

[0033] In the foregoing description and accompanying drawings, specific terms and figure symbols have been set forth to provide a thorough understanding of the disclosed embodiments. In some cases, terms and symbols may imply details that are not necessary to practice these embodiments. For example, any specific number / type of signal polarity, bit depth, interface width, number of memory channels, number of dies per package, etc. may be different from those in the above-described alternative embodiments. Signal paths depicted or described as individual signal lines may instead be implemented by a multi-conductor signal bus, or vice versa, and each transmitted signal may include multiple conductors (e.g., differential or pseudo-differential signals). The term "coupled" is used herein to represent direct connections as well as connections through one or more intermediate functional components or structures. Programming of operating parameters (e.g., enabling strobe sharing, strobe and auxiliary die, etc.) or any other configurable parameters may be accomplished, for example, but not limited to, by loading control values ​​into configuration registers, mode registers, or other storage circuits within the integrated circuit device described above in response to host instructions and / or an onboard processor or controller (and thereby controlling operational aspects of the device and / or establishing a device configuration), or by a one-time programming operation (e.g., blowing fuses within a configuration circuit during device production), and / or connecting one or more selected pins or other contact structures of the device to reference voltage lines within the package (e.g., on a substrate or external to the integrated circuit package, such as IC contacts coupled to printed circuit board traces, also known as strapping) to establish a particular device configuration or operational aspect of the device. The terms "exemplary" and "embodiment" are used to indicate examples, not preferences or requirements. In addition, the terms "may" and "might" are used interchangeably to indicate optional (permitted) subject matter. The absence of any one term should not be construed as requiring a given feature or technique.

[0034] Various modifications and variations may be made to the embodiments presented herein without departing from the broader spirit and scope of the present disclosure. For example, the features or aspects of any embodiment may be applied in combination with any other embodiment, or in place of the corresponding features or aspects thereof. Therefore, the description and drawings should be regarded as illustrative rather than restrictive.

Claims

1. An integrated circuit memory component, comprising: A first data interface and a second data interface; a first command / address interface and a second command / address interface for receiving respective first and second memory access commands, the first memory access command indicating that a first write data burst is to be received via the first data interface and the second memory access command indicating that a second write data burst is to be received via the second data interface; A shared data strobe interface, configured to receive a first data strobe signal; as well as Control circuit device for: enabling the first write data burst to be sampled within the first data interface at a time indicated by the first data strobe signal, and The second write data burst is enabled to be sampled within the second data interface at a time indicated by the first data strobe signal.

2. An integrated circuit memory component according to claim 1, wherein the first command / address interface and the second command / address interface are used to receive corresponding first memory access commands and second memory access commands at corresponding times offset from each other by a first interval, and wherein the control circuit device for enabling the first write data burst and the second write data burst to be sampled within the first data interface and the second data interface includes a circuit device for enabling the first write data burst and the second write data burst to be sampled within corresponding second intervals and third intervals offset from each other by the first interval.

3. An integrated circuit memory component according to claim 1, wherein the first command / address interface and the second command / address interface and the first data interface and the second data interface are arranged on a first integrated circuit die forming at least a portion of the integrated circuit memory component.

4. An integrated circuit memory component according to claim 1, wherein the control circuit device for enabling the first write data burst to be sampled at the time indicated by the first data select signal includes a circuit device for (i) generating a first delayed data select signal having a first calibrated phase offset from the first data select signal and (ii) enabling the first write data burst to be sampled in response to a transition of the first delayed data select signal.

5. An integrated circuit memory component according to claim 4, wherein the circuit device for enabling the first write data burst to be sampled in response to the transition of the first delayed data enable signal includes a circuit device for enabling the first write data burst to be sampled twice in succession within each cycle of the first delayed data enable signal.

6. An integrated circuit memory component according to claim 4, wherein the control circuit device for enabling the second write data burst to be sampled at the time indicated by the second data select signal includes a circuit device for (i) generating a second delayed data select signal having a second calibrated phase offset from the first data select signal and (ii) enabling the second write data burst to be sampled in response to a transition of the second delayed data select signal.

7. An integrated circuit memory component according to claim 1, wherein the first data selection signal includes a plurality of active transitions, the plurality of active transitions are preceded by a selection preamble code and followed by a selection post-synchronization code, and the active transitions continue throughout an interval that exceeds the duration of the first write data burst and exceeds the duration of the second write data burst.

8. An integrated circuit memory component according to claim 1, wherein the first data selection signal includes an active transition, the active transition is preceded by a selection preamble code and followed by a selection post-synchronization code, and wherein the first subset of active edges indicates the time when the initial portion of the first write data burst will be sampled, and the second subset of active edges indicates the time when the end portion of the second write data burst will be sampled, the first subset includes at least one active edge not included in the second subset and the second subset includes at least one active edge not included in the first subset.

9. An integrated circuit memory component according to claim 1, wherein the first command / address interface, the first data interface and the shared data select interface are implemented in a first integrated circuit die within the integrated circuit memory component, and the second command / address interface and the second data interface are implemented in a second integrated circuit die within the integrated circuit memory component, and wherein the control circuit device for enabling the second write data burst to be sampled within the second data interface at a time indicated by the first data select signal includes a circuit device for transmitting the first data select signal from the first integrated circuit die to the second integrated circuit die.

10. An integrated circuit memory component according to claim 11, wherein the first command / address interface and the second command / address interface include a circuit device for receiving a corresponding third memory access command and a fourth memory access command, the third memory access command indicating that a first read data burst is to be sent to the memory control component via the first data interface, and the fourth memory access command indicating that a second read data burst is to be sent to the memory control component via the second data interface, and wherein the control circuit device includes a circuit device for sending a second data selection signal via the shared selection signaling interface to indicate the time when the memory control component will sample the first read data burst and the second read data burst.

11. An operation method in an integrated circuit memory component, the integrated circuit memory component having a first command / address interface and a second command / address interface and a first data interface and a second data interface, the method comprising: receiving a first memory access command and a second memory access command via the first command / address interface and the second command / address interface, respectively, the first memory access command indicating that a first write data burst is to be received via the first data interface and the second memory access command indicating that a second write data burst is to be received via the second data interface; Firstly, receiving a first data strobe signal via a shared strobe signaling interface; sampling the first write data burst within the first data interface at a time indicated by the first data strobe signal; as well as The second write data burst is sampled within the second data interface at a time indicated by the first data strobe signal.

12. The method of claim 11 , wherein receiving the first memory access command and the second memory access command via the first command / address interface and the second command / address interface comprises receiving the first memory access command and the second memory access command at respective times offset from each other by a first interval, and wherein sampling the first write data burst and the second write data burst within the first data interface and the second data interface comprises sampling the first write data burst and the second write data burst within respective second and third intervals offset from each other by the first interval.

13. The method of claim 11, wherein first and second command / address interfaces and first and second data interfaces are disposed on a first integrated circuit die forming at least a portion of the integrated circuit memory component.

14. The method of claim 11, wherein sampling the first write data burst at a time indicated by the first data strobe signal comprises: A first delayed data strobe signal is generated having a first calibrated phase offset from the first data strobe signal, and the first write data burst is sampled in response to transitions of the first delayed data strobe signal. 15 . The method of claim 14 , wherein sampling the first write data burst in response to a transition of the first delayed data strobe signal comprises sampling the write data burst twice consecutively within each cycle of the first delayed data strobe signal.

16. The method of claim 14, wherein sampling the second write data burst at a time indicated by the first data strobe signal comprises: A second delayed data strobe signal is generated having a second calibrated phase offset from the first data strobe signal, and the second write data burst is sampled in response to transitions of the second delayed data strobe signal.

17. The method of claim 11, wherein the first data select signal comprises a plurality of active transitions preceded by a select preamble and followed by a select postamble, the active transitions persisting throughout an interval that exceeds a duration of the first write data burst and exceeds a duration of the second write data burst.

18. The method of claim 11, wherein the first data select signal comprises an active transition, the active transition is preceded by a select preamble and followed by a select post-sync, and wherein a first subset of the active edges indicates a time when an initial portion of a first write data burst is to be sampled and a second subset of the active edges indicates a time when an end portion of the second write data burst is to be sampled, the first subset includes at least one active edge not included in the second subset and the second subset includes at least one active edge not included in the first subset.

19. The method of claim 11, wherein the first command / address interface and the first data interface are implemented in a first integrated circuit die within the integrated circuit memory component, and the second command / address interface and the second data interface are implemented in a second integrated circuit die within the integrated circuit memory component, and wherein receiving the first data strobe signal via the shared strobe signaling interface comprises: The first data strobe signal is received via a strobe signaling interface of the first integrated circuit die and transmitted from the first integrated circuit die to the second integrated circuit die to enable sampling of the second write data burst to be sampled within the second data interface at a time indicated by the first strobe signal.

20. The method according to claim 11, further comprising: receiving a third memory access command and a fourth memory access command via the first command / address interface and the second command / address interface, respectively, the third memory access command indicating that a first read data burst is to be sent to a memory control component via the first data interface, and the fourth memory access command indicating that a second read data burst is to be sent to the memory control component via the second data interface; as well as A second data strobe signal is sent via the shared strobe signaling interface to indicate when the memory control unit is to sample the first and second read data bursts.

21. An integrated circuit memory component comprising: A first data interface and a second data interface; a first command / address interface and a second command / address interface for receiving respective first and second memory access commands, the first memory access command indicating that a first write data burst is to be received via the first data interface and the second memory access command indicating that a second write data burst is to be received via the second data interface; A shared data strobe interface, configured to receive a first data strobe signal; as well as Means for enabling the first write data burst to be sampled within the first data interface at a time indicated by the first data strobe signal and for enabling the second write data burst to be sampled within the second data interface at a time indicated by the first data strobe signal.

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