Data Detection on a Serial Communication Link

Abstract

The serial data receiver subsystem included in a computer system may include data detection circuitry, speed detection circuitry, and receiver circuitry including a plurality of sub-circuits. The data detection circuitry performs a comparison of a reference voltage with an amplitude of a signal that encodes a serial data stream composed of a plurality of data symbols received via a communication link. Using the result of the comparison, the data detection circuitry may activate a signal presence indicator indicative of the presence of data on the communication link. Once the signal presence indicator is valid, the speed detection circuitry checks the number of transitions to determine the rate at which data is being transmitted. In response to determining that the rate of the data being transmitted exceeds a threshold, the receiver circuitry activates one or more of the plurality of sub-circuits.

Description

Technical Field

[0001] This disclosure relates to the field of high-speed communication interface design, and more particularly to detecting the presence of data on a serial communication link. Background Art

[0002] Computing systems typically include multiple interconnected integrated circuits. In some cases, the integrated circuits may communicate by sending and receiving data bits using a communication channel or link. The communication channel may support parallel communication that sends multiple data bits in parallel, or serial communication that sends data bits one at a time in series.

[0003] Data sent between integrated circuits may be encoded to assist in the transmission. For example, in the case of serial communication, the data may be encoded to provide transitions between logical states that are sufficient to allow clock and data recovery circuitry to operate. Alternatively, in the case of parallel communication, the data may be encoded to reduce switching noise or improve signal integrity.

[0004] During data transmission, the physical characteristics of the communication channel may attenuate the transmitted signal associated with a particular data bit. For example, the impedance of the wiring included in the communication channel or link may attenuate certain frequency ranges of the transmitted signal. Additionally, an impedance mismatch between the wiring included in the communication channel and the devices coupled to the communication channel may cause reflections of the transmitted signal, which may degrade subsequent transmitted signals corresponding to other data bits. Brief Description of the Drawings

[0005] Figure 1 is a block diagram of an embodiment of a receiver circuit for a serial communication link in a computer system.

[0006] Figure 2 is a block diagram of an embodiment of a data detection circuit.

[0007] Figure 3 is a block diagram of an embodiment of a speed detection circuit.

[0008] Figure 4 is a block diagram of an embodiment of a receiver circuit.

[0009] Figure 5 is a block diagram of a computer system including a transmitter circuit and a receiver circuit.

[0010] Figure 6 is a diagram depicting sampling a signal used in a serial communication link to determine transitions.

[0011] Figure 7 is a flowchart of an embodiment of a method for detecting data on a serial link.

[0012] Figure 8It is a block diagram of one embodiment of a system-on-chip including a detector circuit.

[0013] Figure 9 It is a block diagram of various embodiments of a computer system that may include a receiver circuit.

[0014] Figure 10 Illustrates an example of a non-transitory computer-readable storage medium storing circuit design information.

[0015] Although the embodiments described in this disclosure may be subject to various modified forms and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will be described in detail herein. However, it should be understood that the drawings and the specific implementation thereof are not intended to limit the embodiments to the particular forms disclosed, but on the contrary, the present invention is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the appended claims. Detailed Description

[0016] A computing system may include one or more integrated circuits, such as, for example, a central processing unit (CPU) and a memory. Various integrated circuits of the computing system may communicate via a serial or parallel interface. In a parallel interface, multiple data bits are transmitted simultaneously, while in a serial interface, data is transmitted as a series of sequential single data bits. When a serial interface is employed to transmit data between two devices included in a computing system, the data may be sent according to different protocols. For example, the return-to-zero (RZ) protocol, non-return-to-zero (NRZ) protocol, pulse amplitude modulation (PAM), or any suitable combination thereof may be used to send data.

[0017] Serial data streams are often transmitted without an accompanying clock signal. In such cases, the clock signal is recovered from the serial data stream (in a process known as "clock recovery") and is used to sample the serial data stream to determine the values of the included data symbols. Various techniques may be employed to recover the clock signal. For example, a receiver circuit may generate a clock signal having a frequency approximately the same as the frequency of the clock signal used to create the data stream. A phase-locked loop circuit may then be used to align the phase of the clock signal with transitions in the serial data stream. Alternatively, the serial data stream may be oversampled, i.e., sampled at a frequency higher than the frequency of the clock signal used to generate the serial data stream.

[0018] In some computer systems, a communication link may operate in different modes. For example, in addition to a high-speed data mode, some communication links also have an idle mode, a low-speed periodic signaling mode. Depending on the operation of the computer system, the communication link may switch between different modes. For example, in response to the activation of a sleep or power-down mode of the computer system, the communication link may be placed in an idle mode during which no data is transmitted.

[0019] A receiver circuit coupled to a communication link must monitor the communication to determine the state of the communication link. Different circuits within the receiver circuit can be used for different modes of the communication link. The circuits for a particular mode can be disabled when that mode is not in use and must be re-enabled when that particular mode is detected on the communication link. Failure to detect a change in the communication link mode can result in loss of the transmitted data. For example, the circuits within a receiver circuit suitable for use with a low-speed mode are not sufficient to correctly sample and recover data transmitted in a high-speed mode.

[0020] The embodiments illustrated in the figures and described below provide techniques for monitoring the mode of a communication link. Such monitoring includes detecting the data transmitted on the communication link and determining whether the data being transmitted is high-speed data. By detecting the presence of high-speed data on a serial link, portions of the receiver circuit can be powered up to prevent loss of data, which would require retransmission and thus result in an increased latency for recovering communication on the serial communication link.

[0021] Figure 1 A block diagram depicting an embodiment of a receiver subsystem is illustrated. As shown, the receiver subsystem 100 includes a signal detection circuit 101, a speed detection circuit 102, and a data receiver circuit 103.

[0022] The signal detection circuit 101 is configured to perform a comparison of the amplitude of a signal 105 with a reference voltage 107. In various embodiments, the signal 105 is transmitted via a communication link 111 and encodes a serial data stream including data symbols 112. The signal detection circuit 101 is also configured to use the result of the comparison to activate a signal presence indicator 108. As described below, the signal detection circuit 101 can be configured to use a reference adjustment signal 115 to adjust the value of the reference voltage 107.

[0023] The speed detection circuit 102 is configured to generate a speed signal 109 based on the number of transitions of the signal 105 within a reference time period 113 in response to the activation of the signal presence indicator 108. In some embodiments, the speed detection circuit 102 can employ samples 116 generated by the data receiver circuit 103 to determine the number of transitions of the signal 105. As described below, the duration of the reference time period 113 can be adjusted based on the communication link 111 and the electrical characteristics of the receiver subsystem 100. In various embodiments, the activation of the speed signal 109 can correspond to detecting that the data rate of the data symbol 106 exceeds a threshold. In various embodiments, the speed detection circuit 102 is also configured to generate a reference adjustment signal 115 based on the amplitude of the signal 105.

[0024] As used herein, when a signal is activated, it is set to a logic or voltage level that activates a load circuit or device. Depending on the load circuit, the logic level can be a high logic level or a low logic level. For example, the valid state of a signal coupled to a p-channel metal oxide semiconductor field effect transistor (MOSFET), a fin field effect transistor (FinFET), or a gate-all-around field effect transistor (GAAFET) is a low logic level (referred to as a "low-state active signal"), while the valid state of a signal coupled to an n-channel MOSFET, FinFET, or GAAFET is a high logic level (referred to as a "high-state active signal").

[0025] The data receiver circuit 103 includes subcircuits 114 and is configured to activate one or more of the subcircuits 114 in response to activation of the speed signal 109. As described below, the subcircuits 114 may include filter circuits, equalization circuits, data and clock recovery circuits, etc. In addition, the data receiver circuit 103 is configured to sample the signal 105 to generate samples 116. In various embodiments, the data receiver circuit 103 is further configured to process the samples 116 to generate recovered data symbols 110. It is noted that in some embodiments, the data receiver circuit 103 may be configured to adjust the sampling threshold based on the reference adjustment signal 115.

[0026] Go to Figure 2 , depicts a block diagram of an embodiment of the signal detection circuit 101. As shown, the signal detection circuit 101 includes a reference generator circuit 201 and a comparator circuit 202.

[0027] The reference generator circuit 201 is configured to generate a reference voltage 107. In various embodiments, the reference generator circuit 201 may be further configured to adapt or change the value of the reference voltage 107 using the reference adjustment signal 115. In some cases, the reference generator circuit 201 may be configured to increase the value of the reference voltage 107 in response to determining that the magnitude of the signal 105 has exceeded the initial value of the reference voltage 107. In some embodiments, the reference generator circuit 201 may also be configured to reset the value of the reference voltage 107 to the initial value in response to determining that the communication link or bus through which the signal 105 propagated has entered an idle or dormant state. Note that in some embodiments, the initial value of the reference voltage 107 and the adapted value of the reference voltage 107 may be programmable.

[0028] Reference generator circuit 201 may be implemented using a bandgap reference circuit, a voltage scaling circuit, or any other circuit suitable for generating a reference voltage value. In some cases, reference generator circuit 201 may be configured to generate reference voltage 107 to be independent of temperature and / or supply voltage levels.

[0029] Comparator circuit 202 is configured to generate a signal presence indicator 108 using signal 105 and reference voltage 107. In various embodiments, comparator circuit 202 may be configured to compare the voltage level of signal 105 with reference voltage 107 and use the result of the comparison to generate signal presence indicator 108. Note that although comparator circuit 202 is depicted as comparing two signals, in other embodiments, additional comparators may be employed in cases where multiple signals are used to transmit data symbol 106 to receiver subsystem 100.

[0030] In various embodiments, comparator circuit 202 may be implemented using a differential amplifier circuit or any other circuit suitable for comparing the respective voltage levels of two or more signals. In cases where signal presence indicator 108 is a digital signal, comparator circuit 202 may be implemented using a Schmitt trigger circuit or other suitable circuit.

[0031] Figure 3 A block diagram of speed detection circuit 102 is depicted. As shown, speed detection circuit 102 includes logic circuit 301 and filter circuit 302.

[0032] Logic circuit 301 is configured to generate speed signal 109 and reference adjustment signal 115 using sample 116. In various embodiments, to generate speed signal 109, logic circuit 301 is configured to determine the number of samples detected in sample 116 during sample window 306 in response to the activation of enable signal 305. In various embodiments, the width of sample window 306 may correspond to reference time period 113. Logic circuit 301 is further configured to activate speed signal 109 in response to determining that the number of samples in sample 116 during sample window 306 is greater than a threshold. In response to the deactivation of enable signal 305, logic circuit 301 is further configured to hold speed signal 109 in a deactivated or inactive state.

[0033] In various embodiments, logic circuit 301 may be configured to change the value of reference adjustment signal 115 based on one or more values of sampled signal 304. In some cases, in response to detecting an increase in the number of samples 116 measured within consecutive sample windows in sample window 306, logic circuit 301 may be configured to increase the value of reference adjustment signal 115. In various embodiments, reference adjustment signal 115 may be a digital signal including multiple bits encoding information indicative of an expected value of reference voltage 107. Alternatively, reference adjustment signal 115 may be an analog signal used by reference generator circuit 201 to adjust the value of reference voltage 107.

[0034] The logic circuit 301 can be implemented using a microcontroller, a state machine, or any other suitable combination of sequential and combinational logic circuits. In some embodiments, the logic circuit 301 can be configured to receive information indicating the operating characteristics of a computer system including the receiver subsystem circuit 100 and adjust the duration of the sample window 306 based on the received information. In various embodiments, such information can include temperature, the noise level on the communication link 111, the power supply voltage level, and the like. Alternatively, the logic circuit 301 can include one or more register circuits that can be programmed with different values of the sample window 306.

[0035] When the amplitude of the signal 105 approaches the reference voltage 107, the output of the comparator circuit 202 can switch between a high logic level and a low logic level due to the tolerances of the circuit elements in the comparator circuit 202 and the variation of the reference voltage 107 due to power supply noise and the like. Thus, there can be a range of voltage levels of the signal 105 during which the value of the signal presence indicator 108 may be changing. To remedy this problem, a filter is employed.

[0036] The filter circuit 302 is configured to generate an enable signal 305 using the signal presence indicator 108. In various embodiments, the filter circuit 302 can be configured to perform a digital filter operation on the signal presence indicator 108 to generate the enable signal 305. The digital filter operation can include performing multiple averaging operations. In some embodiments, the filter circuit 302 can be programmable to account for changes in the operating characteristics of a computer system including the receiver subsystem 100. In various embodiments, the filter circuit 302 can be implemented using a state machine or any other suitable combination of sequential and combinational logic circuits.

[0037] Turning to Figure 4 , a block diagram of the data receiver circuit 103 is depicted. As shown, the data receiver circuit 103 includes a front-end circuit 401, a sampling circuit 402, a recovery circuit 403, and an equalization circuit 404. In various embodiments, one or more of the front-end circuit 401, the sampling circuit 402, the recovery circuit 403, and the equalization circuit 404 can be included in the sub-circuit 114.

[0038] The front-end circuit 401 is configured to generate an equalization signal 405 using the signal 105. In various embodiments, the front-end circuit 401 can be implemented using a filter circuit and an automatic gain control circuit. In some embodiments, the front-end circuit 401 can employ continuous-time linear equalization techniques, while in other embodiments, the front-end circuit 401 can employ any suitable equalization technique.

[0039] The sampling circuit 402 is configured to generate a sample 116 using a combination of the equalization signal 405 and the adjustment signal 407, as well as the edge clock 410 and the data clock 411. In various embodiments, the sampling circuit 402 may employ a plurality of limiting circuits configured to compare the combination of the equalization signal 405 and the adjustment signal 407 with corresponding thresholds to generate the sample 116. In some cases, the sampling circuit 402 is further configured to adjust the thresholds based on a reference adjustment signal 115. In some embodiments, the reference adjustment signal 115 may actuated one or more analog switches to select different thresholds from a plurality of thresholds. Alternatively, the reference adjustment signal 115 may adjust a bias voltage and / or current within a reference generator circuit to change the thresholds.

[0040] In other embodiments, the sampling circuit 402 may include one or more analog-to-digital converter circuits configured to generate a plurality of bits whose values encode the magnitude of the combination of the equalization signal 405 and the adjustment signal 407 at a particular point in time. In various embodiments, the time at which the analog-to-digital converter circuit output is captured may be controlled by the edge clock 410 and the data clock 411.

[0041] In various embodiments, the edge clock 411 and the data clock 411 are synchronized to a transition of a signal 105 corresponding to a change in the data symbol 112. The sampling circuit 402 is configured to sample the combination of the equalization signal 405 and the adjustment signal 407 near the transition using the rising and falling edges of the edge clock 410. In a similar manner, the sampling circuit 402 is configured to sample the combination of the equalization signal 405 and the adjustment signal 407 between the transitions using the data clock 411.

[0042] The recovery circuit 403 is configured to generate recovered data 408, a recovered clock 409, the edge clock 410, and the data clock 411 using the sample 116. In various embodiments, the recovery circuit 403 may perform various operations (e.g., feedforward equalization) to generate the recovered data 408. In some cases, the recovery circuit 403 may operate on a plurality of symbols in parallel. In such cases, the recovery circuit 403 may wait until a particular number of samples have been received from the received samples 406 before performing some of the clock and data recovery operations among the various clock and data recovery operations. In some embodiments, the recovery circuit 403 may include a phase-locked loop circuit, a delay-locked loop circuit, or any other suitable circuit to generate the edge clock 410 such that the edge clock is aligned with a transition of the combination of the equalization signal 405 and the adjustment signal 407. The recovery circuit 403 may employ a similar circuit to generate the data clock 411 having a known phase difference (e.g., 90 degrees) relative to the edge clock 410.

[0043] The equalization circuit 404 is configured to generate an adjustment signal 407 using the recovered data 408 and the recovered clock 409. In various embodiments, the equalization circuit 404 may be implemented using a decision feedback equalization (DFE) circuit that is configured to scale an analog voltage level using a plurality of symbols included in the recovered data 408 to generate the adjustment signal 407 in order to eliminate inter-symbol interference (ISI) that occurs when the signal 105 is transmitted over the communication link 111.

[0044] As described above, a detector circuit such as the receiving subsystem 100 may be used in a computer system having a communication link. Figure 5 A block diagram of an embodiment of such a computer system is depicted. As shown, the computer system 500 includes devices 501 and 502 coupled by a communication bus 507.

[0045] The device 501 includes a circuit block 503 and a transmitter circuit 504. In various embodiments, the device 501 may be a processor circuit, a processor core, a memory circuit, or any other suitable circuit block that may be included on an integrated circuit in a computer system. Note that although the device 501 depicts only a single circuit block and a single transmitter circuit, in other embodiments, additional circuit blocks and additional transmitter circuits may be employed.

[0046] The transmitter circuit 504 is configured to serially transmit a signal corresponding to data received from the circuit block 503 via the communication bus 507. Such a signal may differentially encode one or more bits such that at a particular point in time, the difference between the respective voltage levels of lines 508A and 508B corresponds to a particular bit value. In some cases, the generation of the signal may include encoding the bits prior to transmission. Note that although the communication bus 507 is depicted as including two lines, any suitable number of lines may be employed in other embodiments. In some cases, the transmitter circuit 504 may be further configured to generate a transmission signal in accordance with one of various communication protocols such as the USB protocol.

[0047] The device 502 includes a signal detection circuit 101, a receiver circuit 505, and a circuit block 506. Similar to the device 501, the device 502 may be a processor circuit, a processor core, a memory circuit, or any other suitable circuit block configured to receive data from the transmitter circuit 504. In various embodiments, the receiver circuit 505 may be configured to place certain sub-circuits within the receiver circuit 505 in a sleep or power-down state when the communication bus 507 is idle. As described above, the signal detection circuit 101 is configured to generate an enable signal when data transmission resumes on the communication bus 507. The enable signal is used by the receiver circuit 505 to reactivate any circuit blocks that have previously been placed in a sleep or power-down state.

[0048] In some embodiments, devices 501 and 502 may be fabricated on a common integrated circuit. In other embodiments, devices 501 and 502 may be located on different integrated circuits mounted on a common substrate or circuit board. In such cases, communication bus 507 may include metal or other conductive traces on the substrate or circuit board. Although only two devices are depicted in computer system 500, any suitable number of devices may be employed in other embodiments.

[0049] Turning to Figure 6 , an example waveform depicting sampling of signals used in a serial communication link to determine transitions is illustrated. Note that the waveform is an example and in other embodiments, the relative timing of the waveform may be different. In various embodiments, edge clock 307 may be 90 degrees out of phase with data clock 308.

[0050] As described above, once signal detection circuit 101 determines the presence of data on communication link 111, edge clock 307 and data clock 308 may be aligned using transitions of signal 105. Edge clock 307 and data clock 308 may be aligned using a clock recovery circuit or any other suitable method for aligning the clock with transitions of signal 105.

[0051] At time t1, the rising edge of edge clock 307 is used to sample signal 105. At time t2, the falling edge of edge clock 307 is used to sample signal 105. In various embodiments, the sample from time t1 is compared with the sample from t3. In response to determining that the two samples have different values, sampling circuit 301 is configured to detect a transition in signal 105 that occurs between times t1 and t3.

[0052] At time t2, the falling edge of data clock 308 is used to sample signal 105, and at time t4, the rising edge of data clock 308 is used to sample signal 105. In various embodiments, sampling circuit 301 is configured to compare the sample taken at time t2 with the sample taken at time t4. Since data clock 308 should be sampling signal 105 during a valid data period, the two samples may be used to determine whether a transition has occurred. In some cases, such information may be relayed to a clock recovery circuit to adjust the timing of data clock 308.

[0053] In some embodiments, the sampling circuit 301 may be configured to compare a sample taken at time t2 with a sample taken at time t3. If the two samples do not have the same value, the sampling circuit 301 is configured to indicate a transition. By using both the rising and falling edges of the edge clock 307 and the data clock 308, the granularity at which the sampling circuit 301 samples the signal 105 can be very fine. In the case where a transition is detected at an unexpected location (e.g., between time t3 and t4), the timing of the edge clock 307 and the data clock 308 can be adjusted. In a similar manner, if a transition is not detected at an expected location (e.g., between time t1 and t2), the timing of the edge clock 307 and the data clock 308 can be further adjusted.

[0054] Note that the comparison of the above samples is merely an example. In other embodiments, the samples taken at the rising and falling edges of the edge clock 307 and the data clock 308 can be compared according to any suitable algorithm.

[0055] In summary, various embodiments of a serial data receiver circuit including a detector circuit are disclosed. Generally, a device is envisioned in which a signal detection circuit is configured to perform a first comparison of the amplitude of at least one signal with a reference voltage. In various embodiments, the at least one signal encodes a serial data stream including a plurality of data symbols. The signal detection circuit is further configured to use the result of the comparison to activate a signal presence indicator. A speed detection circuit is configured to generate an enable signal based on the number of transitions of the serial data stream within a reference time period in response to the activation of the signal presence indicator. The receiver circuit includes a plurality of sub-circuits and is configured to activate one or more of the plurality of sub-circuits in response to the activation of the enable signal.

[0056] In other embodiments, to generate the enable signal, the speed detection circuit is further configured to sample the at least one signal to generate a plurality of samples and use the plurality of samples to determine the number of transitions of the serial data stream within a reference time period. The speed detection circuit may be further configured to perform a second comparison of the number of transitions with a threshold and use the result of the second comparison to activate the enable signal.

[0057] In some embodiments, the speed detection circuit is further configured to filter a data valid signal to generate a filtered valid signal and sample the at least one signal to generate the plurality of samples in response to determining that the filtered valid signal has a particular value. In different embodiments, the speed detection circuit is further configured to adjust the value of the reference time period using one or more operating characteristics of a computer system including the receiver circuit.

[0058] In various embodiments, to sample the at least one signal, the speed detection circuit is further configured to sample the at least one signal using a first edge of a clock signal to generate a first sample, and to sample the at least one signal using a second edge of the clock signal to generate a second sample. In this case, to perform a second comparison, the speed detection circuit is further configured to compare the first sample with the second sample. In other embodiments, the data detection circuit is further configured to set the reference voltage to an initial value and to modify the value of the reference voltage in response to determining that the amplitude of the at least one signal exceeds the initial value of the reference voltage.

[0059] Go to Figure 7 , a flowchart illustrating an embodiment of a method for detecting data on a communication link is shown. The method, which can be applied to various receiver subsystems such as the receiver subsystem 100 depicted in Figure 1 , begins at block 701.

[0060] The method includes: receiving, by a detector circuit via a communication link, one or more signals encoding a serial data stream including a plurality of data symbols (block 702). In various embodiments, the serial data stream can be encoded as one of various communication protocols, such as the USB protocol.

[0061] The method further includes: performing, by the detector circuit, a first comparison of the amplitude of at least one of the plurality of signals with a reference voltage (block 703). In various embodiments, the method can further include: setting the reference voltage to an initial value and modifying the value of the reference voltage in response to determining that the amplitude of the at least one signal exceeds the initial value of the reference voltage.

[0062] The method further includes: generating, by the detector circuit, a signal presence indicator using the result of the first comparison (block 704). In some embodiments, generating can include: generating a digital value based on the result of the first comparison.

[0063] The method further includes: sampling, by the detector circuit, the at least one signal to generate a plurality of samples in response to activating the signal presence indicator (block 705). In some embodiments, the method can further include: filtering, by the detector circuit, a data valid signal to generate a filtered valid signal, and sampling, by the detector circuit, the at least one signal to generate the plurality of samples in response to determining that the filtered valid signal has a particular value. In various embodiments, the method can further include: sampling the at least one signal using one or more thresholds and adjusting the one or more thresholds in response to determining that the amplitude of the at least one signal exceeds the initial value of the reference voltage.

[0064] In other embodiments, sampling the at least one signal includes: sampling the at least one signal using a first edge of a clock signal to generate a first sample, and sampling the at least one signal using a second edge of the clock signal to generate a second sample. The method may further include: determining the number of transitions includes comparing the first sample with the second sample. Note that while the method describes the use of a single clock signal, in other embodiments, different clock signals (e.g., an edge clock signal and a data clock signal) may be used to sample the at least one signal, and different samples from the different clock signals may be compared to determine the number of transitions.

[0065] The method further includes: the detector circuit using the plurality of samples to determine the number of transitions of the serial data stream during a reference period (block 706). In some embodiments, the method may further include: using one or more operating characteristics of a computer system including the detector circuit to determine the value of the reference period. In different embodiments, the one or more operating characteristics may include the noise level of the communication link, the temperature of the computer system, the voltage level of a power supply node coupled to the detector circuit, or any other suitable operating characteristic of the computer system.

[0066] The method further includes: activating one or more sub-circuits among a plurality of sub-circuits included in a receiver circuit coupled to the communication link based on the number of transitions (block 707). In various embodiments, activating the one or more sub-circuits may include: performing a second comparison of the number of transitions with a threshold, and using the result of the second comparison to generate an enable signal. The method may further include: activating the one or more sub-circuits in response to activating the enable signal.

[0067] In other embodiments, the method may include: in response to activating the one or more sub-circuits, the receiver circuit recovering one or more data symbols from the one or more signals. The method ends at block 708.

[0068] In Figure 8 A block diagram of a system-on-chip (SoC) is illustrated. In the illustrated embodiment, SoC 800 includes a processor circuit 801, a memory circuit 802, an analog / hybrid signal circuit 803, and an input / output circuit 804, each of which is coupled to a communication bus 805. In various embodiments, SoC 800 may be configured for use in a desktop computer, a server, or in a mobile computing application (such as, for example, a tablet computer, a laptop computer, or a wearable computing device).

[0069] In various embodiments, the processor circuit 801 may represent a general-purpose processor that performs computational operations. For example, the processor circuit 801 may be a central processing unit (CPU) such as a microprocessor, a microcontroller, an application-specific integrated circuit (ASIC), or a field-programmable gate array (FPGA).

[0070] In various embodiments, the memory circuit 802 may include any suitable type of memory, such as, for example, dynamic random access memory (DRAM), static random access memory (SRAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or non-volatile memory. Note that while a single memory circuit is illustrated in Figure 8 , any suitable number of memory circuits may be employed in other embodiments.

[0071] The analog / hybrid signal circuit 803 may include a crystal oscillator circuit, a phase-locked loop (PLL) circuit, an analog-to-digital converter (ADC) circuit, and a digital-to-analog converter (DAC) circuit (all not shown). In other embodiments, the analog / hybrid signal circuit 803 may be configured to perform power management tasks by including on-chip power supplies and voltage regulators.

[0072] The input / output circuit 804 may be configured to coordinate data transfer between the SoC 800 and one or more peripheral devices. Such peripheral devices may include, but are not limited to, storage devices (e.g., storage devices based on magnetic or optical media, including hard disk drives, tape drives, CD drives, DVD drives, etc.), audio processing subsystems, or any other suitable type of peripheral device. In some embodiments, the input / output circuit 804 may be configured to implement the Universal Serial Bus (USB) protocol or a version of the IEEE 1394 protocol and include the receiver subsystem 100 as depicted in the Figure 1 embodiment.

[0073] The input / output circuit 804 may also be configured to coordinate data transfer between the SoC 800 and one or more devices (e.g., other computing systems or integrated circuits) coupled to the SoC 800 via a network. In one embodiment, the input / output circuit 804 may be configured to perform the data processing necessary to implement an Ethernet (IEEE 802.3) networking standard such as, for example, Gigabit Ethernet or 10 Gigabit Ethernet, although any suitable networking standard is contemplated. In some embodiments, the input / output circuit 804 may be configured to implement multiple discrete network interface ports.

[0074] Now turning to Figure 9, which illustrates various types of systems that may include any of the circuits, devices, or systems described above. A system or device 900 that can incorporate or otherwise utilize one or more of the techniques described herein can be used in a wide range of fields. For example, system or device 900 can be used as part of the hardware of a system such as a desktop computer 910, a laptop computer 920, a tablet computer 930, a cellular or mobile phone 940, or a television 950 (or a set-top box coupled to a television).

[0075] Similarly, the disclosed elements can be used in wearable devices 960, such as smartwatches or health monitoring devices. In many embodiments, a smartwatch can implement a variety of different functions—for example, access to email, cellular services, calendars, health monitoring, etc. Wearable devices can also be designed to perform only health monitoring functions, such as monitoring a user's vital signs, performing epidemiological functions such as contact tracing, providing communication to emergency medical services, etc. Other types of devices are also contemplated, including devices worn around the neck, devices implantable in the human body, glasses or helmets designed to provide computer-generated reality experiences, such as those based on augmented reality and / or virtual reality, etc.

[0076] System or device 900 can also be used in a variety of other contexts. For example, system or device 900 can be used in the context of a server computer system (such as a dedicated server) or on shared hardware that implements cloud-based services 970. Further still, system or device 900 can be implemented in a wide range of dedicated everyday devices, including devices 980 common in the home, such as refrigerators, thermostats, security cameras, etc. The interconnection of such devices is commonly referred to as the "Internet of Things" (IoT). The elements can also be implemented in a variety of modes of transportation. For example, system or device 900 can be used in control systems, guidance systems, entertainment systems, etc. of various types of vehicles 990.

[0077] Figure 9 The applications shown in are merely exemplary and are not intended to limit the potential future applications of the disclosed system or device. Other example applications include, but are not limited to: portable gaming devices, music players, data storage devices, unmanned aerial vehicles, etc.

[0078] Figure 10 is a block diagram showing an example of a non-transitory computer-readable storage medium storing circuit design information according to some embodiments. In the illustrated embodiment, a semiconductor manufacturing system 1020 is configured to process design information 1015 stored on a non-transitory computer-readable storage medium 1010 and manufacture an integrated circuit 1030 based on the design information 1015.

[0079] The non-transitory computer-readable storage medium 1010 may include any one of various suitable types of memory devices or storage devices. The non-transitory computer-readable storage medium 1010 may be an installation medium, such as, for example, a CD-ROM, a floppy disk, or a magnetic tape device; a computer system memory or random access memory, such as DRAM, DDR RAM, SRAM, EDO RAM, Rambus RAM, etc.; a non-volatile memory, such as flash memory, a magnetic medium, such as a hard disk drive or an optical storage device; registers, or other similar types of memory elements, etc. The non-transitory computer-readable storage medium 1010 may also include other types of non-transitory memory or combinations thereof. The non-transitory computer-readable storage medium 1010 may include two or more memory media that may reside in different locations (e.g., in different computer systems connected by a network).

[0080] The design information 1015 may be specified using any of a variety of suitable computer languages, including hardware description languages such as, but not limited to: VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, MyHDL, etc. The design information 1015 may be capable of being used by the semiconductor manufacturing system 1020 to fabricate at least a portion of the integrated circuit 1030. The format of the design information 1015 may be recognized by at least one semiconductor manufacturing system, such as, for example, the semiconductor manufacturing system 1020. In some embodiments, the design information 1415 may include a netlist that specifies elements of a cell library and their connectivity. One or more cell libraries used during the logic synthesis of the circuits included in the integrated circuit 1030 may also be included in the design information 1015. Such cell libraries may include information indicative of device or transistor-level netlists, mask design data, characterization data, etc. of the cells included in the cell library.

[0081] In various embodiments, the integrated circuit 1030 may include one or more custom macro cells, such as memories, analog or mixed-signal circuits, etc. In such a case, the design information 1015 may include information related to the included macro cells. Such information may include, but is not limited to, a schematic capture database, mask design data, behavioral models, and device or transistor-level netlists. As used herein, the mask design data may be formatted according to the Graphic Data System (GDSII) or any other suitable format.

[0082] The semiconductor manufacturing system 1020 may include any of a variety of suitable elements configured to manufacture integrated circuits. This may include, for example, elements for depositing semiconductor materials (e.g., on a wafer that may include a mask), removing materials, shaping the deposited materials, modifying the materials (e.g., by doping materials or using ultraviolet treatment to modify the dielectric constant), etc. The semiconductor manufacturing system 1020 may also be configured to perform various tests on the manufactured circuits for proper operation.

[0083] In various embodiments, the integrated circuit 1030 is configured to operate according to a circuit design specified by the design information 1015, which may include performing any of the functions described herein. For example, the integrated circuit 1030 may include any of the various elements shown or described herein. Additionally, the integrated circuit 1030 may be configured to perform various functions described herein in connection with other components. Additionally, the functionality described herein may be performed by multiple connected integrated circuits.

[0084] As used herein, a phrase of the form "design information specifying a design of a circuit configured to..." does not imply that the circuit in question must be manufactured in order to meet the element. Instead, the phrase indicates that the design information describes a circuit that, when manufactured, will be configured to perform the indicated actions or will include the specified components.

[0085] ***

[0086] This disclosure includes references to "embodiments," which are non-limiting specific implementations of the disclosed concepts. References to "an embodiment," "one embodiment," "a particular embodiment," "some embodiments," "various embodiments," etc. do not necessarily refer to the same embodiment. A large number of possible embodiments are envisioned, including the specific embodiments detailed, as well as modified or alternative forms that fall within the substance or scope of this disclosure. Not all of these embodiments will necessarily exhibit any or all of the potential advantages described herein.

[0087] Unless otherwise indicated, a specific embodiment is not intended to limit the scope of the claims drafted based on the disclosed subject matter, even if only a single example of a particular feature is described. Thus, the disclosed embodiments are intended to be illustrative rather than restrictive, without any contrary statement. This patent application is intended to cover such alternative forms, modifications, and equivalent forms, which will be apparent to those skilled in the art who benefit from this disclosure.

[0088] Specific features, structures, or characteristics may be combined in any suitable manner consistent with this disclosure. Accordingly, this disclosure is intended to cover any feature or combination of these features (explicitly or implicitly) disclosed herein, or any generalization thereof. Thus, during the prosecution of this application (or an application claiming priority thereto), new claims may be made to any such combination of features. Specifically, with reference to the appended claims, the features of a dependent claim may be combined with the features of an independent claim, and the features from corresponding independent claims may be combined in any appropriate manner other than only by the specific combinations recited in the appended claims.

[0089] For example, while the appended dependent claims are drafted such that each dependent claim depends from a single other claim, additional dependencies are also contemplated. In appropriate cases, it is also contemplated that claims drafted in one statutory type (e.g., apparatus) may inspire corresponding claims in another statutory type (e.g., method).

[0090] ***

[0091] Because this disclosure is a legal document, various terms and phrases are subject to regulatory and judicial interpretation. Notice is hereby given that the following paragraphs, as well as the definitions provided throughout this disclosure, will be used to determine how claims drafted based on this disclosure are to be interpreted.

[0092] References to singular forms such as "a," "an," and "the" are intended to mean "one or more" unless the context clearly dictates otherwise. Thus, a reference to "item" in a claim does not exclude additional instances of that item.

[0093] The word "may" is used herein in an enabling sense (i.e., having the potential to, being able to), rather than in a mandatory sense (i.e., must).

[0094] The terms "comprising" and "including" and their forms are open-ended and mean "including but not limited to."

[0095] When the term "or" is used in this disclosure with respect to a list of options, it will generally be understood to be used in an inclusive sense unless the context provides otherwise. Thus, the statement "x or y" is equivalent to "x or y, or both," covering x but not y, y but not x, and both x and y. On the other hand, phrases such as "either x or y, but not both" make it clear that "or" is used in an exclusive sense.

[0096] The phrase "w, x, y, or z, or any combination thereof" or "at least one of... w, x, y, and z" is intended to cover all possibilities of a single element up to the total number of elements in the set. For example, given the set [w, x, y, z], these phrases cover any single element in the set (e.g., w but not x, y, or z), any two elements (e.g., w and x but not y or z), any three elements (e.g., w, x, and y but not z), and all four elements. Thus, the phrase "at least one of... w, x, y, and z" means at least one element of the elements in the set [w, x, y, z], thereby covering all possible combinations in this list of options. This phrase should not be construed as requiring the existence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0097] In this disclosure, various "labels" may precede a noun. Unless the context otherwise provides, different labels used for features (e.g., "first circuit", "second circuit", "specific circuit", "given circuit", etc.) refer to different instances of the feature. Unless otherwise stated, the labels "first", "second", and "third" do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) when applied to a particular feature.

[0098] Within this disclosure, different entities (which may be variously referred to as "units", "circuits", other components, etc.) may be described or claimed as "configured to" perform one or more tasks or operations. This expression—the [entity] that is [configured to perform one or more tasks]—is used herein to refer to a structure (i.e., a physical thing). More specifically, this expression is used to indicate that this structure is arranged to perform one or more tasks during operation. A structure may be considered "configured to" perform a certain task even if the structure is not currently being operated. Thus, an entity described or stated as "configured to" perform a certain task refers to a physical thing for implementing that task, such as a device, a circuit, a memory storing executable program instructions, and so on. This phrase is not used herein to refer to intangible things.

[0099] The term "configured to" is not intended to mean "configurable to". For example, an unprogrammed FPGA would not be considered "configured to" perform a particular function. However, the unprogrammed FPGA can be "configurable to" perform that function.

[0100] The phrase "configured to" in the claimed structure in the appended claims is expressly intended not to invoke 35 U.S.C. § 112(f) for that claim element. If the applicant wishes to invoke section 112(f) during the application process, it will use the "means for [performing a function]" structure to phrase the claim element.

[0101] The phrase "based on" is used to describe one or more factors that affect a determination. This term does not exclude the possibility that additional factors may affect the determination. That is, the determination may be based solely on the specified factors or on the specified factors and other unspecified factors. Consider the phrase "determine A based on B". This phrase specifies that B is a factor used to determine A or that B affects the determination of A. This phrase does not exclude the possibility that the determination of A may also be based on some other factors such as C. This phrase also intends to cover embodiments in which A is determined based solely on B. As used herein, the phrase "based on" is synonymous with the phrase "at least partially based on".

[0102] The phrase "responsive to" describes one or more factors that trigger an effect. This phrase does not exclude the possibility that additional factors may affect or otherwise trigger the effect. That is, the effect may be responsive solely to these factors, or may be responsive to the specified factors and other unspecified factors. Consider the phrase "perform A responsive to B". This phrase specifies that B is a factor that triggers the performance of A. This phrase does not exclude the possibility that the performance of A may also be responsive to some other factors, such as C. This phrase also intends to cover embodiments in which A is performed solely responsive to B.

Claims

1. A device, the device comprising: a data detection circuit configured to detect transmitted data on a communication link, wherein, when detecting the transmitted data, the data detection circuit is configured to: perform a first comparison of an amplitude of at least one signal with a reference voltage, wherein the at least one signal pair encodes a serial data stream including a plurality of data symbols; and use a result of the first comparison to activate a signal presence indicator; a speed detection circuit configured to determine whether the communication link is operating in a high-speed mode or a low-speed mode in response to activation of the signal presence indicator, wherein a speed detection signal indicating operation in the high-speed mode is generated in response to detecting that a number of transitions of the serial data stream within a reference time period exceeds a threshold; and a receiver circuit including a plurality of sub-circuits, wherein the receiver circuit is configured to activate one or more of the plurality of sub-circuits in response to activation of the speed detection signal.

2. The device according to claim 1, wherein the receiver circuit is further configured to sample at least one signal to generate a plurality of samples, and wherein, in order to generate the speed detection signal, the speed detection circuit is further configured to: use the plurality of samples to determine the number of transitions of the serial data stream within the reference time period; perform a second comparison of the number of transitions with the threshold; and use a result of the second comparison to activate the speed detection signal.

3. The device according to claim 2, wherein the speed detection circuit is further configured to filter the signal presence indicator to generate an enable signal.

4. The device according to claim 2, wherein the speed detection circuit is further configured to adjust a value of the reference time period using one or more operating characteristics of a computer system including the receiver circuit.

5. The device according to claim 2, wherein, in order to sample the at least one signal, the receiver circuit is further configured to: sample the at least one signal using a first edge of a clock signal to generate a first sample; and sample the at least one signal using a second edge of the clock signal to generate a second sample; and wherein, in order to perform the second comparison, the speed detection circuit is further configured to compare the first sample with the second sample.

6. The device according to claim 1, wherein the data detection circuit is further configured to: set the reference voltage to an initial value; and modify a value of the reference voltage in response to determining that the amplitude of the at least one signal exceeds the initial value of the reference voltage.

7. A method, the method comprising: receiving, by a detector circuit via a communication link, at least one signal encoding a serial data stream including a plurality of data symbols; performing, by the detector circuit, a first comparison of an amplitude of at least one of the one or more signals with a reference voltage; The detector circuit uses the result of the first comparison to generate a signal presence indicator to indicate the presence of data transmitted on the communication link; In response to activating the signal presence indicator, the detector circuit samples the at least one signal to generate a plurality of samples; The detector circuit determines whether the communication link is operating in a high-speed mode or a low-speed mode, where the determination includes performing a second comparison of the number of transitions of the serial data stream during a reference period with a threshold value using the plurality of samples; And In response to determining that the number of transitions exceeds the threshold value, one or more sub-circuits included in a receiver circuit coupled to the communication link are activated.

8. The method according to claim 7, wherein activating the one or more sub-circuits includes: Performing the second comparison of the number of transitions with the threshold value; Using the result of the second comparison to generate an enable signal; And In response to activating the enable signal, activating the one or more sub-circuits.

9. The method according to claim 7, the method further comprising: Determine the value of the reference period using one or more operating characteristics of a computer system including the detector circuit.

10. The method according to claim 7, the method further comprising: Setting the reference voltage to an initial value; And In response to determining that the amplitude of the at least one signal exceeds the initial value of the reference voltage, modifying the value of the reference voltage.

11. The method according to claim 7, the method further comprising: Filtering the signal presence indicator by the detector circuit to generate a filtered valid signal; And The detector circuit samples the at least one signal in response to determining that the filtered valid signal has a specific value to generate the plurality of samples.

12. The method according to claim 7, wherein sampling the at least one signal by the detector circuit includes: Sampling the at least one signal using a first edge of a clock signal to generate a first sample; And Sampling the at least one signal using a second edge of the clock signal to generate a second sample; And Wherein determining the number of transitions includes: comparing the first sample with the second sample.

13. The method according to claim 7, the method further comprising: In response to activating the one or more sub-circuits, the receiver circuit recovers one or more data symbols from the at least one signal.

14. An apparatus, the apparatus comprising: A first device configured to transmit at least one signal via a communication link, where the one or more signals encode a serial data stream including a plurality of data symbols; And A second device coupled to the communication link, where the second device includes a detector circuit configured to: Receive the one or more signals via the communication link; Detect the presence of the one or more signals, where when detecting the presence of the one or more signals, the detector circuit is configured to perform a first comparison of the amplitude of at least one of the one or more signals with a reference voltage; In response to detecting the presence of the one or more signals, use the result of the first comparison to generate a signal presence indicator; In response to activation of the signal presence indicator, sample the at least one signal to generate a plurality of samples; And Determine whether the communication link is operating in a high-speed mode or a low-speed mode by performing a second comparison of the number of transitions of the serial data stream during a reference period with a threshold; And Wherein the second device further includes a receiver circuit, the receiver circuit includes a plurality of sub-circuits, and wherein the receiver circuit is configured to activate one or more of the plurality of sub-circuits in response to determining that the communication link is operating in a high-speed mode.

15. The apparatus according to claim 14, wherein the detector circuit is further configured to: Perform the second comparison of the number of transitions with the threshold; and Use the result of the second comparison to generate an enable signal; and Wherein the receiver circuit is further configured to activate the one or more sub-circuits in response to activation of the enable signal.

16. The apparatus according to claim 14, wherein the detector circuit is further configured to determine the value of the reference period using one or more operating characteristics of a computer system including the first device and the second device.

17. The apparatus according to claim 14, wherein the detector circuit is further configured to: Set the reference voltage to an initial value; and Modify the value of the reference voltage in response to determining that the amplitude of the at least one signal exceeds the initial value of the reference voltage.

18. The apparatus according to claim 14, wherein the detector circuit is further configured to: Filter the signal presence indicator to generate a filtered valid signal; and Sample the at least one signal to generate the plurality of samples in response to determining that the filtered valid signal has a specific value.

19. The apparatus according to claim 14, wherein in order to sample the at least one signal, the detector circuit is further configured to: Sample the at least one signal using a first edge of a clock signal to generate a first sample; and Sample the at least one signal using a second edge of the clock signal to generate a second sample.

20. The apparatus according to claim 19, wherein in order to determine the number of transitions, the detector circuit is further configured to include comparing the first sample with the second sample.

Images