Driving circuit, driving method, driving module and display device

Abstract

The invention discloses a driving circuit, a driving method, a driving module and a display device, which can realize updating of local pictures of a display screen by controlling a gating input signal provided by a gating input end (VCT) so as to reduce power consumption. Wherein the driving circuit comprises a driving signal generating circuit (10), an output control circuit (12), a gating circuit (11), a voltage control circuit (14), a second node control circuit (15) and an output circuit (13); the driving signal generation circuit (10) generates an Nth-stage driving signal; n is a positive integer; the output control circuit (12) controls the connection between the first control node (NC1) and the second node (N2) under the control of the potential of the first node (N1); the gating circuit (11) controls the gating input signal to be written into the first node (N1) under the control of the gating control signal; the voltage control circuit (14) controls the potential of the second node (N2) according to the potential of the first node (N1). The second node control circuit (15) controls the connection between the second node (N2) and the first voltage end (V1) under the control of the potential of the first node (N1).

Description

Driving circuit, driving method, driving module and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a driving circuit, a driving method, a driving module, and a display device. Background Art

[0002] In related technologies, when an OLED (organic light-emitting diode) display updates its screen, it is necessary to initialize and write pixel voltages to all rows of pixel circuits within one frame. However, in certain special screens (such as the AOD display screen (the AOD display screen is a screen that controls the partial lighting of the screen without lighting the entire mobile phone screen), static screens, or screens that are updated less frequently), the pixel voltages of most pixel circuits on the entire screen do not need to be updated. That is, most pixel circuits can be maintained at the original display brightness through low-leakage LTPO (low-temperature polycrystalline oxide) TFTs (thin-film transistors), and repeated refreshing of these pixel circuits results in a waste of power consumption.

[0003] Summary of the Invention

[0004] In one aspect, an embodiment of the present disclosure provides a driving circuit, including a driving signal generating circuit, an output control circuit, a gating circuit, a voltage control circuit, a second node control circuit, and an output circuit;

[0005] The drive signal generating circuit is electrically connected to the first control node, the second control node and the N-th level drive signal output terminal, respectively, and is configured to generate and output an N-th level drive signal through the N-th level drive signal output terminal under the control of the potential of the first control node and the potential of the second control node; N is a positive integer;

[0006] The output control circuit is electrically connected to the first node, the first control node, and the second node, respectively, and is configured to control the connection between the first control node and the second node under the control of the potential of the first node;

[0007] The gating circuit is electrically connected to the first node, the gating input terminal and the gating control terminal respectively, and is used to control the gating input signal provided by the gating input terminal to be written into the first node under the control of the gating control signal provided by the gating control terminal;

[0008] The voltage control circuit is electrically connected to the first node and the second node respectively, and is used to control the potential of the second node according to the potential of the first node;

[0009] The second node control circuit is electrically connected to the first node, the second node and the first voltage terminal respectively, and is used to control the connection between the second node and the first voltage terminal under the control of the potential of the first node;

[0010] The output circuit is electrically connected to the second node, the second control node, the first node and the first voltage terminal, the second voltage terminal and the output driver terminal, respectively, and is used to control the connection between the output driver terminal and the first voltage terminal under the control of the potential of the second node, control the connection between the output driver terminal and the second voltage terminal under the control of the potential of the second control node, and control the connection between the output driver terminal and the second voltage terminal under the control of the potential of the first node.

[0011] Optionally, the gating circuit is used to control the writing of the gating input signal provided by the gating input terminal into the first node when the potential of the third node of the N-1th level is the second voltage and the potential of the Nth level driving signal is the second voltage.

[0012] Optionally, the gating circuit includes a first transistor; the gate of the first transistor is electrically connected to the gating control terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the gating input terminal.

[0013] Optionally, the gating control terminal includes a first gating control terminal and a second gating control terminal; the gating circuit includes a first transistor and a second transistor;

[0014] The gate of the first transistor is electrically connected to the first selection control terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the first electrode of the second transistor;

[0015] The gate of the second transistor is electrically connected to the second gate control terminal, and the second electrode of the second transistor is electrically connected to the gate input terminal;

[0016] The first gating control terminal is the Nth stage driving signal output terminal, the second gating control terminal is the N-1th stage third node, and the first transistor and the second transistor are both p-type transistors; or

[0017] The first gating control terminal is the third node of the N-1th stage, the second gating control terminal is the driving signal output terminal of the Nth stage, and the first transistor and the second transistor are both p-type transistors; or

[0018] The first strobe control terminal is an N-1th level drive signal output terminal, the second strobe control terminal is an Nth level drive signal output terminal, the first transistor is an n-type transistor, and the second transistor is a p-type transistor; or

[0019] The first strobe control terminal is an N-th level drive signal output terminal, the second strobe control terminal is an N-1-th level drive signal output terminal, the first transistor is a p-type transistor, and the second transistor is an n-type transistor; or

[0020] The first strobe control terminal is connected to the inverted signal of the N-1th level drive signal, the second strobe control terminal is the output terminal of the Nth level drive signal, and the first transistor and the second transistor are both p-type transistors; or

[0021] The first gate control terminal is an output terminal of the Nth level driving signal, and the second gate control terminal is connected to the inverted signal of the N-1th level driving signal; the first transistor and the second transistor are both p-type transistors; or,

[0022] The first gate control terminal is the N-1th level driving signal terminal, the second gate control terminal is connected to the inverted signal of the Nth level driving signal, and the first transistor and the second transistor are both n-type transistors; or

[0023] The first strobe control terminal is connected to the inverted signal of the Nth level driving signal, the second strobe control terminal is the N-1th level driving signal terminal, and the first transistor and the second transistor are both n-type transistors.

[0024] Optionally, the output control circuit includes a third transistor, and the voltage control circuit includes a first capacitor;

[0025] The gate of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the first control node, and the second electrode of the third transistor is electrically connected to the second node;

[0026] A first end of the first capacitor is electrically connected to the second node, and a second end of the first capacitor is electrically connected to the first voltage end.

[0027] Optionally, the second node control circuit includes a fourth transistor, and the output circuit includes a fifth transistor, a sixth transistor, a seventh transistor and a second capacitor;

[0028] The gate of the fourth transistor is electrically connected to the first node, the first electrode of the fourth transistor is electrically connected to the first voltage terminal, and the second electrode of the fourth transistor is electrically connected to the second node;

[0029] The gate of the fifth transistor is electrically connected to the second node, the first electrode of the fifth transistor is electrically connected to the first voltage terminal, and the second electrode of the fifth transistor is electrically connected to the output driving terminal;

[0030] The gate of the sixth transistor is electrically connected to the second control node, the first electrode of the sixth transistor is electrically connected to the output driving terminal, and the second electrode of the sixth transistor is electrically connected to the second voltage terminal;

[0031] The gate of the seventh transistor is electrically connected to the first node, the first electrode of the seventh transistor is electrically connected to the output driving terminal, and the second electrode of the seventh transistor is electrically connected to the second voltage terminal;

[0032] A first end of the second capacitor is electrically connected to the second node, and a second end of the second capacitor is electrically connected to the first voltage end.

[0033] Optionally, the driving circuit described in at least one embodiment of the present disclosure further includes an initialization circuit;

[0034] The initialization circuit is electrically connected to the initial control terminal, the first node and the second voltage terminal respectively, and is used to control the connection between the first node and the second voltage terminal under the control of the initial control signal provided by the initial control terminal.

[0035] Optionally, the driving circuit according to at least one embodiment of the present disclosure further includes a first node control circuit;

[0036] The first node control circuit is electrically connected to the fourth node, the first node and the second voltage terminal respectively, and is used to control the connection between the first node and the second voltage terminal under the control of the potential of the fourth node.

[0037] Optionally, the initialization circuit includes an eighth transistor;

[0038] A gate of the eighth transistor is electrically connected to the initial control terminal, a first electrode of the eighth transistor is electrically connected to the first node, and a second electrode of the eighth transistor is electrically connected to the second voltage terminal.

[0039] Optionally, the first node control circuit includes a ninth transistor;

[0040] The gate of the ninth transistor is electrically connected to the fourth node, the first electrode of the ninth transistor is electrically connected to the first node, and the second electrode of the ninth transistor is electrically connected to the second voltage terminal.

[0041] Optionally, the driving circuit according to at least one embodiment of the present disclosure further includes a voltage maintaining circuit, wherein the voltage maintaining circuit includes a first inverter, a second inverter, and a maintaining control circuit;

[0042] The input terminal of the first inverter is electrically connected to the first node, the output terminal of the first inverter is electrically connected to the fifth node, the input terminal of the second inverter is electrically connected to the fifth node, and the output terminal of the second inverter is electrically connected to the sixth node;

[0043] The first inverter is used to invert the potential of the first node and output the inverted potential of the first node through the output terminal of the first inverter;

[0044] The second inverter is used to invert the potential of its input terminal and output the inverted potential through the output terminal of the second inverter;

[0045] The sustain control circuit is electrically connected to the sustain control terminal, the sixth node and the first node respectively, and is used to control the connection or disconnection between the sixth node and the first node under the control of the sustain control signal provided by the sustain control terminal.

[0046] Optionally, the maintenance control terminal includes a first maintenance control terminal and a second maintenance control terminal;

[0047] The sustain control circuit includes a tenth transistor and an eleventh transistor;

[0048] The gate of the tenth transistor is electrically connected to the first sustain control terminal, the first electrode of the tenth transistor is electrically connected to the first node, and the second electrode of the tenth transistor is electrically connected to the sixth node;

[0049] The gate of the eleventh transistor is electrically connected to the second sustain control terminal, the first electrode of the eleventh transistor is electrically connected to the sixth node, and the second electrode of the eleventh transistor is electrically connected to the first node;

[0050] The tenth transistor is a p-type transistor, and the eleventh transistor is an n-type transistor;

[0051] The first sustain control terminal is the N-1th level driving signal terminal, and the second sustain control terminal is the first clock signal terminal; or

[0052] The first sustain control terminal is a second clock signal terminal, and the second sustain control terminal is a first clock signal terminal.

[0053] Optionally, the first inverter includes a twelfth transistor and a thirteenth transistor, and the second inverter includes a fourteenth transistor and a fifteenth transistor;

[0054] The gate of the twelfth transistor is electrically connected to the first node, the first electrode of the twelfth transistor is electrically connected to the first voltage terminal, and the second electrode of the twelfth transistor is electrically connected to the fifth node;

[0055] The gate of the thirteenth transistor is electrically connected to the first node, the first electrode of the thirteenth transistor is electrically connected to the fifth node, and the second electrode of the thirteenth transistor is electrically connected to the second voltage terminal;

[0056] The twelfth transistor is a p-type transistor, and the thirteenth transistor is an n-type transistor;

[0057] The gate of the fourteenth transistor is electrically connected to the fifth node, the first electrode of the fourteenth transistor is electrically connected to the first voltage terminal, and the second electrode of the fourteenth transistor is electrically connected to the sixth node;

[0058] The gate of the fifteenth transistor is electrically connected to the fifth node, the first electrode of the fifteenth transistor is electrically connected to the sixth node, and the second electrode of the fifteenth transistor is electrically connected to the second voltage terminal;

[0059] The fourteenth transistor is a p-type transistor, and the fifteenth transistor is an n-type transistor.

[0060] Optionally, the driving signal generating circuit includes a first control node control circuit, a second control node control circuit, a first driving output circuit, and a second driving output circuit;

[0061] The first control node control circuit is used to control the potential of the first control node;

[0062] The second control node control circuit is used to control the potential of the second control node;

[0063] The first drive output circuit is electrically connected to the first control node, the first voltage terminal, and the N-th level drive signal output terminal, respectively, and is used to control the connection between the N-th level drive signal output terminal and the first voltage terminal under the control of the potential of the first control node;

[0064] The second drive output circuit is electrically connected to the second control node, the Nth level drive signal output terminal and the second voltage terminal respectively, and is used to control the connection between the Nth level drive signal output terminal and the second voltage terminal under the control of the potential of the second control node.

[0065] Optionally, the first control node control circuit includes a seventh node control circuit, an eighth node control circuit, a third node control circuit and the first control circuit;

[0066] The seventh-node control circuit is electrically connected to the first clock signal terminal, the second voltage terminal, the seventh node, and the ninth node, respectively, and is configured to control communication between the seventh node and the second voltage terminal under the control of the first clock signal provided by the first clock signal terminal, and to control communication between the seventh node and the first clock signal terminal under the control of the potential of the ninth node;

[0067] The eighth node control circuit is electrically connected to the second voltage terminal, the seventh node, and the eighth node, respectively, and is configured to control the seventh node to be connected to the eighth node under the control of the second voltage signal provided by the second voltage terminal;

[0068] The third node control circuit is electrically connected to the eighth node, the second clock signal terminal, and the third node, respectively, and is configured to control the connection between the third node and the second clock signal terminal under the control of the potential of the eighth node, and to control the potential of the third node according to the potential of the eighth node;

[0069] The first control circuit is electrically connected to the second clock signal terminal, the third node, the first control node, the ninth node and the first voltage terminal, respectively, and is used to control the connection between the third node and the first control node under the control of the second clock signal provided by the second clock signal terminal, and to control the connection between the first control node and the first voltage terminal under the control of the potential of the ninth node.

[0070] Optionally, the second control node control circuit includes a ninth node control circuit, a tenth node control circuit, a fourth node control circuit, an eleventh node control circuit, and a second control circuit;

[0071] The ninth node control circuit is electrically connected to the first clock signal terminal, the N-1th level drive signal output terminal, the ninth node, the initial control terminal, and the first voltage terminal, respectively, and is configured to control the ninth node to be connected to the N-1th level drive signal terminal under the control of the first clock signal provided by the first clock signal terminal, and to control the ninth node to be connected to the first voltage terminal under the control of the initial control signal provided by the initial control terminal;

[0072] The tenth node control circuit is electrically connected to the first clock signal terminal, the N-1th stage drive signal output terminal, and the tenth node, respectively, and is used to control the connection between the tenth node and the N-1th stage drive signal output terminal under the control of the first clock signal provided by the first clock signal terminal;

[0073] The fourth node control circuit is electrically connected to the first voltage terminal, the seventh node, the fourth node, the eleventh node, and the second clock signal terminal, respectively, and is configured to control the fourth node to be connected to the first voltage terminal under the control of the potential of the seventh node, and to control the fourth node to be connected to the second clock signal terminal under the control of the potential of the eleventh node;

[0074] the eleventh node control circuit being electrically connected to the fourth node, the eleventh node, the second voltage terminal, and the tenth node, respectively, and being configured to control the potential of the eleventh node according to the potential of the fourth node, and to control the communication between the eleventh node and the tenth node under the control of a second voltage signal provided by the second voltage terminal;

[0075] The second control circuit is electrically connected to the eleventh node and the second control node, respectively, and is configured to control the potential of the second control node under the control of the potential of the eleventh node.

[0076] Optionally, the seventh node control circuit includes a sixteenth transistor and a seventeenth transistor, the eighth node control circuit includes an eighteenth transistor, the third node control circuit includes a nineteenth transistor and a third capacitor, and the first control circuit includes a twentieth transistor and a twenty-first transistor;

[0077] The gate of the sixteenth transistor is electrically connected to the first clock signal terminal, the first electrode of the sixteenth transistor is electrically connected to the second voltage terminal, and the second electrode of the sixteenth transistor is electrically connected to the seventh node;

[0078] The gate of the seventeenth transistor is electrically connected to the ninth node, the first electrode of the seventeenth transistor is electrically connected to the seventh node, and the second electrode of the seventeenth transistor is electrically connected to the first clock signal terminal;

[0079] The gate of the eighteenth transistor is electrically connected to the second voltage terminal, the first electrode of the eighteenth transistor is electrically connected to the seventh node, and the second electrode of the eighteenth transistor is electrically connected to the eighth node;

[0080] The gate of the nineteenth transistor is electrically connected to the eighth node, the first electrode of the nineteenth transistor is electrically connected to the second clock signal terminal, and the second electrode of the nineteenth transistor is electrically connected to the third node;

[0081] A first end of the third capacitor is electrically connected to the eighth node, and a second end of the third capacitor is electrically connected to the third node;

[0082] The gate of the twentieth transistor is electrically connected to the second clock signal terminal, the first electrode of the twentieth transistor is electrically connected to the third node, and the second electrode of the twentieth transistor is electrically connected to the first control node;

[0083] A gate of the twenty-first transistor is electrically connected to the ninth node, a first electrode of the twenty-first transistor is electrically connected to the first control node, and a second electrode of the twenty-first transistor is electrically connected to the first voltage terminal.

[0084] Optionally, the ninth node control circuit includes a twenty-second transistor and a twenty-third transistor, the tenth node control circuit includes a twenty-fourth transistor, the fourth node control circuit includes a twenty-fifth transistor and a twenty-sixth transistor, the eleventh node control circuit includes a twenty-seventh transistor and a fourth capacitor, and the second control circuit includes a twenty-eighth transistor and a twenty-ninth transistor;

[0085] a gate of the twenty-second transistor electrically connected to the first clock signal terminal, a first electrode of the twenty-second transistor electrically connected to the (N-1)th stage driving signal output terminal, and a second electrode of the twenty-second transistor electrically connected to the ninth node;

[0086] The gate of the twenty-third transistor is electrically connected to the initial control terminal, the first electrode of the twenty-third transistor is electrically connected to the first voltage terminal, and the second electrode of the twenty-third transistor is electrically connected to the ninth node;

[0087] a gate of the twenty-fourth transistor is electrically connected to the first clock signal terminal, a first electrode of the twenty-fourth transistor is electrically connected to the (N-1)th stage driving signal output terminal, and a second electrode of the twenty-fourth transistor is electrically connected to the tenth node;

[0088] a gate of the twenty-fifth transistor is electrically connected to the seventh node, a first electrode of the twenty-fifth transistor is electrically connected to the first voltage terminal, and a second electrode of the twenty-fifth transistor is electrically connected to the fourth node;

[0089] a gate of the twenty-sixth transistor is electrically connected to the eleventh node, a first electrode of the twenty-sixth transistor is electrically connected to the fourth node, and a second electrode of the twenty-sixth transistor is electrically connected to the second clock signal terminal;

[0090] A gate of the twenty-seventh transistor is electrically connected to the second voltage terminal, a first electrode of the twenty-seventh transistor is electrically connected to the tenth node, and a second electrode of the twenty-seventh transistor is electrically connected to the eleventh node;

[0091] The first end of the fourth capacitor is electrically connected to the fourth node, and the second end of the fourth capacitor is electrically connected to the eleventh node;

[0092] a gate of the twenty-eighth transistor is electrically connected to the eleventh node, a first electrode of the twenty-eighth transistor is electrically connected to the second control node, and a second electrode of the twenty-eighth transistor is electrically connected to the eleventh node;

[0093] A gate of the twenty-ninth transistor is electrically connected to the second voltage terminal, a first electrode of the twenty-ninth transistor is electrically connected to the ninth node, and a second electrode of the twenty-ninth transistor is electrically connected to the second control node.

[0094] Optionally, the first drive output circuit includes a 30th transistor and a fifth capacitor, and the second drive output circuit includes a 31st transistor and a sixth capacitor;

[0095] The gate of the 30th transistor is electrically connected to the first control node, the first electrode of the 30th transistor is electrically connected to the first voltage terminal, and the second electrode of the 30th transistor is electrically connected to the Nth stage driving signal output terminal;

[0096] A first terminal of the fifth capacitor is electrically connected to the first control node, and a second terminal of the fifth capacitor is electrically connected to the first voltage terminal;

[0097] The gate of the thirty-first transistor is electrically connected to the second control node, the first electrode of the thirty-first transistor is electrically connected to the N-th stage driving signal output terminal, and the second electrode of the thirty-first transistor is electrically connected to the second voltage terminal;

[0098] A first end of the sixth capacitor is electrically connected to the Nth stage driving signal output terminal, and a second end of the sixth capacitor is electrically connected to the second voltage terminal.

[0099] In a second aspect, an embodiment of the present disclosure provides a driving method, applying the above-mentioned driving circuit, the driving method comprising:

[0100] The driving signal generating circuit generates an N-th level driving signal under the control of the potential of the first control node and the potential of the second control node and outputs the N-th level driving signal through the N-th level driving signal output terminal; N is a positive integer;

[0101] The output control circuit controls the connection between the first control node and the second node under the control of the potential of the first node;

[0102] The gating circuit controls the gating input signal to be written into the first node under the control of the gating control signal;

[0103] The voltage control circuit controls the potential of the second node according to the potential of the first node;

[0104] The second node control circuit controls the connection between the second node and the first voltage terminal under the control of the potential of the first node;

[0105] The output circuit controls the output drive terminal to be connected to the first voltage terminal under the control of the potential of the second node. The output circuit controls the output drive terminal to be connected to the second voltage terminal under the control of the potential of the second control node. The output circuit controls the output drive terminal to be connected to the second voltage terminal under the control of the potential of the first node.

[0106] In a third aspect, an embodiment of the present disclosure provides a driving module, comprising a plurality of stages of the driving circuits described above;

[0107] The Nth stage driving circuit is electrically connected to the driving signal output terminal included in the N-1th stage driving circuit; N is a positive integer.

[0108] In a fourth aspect, an embodiment of the present disclosure provides a display device comprising the above-mentioned driving module. BRIEF DESCRIPTION OF THE DRAWINGS

[0109] FIG1 is a structural diagram of a driving circuit according to an embodiment of the present disclosure;

[0110] FIG2 is a circuit diagram of a related pixel circuit;

[0111] FIG3 is an operation timing diagram of the related pixel circuit shown in FIG2 ;

[0112] FIG4 is a circuit diagram of a related pixel circuit;

[0113] 5 is a circuit diagram of at least one embodiment of a gating circuit in a driving circuit according to an embodiment of the present disclosure;

[0114] 6 is a circuit diagram of at least one embodiment of a gating circuit in a driving circuit according to an embodiment of the present disclosure;

[0115] 7 is a circuit diagram of at least one embodiment of a gating circuit in a driving circuit according to an embodiment of the present disclosure;

[0116] FIG8 is a circuit diagram of at least one embodiment of a gating circuit in a driving circuit according to an embodiment of the present disclosure;

[0117] 9 is a circuit diagram of at least one embodiment of a gating circuit in a driving circuit according to an embodiment of the present disclosure;

[0118] FIG10 is a circuit diagram of at least one embodiment of a gating circuit in a driving circuit according to an embodiment of the present disclosure;

[0119] FIG11 is a circuit diagram of at least one embodiment of a gating circuit in a driving circuit according to an embodiment of the present disclosure;

[0120] FIG12 is a circuit diagram of at least one embodiment of a gating circuit in a driving circuit according to an embodiment of the present disclosure;

[0121] FIG13 is a circuit diagram of at least one embodiment of a gating circuit in a driving circuit according to an embodiment of the present disclosure;

[0122] FIG14 is a circuit diagram of at least one embodiment of a gating circuit in a driving circuit according to an embodiment of the present disclosure;

[0123] FIG15 is a circuit diagram of at least one embodiment of an inverter;

[0124] FIG16 is a circuit diagram of at least one embodiment of an inverter;

[0125] FIG17 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0126] FIG18 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0127] FIG19 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0128] FIG20 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0129] FIG21 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0130] FIG22 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0131] FIG23 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0132] FIG24 is a timing diagram of a simulated operation of at least one embodiment of the driving circuit shown in FIG23;

[0133] FIG25 is a timing diagram of a simulated operation of at least one embodiment of the driving circuit shown in FIG23;

[0134] FIG26 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0135] FIG27 is a timing diagram of a simulated operation of at least one embodiment of the driving circuit shown in FIG26 ;

[0136] FIG28 is a structural diagram of a driving module according to at least one embodiment of the present disclosure;

[0137] FIG29 is an operation timing diagram of at least one embodiment of the driving module shown in FIG28;

[0138] FIG30 is a structural diagram of a driving module according to at least one embodiment of the present disclosure;

[0139] FIG31 is an operation timing diagram of at least one embodiment of the driving module shown in FIG30 ;

[0140] FIG32 is a waveform diagram of a first clock signal provided by GCK and a second clock signal provided by GCB. DETAILED DESCRIPTION

[0141] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0142] The transistors used in all embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor except the gate, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0143] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0144] As shown in FIG1 , the driving circuit according to the embodiment of the present disclosure includes a driving signal generating circuit 10 , a gating circuit 11 , an output control circuit 12 , an output circuit 13 , a voltage control circuit 14 and a second node control circuit 15 ;

[0145] The drive signal generating circuit 10 is electrically connected to the first control node NC1, the second control node NC2 and the N-th stage drive signal output terminal NS(N), respectively, and is configured to generate and output an N-th stage drive signal through the N-th stage drive signal output terminal NS(N) under the control of the potential of the first control node NC1 and the potential of the second control node NC2; N is a positive integer;

[0146] The gating circuit 11 is electrically connected to the first node N1, the gating input terminal VCT and the gating control terminal CX, respectively, and is used to control the gating input signal provided by the gating input terminal VCT to be written into the first node N1 under the control of the gating control signal provided by the gating control terminal CX;

[0147] The output control circuit 12 is electrically connected to the first node N1, the first control node NC1, and the second node N2, respectively, and is configured to control the connection between the first control node NC1 and the second node N2 under the control of the potential of the first node N1;

[0148] The voltage control circuit 14 is electrically connected to the first node N1 and the second node N2, respectively, and is configured to control the potential of the second node N2 according to the potential of the first node N1;

[0149] The second node control circuit 15 is electrically connected to the first node N1, the second node N2 and the first voltage terminal V1 respectively, and is used to control the connection between the second node N2 and the first voltage terminal V1 under the control of the potential of the first node N1;

[0150] The output circuit 13 is electrically connected to the second node N2, the second control node NC2, the first node N1 and the first voltage terminal V1, the second voltage terminal V2 and the output drive terminal NO(N), respectively, and is used to control the connection between the output drive terminal NO(N) and the first voltage terminal V1 under the control of the potential of the second node N2, control the connection between the output drive terminal NO(N) and the second voltage terminal V2 under the control of the potential of the second control node NC2, and control the connection between the output drive terminal NO(N) and the second voltage terminal V2 under the control of the potential of the first node N1.

[0151] In the embodiment of the driving circuit shown in FIG1 of the present disclosure, when in operation, the driving signal generating circuit 10 generates and outputs an N-level driving signal through the N-level driving signal output terminal NS(N) under the control of the potential of the first control node NC1 and the potential of the second control node NC2; the gating circuit 11 controls the writing of the gating input signal into the first node N1 under the control of the gating control signal; the output control circuit 12 controls the connection between the first control node NC1 and the second node N2 under the control of the potential of the first node N1; the voltage control circuit 14 controls the potential of the second node N2 according to the potential of the first node N1; the second node control circuit 15 controls the connection between the second node N2 and the first voltage terminal V1 under the control of the potential of the first node N1; the output circuit 13 controls the connection between the output driving terminal NO(N) and the first voltage terminal V1 under the control of the potential of the second node N2, controls the connection between the output driving terminal NO(N) and the second voltage terminal V2 under the control of the potential of the second control node NC2, and controls the connection between the output driving terminal NO(N) and the second voltage terminal V2 under the control of the potential of the first node N1.

[0152] In at least one embodiment of the present disclosure, the first voltage end may be a high voltage end, and the second voltage end may be a low voltage end, but the present invention is not limited thereto.

[0153] The embodiment of the driving circuit shown in FIG. 1 of the present disclosure may be an N-th stage driving circuit.

[0154] When the embodiment of the driving circuit shown in FIG1 of the present disclosure is working, within one frame time,

[0155] Before the Nth stage driving signal providing phase, the gating circuit 11 writes the gating input signal provided by the gating input terminal VCT into the first node N1 under the control of the gating control signal;

[0156] When the selection input signal is a high voltage signal, in the N-stage driving signal providing stage, the N-stage driving signal output terminal NS(N) outputs a high voltage signal, the potential of the first node N1 is a high voltage, and the output control circuit 12 controls the first control node NC1 to be disconnected from the second node N2 under the control of the potential of the first node N1. The voltage control circuit 14 controls the potential of the second node N2 to be a high voltage according to the potential of the first node N1. The output circuit controls the output driving terminal NO(N) to maintain the output of the low voltage signal, so that the pixel circuit of the corresponding row can be controlled not to update the pixel voltage.

[0157] When the selection input signal is a low voltage signal, in the N-level drive signal providing stage, the N-level drive signal output terminal NS(N) outputs a high voltage signal, and the potential of the first node N1 is a low voltage. The output control circuit 12 controls the connection between the first control node NC1 and the second node N2 under the control of the potential of the first node N1, so that the potential of the second node N2 is a low voltage. The output circuit 13 controls the connection between the output drive terminal NO(N) and the first voltage terminal V1 under the control of the potential of the second node N2, so that NO(N) outputs a high voltage signal, which can control the corresponding row pixel circuit to update the pixel voltage.

[0158] The embodiment of the present disclosure can realize the update of a partial picture of the display screen by controlling the selection input signal provided by the selection input terminal VCT, thereby reducing power consumption, or realize ultra-low power consumption of OLED display products such as wearable products, mobile terminals, and NB (notebook computers) by partially updating the display picture.

[0159] As shown in FIG2 , the relevant pixel circuit may include a first display control transistor M1, a second display control transistor M2, a driving transistor M3, a fourth display control transistor M4, a fifth display control transistor M5, a sixth display control transistor M6, a seventh display control transistor M7, a storage capacitor Cst, and an organic light emitting diode O1;

[0160] The gate of M1 is electrically connected to the first reset terminal NR(N), the source of M1 is electrically connected to the initial voltage terminal I1, and the drain of M1 is electrically connected to the gate of M3;

[0161] The gate of M2 is electrically connected to the first scanning terminal NG(N), the source of M2 is electrically connected to the gate of M3, and the drain of M2 is electrically connected to the drain of M3;

[0162] The gate of M4 is electrically connected to the second scanning terminal PG(N), the source of M4 is electrically connected to the data line D1, and the drain of M4 is electrically connected to the source of M3;

[0163] The gate of M5 is electrically connected to the light emitting control terminal E(N), the source of M5 is electrically connected to the power supply voltage terminal ELVDD, and the drain of M5 is electrically connected to the source of M3;

[0164] The gate of M6 is electrically connected to the light emitting control terminal E(N), the source of M6 is electrically connected to the drain of M3, the drain of M6 is electrically connected to the anode of O1; the cathode of O1 is electrically connected to the low level terminal ELVSS;

[0165] The gate of M7 is electrically connected to the second scanning terminal PG(N), the source of M7 is electrically connected to the initial voltage terminal I1, and the drain of M7 is electrically connected to the anode of O1.

[0166] In a specific implementation, the first reset terminal NR(N) may be the first scanning terminal NG(N) of the N-1th stage, but is not limited thereto.

[0167] In the relevant pixel circuit shown in FIG2 , M1 and M2 are n-type transistors, M3, M4, M5, M6 and M7 are p-type transistors, M1 and M2 are IGZO TFTs with small leakage current, and M3, M4, M5, M6 and M7 are LTPS TFTs.

[0168] In the relevant pixel circuit shown in FIG2 , M1 and M2 are IGZO TFTs. When using low-frequency display, the IGZO TFTs can ensure that Cst can maintain the voltage of the gate of M3 for a longer period of time.

[0169] In the relevant pixel circuit shown in Figure 2, the second scanning terminal PG (N) is responsible for resetting the voltage of the anode of O1 and writing the data voltage on the data line into the source of the driving transistor, and the first scanning terminal NG (N) is responsible for resetting Cst, extracting Vth (Vth is the threshold voltage of the driving transistor) and writing the data voltage into the gate of the driving transistor.

[0170] In a specific implementation, the first scanning signal provided by the first scanning terminal NG(N) and the second scanning signal provided by the second scanning terminal PG(N) may be in opposite phases to each other, but the present invention is not limited thereto.

[0171] The driving circuit described in at least one embodiment of the present disclosure may provide the first scanning signal to the first scanning terminal NG(N) via the output driving terminal NO(N), but the present invention is not limited thereto.

[0172] As shown in FIG3 , when the relevant pixel circuit shown in FIG2 is in operation, a display cycle may include a first display control phase t1 , a second display control phase t2 , and a third display control phase t3 , which are set in sequence;

[0173] In the first display control stage t1, E(N) outputs a high voltage signal, NR(N) provides a high voltage signal, PG(N) provides a high voltage signal, NG(N) provides a low voltage signal, M5 and M6 are turned off, M1 is turned on, and the potential of the gate of M3 is pulled down to the initial voltage Vinit; the initial voltage terminal I1 is used to provide the initial voltage Vinit;

[0174] In the second display control phase t2, E(N) outputs a high voltage signal, NR(N) provides a low voltage signal, PG(N) provides a low voltage signal, NG(N) provides a high voltage signal, M5 and M6 are turned off, M1 is turned off, M2 is turned on, M4 is turned on, M2 and M3 form a diode structure, and the data voltage Vdata provided by the data line D1 charges Cst until M3 is turned off. At this time, the gate voltage of M3 is Vdata+Vth, where Vth is the threshold voltage of M3; M7 is turned on to reset the anode voltage of O1;

[0175] In the third display control phase t3, E(N) outputs a low voltage signal, NR(N) provides a low voltage signal, PG(N) provides a high voltage signal, NG(N) provides a low voltage signal, M5 and M6 are turned on, M3 drives O1 to emit light; O1 emits light according to the voltage setting of Vdata.

[0176] From the above working process of the relevant pixel circuit, it can be known that NG(N) can control whether the data voltage Vdata (the data voltage Vdata can be the pixel voltage) is written into the gate of M3 in the second display control stage.

[0177] FIG4 is a circuit diagram of a related pixel circuit.

[0178] As shown in FIG4 , the relevant pixel circuit may include a first display control transistor M1, a second display control transistor M2, a driving transistor M3, a fourth display control transistor M4, a fifth display control transistor M5, a sixth display control transistor M6, a seventh display control transistor M7, a storage capacitor Cst, and an organic light emitting diode O1;

[0179] The gate of M1 is electrically connected to the third reset terminal RST1, the source of M1 is electrically connected to the initial voltage terminal I1, and the drain of M1 is electrically connected to the drain of M3;

[0180] The gate of M2 is electrically connected to the first scanning terminal NG(N), the source of M2 is electrically connected to the gate of M3, and the drain of M2 is electrically connected to the drain of M3;

[0181] The gate of M4 is electrically connected to the second scanning terminal PG(N), the source of M4 is electrically connected to the data line D1, and the drain of M4 is electrically connected to the source of M3;

[0182] The gate of M5 is electrically connected to the light emitting control terminal E(N), the source of M5 is electrically connected to the power supply voltage terminal ELVDD, and the drain of M5 is electrically connected to the source of M3;

[0183] The gate of M6 is electrically connected to the light emitting control terminal E(N), the source of M6 is electrically connected to the drain of M3, the drain of M6 is electrically connected to the anode of O1; the cathode of O1 is electrically connected to the low level terminal ELVSS;

[0184] The gate of M7 is electrically connected to the fourth reset terminal RST2 , the source of M7 is electrically connected to the initial voltage terminal I1 , and the drain of M7 is electrically connected to the anode of O1 .

[0185] When the relevant pixel circuit shown in FIG. 4 is in operation, NG(N) can control whether the data voltage Vdata on the data line D1 is written into the gate of the driving transistor M3 .

[0186] In a specific implementation, the first scanning signal provided by NG(N) can be used to control the opening or closing of the second transistor to control whether the data voltage on the data line is written to the gate of the driving transistor, thereby controlling whether the brightness of the pixel circuit of this row is updated; when NG(N) outputs a high voltage signal, the second transistor is turned on, and the brightness of the pixel circuit of this row can be updated; when NG(N) outputs a low voltage signal, the second transistor is always turned off, and the change of the data voltage on the data line will not be written to the gate of the driving transistor, and the luminous brightness of the organic light emitting diode will not change, that is, the display brightness of the pixel circuit of the current row in the current frame remains unchanged. In summary, it can be seen that the pixel brightness can be refreshed by controlling the opening or closing of the N-type transistor. Therefore, when you want to prevent some pixels from being refreshed, just ensure that the N-type transistor is turned off.

[0187] In at least one embodiment of the present disclosure, the gating circuit is used to control the writing of the gating input signal provided by the gating input terminal into the first node when the potential of the third node of the N-1th level is the second voltage and the potential of the Nth level driving signal is the second voltage.

[0188] Optionally, the second voltage may be a low voltage, but is not limited thereto.

[0189] Optionally, the gating circuit includes a first transistor; the gate of the first transistor is electrically connected to the gating control terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the gating input terminal.

[0190] As shown in FIG5 , the gating circuit may include a first transistor T1;

[0191] The gate of the first transistor T1 is electrically connected to the strobe control terminal S0, the drain of the first transistor T1 is electrically connected to the first node N1, and the source of the first transistor T1 is electrically connected to the strobe input terminal VCT;

[0192] T1 is a p-type transistor.

[0193] As shown in FIG6 , the gating circuit may include a first transistor T1;

[0194] The gate of the first transistor T1 is electrically connected to the strobe control terminal S0, the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the strobe input terminal VCT;

[0195] T1 is an n-type transistor.

[0196] Optionally, the gating control terminal includes a first gating control terminal and a second gating control terminal; the gating circuit includes a first transistor and a second transistor;

[0197] The gate of the first transistor is electrically connected to the first selection control terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the first electrode of the second transistor;

[0198] The gate of the second transistor is electrically connected to the second gate control terminal, and the second electrode of the second transistor is electrically connected to the gate input terminal;

[0199] The first gating control terminal is the Nth stage driving signal output terminal, the second gating control terminal is the N-1th stage third node, and the first transistor and the second transistor are both p-type transistors; or

[0200] The first gating control terminal is the third node of the N-1th stage, the second gating control terminal is the driving signal output terminal of the Nth stage, and the first transistor and the second transistor are both p-type transistors; or

[0201] The first strobe control terminal is an N-1th level drive signal output terminal, the second strobe control terminal is an Nth level drive signal output terminal, the first transistor is an n-type transistor, and the second transistor is a p-type transistor; or

[0202] The first strobe control terminal is an N-th level drive signal output terminal, the second strobe control terminal is an N-1-th level drive signal output terminal, the first transistor is a p-type transistor, and the second transistor is an n-type transistor; or

[0203] The first strobe control terminal is connected to the inverted signal of the N-1th level drive signal, the second strobe control terminal is the output terminal of the Nth level drive signal, and the first transistor and the second transistor are both p-type transistors; or

[0204] The first gate control terminal is an output terminal of the Nth level driving signal, and the second gate control terminal is connected to the inverted signal of the N-1th level driving signal; the first transistor and the second transistor are both p-type transistors; or,

[0205] The first gate control terminal is the N-1th level driving signal terminal, the second gate control terminal is connected to the inverted signal of the Nth level driving signal, and the first transistor and the second transistor are both n-type transistors; or

[0206] The first strobe control terminal is connected to the inverted signal of the Nth level driving signal, the second strobe control terminal is the N-1th level driving signal terminal, and the first transistor and the second transistor are both n-type transistors.

[0207] As shown in FIG7 , the gating circuit may include a first transistor T1 and a second transistor T2 ;

[0208] The gate of the first transistor T1 is electrically connected to the N-1th stage driving signal output terminal NS(N-1), the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the drain of the second transistor T2;

[0209] The gate of the second transistor T2 is electrically connected to the N-th stage driving signal output terminal NS(N), and the source of the second transistor T2 is electrically connected to the selection input terminal VCT;

[0210] T1 is an n-type transistor, and T2 is a p-type transistor.

[0211] As shown in FIG8 , the gating circuit may include a first transistor T1 and a second transistor T2 ;

[0212] The gate of the first transistor T1 is electrically connected to the N-th stage driving signal output terminal NS(N), the drain of the first transistor T1 is electrically connected to the first node N1, and the source of the first transistor T1 is electrically connected to the source of the second transistor T2;

[0213] The gate of the second transistor T2 is electrically connected to the N-1th stage driving signal output terminal NS(N-1), and the drain of the second transistor T2 is electrically connected to the selection input terminal VCT;

[0214] T1 is a p-type transistor, and T2 is an n-type transistor.

[0215] As shown in FIG9 , the gating circuit may include a first transistor T1 and a second transistor T2 ;

[0216] The gate of the first transistor T1 is electrically connected to the third node N3 (N-1) of the N-1th stage, the drain of the first transistor T1 is electrically connected to the first node N1, and the source of the first transistor T1 is electrically connected to the drain of the second transistor T2;

[0217] The gate of the second transistor T2 is electrically connected to the N-th stage driving signal output terminal NS(N), and the source of the second transistor T2 is electrically connected to the selection input terminal VCT;

[0218] T1 is a p-type transistor, and T2 is a p-type transistor.

[0219] In at least one embodiment of the present disclosure, the N-1th stage third node N3 (N-1) may be the third node in the N-1th stage driving circuit.

[0220] As shown in FIG10 , the gating circuit may include a first transistor T1 and a second transistor T2 ;

[0221] The gate of the first transistor T1 is electrically connected to the N-th stage driving signal output terminal NS(N), the drain of the first transistor T1 is electrically connected to the first node N1, and the source of the first transistor T1 is electrically connected to the drain of the second transistor T2;

[0222] The gate of the second transistor T2 is electrically connected to the third node N3 (N-1) of the N-1th stage, and the source of the second transistor T2 is electrically connected to the selection input terminal VCT;

[0223] T1 is a p-type transistor, and T2 is a p-type transistor.

[0224] As shown in FIG11 , the gating circuit may include a first transistor T1 and a second transistor T2 ;

[0225] The gate of the first transistor T1 is electrically connected to the first inverted driving signal terminal NGI1, the drain of the first transistor T1 is electrically connected to the first node N1, and the source of the first transistor T1 is electrically connected to the drain of the second transistor T2; the first inverted driving signal provided by the first inverted driving signal terminal NGI1 is inverted to the N-1th level driving signal provided by the N-1th level driving signal output terminal NS(N-1);

[0226] The gate of the second transistor T2 is electrically connected to the N-th stage driving signal output terminal NS(N), and the source of the second transistor T2 is electrically connected to the selection input terminal VCT;

[0227] T1 is a p-type transistor, and T2 is a p-type transistor.

[0228] As shown in FIG12 , the gating circuit may include a first transistor T1 and a second transistor T2 ;

[0229] The gate of the first transistor T1 is electrically connected to the N-th stage driving signal output terminal NS(N), the drain of the first transistor T1 is electrically connected to the first node N1, and the source of the first transistor T1 is electrically connected to the drain of the second transistor T2;

[0230] The gate of the second transistor T2 is electrically connected to the first inverted driving signal terminal NGI1, and the source of the second transistor T2 is electrically connected to the selection input terminal VCT; the first inverted driving signal provided by the first inverted driving signal terminal NGI1 is inversely proportional to the N-1-th level driving signal provided by the N-1-th level driving signal output terminal NS(N-1);

[0231] T1 is a p-type transistor, and T2 is a p-type transistor.

[0232] As shown in FIG13 , the gating circuit may include a first transistor T1 and a second transistor T2 ;

[0233] The gate of the first transistor T1 is electrically connected to the N-1th stage driving signal output terminal NS(N-1), the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the source of the second transistor T2;

[0234] The gate of the second transistor T2 is electrically connected to the second inverted driving signal terminal NGI2, and the drain of the second transistor T2 is electrically connected to the selection input terminal VCT; the second inverted driving signal provided by the second inverted driving signal terminal NGI2 is inverted with the N-th stage driving signal provided by the N-th stage driving signal output terminal NS(N);

[0235] T1 is an n-type transistor, and T2 is an n-type transistor.

[0236] As shown in FIG14 , the gating circuit may include a first transistor T1 and a second transistor T2 ;

[0237] The gate of the first transistor T1 is electrically connected to the second inverted driving signal terminal NGI2, the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the source of the second transistor T2; the second inverted driving signal provided by the second inverted driving signal terminal NGI2 is inverted with the N-stage driving signal provided by the N-stage driving signal output terminal NS(N);

[0238] The gate of the second transistor T2 is electrically connected to the N-1th stage driving signal output terminal NS(N-1), and the drain of the second transistor T2 is electrically connected to the selection input terminal VCT;

[0239] T1 is an n-type transistor, and T2 is an n-type transistor.

[0240] As shown in FIG15 , the N-1th stage driving signal provided by the N-1th stage driving signal output terminal NS(N-1) can be inverted by the first inverter to obtain the first inverted driving signal provided by the first inverted driving signal terminal NGI1;

[0241] The first inverter includes a first inverting control transistor T01 and a second inverting control transistor T02;

[0242] T01 is a p-type transistor, and T02 is an n-type transistor.

[0243] As shown in FIG16 , the N-th level driving signal provided by the N-th level driving signal output terminal NS(N) can be inverted by the second inverter to obtain the second inverted driving signal provided by the second inverted driving signal terminal NGI2;

[0244] The second inverter includes a third inverting control transistor T03 and a fourth inverting control transistor T04;

[0245] T03 is a p-type transistor, and T04 is an n-type transistor.

[0246] Optionally, the output control circuit includes a third transistor, and the voltage control circuit includes a first capacitor;

[0247] The gate of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the first control node, and the second electrode of the third transistor is electrically connected to the second node;

[0248] A first end of the first capacitor is electrically connected to the second node, and a second end of the first capacitor is electrically connected to the first voltage end.

[0249] Optionally, the second node control circuit includes a fourth transistor, and the output circuit includes a fifth transistor, a sixth transistor, a seventh transistor and a second capacitor;

[0250] The gate of the fourth transistor is electrically connected to the first node, the first electrode of the fourth transistor is electrically connected to the first voltage terminal, and the second electrode of the fourth transistor is electrically connected to the second node;

[0251] The gate of the fifth transistor is electrically connected to the second node, the first electrode of the fifth transistor is electrically connected to the first voltage terminal, and the second electrode of the fifth transistor is electrically connected to the output driving terminal;

[0252] The gate of the sixth transistor is electrically connected to the second control node, the first electrode of the sixth transistor is electrically connected to the output driving terminal, and the second electrode of the sixth transistor is electrically connected to the second voltage terminal;

[0253] The gate of the seventh transistor is electrically connected to the first node, the first electrode of the seventh transistor is electrically connected to the output driving terminal, and the second electrode of the seventh transistor is electrically connected to the second voltage terminal;

[0254] A first end of the second capacitor is electrically connected to the second node, and a second end of the second capacitor is electrically connected to the first voltage end.

[0255] The driving circuit according to at least one embodiment of the present disclosure further includes an initialization circuit;

[0256] The initialization circuit is electrically connected to the initial control terminal, the first node and the second voltage terminal respectively, and is used to control the connection between the first node and the second voltage terminal under the control of the initial control signal provided by the initial control terminal.

[0257] In a specific implementation, the driving circuit may further include an initialization circuit, and the initialization circuit is used to control the connection between the first node and the second voltage terminal under the control of an initial control signal.

[0258] In at least one embodiment of the present disclosure, the driving circuit further includes a first node control circuit;

[0259] The first node control circuit is electrically connected to the fourth node, the first node and the second voltage terminal respectively, and is used to control the connection between the first node and the second voltage terminal under the control of the potential of the fourth node.

[0260] In a specific implementation, the driving circuit may further include a first node control circuit; the first node control circuit controls the connection between the first node and the second voltage terminal under the control of the potential of the fourth node.

[0261] As shown in FIG17 , based on the embodiment of the driving circuit shown in FIG1 , the driving circuit may further include an initialization circuit 21 and a first node control circuit 22 ;

[0262] The initialization circuit 21 is electrically connected to the initial control terminal NCX, the first node N1 and the second voltage terminal V2 respectively, and is used to control the connection between the first node N1 and the second voltage terminal V2 under the control of the initial control signal provided by the initial control terminal NCX;

[0263] The first node control circuit 22 is electrically connected to the fourth node N4, the first node N1 and the second voltage terminal V2 respectively, and is used to control the connection between the first node N1 and the second voltage terminal V2 under the control of the potential of the fourth node N4.

[0264] Optionally, the initialization circuit includes an eighth transistor;

[0265] A gate of the eighth transistor is electrically connected to the initial control terminal, a first electrode of the eighth transistor is electrically connected to the first node, and a second electrode of the eighth transistor is electrically connected to the second voltage terminal.

[0266] Optionally, the first node control circuit includes a ninth transistor;

[0267] The gate of the ninth transistor is electrically connected to the fourth node, the first electrode of the ninth transistor is electrically connected to the first node, and the second electrode of the ninth transistor is electrically connected to the second voltage terminal.

[0268] The driving circuit according to at least one embodiment of the present disclosure further includes a voltage maintaining circuit, wherein the voltage maintaining circuit includes a first inverter, a second inverter, and a maintaining control circuit;

[0269] The input terminal of the first inverter is electrically connected to the first node, the output terminal of the first inverter is electrically connected to the fifth node, the input terminal of the second inverter is electrically connected to the fifth node, and the output terminal of the second inverter is electrically connected to the sixth node;

[0270] The first inverter is used to invert the potential of the first node and output the inverted potential of the first node through the output terminal of the first inverter;

[0271] The second inverter is used to invert the potential of its input terminal and output the inverted potential through the output terminal of the second inverter;

[0272] The sustain control circuit is electrically connected to the sustain control terminal, the sixth node and the first node respectively, and is used to control the connection or disconnection between the sixth node and the first node under the control of the sustain control signal provided by the sustain control terminal.

[0273] In a specific implementation, the driving circuit may further include a voltage maintaining circuit, the voltage maintaining circuit including a first inverter, a second inverter, and a maintaining control circuit; the first inverter inverts the potential of the first node; the second inverter inverts the potential of its input terminal; the maintaining control circuit controls the connection between the sixth node and the first node under the control of a maintaining control signal; the maintaining control circuit controls the connection or disconnection between the sixth node and the first node under the control of the maintaining control signal;

[0274] The sustain control circuit may control the sixth node to be disconnected from the first node when the gating circuit controls the gating input signal to be written into the first node, so as not to affect the potential of the first node.

[0275] When the driving circuit described in at least one embodiment of the present disclosure is in operation, by adding a voltage maintenance circuit, the first inverter and the second inverter included in the voltage maintenance circuit can control the output terminal of the second inverter to be connected to the high voltage terminal when the potential of the first node is a high voltage, so that the potential of the output terminal of the second inverter can be higher than the potential of the first node, and can control the output terminal of the second inverter to be connected to the low voltage terminal when the potential of the first node is a low voltage, so that the potential of the output terminal of the second inverter can be lower than the potential of the first node. In addition, the maintenance control circuit included in the voltage maintenance circuit can control the output terminal of the second inverter to be connected to the first node in the N-level drive signal output stage, thereby increasing the absolute value of the potential of the first node, so that the first node can better control the transistor included in the output control circuit, whose gate is electrically connected to the first node.

[0276] As shown in FIG18 , based on at least one embodiment of the driving circuit shown in FIG17 , the driving circuit according to at least one embodiment of the present disclosure may further include a voltage maintaining circuit, wherein the voltage maintaining circuit includes a first inverter F1, a second inverter F2, and a maintaining control circuit W1; the maintaining control terminal includes an N-1th stage driving signal output terminal NS(N-1) and a first clock signal terminal GCK;

[0277] The input terminal of the first inverter F1 is electrically connected to the first node N1, the output terminal of the first inverter F1 is electrically connected to the fifth node N5, the input terminal of the second inverter F2 is electrically connected to the fifth node N5, and the output terminal of the second inverter F2 is electrically connected to the sixth node N6;

[0278] The first inverter F1 is used to invert the potential of the first node N1 and output the inverted potential of the first node N1 through the output terminal of the first inverter F1;

[0279] The second inverter F2 is used to invert the potential of its input terminal and output the inverted potential through the output terminal of the second inverter F2;

[0280] The maintenance control circuit W1 is electrically connected to the N-1th level drive signal output terminal NS(N-1), the first clock signal terminal GCK, the sixth node N6 and the first node N1, respectively, and is used to control the connection or disconnection between the sixth node N6 and the first node N1 under the control of the N-1th level drive signal provided by the N-1th level drive signal output terminal NS(N-1), and to control the connection or disconnection between the sixth node N6 and the first node N1 under the control of the first clock signal provided by the first clock signal terminal GCK.

[0281] In at least one embodiment shown in FIG. 18 , the N−1th stage driving signal output terminal may be replaced by a second clock signal terminal, but the present invention is not limited thereto.

[0282] In at least one embodiment of the present disclosure, the maintenance control terminal includes a first maintenance control terminal and a second maintenance control terminal;

[0283] The sustain control circuit includes a tenth transistor and an eleventh transistor;

[0284] The gate of the tenth transistor is electrically connected to the first sustain control terminal, the first electrode of the tenth transistor is electrically connected to the first node, and the second electrode of the tenth transistor is electrically connected to the sixth node;

[0285] The gate of the eleventh transistor is electrically connected to the second sustain control terminal, the first electrode of the eleventh transistor is electrically connected to the sixth node, and the second electrode of the eleventh transistor is electrically connected to the first node;

[0286] The tenth transistor is a p-type transistor, and the eleventh transistor is an n-type transistor;

[0287] The first sustain control terminal is the N-1th level driving signal terminal, and the second sustain control terminal is the first clock signal terminal; or

[0288] The first sustain control terminal is a second clock signal terminal, and the second sustain control terminal is a first clock signal terminal.

[0289] Optionally, the first inverter includes a twelfth transistor and a thirteenth transistor, and the second inverter includes a fourteenth transistor and a fifteenth transistor;

[0290] The gate of the twelfth transistor is electrically connected to the first node, the first electrode of the twelfth transistor is electrically connected to the first voltage terminal, and the second electrode of the twelfth transistor is electrically connected to the fifth node;

[0291] The gate of the thirteenth transistor is electrically connected to the first node, the first electrode of the thirteenth transistor is electrically connected to the fifth node, and the second electrode of the thirteenth transistor is electrically connected to the second voltage terminal;

[0292] The twelfth transistor is a p-type transistor, and the thirteenth transistor is an n-type transistor;

[0293] The gate of the fourteenth transistor is electrically connected to the fifth node, the first electrode of the fourteenth transistor is electrically connected to the first voltage terminal, and the second electrode of the fourteenth transistor is electrically connected to the sixth node;

[0294] The gate of the fifteenth transistor is electrically connected to the fifth node, the first electrode of the fifteenth transistor is electrically connected to the sixth node, and the second electrode of the fifteenth transistor is electrically connected to the second voltage terminal;

[0295] The fourteenth transistor is a p-type transistor, and the fifteenth transistor is an n-type transistor.

[0296] In at least one embodiment of the present disclosure, the drive signal generating circuit includes a first control node control circuit, a second control node control circuit, a first drive output circuit, and a second drive output circuit;

[0297] The first control node control circuit is used to control the potential of the first control node;

[0298] The second control node control circuit is used to control the potential of the second control node;

[0299] The first drive output circuit is electrically connected to the first control node, the first voltage terminal, and the N-th level drive signal output terminal, respectively, and is used to control the connection between the N-th level drive signal output terminal and the first voltage terminal under the control of the potential of the first control node;

[0300] The second drive output circuit is electrically connected to the second control node, the Nth level drive signal output terminal and the second voltage terminal respectively, and is used to control the connection between the Nth level drive signal output terminal and the second voltage terminal under the control of the potential of the second control node.

[0301] In a specific implementation, the drive signal generating circuit may include a first control node control circuit, a second control node control circuit, a first drive output circuit, and a second drive output circuit; the first control node control circuit controls the potential of the first control node; the second control node control circuit controls the potential of the second control node; the first drive output circuit controls the connection between the N-th level drive signal output terminal and the first voltage terminal under the control of the potential of the first control node; the second drive output circuit controls the connection between the N-th level drive signal output terminal and the second voltage terminal under the control of the potential of the second control node.

[0302] As shown in FIG19 , based on at least one embodiment of the driving circuit shown in FIG17 , the driving signal generating circuit includes a first control node control circuit 31 , a second control node control circuit 32 , a first driving output circuit 33 and a second driving output circuit 34 ;

[0303] The first control node control circuit 31 is electrically connected to the first control node NC1 and is used to control the potential of the first control node NC1;

[0304] The second control node control circuit 32 is electrically connected to the second control node NC2 and is used to control the potential of the second control node NC2;

[0305] The first drive output circuit 33 is electrically connected to the first control node NC1, the first voltage terminal V1, and the N-th stage drive signal output terminal NS(N), respectively, and is used to control the communication between the N-th stage drive signal output terminal NS(N) and the first voltage terminal V1 under the control of the potential of the first control node NC1;

[0306] The second drive output circuit 34 is electrically connected to the second control node NC2, the N-th level drive signal output terminal NS(N) and the second voltage terminal V2, respectively, and is used to control the connection between the N-th level drive signal output terminal NS(N) and the second voltage terminal V2 under the control of the potential of the second control node NC2.

[0307] As shown in FIG20 , based on at least one embodiment of the driving circuit shown in FIG18 , the driving signal generating circuit includes a first control node control circuit 31 , a second control node control circuit 32 , a first driving output circuit 33 and a second driving output circuit 34 ;

[0308] The first control node control circuit 31 is electrically connected to the first control node NC1 and is used to control the potential of the first control node NC1;

[0309] The second control node control circuit 32 is electrically connected to the second control node NC2 and is used to control the potential of the second control node NC2;

[0310] The first drive output circuit 33 is electrically connected to the first control node NC1, the first voltage terminal V1, and the N-th stage drive signal output terminal NS(N), respectively, and is used to control the communication between the N-th stage drive signal output terminal NS(N) and the first voltage terminal V1 under the control of the potential of the first control node NC1;

[0311] The second drive output circuit 34 is electrically connected to the second control node NC2, the N-th level drive signal output terminal NS(N) and the second voltage terminal V2, respectively, and is used to control the connection between the N-th level drive signal output terminal NS(N) and the second voltage terminal V2 under the control of the potential of the second control node NC2.

[0312] In at least one embodiment of the present disclosure, the first control node control circuit includes a seventh node control circuit, an eighth node control circuit, a third node control circuit, and a first control circuit;

[0313] The seventh-node control circuit is electrically connected to the first clock signal terminal, the second voltage terminal, the seventh node, and the ninth node, respectively, and is configured to control communication between the seventh node and the second voltage terminal under the control of the first clock signal provided by the first clock signal terminal, and to control communication between the seventh node and the first clock signal terminal under the control of the potential of the ninth node;

[0314] The eighth node control circuit is electrically connected to the second voltage terminal, the seventh node, and the eighth node, respectively, and is configured to control the seventh node to be connected to the eighth node under the control of the second voltage signal provided by the second voltage terminal;

[0315] The third node control circuit is electrically connected to the eighth node, the second clock signal terminal, and the third node, respectively, and is configured to control the connection between the third node and the second clock signal terminal under the control of the potential of the eighth node, and to control the potential of the third node according to the potential of the eighth node;

[0316] The first control circuit is electrically connected to the second clock signal terminal, the third node, the first control node, the ninth node and the first voltage terminal, respectively, and is used to control the connection between the third node and the first control node under the control of the second clock signal provided by the second clock signal terminal, and to control the connection between the first control node and the first voltage terminal under the control of the potential of the ninth node.

[0317] In a specific implementation, the first control node control circuit may include a seventh node control circuit, an eighth node control circuit, a third node control circuit and a first control circuit; the seventh node control circuit controls the potential of the seventh node; the eighth node control circuit controls the potential of the eighth node; the third node control circuit controls the potential of the third node; and the first control circuit controls the potential of the first control node.

[0318] In at least one embodiment of the present disclosure, the second control node control circuit includes a ninth node control circuit, a tenth node control circuit, a fourth node control circuit, an eleventh node control circuit, and a second control circuit;

[0319] The ninth node control circuit is electrically connected to the first clock signal terminal, the N-1th level drive signal output terminal, the ninth node, the initial control terminal, and the first voltage terminal, respectively, and is configured to control the ninth node to be connected to the N-1th level drive signal terminal under the control of the first clock signal provided by the first clock signal terminal, and to control the ninth node to be connected to the first voltage terminal under the control of the initial control signal provided by the initial control terminal;

[0320] The tenth node control circuit is electrically connected to the first clock signal terminal, the N-1th stage drive signal output terminal, and the tenth node, respectively, and is used to control the connection between the tenth node and the N-1th stage drive signal output terminal under the control of the first clock signal provided by the first clock signal terminal;

[0321] The fourth node control circuit is electrically connected to the first voltage terminal, the seventh node, the fourth node, the eleventh node, and the second clock signal terminal, respectively, and is configured to control the fourth node to be connected to the first voltage terminal under the control of the potential of the seventh node, and to control the fourth node to be connected to the second clock signal terminal under the control of the potential of the eleventh node;

[0322] the eleventh node control circuit being electrically connected to the fourth node, the eleventh node, the second voltage terminal, and the tenth node, respectively, and being configured to control the potential of the eleventh node according to the potential of the fourth node, and to control the communication between the eleventh node and the tenth node under the control of a second voltage signal provided by the second voltage terminal;

[0323] The second control circuit is electrically connected to the eleventh node and the second control node, respectively, and is configured to control the potential of the second control node under the control of the potential of the eleventh node.

[0324] In a specific implementation, the second control node control circuit may include a ninth node control circuit, a tenth node control circuit, a fourth node control circuit, an eleventh node control circuit and a second control circuit; the ninth node control circuit controls the potential of the ninth node; the tenth node control circuit controls the potential of the tenth node; the fourth node control circuit controls the potential of the fourth node; the eleventh node control circuit controls the potential of the eleventh node; and the second control circuit controls the potential of the second control node.

[0325] Optionally, the first voltage end may be a high voltage end, and the second voltage end may be a low voltage end, but the present invention is not limited thereto.

[0326] As shown in FIG21 , based on at least one embodiment of the driving circuit shown in FIG19 , the first control node control circuit includes a seventh node control circuit 41 , an eighth node control circuit 42 , a third node control circuit 43 and a first control circuit 44 ;

[0327] The seventh node control circuit 41 is electrically connected to the first clock signal terminal GCK, the second voltage terminal V2, the seventh node N7, and the ninth node N9, respectively, and is configured to control the seventh node N7 to be connected to the second voltage terminal V2 under the control of the first clock signal provided by the first clock signal terminal GCK, and to control the seventh node N7 to be connected to the first clock signal terminal GCK under the control of the potential of the ninth node N9;

[0328] The eighth node control circuit 42 is electrically connected to the second voltage terminal V2, the seventh node N7, and the eighth node N8, respectively, and is configured to control the seventh node N7 and the eighth node N8 to be connected to each other under the control of the second voltage signal provided by the second voltage terminal V2;

[0329] The third node control circuit 43 is electrically connected to the eighth node N8, the second clock signal terminal GCB, and the third node N3, respectively, and is configured to control the connection between the third node N3 and the second clock signal terminal GCB under the control of the potential of the eighth node N8, and to control the potential of the third node N3 according to the potential of the eighth node N8;

[0330] The first control circuit 44 is electrically connected to the second clock signal terminal GCB, the third node N3, the first control node NC1, the ninth node N9, and the first voltage terminal V1, respectively, and is configured to control the communication between the third node N3 and the first control node NC1 under the control of the second clock signal provided by the second clock signal terminal GCB, and to control the communication between the first control node NC1 and the first voltage terminal V1 under the control of the potential of the ninth node N9;

[0331] The second control node control circuit includes a ninth node control circuit 51, a tenth node control circuit 52, a fourth node control circuit 53, an eleventh node control circuit 54 and a second control circuit 55;

[0332] The ninth node control circuit 51 is electrically connected to the first clock signal terminal GCK, the N-1th stage drive signal output terminal NS(N-1), the ninth node N9, the initial control terminal NCX, and the first voltage terminal V1, respectively, and is configured to control the ninth node N9 to be connected to the N-1th stage drive signal terminal NS(N-1) under the control of the first clock signal provided by the first clock signal terminal GCK, and to control the ninth node N9 to be connected to the first voltage terminal V1 under the control of the initial control signal provided by the initial control terminal NCX.

[0333] The tenth node control circuit 52 is electrically connected to the first clock signal terminal GCK, the N-1th stage drive signal output terminal NS(N-1), and the tenth node N10, respectively, and is used to control the communication between the tenth node N10 and the N-1th stage drive signal output terminal NS(N-1) under the control of the first clock signal provided by the first clock signal terminal GCK;

[0334] The fourth node control circuit 53 is electrically connected to the first voltage terminal V1, the seventh node N7, the fourth node N4, the eleventh node N11, and the second clock signal terminal GCB, respectively, and is configured to control the fourth node N4 to be connected to the first voltage terminal V1 under the control of the potential of the seventh node N7, and to control the fourth node N4 to be connected to the second clock signal terminal GCB under the control of the potential of the eleventh node N11;

[0335] The eleventh node control circuit 54 is electrically connected to the fourth node N4, the eleventh node N11, the second voltage terminal V2, and the tenth node N10, respectively, and is configured to control the potential of the eleventh node N11 according to the potential of the fourth node N4, and control the communication between the eleventh node N11 and the tenth node N10 under the control of the second voltage signal provided by the second voltage terminal V2;

[0336] The second control circuit 55 is electrically connected to the eleventh node N11 and the second control node NC2, respectively, and is configured to control the potential of the second control node NC2 under the control of the potential of the eleventh node N11.

[0337] As shown in FIG22 , based on at least one embodiment of the driving circuit shown in FIG20 , the first control node control circuit includes a seventh node control circuit 41 , an eighth node control circuit 42 , a third node control circuit 43 and a first control circuit 44 ;

[0338] The seventh node control circuit 41 is electrically connected to the first clock signal terminal GCK, the second voltage terminal V2, the seventh node N7, and the ninth node N9, respectively, and is configured to control the seventh node N7 to be connected to the second voltage terminal V2 under the control of the first clock signal provided by the first clock signal terminal GCK, and to control the seventh node N7 to be connected to the first clock signal terminal GCK under the control of the potential of the ninth node N9;

[0339] The eighth node control circuit 42 is electrically connected to the second voltage terminal V2, the seventh node N7, and the eighth node N8, respectively, and is configured to control the seventh node N7 and the eighth node N8 to be connected to each other under the control of the second voltage signal provided by the second voltage terminal V2;

[0340] The third node control circuit 43 is electrically connected to the eighth node N8, the second clock signal terminal GCB, and the third node N3, respectively, and is configured to control the connection between the third node N3 and the second clock signal terminal GCB under the control of the potential of the eighth node N8, and to control the potential of the third node N3 according to the potential of the eighth node N8;

[0341] The first control circuit 44 is electrically connected to the second clock signal terminal GCB, the third node N3, the first control node NC1, the ninth node N9, and the first voltage terminal V1, respectively, and is configured to control the communication between the third node N3 and the first control node NC1 under the control of the second clock signal provided by the second clock signal terminal GCB, and to control the communication between the first control node NC1 and the first voltage terminal V1 under the control of the potential of the ninth node N9;

[0342] The second control node control circuit includes a ninth node control circuit 51, a tenth node control circuit 52, a fourth node control circuit 53, an eleventh node control circuit 54 and a second control circuit 55;

[0343] The ninth node control circuit 51 is electrically connected to the first clock signal terminal GCK, the N-1th stage drive signal output terminal NS(N-1), the ninth node N9, the initial control terminal NCX, and the first voltage terminal V1, respectively, and is configured to control the ninth node N9 to be connected to the N-1th stage drive signal terminal NS(N-1) under the control of the first clock signal provided by the first clock signal terminal GCK, and to control the ninth node N9 to be connected to the first voltage terminal V1 under the control of the initial control signal provided by the initial control terminal NCX.

[0344] The tenth node control circuit 52 is electrically connected to the first clock signal terminal GCK, the N-1th stage drive signal output terminal NS(N-1), and the tenth node N10, respectively, and is used to control the communication between the tenth node N10 and the N-1th stage drive signal output terminal NS(N-1) under the control of the first clock signal provided by the first clock signal terminal GCK;

[0345] The fourth node control circuit 53 is electrically connected to the first voltage terminal V1, the seventh node N7, the fourth node N4, the eleventh node N11, and the second clock signal terminal GCB, respectively, and is configured to control the fourth node N4 to be connected to the first voltage terminal V1 under the control of the potential of the seventh node N7, and to control the fourth node N4 to be connected to the second clock signal terminal GCB under the control of the potential of the eleventh node N11;

[0346] The eleventh node control circuit 54 is electrically connected to the fourth node N4, the eleventh node N11, the second voltage terminal V2, and the tenth node N10, respectively, and is configured to control the potential of the eleventh node N11 according to the potential of the fourth node N4, and control the communication between the eleventh node N11 and the tenth node N10 under the control of the second voltage signal provided by the second voltage terminal V2;

[0347] The second control circuit 55 is electrically connected to the eleventh node N11 and the second control node NC2, respectively, and is configured to control the potential of the second control node NC2 under the control of the potential of the eleventh node N11.

[0348] Optionally, the seventh node control circuit includes a sixteenth transistor and a seventeenth transistor, the eighth node control circuit includes an eighteenth transistor, the third node control circuit includes a nineteenth transistor and a third capacitor, and the first control circuit includes a twentieth transistor and a twenty-first transistor;

[0349] The gate of the sixteenth transistor is electrically connected to the first clock signal terminal, the first electrode of the sixteenth transistor is electrically connected to the second voltage terminal, and the second electrode of the sixteenth transistor is electrically connected to the seventh node;

[0350] The gate of the seventeenth transistor is electrically connected to the ninth node, the first electrode of the seventeenth transistor is electrically connected to the seventh node, and the second electrode of the seventeenth transistor is electrically connected to the first clock signal terminal;

[0351] The gate of the eighteenth transistor is electrically connected to the second voltage terminal, the first electrode of the eighteenth transistor is electrically connected to the seventh node, and the second electrode of the eighteenth transistor is electrically connected to the eighth node;

[0352] The gate of the nineteenth transistor is electrically connected to the eighth node, the first electrode of the nineteenth transistor is electrically connected to the second clock signal terminal, and the second electrode of the nineteenth transistor is electrically connected to the third node;

[0353] A first end of the third capacitor is electrically connected to the eighth node, and a second end of the third capacitor is electrically connected to the third node;

[0354] The gate of the twentieth transistor is electrically connected to the second clock signal terminal, the first electrode of the twentieth transistor is electrically connected to the third node, and the second electrode of the twentieth transistor is electrically connected to the first control node;

[0355] A gate of the twenty-first transistor is electrically connected to the ninth node, a first electrode of the twenty-first transistor is electrically connected to the first control node, and a second electrode of the twenty-first transistor is electrically connected to the first voltage terminal.

[0356] Optionally, the ninth node control circuit includes a twenty-second transistor and a twenty-third transistor, the tenth node control circuit includes a twenty-fourth transistor, the fourth node control circuit includes a twenty-fifth transistor and a twenty-sixth transistor, the eleventh node control circuit includes a twenty-seventh transistor and a fourth capacitor, and the second control circuit includes a twenty-eighth transistor and a twenty-ninth transistor;

[0357] a gate of the twenty-second transistor electrically connected to the first clock signal terminal, a first electrode of the twenty-second transistor electrically connected to the (N-1)th stage driving signal output terminal, and a second electrode of the twenty-second transistor electrically connected to the ninth node;

[0358] The gate of the twenty-third transistor is electrically connected to the initial control terminal, the first electrode of the twenty-third transistor is electrically connected to the first voltage terminal, and the second electrode of the twenty-third transistor is electrically connected to the ninth node;

[0359] a gate of the twenty-fourth transistor is electrically connected to the first clock signal terminal, a first electrode of the twenty-fourth transistor is electrically connected to the (N-1)th stage driving signal output terminal, and a second electrode of the twenty-fourth transistor is electrically connected to the tenth node;

[0360] a gate of the twenty-fifth transistor is electrically connected to the seventh node, a first electrode of the twenty-fifth transistor is electrically connected to the first voltage terminal, and a second electrode of the twenty-fifth transistor is electrically connected to the fourth node;

[0361] a gate of the twenty-sixth transistor is electrically connected to the eleventh node, a first electrode of the twenty-sixth transistor is electrically connected to the fourth node, and a second electrode of the twenty-sixth transistor is electrically connected to the second clock signal terminal;

[0362] A gate of the twenty-seventh transistor is electrically connected to the second voltage terminal, a first electrode of the twenty-seventh transistor is electrically connected to the tenth node, and a second electrode of the twenty-seventh transistor is electrically connected to the eleventh node;

[0363] The first end of the fourth capacitor is electrically connected to the fourth node, and the second end of the fourth capacitor is electrically connected to the eleventh node;

[0364] a gate of the twenty-eighth transistor is electrically connected to the eleventh node, a first electrode of the twenty-eighth transistor is electrically connected to the second control node, and a second electrode of the twenty-eighth transistor is electrically connected to the eleventh node;

[0365] A gate of the twenty-ninth transistor is electrically connected to the second voltage terminal, a first electrode of the twenty-ninth transistor is electrically connected to the ninth node, and a second electrode of the twenty-ninth transistor is electrically connected to the second control node.

[0366] Optionally, the first drive output circuit includes a 30th transistor and a fifth capacitor, and the second drive output circuit includes a 31st transistor and a sixth capacitor;

[0367] The gate of the 30th transistor is electrically connected to the first control node, the first electrode of the 30th transistor is electrically connected to the first voltage terminal, and the second electrode of the 30th transistor is electrically connected to the Nth stage driving signal output terminal;

[0368] A first terminal of the fifth capacitor is electrically connected to the first control node, and a second terminal of the fifth capacitor is electrically connected to the first voltage terminal;

[0369] The gate of the thirty-first transistor is electrically connected to the second control node, the first electrode of the thirty-first transistor is electrically connected to the N-th stage driving signal output terminal, and the second electrode of the thirty-first transistor is electrically connected to the second voltage terminal;

[0370] A first end of the sixth capacitor is electrically connected to the Nth stage driving signal output terminal, and a second end of the sixth capacitor is electrically connected to the second voltage terminal.

[0371] As shown in FIG23 , based on at least one embodiment of the driving circuit shown in FIG21 , the gating circuit may include a first transistor T1 and a second transistor T2 ;

[0372] The gate of the first transistor T1 is electrically connected to the N-th stage driving signal output terminal NS(N), the drain of the first transistor T1 is electrically connected to the first node N1, and the source of the first transistor T1 is electrically connected to the drain of the second transistor T2;

[0373] The gate of the second transistor T2 is electrically connected to the third node N3 (N-1) of the N-1th stage, and the source of the second transistor T2 is electrically connected to the selection input terminal VCT;

[0374] The output control circuit includes a third transistor T3, and the voltage control circuit includes a first capacitor C1;

[0375] The gate of the third transistor T3 is electrically connected to the first node N1, the source of the third transistor T3 is electrically connected to the first control node NC1, and the drain of the third transistor T3 is electrically connected to the second node N2;

[0376] A first end of the first capacitor C1 is electrically connected to the second node N2, and a second end of the first capacitor C1 is electrically connected to the high voltage terminal VGH;

[0377] The second node control circuit includes a fourth transistor T4, and the output circuit includes a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and a second capacitor C2;

[0378] The gate of the fourth transistor T4 is electrically connected to the first node N1, the source of the fourth transistor T4 is electrically connected to the high voltage terminal VGH, and the drain of the fourth transistor T4 is electrically connected to the second node N2;

[0379] The gate of the fifth transistor T5 is electrically connected to the second node N2, the source of the fifth transistor T5 is electrically connected to the high voltage terminal VGH, and the drain of the fifth transistor T5 is electrically connected to the output driving terminal NO (N);

[0380] The gate of the sixth transistor T6 is electrically connected to the second control node NC2, the source of the sixth transistor T6 is electrically connected to the output driving terminal NO(N), and the drain of the sixth transistor T6 is electrically connected to the low voltage terminal VGL;

[0381] The gate of the seventh transistor T7 is electrically connected to the first node N1, the source of the seventh transistor T7 is electrically connected to the output driving terminal NO(N), and the drain of the seventh transistor T7 is electrically connected to the low voltage terminal VGL;

[0382] A first end of the second capacitor C2 is electrically connected to the second node N2, and a second end of the second capacitor C2 is electrically connected to the high voltage terminal VGH;

[0383] The initialization circuit includes an eighth transistor T8;

[0384] The gate of the eighth transistor T8 is electrically connected to the initial control terminal NCX, the source of the eighth transistor T8 is electrically connected to the first node N1, and the drain of the eighth transistor T8 is electrically connected to the low voltage terminal VGL;

[0385] The first node control circuit includes a ninth transistor T9;

[0386] The gate of the ninth transistor T9 is electrically connected to the fourth node N4, the source of the ninth transistor T9 is electrically connected to the first node N1, and the drain of the ninth transistor T9 is electrically connected to the low voltage terminal VGL;

[0387] The seventh node control circuit includes a sixteenth transistor T16 and a seventeenth transistor T17, the eighth node control circuit includes an eighteenth transistor T18, the third node control circuit includes a nineteenth transistor T19 and a third capacitor C3, and the first control circuit includes a twentieth transistor T20 and a twenty-first transistor T21;

[0388] The gate of the sixteenth transistor T16 is electrically connected to the first clock signal terminal GCK, the source of the sixteenth transistor T16 is electrically connected to the low voltage terminal VGL, and the drain of the sixteenth transistor T16 is electrically connected to the seventh node N7;

[0389] The gate of the seventeenth transistor T17 is electrically connected to the ninth node N9, the source of the seventeenth transistor T17 is electrically connected to the seventh node N7, and the drain of the seventeenth transistor T17 is electrically connected to the first clock signal terminal GCK;

[0390] The gate of the eighteenth transistor T18 is electrically connected to the low voltage terminal VGL, the source of the eighteenth transistor T18 is electrically connected to the seventh node N7, and the drain of the eighteenth transistor T18 is electrically connected to the eighth node N8;

[0391] The gate of the nineteenth transistor T19 is electrically connected to the eighth node N8, the source of the nineteenth transistor T19 is electrically connected to the second clock signal terminal GCB, and the drain of the nineteenth transistor T19 is electrically connected to the third node N3;

[0392] A first end of the third capacitor C3 is electrically connected to the eighth node N8, and a second end of the third capacitor C3 is electrically connected to the third node N3;

[0393] The gate of the twentieth transistor T20 is electrically connected to the second clock signal terminal GCB, the source of the twentieth transistor T20 is electrically connected to the third node N3, and the drain of the twentieth transistor T20 is electrically connected to the first control node NC1;

[0394] A gate of the twenty-first transistor T21 is electrically connected to the ninth node N9, a source of the twenty-first transistor T21 is electrically connected to the first control node NC1, and a drain of the twenty-first transistor T21 is electrically connected to the high voltage terminal VGH;

[0395] The ninth node control circuit includes a twenty-second transistor T22 and a twenty-third transistor T23, the tenth node control circuit includes a twenty-fourth transistor T24, the fourth node control circuit includes a twenty-fifth transistor T25 and a twenty-sixth transistor T26, the eleventh node control circuit includes a twenty-seventh transistor T27 and a fourth capacitor C4, and the second control circuit includes a twenty-eighth transistor T28 and a twenty-ninth transistor T29;

[0396] The gate of the 22nd transistor T22 is electrically connected to the first clock signal terminal GCK, the source of the 22nd transistor T22 is electrically connected to the N-1th stage driving signal output terminal NS(N-1), and the drain of the 22nd transistor T22 is electrically connected to the ninth node N9;

[0397] A gate of the twenty-third transistor T23 is electrically connected to the initial control terminal NCX, a source of the twenty-third transistor T23 is electrically connected to the high voltage terminal VGH, and a drain of the twenty-third transistor T23 is electrically connected to the ninth node N9;

[0398] The gate of the twenty-fourth transistor T24 is electrically connected to the first clock signal terminal GCK, the source of the twenty-fourth transistor T24 is electrically connected to the N-1th stage driving signal output terminal NS(N-1), and the drain of the twenty-fourth transistor T24 is electrically connected to the tenth node N10;

[0399] A gate of the twenty-fifth transistor T25 is electrically connected to the seventh node N7, a source of the twenty-fifth transistor T25 is electrically connected to the high voltage terminal VGH, and a drain of the twenty-fifth transistor T25 is electrically connected to the fourth node N4;

[0400] A gate of the twenty-sixth transistor T26 is electrically connected to the eleventh node N11, a source of the twenty-sixth transistor T26 is electrically connected to the fourth node N4, and a drain of the twenty-sixth transistor T26 is electrically connected to the second clock signal terminal GCB;

[0401] The gate of the twenty-seventh transistor T27 is electrically connected to the low voltage terminal VGL, the source of the twenty-seventh transistor T27 is electrically connected to the tenth node N10, and the drain of the twenty-seventh transistor T27 is electrically connected to the eleventh node N11;

[0402] A first end of the fourth capacitor C4 is electrically connected to the fourth node N4, and a second end of the fourth capacitor C4 is electrically connected to the eleventh node N11;

[0403] A gate of the twenty-eighth transistor T28 is electrically connected to the eleventh node N11, a source of the twenty-eighth transistor T28 is electrically connected to the second control node NC2, and a drain of the twenty-eighth transistor T28 is electrically connected to the eleventh node N11;

[0404] A gate of the twenty-ninth transistor T29 is electrically connected to the low voltage terminal VGL, a source of the twenty-ninth transistor T29 is electrically connected to the ninth node N9, and a drain of the twenty-ninth transistor T29 is electrically connected to the second control node NC2;

[0405] The first driving output circuit includes a 30th transistor T30 and a fifth capacitor C5, and the second driving output circuit includes a 31st transistor T31 and a sixth capacitor C6;

[0406] The gate of the 30th transistor T30 is electrically connected to the first control node NC1, the source of the 30th transistor T30 is electrically connected to the high voltage terminal VGH, and the drain of the 30th transistor T30 is electrically connected to the N-th stage driving signal output terminal NS(N-1);

[0407] A first end of the fifth capacitor C5 is electrically connected to the first control node NC1, and a second end of the fifth capacitor C5 is electrically connected to the high voltage terminal VGH;

[0408] The gate of the thirty-first transistor T31 is electrically connected to the second control node NC2, the source of the thirty-first transistor T31 is electrically connected to the N-th stage driving signal output terminal NS(N), and the drain of the thirty-first transistor T31 is electrically connected to the low voltage terminal VGL;

[0409] A first end of the sixth capacitor C6 is electrically connected to the Nth stage driving signal output terminal NS(N), and a second end of the sixth capacitor C6 is electrically connected to the low voltage terminal VGL.

[0410] In at least one embodiment of the driving circuit shown in Figure 23, T1 and T2 are p-type transistors, T3 is a p-type transistor, T4 is an n-type transistor, T5 is a p-type transistor, T6 is a p-type transistor, T7 is an n-type transistor, T8 and T9 are p-type transistors, and T16-T31 are p-type transistors.

[0411] In at least one embodiment of the driving circuit shown in FIG. 23 , the first voltage end is a high voltage end, and the second voltage end is a low voltage end, but the present invention is not limited thereto.

[0412] In at least one embodiment of the driving circuit shown in FIG. 23 , N12 is the twelfth node.

[0413] In at least one embodiment of the present disclosure, the structure of the drive signal generating circuit is not limited to that shown in FIG. 23 . The drive signal generating circuit may be, for example, a 16T3C circuit, a 13T3C circuit, a 12T3C circuit, a 10T3C circuit, etc., but is not limited thereto.

[0414] At least one embodiment of the driving circuit shown in FIG. 23 of the present disclosure is in operation.

[0415] In the first stage, NS(N-1) outputs a low voltage signal, GCK outputs a low voltage signal, and GCB provides a high voltage signal. T22 and T24 are turned on, the potentials of N9 and N11 are low voltage, T29 and T27 are turned on, ensuring that the potentials of NC2 and N11 are low voltage, T31 is turned on, NS(N) outputs a low voltage signal; the potential of N11 is low voltage to ensure that T28 is turned on, the potential of N9 is low voltage to turn on T17, T16 is turned on, T18 is turned on, the potentials of N7 and N8 are pulled low, T19 is turned on, GCB writes a high voltage signal to N3, the potential of N9 is low voltage to turn on T21, the potential of NC1 is pulled high voltage, and T30 is turned off;

[0416] In the second stage, NS(N-1) outputs a low voltage signal, the potential of the first clock signal output by GCK jumps from a low voltage to a high voltage, T22 and T24 are turned off, the potential of N9 is a low voltage, T17 is turned on, T16 is turned off, T18 is turned on, the potentials of N7 and N8 are high voltages, T19 is turned off, the potential of N3 is maintained at a high voltage, GCB outputs a low voltage signal, T20 is turned on, the potential of NC1 is maintained at a high voltage, and T30 is turned off; at the same time, the potential of N11 is maintained at a low voltage, T28 is turned on, GCB writes the low voltage signal to N4, and the potential of N11 is pulled down to a lower voltage (5V to 10V lower than the voltage value of the low voltage signal provided by GCB) through C4, T28 is turned on, and the low voltage signal is written to NC2 (the potential of NC2 is 3V to 8V lower than the voltage value of the low voltage signal provided by GCB), and T31 is fully turned on to ensure that NS(N) outputs a low voltage signal;

[0417] In the third stage, NS(N-1) outputs a high voltage signal, GCK outputs a low voltage signal, GCB outputs a high voltage signal, T22 and T24 are turned on, controlling the potential of N9 and the potential of N11 to be high voltage, T29 and T27 are turned on, the potential of NC2 and the potential of N11 are high voltage, and T31 is turned off; the potential of N11 is high voltage, T26 is turned off, the potential of N9 is high voltage, T17 is turned off, T16 is turned on, T18 is turned on, pulling the potential of N7 and the potential of N8 down, T19 is turned on, GCB writes a high voltage signal to N3, T20 is turned off, the potential of N9 is high voltage, T21 is turned off, the potential of NC1 is maintained at a high voltage, and T30 is ensured to be turned off;

[0418] In the fourth stage, NS(N-1) outputs a high voltage signal, the potential of the first clock signal output by GCK jumps from a low voltage to a high voltage, GCB outputs a low voltage signal, T22 and T24 are turned off, the potential of N9 is high, T17 is turned off, T16 is turned off, T18 is turned on, the potentials of N7 and N8 remain low, T19 is turned on, T20 is turned on, the potentials of N3 and NC1 are low, T30 is turned on, and NS(N) outputs a high voltage signal; at the same time, the potential of N11 is high, T26 is turned off, the potential of N4 remains unchanged, and the potential of N11 is ensured to be high voltage;

[0419] In the fifth stage, the potential of the N-1th level driving signal output by NS(N-1) jumps from high voltage to low voltage, GCK outputs a high voltage signal, GCB outputs a low voltage signal, T22 and T24 are turned off, the potentials of N9 and N11 remain high voltage, and the potentials of other nodes remain unchanged, ensuring that NS(N) outputs a high voltage signal;

[0420] In the sixth stage, NS(N-1) outputs a low voltage signal, the potential of the first clock signal output by GCK jumps from high voltage to low voltage, GCB outputs a high voltage signal, T22 and T24 are turned on, the potential of N9 and the potential of N11 are low voltage, T29 and T27 are turned on, ensuring that the potential of NC2 and the potential of N11 are low voltage, T31 is turned on, NS(N) inputs a low voltage signal; the potential of N11 is low voltage, ensuring that T26 is turned on, the potential of N9 is low voltage, T17 is turned on, T16 is turned on, T18 is turned on, the potential of N7 and the potential of N8 are pulled low, T19 is turned on, GCB writes a high voltage signal to N3, the potential of N9 is low voltage, T21 is turned on, the potential of NC1 is pulled up to a high voltage, and T30 is ensured to be closed.

[0421] Optionally, when the display starts (that is, when the display device is turned on), in order to prevent the display screen from flickering when it is turned on, in the power-on stage before the first stage, NCX outputs a low voltage signal, T8 is turned on, the potential of N1 is low voltage, and T3 is turned on; T23 is turned on, the potential of N9 is high voltage, and T17 is turned off. When GCK outputs a low voltage signal, T16 is turned on, so that the potential of N7 is low voltage, T18 is turned on, and the potential of N8 is low voltage. When GCB outputs a low voltage signal, T20 is turned on, the potential of NC1 is low voltage, T30 is turned on, and NS (N) outputs a high voltage signal. Since T3 is turned on, NC1 is connected to N2, the potential of N2 is low voltage, T5 is turned on, and NO (N) outputs a high voltage signal. The second display control transistor M2 included in all pixel circuits in the effective display area can be turned on to clear the residual charge in the storage capacitor Cst, thereby improving the problem of flickering when the display screen is turned on.

[0422] Afterwards, when both NS(N) and N3(N-1) output low voltage signals, T1 and T2 are turned on to control the connection between VCT and N1;

[0423] When VCT provides a low voltage signal, the potential of N1 is low, and C1 maintains the potential of N1; T3 is turned on to control the connection between NC1 and N2. At this time, the potential of NC1 is high, the potential of N2 is high, T5 is turned off, the potential of NC2 is low, T6 is turned on, and NO (N) outputs a low voltage signal;

[0424] When VCT provides a high voltage signal, the potential of N1 is high, T3 is turned off, NC1 and N2 are disconnected, C1 controls the potential of N2 to be high, T5 is turned off, the potential of NC2 is low, T6 is turned on, and NO(N) outputs a low voltage signal; T4 is turned on to ensure that the potential of N2 is high and T5 is turned off; T7 is turned on to ensure that NO(N) outputs a low voltage signal;

[0425] Afterwards, in the Nth stage driving signal providing phase, NS(N) outputs a high voltage signal. At this time, the potential of NC1 is a low voltage and the potential of NC2 is a high voltage.

[0426] When the potential of N1 is low, T3 is turned on, NC1 is connected to N2, the potential of N2 is low, T5 is turned on, and NO(N) outputs a high voltage signal;

[0427] When the potential of N1 is high voltage, T3 is turned off, NC1 and N2 are disconnected, the potential of N2 is high voltage, the potential of NC2 is high voltage, and NO(N) maintains the output of low voltage signal; T4 is turned on to ensure that the potential of N2 is high voltage and T5 is turned off; T7 is turned on to ensure that NO(N) outputs low voltage signal;

[0428] After the Nth level driving signal providing stage, when the potential of N4 is low voltage, T9 is turned on to control the connection between N1 and VGL, the potential of N1 is low voltage, T3 is turned on to control the connection between NC1 and N2, at this time, the potential of NC1 is high voltage, the potential of NC2 is low voltage, the potential of N2 is high voltage, T5 is turned off, T6 is turned on, and NO(N) outputs a low voltage signal.

[0429] When at least one embodiment of the driving circuit shown in Figure 23 of the present disclosure is in operation, when N3(N-1) outputs a low voltage signal and NS(N) outputs a low voltage signal, T1 and T2 are turned on. By simultaneously selecting the above two signals, the selection input signal state within a high-low frequency switching cycle can be obtained.

[0430] FIG24 is a simulation operation timing diagram of at least one embodiment of the driving circuit shown in FIG23 of the present disclosure;

[0431] FIG. 25 is a simulation operation timing diagram of at least one embodiment of the driving circuit shown in FIG. 23 of the present disclosure.

[0432] The difference between at least one embodiment of the driving circuit shown in FIG. 26 of the present disclosure and at least one embodiment of the driving circuit shown in FIG. 23 of the present disclosure is as follows: T9 is not provided.

[0433] FIG. 27 is a simulation operation timing diagram of at least one embodiment of the driving circuit shown in FIG. 26 of the present disclosure.

[0434] The difference between at least one embodiment of the driving circuit shown in FIG. 28 of the present disclosure and at least one embodiment of the driving circuit shown in FIG. 26 of the present disclosure is as follows: a voltage maintaining circuit is added; T1 is an n-type transistor, the gate of T1 is electrically connected to the N-1th stage driving signal output terminal NS(N-1), and the gate of T2 is electrically connected to the Nth stage driving signal output terminal NS(N);

[0435] The voltage maintaining circuit includes a first inverter, a second inverter and a maintaining control circuit;

[0436] The sustain control circuit includes a tenth transistor T10 and an eleventh transistor T11;

[0437] The gate of the tenth transistor T10 is electrically connected to the N-1th stage driving signal output terminal NS(N-1), the source of the tenth transistor T10 is electrically connected to the first node N1, and the drain of the tenth transistor T10 is electrically connected to the sixth node N6;

[0438] The gate of the eleventh transistor T11 is electrically connected to the first clock signal terminal GCK, the source of the eleventh transistor T11 is electrically connected to the sixth node N6, and the drain of the eleventh transistor T11 is electrically connected to the first node N1;

[0439] The tenth transistor T10 is a p-type transistor, and the eleventh transistor T11 is an n-type transistor;

[0440] The first inverter includes a twelfth transistor T12 and a thirteenth transistor T13, and the second inverter includes a fourteenth transistor T14 and a fifteenth transistor T15;

[0441] The gate of the twelfth transistor T12 is electrically connected to the first node N1, the source of the twelfth transistor T12 is electrically connected to the high voltage terminal VGH, and the drain of the twelfth transistor T12 is electrically connected to the fifth node N5;

[0442] The gate of the thirteenth transistor T13 is electrically connected to the first node N1, the source of the thirteenth transistor T13 is electrically connected to the fifth node N5, and the drain of the thirteenth transistor T13 is electrically connected to the low voltage terminal VGL;

[0443] The twelfth transistor T12 is a p-type transistor, and the thirteenth transistor T13 is an n-type transistor;

[0444] The gate of the fourteenth transistor T14 is electrically connected to the fifth node N5, the source of the fourteenth transistor T14 is electrically connected to the high voltage terminal VGH, and the drain of the fourteenth transistor T14 is electrically connected to the sixth node N6;

[0445] The gate of the fifteenth transistor T15 is electrically connected to the fifth node N5, the source of the fifteenth transistor T15 is electrically connected to the sixth node N6, and the drain of the fifteenth transistor T15 is electrically connected to the low voltage terminal VGL;

[0446] The fourteenth transistor T14 is a p-type transistor, and the fifteenth transistor T15 is an n-type transistor.

[0447] In at least one embodiment of the driving circuit shown in FIG. 28 of the present disclosure, the first maintenance control terminal is the N-1th level driving signal terminal, and the second maintenance control terminal is the first clock signal terminal.

[0448] In at least one embodiment of the driving circuit shown in FIG28 of the present disclosure, since the p-type transistor has a threshold voltage loss when transmitting a low voltage and the n-type transistor has a threshold voltage loss when transmitting a high voltage, the absolute value of the potential of N1 will be lower. The absolute value of the potential of N1 can be controlled to increase by the first inverter, the second inverter and the voltage maintenance circuit, so as to better control the corresponding transistors in the output circuit to be turned on or off. The maintenance control circuit controls the disconnection between N1 and N6 when T1 and T2 are turned on so as not to affect the writing of the potential of N1.

[0449] When at least one embodiment of the driving circuit shown in FIG. 28 of the present disclosure is in operation, when NS(N-1) provides a low voltage signal, N1 and N6 are connected; when GCK provides a high voltage signal, N1 and N6 are connected.

[0450] FIG. 29 is a simulation operation timing diagram of at least one embodiment of the driving circuit shown in FIG. 28 of the present disclosure.

[0451] The driving method described in the embodiment of the present disclosure uses the above-mentioned driving circuit, and the driving method includes:

[0452] The driving signal generating circuit generates an N-th level driving signal under the control of the potential of the first control node and the potential of the second control node and outputs the N-th level driving signal through the N-th level driving signal output terminal; N is a positive integer;

[0453] The output control circuit controls the connection between the first control node and the second node under the control of the potential of the first node;

[0454] The gating circuit controls the gating input signal to be written into the first node under the control of the gating control signal;

[0455] The voltage control circuit controls the potential of the second node according to the potential of the first node;

[0456] The second node control circuit controls the connection between the second node and the first voltage terminal under the control of the potential of the first node;

[0457] The output circuit controls the output drive terminal to be connected to the first voltage terminal under the control of the potential of the second node. The output circuit controls the output drive terminal to be connected to the second voltage terminal under the control of the potential of the second control node. The output circuit controls the output drive terminal to be connected to the second voltage terminal under the control of the potential of the first node.

[0458] The driving module described in the embodiment of the present disclosure includes multiple stages of the above-mentioned driving circuits;

[0459] The Nth stage driving circuit is electrically connected to the driving signal output terminal of the N-1th stage driving circuit; N is a positive integer.

[0460] As shown in FIG30 , the first-stage driving circuit is labeled S1, the second-stage driving circuit is labeled S2, the third-stage driving circuit is labeled S3, the fourth-stage driving circuit is labeled S4, the fifth-stage driving circuit is labeled S5, the sixth-stage driving circuit is labeled S6, the seventh-stage driving circuit is labeled S7, the eighth-stage driving circuit is labeled S8, the ninth-stage driving circuit is labeled S9, the tenth-stage driving circuit is labeled S10, the eleventh-stage driving circuit is labeled S11, and the twelfth-stage driving circuit is labeled S12.

[0461] The terminal labeled NS(1) is the drive signal output terminal of S1, and the terminal labeled NO(1) is the output drive terminal of S1;

[0462] The terminal labeled NS(2) is the drive signal output terminal of S2, and the terminal labeled NO(2) is the output drive terminal of S2; S2 is electrically connected to NS(1);

[0463] The terminal labeled NS (3) is the drive signal output terminal of S3, and the terminal labeled NO (3) is the output drive terminal of S3; S3 is electrically connected to NS (2);

[0464] The terminal labeled NS (4) is the drive signal output terminal of S4, and the terminal labeled NO (4) is the output drive terminal of S4; S4 is electrically connected to NS (3);

[0465] The terminal labeled NS (5) is the drive signal output terminal of S5, and the terminal labeled NO (5) is the output drive terminal of S5; S5 is electrically connected to NS (4);

[0466] The terminal labeled NS (6) is the drive signal output terminal of S6, and the terminal labeled NO (6) is the output drive terminal of S6; S6 is electrically connected to NS (5);

[0467] The terminal labeled NS (7) is the drive signal output terminal of S7, and the terminal labeled NO (7) is the output drive terminal of S7; S7 is electrically connected to NS (6);

[0468] The terminal labeled NS (8) is the drive signal output terminal of S8, and the terminal labeled NO (8) is the output drive terminal of S8; S8 is electrically connected to NS (7);

[0469] The terminal labeled NS (9) is the drive signal output terminal of S9, and the terminal labeled NO (9) is the output drive terminal of S9; S9 is electrically connected to NS (8);

[0470] The terminal labeled NS (10) is the drive signal output terminal of S10, and the terminal labeled NO (10) is the output drive terminal of S10; S10 is electrically connected to NS (9);

[0471] The terminal labeled NS (11) is the drive signal output terminal of S11, and the terminal labeled NO (11) is the output drive terminal of S11; S11 is electrically connected to NS (10);

[0472] The terminal labeled NS (12) is the drive signal output terminal of S12, and the terminal labeled NO (12) is the output drive terminal of S12; S12 is electrically connected to NS (11);

[0473] S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11 and S12 are all electrically connected to the selection input terminal VCT;

[0474] S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11 and S12 are all electrically connected to the first clock signal terminal GCK;

[0475] S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11 and S12 are all electrically connected to the second clock signal terminal GCB.

[0476] In FIG30 , the terminal labeled STV is the starting voltage terminal, and S1 is electrically connected to STV.

[0477] FIG. 31 is a timing diagram illustrating the operation of at least one embodiment of the driving module shown in FIG. 30 .

[0478] In at least one embodiment of the driving module shown in FIG. 25 of the present disclosure, when NS(N-1) outputs a high voltage signal and NS(N) outputs a low voltage signal, if VCT outputs a low voltage signal, then when NS(N) outputs a high voltage signal, NO(N) outputs a high voltage signal;

[0479] When NS(N-1) outputs a high voltage signal and NS(N) outputs a low voltage signal, if VCT outputs a high voltage signal, then when NS(N) outputs a high voltage signal, NO(N) outputs a low voltage signal.

[0480] FIG32 is a waveform diagram of a first clock signal provided by GCK and a second clock signal provided by GCB.

[0481] The display device described in the embodiment of the present disclosure includes the above-mentioned driving module.

[0482] The display device provided in the embodiments of the present disclosure may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or the like.

[0483] The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

Claims

1. A driving circuit comprising a driving signal generating circuit, an output control circuit, a gating circuit, a voltage control circuit, a second node control circuit, and an output circuit; The drive signal generating circuit is electrically connected to the first control node, the second control node and the N-th level drive signal output terminal, respectively, and is configured to generate an N-th level drive signal under the control of the potential of the first control node and the potential of the second control node and output the N-th level drive signal through the N-th level drive signal output terminal; N is a positive integer; The output control circuit is electrically connected to the first node, the first control node, and the second node, respectively, and is configured to control the connection between the first control node and the second node under the control of the potential of the first node; The gating circuit is electrically connected to the first node, the gating input terminal and the gating control terminal respectively, and is used to control the gating input signal provided by the gating input terminal to be written into the first node under the control of the gating control signal provided by the gating control terminal; The voltage control circuit is electrically connected to the first node and the second node respectively, and is used to control the potential of the second node according to the potential of the first node; The second node control circuit is electrically connected to the first node, the second node and the first voltage terminal respectively, and is used to control the connection between the second node and the first voltage terminal under the control of the potential of the first node; The output circuit is electrically connected to the second node, the second control node, the first node and the first voltage terminal, the second voltage terminal and the output driver terminal, respectively, and is used to control the connection between the output driver terminal and the first voltage terminal under the control of the potential of the second node, control the connection between the output driver terminal and the second voltage terminal under the control of the potential of the second control node, and control the connection between the output driver terminal and the second voltage terminal under the control of the potential of the first node.

2. The driving circuit according to claim 1, wherein: The gating circuit is used to control the writing of the gating input signal provided by the gating input terminal into the first node when the potential of the third node of the N-1th stage is the second voltage and the potential of the Nth stage driving signal is the second voltage.

3. The driving circuit according to claim 1, wherein: The gating circuit includes a first transistor; a gate of the first transistor is electrically connected to the gating control terminal, a first electrode of the first transistor is electrically connected to the first node, and a second electrode of the first transistor is electrically connected to the gating input terminal.

4. The driving circuit according to claim 1, wherein: The gating control terminal includes a first gating control terminal and a second gating control terminal; the gating circuit includes a first transistor and a second transistor; The gate of the first transistor is electrically connected to the first selection control terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the first electrode of the second transistor; The gate of the second transistor is electrically connected to the second gate control terminal, and the second electrode of the second transistor is electrically connected to the gate input terminal; The first gating control terminal is the Nth stage driving signal output terminal, the second gating control terminal is the N-1th stage third node, and the first transistor and the second transistor are both p-type transistors; or The first gating control terminal is the third node of the N-1th stage, the second gating control terminal is the driving signal output terminal of the Nth stage, and the first transistor and the second transistor are both p-type transistors; or The first strobe control terminal is an N-1th level drive signal output terminal, the second strobe control terminal is an Nth level drive signal output terminal, the first transistor is an n-type transistor, and the second transistor is a p-type transistor; or The first gating control terminal is an N-th level driving signal output terminal, the second gating control terminal is an N-1-th level driving signal output terminal, the first transistor is a p-type transistor, and the second transistor is an n-type transistor; or, The first strobe control terminal is connected to the inverted signal of the N-1th level drive signal, the second strobe control terminal is the output terminal of the Nth level drive signal, and the first transistor and the second transistor are both p-type transistors; or The first gate control terminal is an output terminal of the Nth level driving signal, and the second gate control terminal is connected to the inverted signal of the N-1th level driving signal; the first transistor and the second transistor are both p-type transistors; or, The first gating control terminal is an N-1th level driving signal terminal, the second gating control terminal is connected to an inverted signal of the Nth level driving signal, and the first transistor and the second transistor are both n-type transistors; or, The first strobe control terminal is connected to the inverted signal of the Nth level driving signal, the second strobe control terminal is the N-1th level driving signal terminal, and the first transistor and the second transistor are both n-type transistors.

5. The driving circuit according to any one of claims 1 to 4, wherein: The output control circuit includes a third transistor, and the voltage control circuit includes a first capacitor; The gate of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the first control node, and the second electrode of the third transistor is electrically connected to the second node; A first end of the first capacitor is electrically connected to the second node, and a second end of the first capacitor is electrically connected to the first voltage end.

6. The driving circuit according to any one of claims 1 to 4, wherein: The second node control circuit includes a fourth transistor, and the output circuit includes a fifth transistor, a sixth transistor, a seventh transistor and a second capacitor; The gate of the fourth transistor is electrically connected to the first node, the first electrode of the fourth transistor is electrically connected to the first voltage terminal, and the second electrode of the fourth transistor is electrically connected to the second node; The gate of the fifth transistor is electrically connected to the second node, the first electrode of the fifth transistor is electrically connected to the first voltage terminal, and the second electrode of the fifth transistor is electrically connected to the output driving terminal; The gate of the sixth transistor is electrically connected to the second control node, the first electrode of the sixth transistor is electrically connected to the output driving terminal, and the second electrode of the sixth transistor is electrically connected to the second voltage terminal; The gate of the seventh transistor is electrically connected to the first node, the first electrode of the seventh transistor is electrically connected to the output driving terminal, and the second electrode of the seventh transistor is electrically connected to the second voltage terminal; A first end of the second capacitor is electrically connected to the second node, and a second end of the second capacitor is electrically connected to the first voltage end.

7. The driving circuit according to any one of claims 1 to 4, wherein: Also included is an initialization circuit; The initialization circuit is electrically connected to the initial control terminal, the first node and the second voltage terminal respectively, and is used to control the connection between the first node and the second voltage terminal under the control of the initial control signal provided by the initial control terminal.

8. The driving circuit according to any one of claims 1 to 4, wherein: Also included is a first node control circuit; The first node control circuit is electrically connected to the fourth node, the first node and the second voltage terminal respectively, and is used to control the connection between the first node and the second voltage terminal under the control of the potential of the fourth node.

9. The driving circuit according to claim 7, wherein: The initialization circuit includes an eighth transistor; A gate of the eighth transistor is electrically connected to the initial control terminal, a first electrode of the eighth transistor is electrically connected to the first node, and a second electrode of the eighth transistor is electrically connected to the second voltage terminal.

10. The driving circuit according to claim 8, wherein: The first node control circuit includes a ninth transistor; The gate of the ninth transistor is electrically connected to the fourth node, the first electrode of the ninth transistor is electrically connected to the first node, and the second electrode of the ninth transistor is electrically connected to the second voltage terminal.

11. The driving circuit according to any one of claims 1 to 4, wherein: Also included is a voltage maintaining circuit, the voltage maintaining circuit including a first inverter, a second inverter and a maintaining control circuit; The input terminal of the first inverter is electrically connected to the first node, the output terminal of the first inverter is electrically connected to the fifth node, the input terminal of the second inverter is electrically connected to the fifth node, and the output terminal of the second inverter is electrically connected to the sixth node; The first inverter is used to invert the potential of the first node and output the inverted potential of the first node through the output terminal of the first inverter; The second inverter is used to invert the potential of its input terminal and output the inverted potential through the output terminal of the second inverter; The sustain control circuit is electrically connected to the sustain control terminal, the sixth node and the first node respectively, and is used to control the connection or disconnection between the sixth node and the first node under the control of the sustain control signal provided by the sustain control terminal.

12. The driving circuit according to claim 11, wherein: The maintenance control terminal includes a first maintenance control terminal and a second maintenance control terminal; The sustain control circuit includes a tenth transistor and an eleventh transistor; The gate of the tenth transistor is electrically connected to the first sustain control terminal, the first electrode of the tenth transistor is electrically connected to the first node, and the second electrode of the tenth transistor is electrically connected to the sixth node; The gate of the eleventh transistor is electrically connected to the second sustain control terminal, the first electrode of the eleventh transistor is electrically connected to the sixth node, and the second electrode of the eleventh transistor is electrically connected to the first node; The tenth transistor is a p-type transistor, and the eleventh transistor is an n-type transistor; The first sustain control terminal is the N-1th level driving signal terminal, and the second sustain control terminal is the first clock signal terminal; or The first sustain control terminal is a second clock signal terminal, and the second sustain control terminal is a first clock signal terminal.

13. The driving circuit according to claim 11, wherein: The first inverter includes a twelfth transistor and a thirteenth transistor, and the second inverter includes a fourteenth transistor and a fifteenth transistor; The gate of the twelfth transistor is electrically connected to the first node, the first electrode of the twelfth transistor is electrically connected to the first voltage terminal, and the second electrode of the twelfth transistor is electrically connected to the fifth node; The gate of the thirteenth transistor is electrically connected to the first node, the first electrode of the thirteenth transistor is electrically connected to the fifth node, and the second electrode of the thirteenth transistor is electrically connected to the second voltage terminal; The twelfth transistor is a p-type transistor, and the thirteenth transistor is an n-type transistor; The gate of the fourteenth transistor is electrically connected to the fifth node, the first electrode of the fourteenth transistor is electrically connected to the first voltage terminal, and the second electrode of the fourteenth transistor is electrically connected to the sixth node; The gate of the fifteenth transistor is electrically connected to the fifth node, the first electrode of the fifteenth transistor is electrically connected to the sixth node, and the second electrode of the fifteenth transistor is electrically connected to the second voltage terminal; The fourteenth transistor is a p-type transistor, and the fifteenth transistor is an n-type transistor.

14. The driving circuit according to any one of claims 1 to 4, wherein: The drive signal generating circuit includes a first control node control circuit, a second control node control circuit, a first drive output circuit and a second drive output circuit; The first control node control circuit is used to control the potential of the first control node; The second control node control circuit is used to control the potential of the second control node; The first drive output circuit is electrically connected to the first control node, the first voltage terminal, and the N-th level drive signal output terminal, respectively, and is used to control the connection between the N-th level drive signal output terminal and the first voltage terminal under the control of the potential of the first control node; The second drive output circuit is electrically connected to the second control node, the Nth level drive signal output terminal and the second voltage terminal respectively, and is used to control the connection between the Nth level drive signal output terminal and the second voltage terminal under the control of the potential of the second control node.

15. The driving circuit according to claim 14, wherein: The first control node control circuit includes a seventh node control circuit, an eighth node control circuit, a third node control circuit and a first control circuit; The seventh-node control circuit is electrically connected to the first clock signal terminal, the second voltage terminal, the seventh node, and the ninth node, respectively, and is configured to control communication between the seventh node and the second voltage terminal under the control of the first clock signal provided by the first clock signal terminal, and to control communication between the seventh node and the first clock signal terminal under the control of the potential of the ninth node; The eighth node control circuit is electrically connected to the second voltage terminal, the seventh node, and the eighth node, respectively, and is configured to control the seventh node to be connected to the eighth node under the control of the second voltage signal provided by the second voltage terminal; The third node control circuit is electrically connected to the eighth node, the second clock signal terminal, and the third node, respectively, and is configured to control the connection between the third node and the second clock signal terminal under the control of the potential of the eighth node, and to control the potential of the third node according to the potential of the eighth node; The first control circuit is electrically connected to the second clock signal terminal, the third node, the first control node, the ninth node and the first voltage terminal, respectively, and is used to control the connection between the third node and the first control node under the control of the second clock signal provided by the second clock signal terminal, and to control the connection between the first control node and the first voltage terminal under the control of the potential of the ninth node.

16. The driving circuit according to claim 14, wherein: The second control node control circuit includes a ninth node control circuit, a tenth node control circuit, a fourth node control circuit, an eleventh node control circuit and a second control circuit; The ninth node control circuit is electrically connected to the first clock signal terminal, the N-1th level drive signal output terminal, the ninth node, the initial control terminal, and the first voltage terminal, respectively, and is configured to control the ninth node to be connected to the N-1th level drive signal terminal under the control of the first clock signal provided by the first clock signal terminal, and to control the ninth node to be connected to the first voltage terminal under the control of the initial control signal provided by the initial control terminal; The tenth node control circuit is electrically connected to the first clock signal terminal, the N-1th stage drive signal output terminal, and the tenth node, respectively, and is used to control the connection between the tenth node and the N-1th stage drive signal output terminal under the control of the first clock signal provided by the first clock signal terminal; The fourth node control circuit is electrically connected to the first voltage terminal, the seventh node, the fourth node, the eleventh node, and the second clock signal terminal, respectively, and is configured to control the fourth node to be connected to the first voltage terminal under the control of the potential of the seventh node, and to control the fourth node to be connected to the second clock signal terminal under the control of the potential of the eleventh node; The eleventh-node control circuit is electrically connected to the fourth node, the eleventh node, the second voltage terminal, and the tenth node, respectively, and is configured to control the potential of the eleventh node according to the potential of the fourth node, and control the communication between the eleventh node and the tenth node under the control of the second voltage signal provided by the second voltage terminal; The second control circuit is electrically connected to the eleventh node and the second control node, respectively, and is configured to control the potential of the second control node under the control of the potential of the eleventh node.

17. The driving circuit according to claim 15, wherein: The seventh node control circuit includes a sixteenth transistor and a seventeenth transistor, the eighth node control circuit includes an eighteenth transistor, the third node control circuit includes a nineteenth transistor and a third capacitor, and the first control circuit includes a twentieth transistor and a twenty-first transistor; The gate of the sixteenth transistor is electrically connected to the first clock signal terminal, the first electrode of the sixteenth transistor is electrically connected to the second voltage terminal, and the second electrode of the sixteenth transistor is electrically connected to the seventh node; The gate of the seventeenth transistor is electrically connected to the ninth node, the first electrode of the seventeenth transistor is electrically connected to the seventh node, and the second electrode of the seventeenth transistor is electrically connected to the first clock signal terminal; The gate of the eighteenth transistor is electrically connected to the second voltage terminal, the first electrode of the eighteenth transistor is electrically connected to the seventh node, and the second electrode of the eighteenth transistor is electrically connected to the eighth node; The gate of the nineteenth transistor is electrically connected to the eighth node, the first electrode of the nineteenth transistor is electrically connected to the second clock signal terminal, and the second electrode of the nineteenth transistor is electrically connected to the third node; A first end of the third capacitor is electrically connected to the eighth node, and a second end of the third capacitor is electrically connected to the third node; The gate of the twentieth transistor is electrically connected to the second clock signal terminal, the first electrode of the twentieth transistor is electrically connected to the third node, and the second electrode of the twentieth transistor is electrically connected to the first control node; A gate of the twenty-first transistor is electrically connected to the ninth node, a first electrode of the twenty-first transistor is electrically connected to the first control node, and a second electrode of the twenty-first transistor is electrically connected to the first voltage terminal.

18. The driving circuit according to claim 16, wherein: The ninth node control circuit includes a twenty-second transistor and a twenty-third transistor, the tenth node control circuit includes a twenty-fourth transistor, the fourth node control circuit includes a twenty-fifth transistor and a twenty-sixth transistor, the eleventh node control circuit includes a twenty-seventh transistor and a fourth capacitor, and the second control circuit includes a twenty-eighth transistor and a twenty-ninth transistor; a gate of the twenty-second transistor electrically connected to the first clock signal terminal, a first electrode of the twenty-second transistor electrically connected to the (N-1)th stage driving signal output terminal, and a second electrode of the twenty-second transistor electrically connected to the ninth node; The gate of the twenty-third transistor is electrically connected to the initial control terminal, the first electrode of the twenty-third transistor is electrically connected to the first voltage terminal, and the second electrode of the twenty-third transistor is electrically connected to the ninth node; a gate of the twenty-fourth transistor is electrically connected to the first clock signal terminal, a first electrode of the twenty-fourth transistor is electrically connected to the (N-1)th stage driving signal output terminal, and a second electrode of the twenty-fourth transistor is electrically connected to the tenth node; a gate of the twenty-fifth transistor is electrically connected to the seventh node, a first electrode of the twenty-fifth transistor is electrically connected to the first voltage terminal, and a second electrode of the twenty-fifth transistor is electrically connected to the fourth node; a gate of the twenty-sixth transistor is electrically connected to the eleventh node, a first electrode of the twenty-sixth transistor is electrically connected to the fourth node, and a second electrode of the twenty-sixth transistor is electrically connected to the second clock signal terminal; A gate of the twenty-seventh transistor is electrically connected to the second voltage terminal, a first electrode of the twenty-seventh transistor is electrically connected to the tenth node, and a second electrode of the twenty-seventh transistor is electrically connected to the eleventh node; The first end of the fourth capacitor is electrically connected to the fourth node, and the second end of the fourth capacitor is electrically connected to the eleventh node; a gate of the twenty-eighth transistor is electrically connected to the eleventh node, a first electrode of the twenty-eighth transistor is electrically connected to the second control node, and a second electrode of the twenty-eighth transistor is electrically connected to the eleventh node; A gate of the twenty-ninth transistor is electrically connected to the second voltage terminal, a first electrode of the twenty-ninth transistor is electrically connected to the ninth node, and a second electrode of the twenty-ninth transistor is electrically connected to the second control node.

19. The driving circuit according to claim 14, wherein: The first drive output circuit includes a 30th transistor and a fifth capacitor, and the second drive output circuit includes a 31st transistor and a sixth capacitor; The gate of the 30th transistor is electrically connected to the first control node, the first electrode of the 30th transistor is electrically connected to the first voltage terminal, and the second electrode of the 30th transistor is electrically connected to the Nth stage driving signal output terminal; A first terminal of the fifth capacitor is electrically connected to the first control node, and a second terminal of the fifth capacitor is electrically connected to the first voltage terminal; The gate of the thirty-first transistor is electrically connected to the second control node, the first electrode of the thirty-first transistor is electrically connected to the N-th stage driving signal output terminal, and the second electrode of the thirty-first transistor is electrically connected to the second voltage terminal; A first end of the sixth capacitor is electrically connected to the Nth stage driving signal output terminal, and a second end of the sixth capacitor is electrically connected to the second voltage terminal.

20. A driving method, using the driving circuit according to any one of claims 1 to 19, the driving method comprising: The driving signal generating circuit generates an N-level driving signal under the control of the potential of the first control node and the potential of the second control node and outputs the N-level driving signal through the N-level driving signal output terminal; N is a positive integer; The output control circuit controls the connection between the first control node and the second node under the control of the potential of the first node; The gating circuit controls the gating input signal to be written into the first node under the control of the gating control signal; The voltage control circuit controls the potential of the second node according to the potential of the first node; The second node control circuit controls the connection between the second node and the first voltage terminal under the control of the potential of the first node; The output circuit controls the output drive terminal to be connected to the first voltage terminal under the control of the potential of the second node. The output circuit controls the output drive terminal to be connected to the second voltage terminal under the control of the potential of the second control node. The output circuit controls the output drive terminal to be connected to the second voltage terminal under the control of the potential of the first node.

21. A driving module comprising a plurality of driving circuits according to any one of claims 1 to 19; The Nth stage driving circuit is electrically connected to the driving signal output terminal included in the N-1th stage driving circuit; N is a positive integer.

22. A display device comprising the driving module according to claim 21.

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