Dynamic word line reconfiguration for NAND structures

Abstract

Techniques for reconfiguring word lines to data word lines or dummy word lines are disclosed herein. In the sub-block mode, the reconfigurable word lines function as dummy word lines that provide electrical isolation between the data word lines in the block. The block may be divided into an upper level, a middle level, and a lower level, with the reconfigurable word lines located within the middle level. In a full block mode, groups of the word lines that are reconfigurable are used as data word lines. Since the reconfigurable word lines are used as data word lines in the full block mode, the storage capacity in the full block mode is greater than the storage capacity in the sub-block mode. Further, since the sub-blocks are smaller in size but larger in number than the whole block, the memory system may be provided with fewer blocks and still meet user storage requirements in both the whole block mode and the sub-block mode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of the entire contents of U.S. non-provisional application No. 17 / 888,063, filed on August 15, 2022, entitled “DYNAMIC WORD LINE RECONFIGURATION FOR NAND STRUCTURE,” and is hereby incorporated by reference into this U.S. non-provisional application for all purposes. Background Art

[0003] The present disclosure relates to non-volatile memory.

[0004] Semiconductor memories are widely used in various electronic devices, such as cellular phones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, servers, solid-state drives, non-mobile computing devices, and other devices. Semiconductor memories may include non-volatile memory or volatile memory. Non-volatile memory allows information to be stored and retained even when the non-volatile memory is not connected to a power source (e.g., a battery).

[0005] The memory structure in the memory system usually contains many memory cells and various control lines. The memory structure can be three-dimensional. One type of three-dimensional structure has non-volatile memory cells arranged as vertical NAND strings. The memory structure can be arranged into units commonly referred to as blocks. For example, a block in a NAND memory system contains many NAND strings. The NAND string includes memory cell transistors connected in series, a drain side selection gate at one end, and a source side selection gate at the other end. Each NAND string is associated with a bit line. The block usually has many word lines, which provide voltage to the control gate of the memory cell transistor. In some architectures, each word line is connected to the control gate of a memory cell on each corresponding NAND string in the block.

[0006] Non-volatile memory cells can be programmed to store data. Typically, memory cells are programmed to multiple data states. Each cell uses two data states to store a single bit, which is referred to as SLC programming in this article. Using a greater number of data states allows each memory cell to store more bits. Each cell uses another data state to store two or more bits, which is referred to as MLC programming in this article. For example, four data states can be used to store two bits per memory cell, eight data states can be used to store three bits per memory cell, 16 data states can be used to store four bits per memory cell, etc. Some memory cells can be programmed to data states by storing charges in the memory cells. For example, the threshold voltage (Vt) of a NAND memory cell can be set to a target Vt by programming the charge into a charge storage region (such as a charge trapping layer). The amount of charge stored in the charge trapping layer establishes the Vt of the memory cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Like numbered elements refer to common parts in different figures.

[0008] Figure 1 is a block diagram depicting one embodiment of a storage system.

[0009] Figure 2A is a block diagram of one embodiment of a memory die.

[0010] Figure 2B is a block diagram of one embodiment of an integrated memory component.

[0011] Figure 3A and Figure 3B Various embodiments of integrated memory components are depicted.

[0012] Figure 4 is a perspective view of a portion of an exemplary embodiment of a monolithic three dimensional memory structure.

[0013] Figure 4A is a block diagram of one embodiment of a memory structure having two planes.

[0014] Figure 4B is a block diagram depicting a top view of a portion of a block of memory cells.

[0015] Figure 4C One embodiment of a block having data word lines and reconfigurable word lines is depicted.

[0016] Figure 4D An embodiment of a stack is depicted, showing the Figure 4B Cross-sectional view of line AA.

[0017] Figure 4EDepicted Figure 4D View of area 445.

[0018] Figure 4F is a schematic diagram of a portion of one embodiment of a block, depicting several NAND strings.

[0019] Figure 5A , Figure 5B and Figure 5C The threshold voltage distribution is depicted.

[0020] Figure 6 is a flow chart describing one embodiment of a process for programming a memory cell.

[0021] Figure 7 is a flow chart of one embodiment of a process for operating a block in either sub-block mode or full-block mode.

[0022] Fig. 8A Depicted is providing blocks in full block mode.

[0023] Figure 8B Depicted is providing a block in a sub-block mode.

[0024] Fig. 9 is a flow chart of one embodiment of a process for erasing a NAND in either sub-block mode or full-block mode.

[0025] Fig.10 is a flow chart of one embodiment of a process for programming NAND cells in either sub-block mode or full-block mode.

[0026] Fig.11A The NAND strings are shown being precharged during programming of the upper sub-block.

[0027] Fig. 11B The NAND strings are shown being precharged during programming of the lower sub-block.

[0028] Fig.12 Depicted is a table describing the bias conditions applied to word lines during programming in one implementation of sub-block mode.

[0029] Fig.13A is a flow chart of one embodiment of a process for programming memory cells in an upper sub-block.

[0030] Fig. 13B is a flow chart of one embodiment of a process for programming memory cells in a lower sub-block.

[0031] Fig.14A and Fig. 14B is a flow chart of an embodiment of programming memory cells in full block mode. DETAILED DESCRIPTION

[0032] Disclosed herein is a technique for reconfiguring a word line as a data word line or a dummy word line. A memory cell connected to a data word line is referred to herein as a data memory cell. A memory cell connected to a dummy word line is referred to herein as a dummy word line. The data memory cell is suitable for programming data, which may be user data or system data. The dummy memory cell is not suitable for programming user data or system data. In one embodiment, the word lines in a block include a first set of data word lines, a second set of data word lines, and a reconfigurable word line located between the first set and the second set. In one embodiment, a memory system operates a memory structure in a sub-block mode, in which the reconfigurable word lines are used as dummy word lines, which provide electrical isolation between a first set of data word lines in a first block and a second set of data word lines. For example, there may be two sub-blocks, in which a first set of data word lines is located in a lower sub-block, and a second set of data word lines is located in an upper sub-block. The memory system operates a memory structure in a full block mode, in which the reconfigurable word lines are used as data word lines. Since the reconfigurable word lines can be used as data word lines when in full block mode, the storage capacity in full block mode is greater than the storage capacity in sub-block mode. In addition, since sub-blocks are smaller in size but larger in number than full blocks, a memory system can be provided with fewer blocks and still meet user storage requirements in both the full block mode and the sub-block mode. In addition, precharging the NAND channel during program operations is facilitated by having an upper sub-block precharged from the bit line and a lower sub-block precharged from the source line.

[0033] In one embodiment, each block has an upper level, an intermediate level, and a lower level, wherein each level includes different sections of each NAND string. The lower level and the intermediate level can be separated by a first interface layer, which has a first set of manufacturing joints. The intermediate level and the upper level can be separated by a second interface layer, which has a second set of manufacturing joints. There may be dummy word lines adjacent to each interface layer. These dummy word lines can operate as dummy word lines under both full block mode and sub-block mode. In one embodiment, a NAND string is formed in a memory hole, wherein each manufacturing joint provides an electrical connection between a NAND channel located in one level and a NAND channel located in another level. Therefore, a NAND string can extend from a lower level to an upper level. A group of reconfigurable word lines can reside in an intermediate level.

[0034] Figure 11 is a block diagram of one embodiment of a storage system 100 that implements the techniques described herein. In one embodiment, the storage system 100 is a solid state drive ("SSD"). The storage system 100 may also be a memory card, a USB drive, or other types of storage systems. The techniques of the present invention are not limited to any one type of storage system. The storage system 100 is connected to a host 102, which may be a computer, a server, an electronic device (e.g., a smart phone, a tablet computer, or other mobile device), an appliance, or another device that uses memory and has data processing capabilities. In some embodiments, the host 102 is separate from the storage system 100, but is connected to the storage system 100. In other embodiments, the storage system 100 is embedded in the host 102.

[0035] Figure 1 The components of the storage system 100 depicted in FIG. 1 are electronic circuits. The storage system 100 includes a memory controller 120 (or storage device controller) connected to a non-volatile storage device 130 and a local high-speed memory 140 (e.g., DRAM, SRAM, MRAM). The local memory 140 is a non-transient memory that may include a volatile memory or a non-volatile memory. The memory controller 120 uses the local high-speed memory 140 to perform certain operations. For example, the local high-speed memory 140 may store logic in a physical address translation table ("L2P table").

[0036] The memory controller 120 includes a host interface 152 connected to and communicating with the host 102. In one embodiment, the host interface 152 implements NVM Express (NVMe) through PCI Express (PCIe). Other interfaces such as SCSI, SATA, etc. may also be used. The host interface 152 is also connected to a network on chip (NOC) 154. NOC is a communication subsystem on an integrated circuit. NOC can span synchronous and asynchronous clock domains, or use non-clocked asynchronous logic. NOC technology applies network theory and methods to on-chip communication, and brings significant improvements compared to conventional bus and crossbar switch interconnections. Compared with other designs, NOC improves the scalability of the system on chip (SoC) and the power efficiency of complex SoCs. The wires and links of the NOC are shared by many signals. Since all links in the NOC can run simultaneously on different data packets, a high degree of parallelism is achieved. Therefore, as the complexity of the integrated subsystem continues to increase, compared with previous communication architectures (e.g., dedicated point-to-point signal lines, shared buses, or segmented buses with bridges), NOC provides enhanced performance (such as throughput) and scalability. In other embodiments, NOC 154 may be replaced by a bus. Processor 156, ECC engine 158, memory interface 160, and local memory controller 164 are connected to and communicate with NOC 154. Local memory controller 164 is used to operate and communicate with local high-speed memory 140 (e.g., DRAM, SRAM, MRAM).

[0037] The ECC engine 158 performs error correction services. For example, the ECC engine 158 performs data encoding and decoding. In one embodiment, the ECC engine 158 is an electronic circuit programmed by software. For example, the ECC engine 158 can be a programmable processor. In other embodiments, the ECC engine 158 is a customized dedicated hardware circuit without any software. In another embodiment, the functions of the ECC engine 158 are implemented by the processor 156.

[0038] Processor 156 performs various controller memory operations, such as programming, erasing, reading, and memory management processes. In one embodiment, processor 156 is programmed by firmware. In other embodiments, processor 156 is a customized dedicated hardware circuit without any software. Processor 156 also implements a conversion module as a software / firmware process or as a dedicated hardware circuit. In many systems, non-volatile memory is addressed internally to the storage system using a physical address associated with one or more memory dies. However, the host system will use logical addresses to address various memory locations. This enables the host to assign data to consecutive logical addresses while the storage system is idle to store data between the locations of one or more memory dies as desired. In order to implement this system, memory controller 120 (e.g., conversion module) performs address conversion between the logical address used by the host and the physical address used by the memory die. An exemplary specific implementation is to maintain a table (i.e., the above-mentioned L2P table) that identifies the current conversion between the logical address and the physical address. The entries in the L2P table may include identification of the logical address and the corresponding physical address. Although logical address to physical address tables (or L2P tables) include the word "table", they need not be tables in the literal sense. Rather, logical address to physical address tables (or L2P tables) may be any type of data structure. In some examples, the memory space of the storage system is so large that the local memory 140 cannot hold all the L2P tables. In such cases, the entire set of L2P tables is stored in the storage device 130, and a subset of the L2P tables is cached (L2P cache) in the local high-speed memory 140.

[0039] The memory interface 160 communicates with the non-volatile storage device 130. In one embodiment, the memory interface provides a switch mode interface. Other interfaces may also be used. In some exemplary implementations, the memory interface 160 (or another portion of the controller 120) implements a scheduler and buffer for transmitting data to one or more memory dies and receiving data from one or more memory dies.

[0040] In one embodiment, non-volatile storage 130 includes one or more memory dies. Figure 2A is a functional block diagram of one embodiment of a memory die 200 that includes a non-volatile storage device 130. Each of the one or more memory dies of the non-volatile storage device 130 may be implemented as Figure 2A A memory die 200 is provided. Figure 2AThe components depicted in are circuits. The memory die 200 includes a memory structure 202 (e.g., a memory array), which may include non-volatile memory cells (also referred to as non-volatile storage device cells), as described in more detail below. The array terminal lines of the memory structure 202 include one or more various word line layers organized into rows, and one or more various bit line layers organized into columns. However, other orientations may also be implemented. The memory die 200 includes a row control circuit 220, the output of which is connected to the corresponding word lines of the memory structure 202. The row control circuit 220 receives a set of M row address signals and one or more various control signals from the system control logic circuit 260, and may generally include circuits such as a row decoder 222, an array driver 224, and a block selection circuit 226 for both read operations and write (programming) operations. The row control circuit 220 may also include a read / write circuit. The memory die 200 also includes a column control circuit 210, which includes a read / write circuit 225. The read / write circuit 225 may contain sense amplifiers and data latches. One or more sense amplifier inputs / outputs are connected to corresponding bit lines of the memory structure 202. Although only a single block is shown for the structure 202, the memory die may include multiple arrays that can be accessed separately. The column control circuit 210 receives a set of N column address signals and one or more various control signals from the system control logic 260, and may generally include circuits such as a column decoder 212, an array terminal receiver or driver circuit 214, and a read / write circuit 225 and an I / O multiplexer.

[0041] The system control logic 260 receives data and commands from the memory controller 120 and provides output data and status to the host. In some embodiments, the system control logic 260 (which includes one or more circuits) includes a state machine 262 that provides die-level control of memory operations. In one embodiment, the state machine 262 can be programmed by software. In other embodiments, the state machine 262 does not use software and is implemented entirely in hardware (e.g., electronic circuits). In another embodiment, the state machine 262 is replaced by a microcontroller or microprocessor that is on or outside the memory chip. The system control logic 260 may also include a power control module 264 that controls the power and voltage provided to the rows and columns of the memory structure 202 during memory operations. The system control logic 260 includes a storage device 266 (e.g., RAM, registers, latches, etc.) that can be used to store parameters for operating the memory structure 202.

[0042] Commands and data are transmitted between the memory controller 120 and the memory die 200 via a memory controller interface 268 (also referred to as a "communication interface"). The memory controller interface 268 is an electrical interface for communicating with the memory controller 120. Examples of the memory controller interface 268 include a switch mode interface and an open NAND flash interface (ONFI). Other I / O interfaces may also be used.

[0043] In some embodiments, all elements of memory die 200, including system control logic 260, may be formed as part of a single die. In other embodiments, some or all of system control logic 260 may be formed on a different die than the die containing memory structure 202.

[0044] In one embodiment, the memory structure 202 includes a three-dimensional memory array of non-volatile memory cells, where multiple memory levels are formed over a single substrate such as a wafer. The memory structure may include any type of non-volatile memory integrally formed in one or more physical levels of memory cells having active regions disposed over a silicon (or other type) substrate. In one example, the non-volatile memory cells include vertical NAND strings with charge trapping layers.

[0045] In another embodiment, the memory structure 202 includes a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells that utilize floating gates. Other types of memory cells (e.g., NOR-type flash memory) may also be used.

[0046] The exact type of memory array architecture or memory cell included in the memory structure 202 is not limited to the above examples. Many different types of memory array architectures or memory technologies can be used to form the memory structure 202. No specific non-volatile memory technology is required to implement the new embodiments claimed herein. Other examples of suitable technologies for memory cells of the memory structure 202 include ReRAM memory (resistive random access memory), magnetoresistive memory (e.g., MRAM, spin transfer torque MRAM, spin orbit torque MRAM), FeRAM, phase change memory (e.g., PCM), etc. Examples of suitable technologies for the memory cell architecture of the memory structure 202 include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bit line arrays, etc.

[0047] An example of a ReRAM crosspoint memory includes a reversible resistance switching element arranged in a crosspoint array accessed by an X line and a Y line (e.g., a word line and a bit line). In another embodiment, the memory cell may include a conductive bridge memory element. The conductive bridge memory element may also be referred to as a programmable metallization cell. Based on the physical repositioning of ions within a solid electrolyte, the conductive bridge memory element may be used as a state change element. In some cases, the conductive bridge memory element may include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of a solid electrolyte between the two electrodes. As the temperature increases, the mobility of the ions also increases, which causes the programming threshold of the conductive bridge memory cell to decrease. Therefore, the conductive bridge memory element may have a wide range of programming thresholds over the entire temperature range.

[0048] Another example is a magnetoresistive random access memory (MRAM) that stores data via magnetic storage elements. These elements are formed by two ferromagnetic layers separated by a thin insulating layer, each of which can maintain magnetization. One of the two layers is a permanent magnet set to a specific polarity; the magnetization of the other layer can be changed to match the magnetization of the storage memory by the external magnetic field. The memory device is constructed from a grid of such memory cells. In one embodiment for programming, each memory cell is located between a pair of write lines that are arranged at right angles to each other, parallel to the cell, one above the cell and one below the cell. When current passes through them, an induced magnetic field is generated. MRAM-based memory implementations will be discussed in more detail below.

[0049] Phase change memory (PCM) takes advantage of the unique properties of chalcogenide glass. One embodiment uses a GeTe-Sb2Te3 superlattice to achieve non-thermal phase change by changing the coordination state of germanium atoms using only laser pulses (or light pulses from another source). Therefore, the programming dose is a laser pulse. The memory cell can be inhibited by preventing the memory cell from receiving light. In other PCM embodiments, the memory cell is programmed by a current pulse. Note that the use of "pulse" in this document does not require a square pulse, but includes (continuous or discontinuous) vibrations or bursts of current, voltage, light or other waves. These memory elements within each selectable memory cell or bit can include additional series elements as selectors, such as a bidirectional threshold switch or a metal insulator substrate.

[0050] Those of ordinary skill in the art will recognize that the technology described herein is not limited to a single particular memory structure, memory configuration, or material composition, but encompasses many related memory structures within the spirit and scope of the technology as described herein and as understood by those of ordinary skill in the art.

[0051] Figure 2A The components of the invention can be grouped into two parts: (1) memory structure 202 and (2) peripheral circuits, which include Figure 2A 202; however, this reduces the area of ​​the memory die available for peripheral circuits. This can place quite severe constraints on these elements of the peripheral circuits. For example, the need to fit sense amplifier circuits within the available area can be a significant limitation on the sense amplifier design architecture. With respect to the system control logic component 260, the reduction in available area can limit the available functionality that can be implemented on the chip. Therefore, in the design of the memory die of the memory system 100, a fundamental trade-off needs to be made between the amount of area dedicated to the memory structure 202 and the amount of area dedicated to the peripheral circuits.

[0052] Another area where the memory structure 202 and the peripheral circuits often conflict is in the processing involved in forming these areas, as these areas often involve different processing technologies and the trade-offs when implementing different technologies on a single die. For example, when the memory structure 202 is a NAND flash memory, this is an NMOS structure, while the peripheral circuits are often CMOS based. For example, elements such as sense amplifier circuits, charge pumps, logic elements in state machines, and other peripheral circuits in the system control logic component 260 often employ PMOS devices. The processing operations used to manufacture a CMOS die will differ in many respects from processing operations optimized for NMOS flash NAND memory or other memory cell technologies. Three-dimensional NAND structures (see, e.g., Figure 4 ) can especially benefit from specialized processing operations.

[0053] To improve these limitations, the embodiments described below can Figure 2AThe components of the memory structure 202 can be separated into separately formed dies, and then the dies are bonded together. More specifically, the memory structure 202 can be formed on one die (referred to as the memory die), and some or all of the peripheral circuit elements (including one or more control circuits) can be formed on a separate die (referred to as the control die). For example, the memory die can be formed only by memory elements, such as a memory cell array of a flash NAND memory, an MRAM memory, a PCM memory, a ReRAM memory, or other memory types. Some or all of the circuits in the peripheral circuits (even including elements such as decoders and sense amplifiers) can then be moved to a separate control die. This allows each die in the memory die to be optimized individually according to its technology. For example, a NAND memory die can be optimized for an NMOS-based memory array structure without having to worry about CMOS elements that have now been moved to a control die that can be optimized for CMOS processing. This provides more room for peripheral elements, and if the peripheral elements are confined to the edge of the same die that houses the memory cell array, additional capabilities that may not be easily combined can now be combined. The two dies can then be bonded together in a bonded multi-die memory circuit where the array on one die is connected to the peripheral components on the other die. For example, while the following will focus on a bonded memory circuit with one memory die and one control die, other embodiments may use more dies, such as two memory dies and one control die.

[0054] Figure 2B Shows Figure 2A An alternative arrangement to the arrangement of may be implemented using wafer-to-wafer bonding to provide bonded die pairs. Figure 2B A functional block diagram of one embodiment of an integrated memory component 207 is depicted. One or more integrated memory components 207 can be used to implement the non-volatile storage device 130 of the memory system 100. The integrated memory component 207 includes two types of semiconductor dies (or more succinctly, "dies"). The memory structure die 201 includes a memory structure 202. The memory structure 202 includes non-volatile memory cells. The control die 211 includes control circuits 260, 210, and 220 (as described above). In some embodiments, the control die 211 is configured to connect to the memory structure 202 in the memory structure die 201. In some embodiments, the memory structure die 201 and the control die 211 are bonded together.

[0055] Figure 2B An example of a peripheral circuit is shown, which includes a control circuit formed in a peripheral circuit or control die 211, which is coupled to a memory structure 202 formed in a memory structure die 201. Common components are similar to Figure 2AThe system control logic 260, the row control circuit 220, and the column control circuit 210 are located in the control die 211. In some embodiments, all or a portion of the column control circuit 210 and all or a portion of the row control circuit 220 are located on the memory structure die 201. In some embodiments, some of the circuits in the system control logic 260 are located on the memory structure die 201.

[0056] The system control logic 260, row control circuit 220, and column control circuit 210 may be formed by conventional processes (e.g., CMOS processes), so that adding elements and functions more commonly found on the memory controller 120, such as ECC, may require few or no additional process steps (i.e., the same process steps used to manufacture the controller 120 may also be used to manufacture the system control logic 260, row control circuit 220, and column control circuit 210). Therefore, while removing such circuits from a die (such as the memory structure die 201) may reduce the number of steps required to manufacture such a die, adding such circuits to a die (such as the control die 211) may not require many additional process steps. Since some or all of the control circuits 260, 210, 220 are implemented using CMOS technology, the control die 211 may also be referred to as a CMOS die.

[0057] Figure 2B Column control circuitry 210 including read / write circuitry 225 located on control die 211 is shown coupled to memory structure 202 on memory structure die 201 via electrical paths 206. For example, electrical paths 206 can provide electrical connections between column decoders 212, driver circuitry 214, R / W circuitry 225, and bit lines of memory structure 202. Electrical paths can extend from column control circuitry 210 in control die 211 through pads on control die 211 that are bonded to corresponding pads of memory structure die 201 that are connected to bit lines of memory structure 202. Each bit line of memory structure 202 can have a corresponding electrical path located in electrical paths 206 that includes a pair of bond pads connected to column control circuitry 210. Similarly, row control circuitry 220 (including row decoders 222, array drivers 224, and block selectors 226) is coupled to memory structure 202 via electrical paths 208. Each electrical path 208 may correspond to a word line, a dummy word line, or a select gate line. Additional electrical paths may also be provided between the control die 211 and the memory structure die 201 .

[0058] For the purposes of this document, the phrase "control circuitry" or "one or more control circuits" may include any one or any combination of memory controller 120, state machine 262, power control 264, all or a portion of system control logic 260, all or a portion of row control circuitry 220, all or a portion of column control circuitry 210, read / write circuitry 225, sense amplifiers, microcontrollers, microprocessors, and / or other similar functional circuits. The control circuitry may include only hardware or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is an example of a control circuit. The control circuitry may include a processor, an FPGA, an ASIC, an integrated circuit, or other types of circuitry.

[0059] For purposes of this document, the term “device” may include, but is not limited to, one or more of the memory system 100 , the memory controller 120 , the memory device 130 , the memory die 200 , the integrated memory component 207 , and / or the control die 211 .

[0060] In some embodiments, there is more than one control die 211 and more than one memory structure die 201 in the integrated memory component 207. In some embodiments, the integrated memory component 207 includes a stack of multiple control dies 211 and multiple memory structure dies 201. Figure 3A A side view of one embodiment of an integrated memory component 207 (e.g., including a stack of control dies 211 and memory structure dies) stacked on a substrate 271 is depicted. The integrated memory component 207 has three control dies 211 and three memory structure dies 201. In some embodiments, there are more than three memory structure dies 201 and more than three control dies 211. Figure 3A However, in one embodiment, there are more memory structure dies 201 than control dies 211. For example, one control die 211 can control multiple memory structure dies 201.

[0061] Each control die 211 is attached (e.g., bonded) to at least one of the memory structure dies 201. Some of the bonding pads 282 / 284 are depicted. There may be more bonding pads. The space between the two dies 201, 211 bonded together is filled with a solid layer 280, which can be formed of epoxy or other resins or polymers. The solid layer 280 protects the electrical connection between the dies 201, 211 and further secures the dies together. Various materials can be used as the solid layer 280, but in an embodiment, the material can be Hysol epoxy resin from Henkel Corporation (which has offices in California, USA).

[0062] The integrated memory components 207 may be stacked, for example, in a stepped offset manner so that the bonding pads at each level are uncovered and accessible from above. Wire bonds 270 connected to the bonding pads connect the control die 211 to the substrate 271. Multiple such wire bonds may be formed across the width of each control die 211 (i.e., formed to Figure 3A ).

[0063] Memory die through silicon vias (TSVs) 276 may be used to route signals through the memory structure die 201. Control die through silicon vias (TSVs) 278 may be used to route signals through the control die 211. TSVs 276, 278 may be formed before, during, or after the formation of the integrated circuits in the semiconductor die 201, 211. The TSVs may be formed by etching holes through the wafer. The holes may then be lined with a barrier to prevent metal diffusion. The barrier layer may in turn be lined with a seed layer, and the seed layer may be plated with an electrical conductor, such as copper, although other suitable materials may be used, such as aluminum, tin, nickel, gold, doped polysilicon, and alloys or combinations thereof.

[0064] Solder balls 272 may optionally be attached to contact pads 274 on the lower surface of substrate 271. Solder balls 272 may be used to electrically and mechanically couple integrated memory component 207 to a host device such as a printed circuit board. Solder balls 272 may be omitted in the case where integrated memory component 207 is to be used as an LGA package. Solder balls 272 may form part of the interface between integrated memory component 207 and memory controller 120.

[0065] Figure 3B A side view of another embodiment of an integrated memory component 207 stacked on a substrate 271 is depicted. Figure 3BThe integrated memory component 207 has three control dies 211 and three memory structure dies 201. In some embodiments, there are far more than three memory structure dies 201 and far more than three control dies 211. In this example, each control die 211 is bonded to at least one memory structure die 201. Optionally, the control die 211 can be bonded to two or more memory structure dies 201.

[0066] Some of the bonding pads 282, 284 are depicted. There may be more bonding pads. The space between the two dies 201, 211 bonded together is filled with a solid layer 280, which may be formed of epoxy or other resins or polymers. Figure 3A Compared to the example in Figure 3B The integrated memory component 207 in FIG. 2 has no step offset. Memory die through silicon vias (TSVs) 276 may be used to route signals through the memory structure die 201 . Control die through silicon vias (TSVs) 278 may be used to route signals through the control die 211 .

[0067] Solder balls 272 may optionally be attached to contact pads 274 on the lower surface of substrate 271. Solder balls 272 may be used to electrically and mechanically couple integrated memory assembly 207 to a host device such as a printed circuit board. Solder balls 272 may be omitted in the case where integrated memory assembly 207 is to be used as an LGA package.

[0068] As briefly discussed above, the control die 211 and the memory structure die 201 can be bonded together. The bonding pads on each die 201, 211 can be used to bond the two dies together. In some embodiments, in the so-called Cu-Cu bonding process, the bonding pads are directly bonded to each other without solder or other additional materials. In the Cu-Cu bonding process, the bonding pads are controlled to be highly flat and formed in a highly controlled environment, which is substantially free of environmental particles, otherwise the environmental particles may be deposited on the bonding pads and prevent close bonding. Under such properly controlled conditions, the bonding pads are aligned and pressed against each other to form mutual bonding based on surface tension. This bonding can be formed at room temperature, although heat can also be applied. In an embodiment using Cu-Cu bonding, the bonding pads can be about 5 μm square and spaced apart from each other at a spacing of 5 μm to 5 μm. Although the process is referred to as Cu-Cu bonding in this article, the term can also be applied to the case where the bonding pads are formed by materials other than copper.

[0069] When the area of ​​the bonding pad is small, it may be difficult to bond the semiconductor die together. By providing a film layer on the surface of the semiconductor die including the bonding pad, the size of the bonding pad and the spacing between the bonding pads can be further reduced. The film layer is arranged around the bonding pad. When the die are put together, the bonding pads can be bonded to each other, and the film layers on the individual dies can be bonded to each other. This bonding technology can be referred to as hybrid bonding. In an embodiment using hybrid bonding, the bonding pads can be about 5 μm square and spaced apart from each other at a spacing of 1 μm to 5 μm. Bonding technology can be used to provide bonding pads with smaller sizes and spacings.

[0070] Some embodiments may include a film on the surface of the dies 201, 211. If such a film is not initially provided, the space between the dies may be underfilled with epoxy or other resins or polymers. The underfill material may be applied as a liquid and then allowed to harden into a solid layer. This underfill step protects the electrical connection between the dies 201, 211 and further secures the dies together. Various materials may be used as underfill materials.

[0071] Figure 4 is a perspective view of a portion of an exemplary embodiment of a monolithic three-dimensional memory array / structure that may include a memory structure 202 that includes a plurality of non-volatile memory cells arranged as vertical NAND strings. For example, Figure 4 A portion 400 of a memory block is shown. The depicted structure includes a set of bit lines BL located above a stack 401 of alternating dielectric and conductive layers. For illustrative purposes, one of the dielectric layers is labeled D and one of the conductive layers (also referred to as a word line layer) is labeled W. The number of alternating dielectric and conductive layers may vary based on specific implementation requirements. In one embodiment, the alternating dielectric and conductive layers are divided into four (or a different number of) regions (e.g., fingers or strings) by isolation regions IR. Figure 4 An isolation region IR is shown separating the two finger portions. A source line layer SL is located below the alternating dielectric layer and word line layer. A memory hole is formed in the stack of alternating dielectric layers and conductive layers. For example, the memory hole is marked as MH. Note that Figure 4 2, the dielectric layers are depicted as perspective views so that the reader can see the memory holes located in the stack of alternating dielectric layers and conductive layers. In one embodiment, a NAND string is formed by filling the memory holes with a material including a charge trapping material to form vertical columns of memory cells. Each memory cell can store one or more data bits. More details of a three-dimensional monolithic memory array including memory structure 202 are provided below.

[0072] Figure 4Ais a block diagram explaining an exemplary organization of a memory structure 202, which is divided into two planes 403 and 405. Each plane is then divided into M blocks. In one example, each plane has about 2000 blocks. However, a different number of blocks and planes may also be used. In one embodiment of the full block mode, a block of memory cells is the unit of erase. That is, all memory cells of a block are erased together. In one embodiment of the sub-block mode, a block may be divided into sub-blocks, and the sub-blocks are the unit of erase. Memory cells may also be grouped into blocks for other reasons, such as to organize the memory structure to enable signaling and selection circuits. In some embodiments, a block represents a group of connected memory cells because the memory cells of a block share a common set of word lines. For example, the word lines of a block are all connected to all vertical NAND strings of the block. Although Figure 4A Two planes 403 / 405 are shown, but more or less than two planes may be implemented. In some embodiments, memory structure 202 includes four planes. In some embodiments, memory structure 202 includes eight planes. In some embodiments, programming can be performed in parallel in a first selected block in plane 403 and a second selected block in plane 405.

[0073] Figure 4B and Figure 4D-4F An exemplary three-dimensional ("3D") NAND structure is depicted, corresponding to Figure 4 structure and can be used to implement Figure 2A and Figure 2B Memory structure 202. Figure 4B is a block diagram depicting a top view of portion 407 of block 2. Figure 4B As can be seen in Figure 4B The blocks depicted in FIG. extend in the direction of arrow 433. In one embodiment, the memory array has many layers; however, Figure 4B Only the top layer is shown.

[0074] Figure 4B A plurality of circles representing vertical columns are depicted. Each of the vertical columns includes a plurality of select transistors (also referred to as select gates) and a plurality of memory cells. In one embodiment, each vertical column implements a NAND string. For example, Figure 4B Vertical columns 422, 432, 442, 452, and 453 are depicted. Vertical column 422 implements NAND string 482. Vertical column 432 implements NAND string 484. Vertical column 442 implements NAND string 486. Vertical column 452 implements NAND string 488. Vertical column 453 implements NAND string 489. More details of these vertical columns are provided below. Figure 4BThe block depicted in FIG. 4 extends in the direction of arrow 433, so the block includes Figure 4B More vertical columns as depicted in .

[0075] Figure 4B Also depicted is a set of bit lines 415 , including bit lines 411 , 412 , 413 , 414 , . . . , 419 . Figure 4B Twenty-four bit lines are shown because only a portion of the block is shown. It is contemplated that more than twenty-four bit lines are connected to the vertical columns of the block. Each circle representing a vertical column has an "x" to indicate that it is connected to a bit line. For example, bit line 414 is connected to vertical columns 422, 432, 442, 452, and 453.

[0076] Figure 4B The block depicted in FIG. 4 includes a collection of isolation regions 402, 404, 406, 408, 410, and 424 formed of SiO2; however, other dielectric materials may also be used. Isolation regions 402, 404, 406, 408, 410, and 424 are used to divide the top layer of the block into five regions; for example, Figure 4B The top layer depicted in FIG. 1 is divided into regions 420, 430, 440, 450, and 460, which are referred to as fingers. In one embodiment, isolation regions 402 and 424 separate a block from an adjacent block. Thus, isolation regions 402 and 424 may extend down to the substrate. In one embodiment, isolation regions 404, 406, 408, and 410 divide only the layers used to implement select gates so that NAND strings in different fingers can be independently selected. Back to Reference Figure 4 , the IR region may correspond to any of the isolation regions 404, 406, 408, or 410. In one exemplary implementation, the bit line is connected to only one vertical column / NAND string in each of the regions (fingers) 420, 430, 440, 450, and 460. In this implementation, each block has twenty-four rows of active columns, and each bit line is connected to five vertical columns / NAND strings in each block. In one embodiment, all five vertical columns / NAND strings connected to a common bit line are connected to the same word line (or word line group); therefore, the system uses the drain-side select line to select one vertical column / NAND string (or another subset) of the four vertical columns / NAND strings to be subjected to a memory operation (program, verify, read, and / or erase).

[0077] although Figure 4B Each region is shown with four vertical columns, five regions and twenty vertical columns in a block, but these exact numbers are exemplary implementations. Other embodiments may include more or fewer regions per block, more or fewer vertical columns per region, and more or fewer vertical columns per block. Figure 4B It is also shown that the vertical columns are staggered. In other embodiments, different staggered patterns can be used. In some embodiments, the vertical columns are not staggered.

[0078] Figure 4C One embodiment of a block 444 having data word lines and reconfigurable word lines is depicted. Block 444 may represent, for example Figure 4A 4. Block 444 has a first set 443 of data word lines, a second set 447 of data word lines, and a reconfigurable word line 449. The first set 443 of data word lines is located in one area of ​​block 444, the second set 447 of data word lines is located in another area of ​​block 444, and the reconfigurable word line 449 is located between and divides the first and second sets of data word lines.

[0079] The reconfigurable word lines can be used as data word lines in full block mode and as dummy word lines in sub-block mode. Additional dummy word lines may be present in block 444; however, Figure 4C 449. In the full block mode, data can be programmed into the reconfigurable word lines 449. However, in the sub-block mode, data is not programmed into the reconfigurable word lines 449. Therefore, the reconfigurable word lines allow additional storage capacity in the full block mode. For example, in the full block mode, the first set of data word lines 443, the second set of data word lines 447, and all of the reconfigurable word lines 449 can be used for data storage.

[0080] In one embodiment, in full block mode, memory cells connected to the first set 443 of data word lines, memory cells connected to the second set 447 of data word lines, and memory cells connected to the reconfigurable word line 449 are erased as a unit. However, in sub-block mode, memory cells connected to the first set 443 of data word lines are erased independently of memory cells connected to the second set 447 of data word lines. Furthermore, in sub-block mode, the reconfigurable word lines provide electrical isolation between the first set 443 of data word lines and the second set 447 of data word lines. In one embodiment, the voltage applied to the reconfigurable word lines 449 during erasing in sub-block mode enables the reconfigurable word lines to provide electrical isolation between the first set 443 of data word lines and the second set 447 of data word lines.

[0081] Figure 4D A portion of one embodiment of a three-dimensional memory structure 202 is depicted, showing Figure 4B This cross-sectional view cuts through the vertical columns (NAND strings) 422 and 434 of region 420 (see Figure 4B ). Figure 4D An embodiment of a stack with three levels is depicted. The three-level stack includes an upper level 421, an intermediate level 423, and a lower level 425. The memory holes in the lower level 425 and the intermediate level 423 can be connected by manufacturing joints 435. Similarly, the memory holes in the upper level 421 and the intermediate level 423 can be joined by manufacturing joints 435. The manufacturing joints are configured to provide an electrical connection between a channel of a segment of a NAND string located in one level and a channel of a segment of a NAND string located in an adjacent level. The manufacturing joints can include conductive regions such as doped silicon or tungsten to provide such electrical connection. The manufacturing joints 435 reside in the interface layer IF1 or IF2. In addition to the manufacturing joints 435, the interface layers IF1, IF2 can also include insulators such as silicon oxide. In some embodiments, fabrication junction 435 includes a junction transistor that can provide electrical connection between a channel of a segment of a NAND string located in one level and a channel of a segment of a NAND string located in an adjacent level. In this case, each corresponding interface layer (IF1, IF2) can include a conductive layer for driving a gate of the junction transistor.

[0082] Three levels of other multi-level stacking can be used to form a relatively high stack while maintaining a relatively narrow memory hole width (or diameter). After the layer of the lower level 425 is formed, a memory hole portion is formed in the lower level 425. After the layer of the middle level is formed, a memory hole portion is formed in the middle level. After the layer of the upper level is formed, a memory hole portion is formed in the upper level. The memory hole of the upper level is aligned with the memory hole of the middle level, and the upper level and the middle level are connected together. In one embodiment, the manufacturing joint 435 connects the memory hole of the upper level with the memory hole of the middle level. The memory hole of the lower level is aligned with the memory hole of the middle level, and the lower level and the middle level are connected together. In one embodiment, the manufacturing joint 435 connects the memory hole of the middle level with the memory hole in the lower level. Therefore, the corresponding manufacturing joint 435 can provide a conductive connection between a NAND channel located in one level and a NAND channel located in another level. Thus, a NAND string will extend continuously through three levels.Thus, a NAND string may extend from one end of the stack to the other.

[0083] The resulting memory holes are narrower than if the memory holes were etched from the top to the bottom of the stack rather than individually in each level. An interface layer (IF1, IF2) is generated at which each pair of levels is connected. Due to the presence of the interface layer, adjacent word line layers may be affected by edge effects such as programming or erasing difficulties. These adjacent word line layers can therefore be set as dummy word lines (IFDL1, IFDU1, IFDL2, IFDU2). In one embodiment, the memory system operates the dummy word lines (IFDL1, IFDU1, IFDL2, IFDU2) as dummy word lines in both full block mode and sub-block mode.

[0084] Figure 4D The structure also includes a drain side select gate layer (SGD) and a source side select gate layer (SGS). There may be multiple SGD layers and multiple SGS layers. Figure 4D The structure also includes dummy word line layers DD, DDS; two hundred and sixty-eight data word line layers WL0-WL267 for connecting to data memory cells. The dielectric layer is depicted as being located between the conductive layers just described. Other embodiments may implement more or less than the number of the above embodiments. Figure 4D The number of descriptions.

[0085] The middle level 423 has a plurality of reconfigurable word line layers WL_RC1, WL_RC2, WL_RC3, and WL_RC4. Each reconfigurable word line layer is connected to memory cells, which can be reconfigured as data memory cells or dummy memory cells. Therefore, each of these layers can be configured as a data word line layer or a dummy word line layer. In one embodiment, the reconfiguration is performed by the memory controller 120 by, for example, designating the reconfigurable word line layer as a dummy WL or data WL. In one embodiment, when in sub-block mode, the reconfigurable word line layer is configured as a dummy word line. In other words, the memory cells connected to the reconfigurable word line layer can be operated as data memory cells or dummy memory cells.

[0086] In sub-block mode, the upper and lower sub-blocks can be erased independently of each other. Therefore, the data in the upper sub-block can be retained after the lower sub-block is erased. Similarly, the data in the lower sub-block can be retained after the upper sub-block is erased. In sub-block mode, the reconfigurable word line layer can provide electrical isolation between the upper and lower sub-blocks. In one embodiment, when in full-block mode, the reconfigurable word line layer is configured as a data word line. Therefore, the capacity of the block can be larger in full-block mode relative to the combined capacity of the upper word block capacity and the lower sub-block capacity in sub-block mode. In this example, in Figure 4DIn the embodiment of the present invention, the lower sub-block includes data word lines WL0-WL133, and the upper sub-block includes data word lines WL134-WL267. Therefore, each sub-block includes 134 data word lines. In sub-block mode, the two sub-blocks combined have 268 data word lines. However, in full block mode, four reconfigurable word lines bring a total of 272 data word lines. Therefore, the storage capacity of the full block mode is larger than that of the sub-block mode. Note that the sub-block mode in which the upper sub-block and the lower sub-block exist may also be referred to as the half-block mode. In addition, the full block mode may also be referred to as the full NAND string mode, and the half-block mode may also be referred to as the half-NAND string mode. However, since the reconfigurable word lines are used as dummy word lines in the half-block mode and as data word lines in the full block mode, the storage capacity of the half-block mode is less than half of the storage capacity of the full block mode. The term "half block" is used to describe the presence of two sub-blocks in a block.

[0087] Vertical columns 432 and 434 are depicted as protruding through the drain side selection layer, source side selection layer, IF layer, dummy word line layer, reconfigurable word line layer, and data word line layer. In one embodiment, each vertical column includes a vertical NAND string. Below the vertical columns and the layers listed below is a substrate 457, an insulating film 454 located on the substrate, and a source line SL. The NAND string of vertical column 432 has a source terminal at the bottom of the stack and a drain terminal at the top of the stack. Figure 4B Consistent, Figure 4D Vertical columns 432 connected to bit lines 414 via connectors 417 are shown.

[0088] For ease of reference, the drain side selection layer, the source side selection layer, the dummy word line layer, the data word line layer, and the reconfigurable word line layer are collectively referred to as the conductive layer. In one embodiment, the conductive layer is made of a combination of TiN and tungsten. In other embodiments, other materials can be used to form the conductive layer, such as doped polysilicon, metals (such as tungsten or metal silicide). In some embodiments, different conductive layers can be formed of different materials. There are dielectric layers between the conductive layers. In one embodiment, the dielectric layer is made of SiO2. In other embodiments, other dielectric materials can be used to form the dielectric layer.

[0089] The non-volatile memory cells are formed along vertical columns that extend through alternating conductive layers and dielectric layers in the stack. In one embodiment, the memory cells are arranged in a NAND string. The word line layers WL0-W267 are connected to the memory cells (also referred to as data memory cells). The dummy word line layers DD and DDS are connected to the dummy memory cells. The dummy memory cells do not store host data and are not eligible to store host data (data provided from the host, such as data from a host user), while the data memory cells are eligible to store host data. In some embodiments, the data memory cells and the dummy memory cells may have the same structure. The drain side selection layer SGD is used to electrically connect and disconnect (or cut off) the channel of the corresponding NAND string with the bit line. The source side selection layer SGS is used to electrically connect and disconnect (or cut off) the channel of the corresponding NAND string with the source line SL.

[0090] Figure 4E Depicted Figure 4D 4. A view of region 445 of FIG. WL133, WL_RC1, WL_RC2, WL_RC3, and WL_RC4 are included. Reconfigurable memory cell transistors 570, 571, 572, and 573 and data memory cell transistors 574 are indicated by dashed lines. Physically, the reconfigurable memory cell transistors and the data memory cell transistors 574 can have the same structure. In one mode, the reconfigurable memory cell transistors 570, 571, 572, and 573 can be configured as data memory cell transistors. In another mode, the reconfigurable memory cell transistors 570, 571, 572, and 573 can be configured as data memory cell transistors. In one embodiment, the reconfiguration is performed by the memory controller 120, which changes how the reconfigurable memory cell transistors for use are specified. Therefore, the reconfiguration does not require physical changes to the reconfigurable memory cell transistors 570.

[0091] Multiple layers may be deposited along the sidewalls (SW) of the memory hole 422 and / or within each word line layer, for example, using atomic layer deposition. For example, each column (e.g., a column formed by the material within the memory hole) may include a blocking oxide / block high-k material 470, a charge trapping layer or film 463 (such as SiN or other nitrides), a tunnel layer 464, a polysilicon body or channel 465, and a dielectric core 466. The word line layer may include a conductive metal 462 (such as tungsten) as a control gate. For example, control gates 490, 491, 492, 493, and 494 are provided. In this example, all layers except the metal are provided in the memory hole. In other methods, some of the layers may be in the control gate layer. Additional columns are similarly formed in different memory holes. The columns may form a columnar active area (AA) of the NAND string.

[0092] When programming the memory cell transistor, electrons are stored in the portion of the charge trapping layer associated with the memory cell transistor. These electrons are attracted from the channel into the charge trapping layer and travel through the tunnel layer. The Vth of the memory cell transistor increases in proportion to the amount of stored charge. During an erase operation, the electrons return to the channel.

[0093] Each of the memory holes may be filled with a plurality of annular layers (also referred to as memory film layers) including a blocking oxide layer, a charge trapping layer, a tunnel layer, and a channel layer. The core region of each of the memory holes is filled with a body material, and the plurality of annular layers are located between the core region and the WLL in each of the memory holes. In some cases, the tunnel layer 464 may include a plurality of layers, such as in an oxide-nitride-oxide configuration.

[0094] Figure 4F yes Figure 4-4E A schematic diagram of a portion of a memory is depicted in FIG. Figure 4F Physical word lines WL0-WL267 are shown running across the entire block. Figure 4F The structure corresponds to Figure 4A-4B 4, 419. Within the block, each bit line is connected to five NAND strings. Drain side select lines SGD-s0, SGD-s1, SGD-s2, SGD-s3, and SGD-s4 are used to determine which of the five NAND strings (NS0, NS1, NS2, NS3, NS4) is connected to the associated bit line. Figure 4F The other NAND strings and other bit lines of the block are not depicted. The first finger corresponds to the vertical NAND string controlled by SGD-s0. The second finger corresponds to the vertical NAND string controlled by SGD-s1. The third finger corresponds to the vertical NAND string controlled by SGD-s2. The fourth finger corresponds to the vertical NAND string controlled by SGD-s3. The fifth finger corresponds to the vertical NAND string controlled by SGD-s4. There may be more or less than five fingers in a block.

[0095] The source side select line SGS connects / disconnects the NAND string to the common source line. In some embodiments, there is one source side select line for each finger (similar to the five SGD-s0, SGD-s1, SGD-s2, SGD-s3, and SGD-s4). The block can also be viewed as being divided into five fingers: finger 0, finger 1, finger 2, finger 3, and finger 4. Finger 0 corresponds to the vertical NAND string controlled by SGD-s0, finger 1 corresponds to the vertical NAND string controlled by SGD-s1, finger 2 corresponds to the vertical NAND string controlled by SGD-s2, finger 3 corresponds to the vertical NAND string controlled by SGD-s3, and finger 4 corresponds to the vertical NAND string controlled by SGD-s4. Note that the term "fingers" in this context refers to regions that each include an entire NAND string (but a subset of the NAND strings in the block). In some embodiments, there is a sub-block mode in which each sub-block includes only a portion of each NAND string. For example, the upper sub-block may include the upper half of each NAND string in the block, and the lower sub-block may include the lower half of each NAND string in the block. Figure 4F , the sub-blocks may be divided by reconfigurable word lines (WLRC1, WLRC2, WLRC3, WLRC4) that reside in the middle level 423. Thus, the lower sub-block may include data word lines WL0-WL133, and the upper sub-block may include data word lines WL134-WL267.

[0096] Although Figure 4 , Figure 4B and Figure 4D-4F An exemplary memory of is a three-dimensional memory structure including vertical NAND strings with charge trapping material, but other memory structures may also be used with the techniques described herein.

[0097] The memory system discussed above can be erased, programmed, and read. Each memory cell can be associated with a memory state according to the write data in the program command. Based on the memory state of the memory cell, the memory cell will remain in the erased state or be programmed to a memory state different from the erased state (programmed memory state).

[0098] For example, in a two-bit per cell memory device (sometimes referred to as a multi-level cell (MLC)), there are four memory states, including an erased state and three programmed memory states, which are referred to as A, B, and C memory states. In a three-bit per cell memory device (sometimes referred to as a three-level cell (TLC)), there are eight memory states, including an erased state and seven programmed memory states, which are referred to as A, B, C, D, E, F, and G memory states. In a four-bit per cell memory device (sometimes referred to as a quad-level cell (QLC)), there are sixteen memory states, including an erased state and fifteen programmed memory states, which are referred to as Er, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, and S15 memory states.

[0099] Figure 5A An embodiment of the threshold voltage Vth distribution of a four-state memory device is depicted, in which each memory cell stores two bits of data. A first threshold voltage Vth distribution 500 is provided for erasing (Er state) storage elements. Three threshold voltage Vth distributions 502, 504, and 506 represent programmed memory states A, B, and C, respectively. A 2-bit code with a lower bit and a higher bit can be used to represent each memory state in the four memory states. In an embodiment, the "Er", "A", "B", and "C" memory states are represented by "11", "01", "00", and "10", respectively.

[0100] Figure 5B An embodiment of the threshold voltage Vth distribution of an eight-state memory device is depicted, in which each memory cell stores three bits of data. A first threshold voltage Vth distribution 510 is provided for the Er state storage element. Seven threshold voltage Vth distributions 512, 514, 516, 518, 520, 522, and 524 represent programmed memory states A, B, C, D, E, F, and G, respectively. A 3-bit code with a lower page bit, a middle page bit, and an upper page bit can be used to represent each of the eight memory states. In an embodiment, the "Er", "A", "B", "C", "D", "E", "F", and "G" memory states are represented by "111", "011", "001", "000", "010", "110", "100", and "101", respectively.

[0101] Figure 5CAn embodiment of threshold voltage Vth distributions for a sixteen-state memory device is depicted in which each memory cell stores four bits of data. A first threshold voltage Vth distribution 530 is provided for erasing Er state storage elements. Fifteen threshold voltage Vth distributions 532, 534, 536, 538, 540, 542, 544, 546, 548, 550, 552, 554, 556, 558, and 560 represent programmed memory states S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, and S15, respectively.

[0102] A 4-bit code with a lower page bit, a middle page bit, an upper page bit, and a top page bit may be used to represent each of the sixteen memory states. In an embodiment, the S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, and S15 memory states are represented by "1111", "1110", "1100", "1101", "1001", "0001", "0101", "0100", "0110", "0010", "0000", "1000", "1010", "1011", "0011", and "0111", respectively.

[0103] In addition to full sequence programming, the techniques described herein may also be used with other types of programming, including but not limited to multi-level programming / multi-phase programming. In some embodiments, the programmed states (e.g., S1-S15) may overlap, in which case the controller 120 ( Figure 1 ) relies on error correction to identify the correct data stored.

[0104] Figure 6 2 is a flow chart describing one embodiment of a process for programming a memory cell. For the purposes of this document, the term programming is synonymous with writing. In an exemplary embodiment, one or more control circuits (e.g., system control logic 260, column control circuit 210, row control circuit 220) discussed above are used to perform a program for memory structure 202. Figure 6 In one exemplary embodiment, the integrated memory component 207 uses one or more control circuits (e.g., system control logic 260, column control circuit 210, row control circuit 220) of the control die 211 to program the memory cells on the memory structure die 201 to perform Figure 6 The process consists of multiple cycles, each cycle includes a programming phase and a verification phase. Figure 6 The process can be used to implement full sequence programming and other programming schemes including multi-level programming. When implementing multi-level programming, Figure 6 The process is used to implement any / each level of the multi-level programming process.

[0105] Typically, the program voltage applied to the control gate (via a selected data word line) during a program operation is applied as a series of program pulses (e.g., voltage pulses). Between programming pulses, a set of verify pulses (e.g., voltage pulses) may be used to perform verification. In many implementations, the magnitude of the program pulses increases by a predetermined step size with each successive pulse. Figure 6 In step 602, the programming voltage signal (Vpgm) is initialized to a starting value (e.g., about 12V to 16V or another suitable level), and the programming counter PC maintained by the state machine 262 is initialized to 1. In one embodiment, a group of memory cells selected for programming (referred to herein as selected memory cells) are programmed simultaneously and are all connected to the same word line (the selected word line). There may be other memory cells (unselected memory cells) that are not selected for programming that are also connected to the selected word line. That is, the selected word line will also be connected to the memory cells that should be prohibited from programming. In addition, when the memory cells reach their intended target data state, they will be prohibited from further programming. These NAND strings (e.g., unselected NAND strings) have their channels boosted to prohibit programming, and these strings include memory cells that are connected to the selected word line to be prohibited from programming. When the channel has an elevated voltage, the voltage difference between the channel and the word line is not enough to cause programming. To help boost, in step 604, the control die precharges the channels of the NAND strings that include memory cells connected to the selected word line that will be prohibited from programming. In step 606, NAND strings including memory cells connected to the selected word line to be inhibited from programming have their channels boosted to inhibit programming. Such NAND strings are referred to herein as "unselected NAND strings". In one embodiment, the unselected word lines receive one or more boost voltages (e.g., about 7 volts to 11 volts) to perform the boosting scheme. The program inhibit voltage is applied to the bit lines coupling the unselected NAND strings.

[0106] In step 608, a program voltage pulse of a programming voltage signal Vpgm is applied to the selected word line (the word line selected for programming). If the memory cell on the NAND string should be programmed, the corresponding bit line is biased at a programming enable voltage. In step 608, a program pulse is applied simultaneously to all memory cells connected to the selected word line so that all memory cells connected to the selected word line are programmed simultaneously (unless they are prohibited from programming). That is, they are programmed at the same time or during overlapping time (both are considered to be simultaneous). In this way, all memory cells connected to the selected word line will have their threshold voltage changes at the same time unless they are prohibited from programming.

[0107] In step 610, program verification is performed and the memory cell that has reached its target state is locked out from further programming by the control die. Step 610 includes performing verification of programming by sensing at one or more verification reference levels. In one embodiment, the verification process is performed by testing whether the threshold voltage of the memory cell selected for programming has reached the appropriate verification reference voltage. In step 610, after the memory cell has been verified (by testing of Vt) that the memory cell has reached its target state, the memory cell can be locked out. For example, if the memory cell reaches the verification reference voltage, it can be locked out.

[0108] If, in step 612, it is determined that all memory cells have reached their target threshold voltage (PASS), then the programming process is complete and successful because all selected memory cells have been programmed and verified to their target states. In step 614, a "PASS" status is reported. Otherwise, if, in step 612, it is determined that not all memory cells have reached their target threshold voltage (FAIL), then the programming process will continue to step 616.

[0109] In step 616, the number of memory cells that have not yet reached their respective target threshold voltage distribution is counted. That is, the number of memory cells that have so far failed to reach their target state is counted. This counting may be done by the state machine 262, the memory controller 120, or another circuit. In one embodiment, there is a total count that reflects the total number of memory cells currently being programmed that have failed the last verification step. In another embodiment, a separate count is maintained for each data state.

[0110] In step 618, it is determined whether the count from step 616 is less than or equal to a predetermined limit. In one embodiment, the predetermined limit is the number of bits that can be corrected by an error correction code (ECC) during the read process of a page of memory cells. If the number of failed cells is less than or equal to the predetermined limit, the programming process can stop and report a "pass" status in step 614. In this case, enough memory cells are correctly programmed so that the remaining few memory cells that have not been fully programmed can be corrected using ECC during the read process. In some embodiments, the predetermined limit used in step 618 is lower than the number of bits that can be corrected by an error correction code (ECC) during the read process to allow for future / additional errors. When programming less than all memory cells of a page, or comparing counts of only one data state (or less than all states), the predetermined limit can be a portion (proportional or non-proportional) of the number of bits that can be corrected by ECC during the read process of a page of memory cells. In some embodiments, the limit is not predetermined. Instead, it changes based on the number of errors that have been counted for the page, the number of program-erase cycles performed, or other criteria.

[0111] If the number of failed memory cells is not less than the predetermined limit, the programming process continues at step 620 and checks the programming counter PC against the programming limit value (PL). Examples of programming limit values ​​include 6, 12, 16, 19, 20, and 30; however, other values ​​may be used. If the programming counter PC is not less than the programming limit value PL, the programming process is considered to have failed and a "failed" status is reported in step 624. If the programming counter PC is less than the programming limit value PL, the process continues at step 626, during which the programming counter PC is incremented by 1 and the programming voltage signal Vpgm is stepped to the next magnitude. For example, the next pulse will have a magnitude that is a step size ΔVpgm (e.g., a step size of 0.1 volts to 1.0 volts) larger than the previous pulse. After step 626, the process loops back to step 604 and another program pulse is applied to the selected word line to perform a program. Figure 6 Another iteration of the programming process (steps 604-626).

[0112] In one embodiment, the memory cells are erased prior to programming, and erasing is the process of changing the threshold voltage of one or more memory cells from a programmed data state to an erased data state. Figure 5A The state AC changes to state E, from Figure 5B The state AG changes to the state Er, or from Figure 5C State S1-S15 is changed to state Er.

[0113] Techniques for reconfiguring a word line to operate as a dummy word line in a sub-block mode and as a data word line in a full-block mode are disclosed herein. Figure 7 Flowchart of one embodiment of a process 700 for operating a block in sub-block mode and full block mode. In one embodiment, in a three-dimensional memory structure, a block includes a large number of NAND strings. In one embodiment, a block has three levels, such as, for example, an upper level 421, a middle level 423, and a lower level 425. A group of reconfigurable word lines may reside in the middle level. Process 700 may be performed by one or more control circuits (e.g., memory controller 120, state machine 262, power control 264, all or a portion of system control logic 260, all or a portion of row control circuit 220, all or a portion of column control circuit 210, or any combination thereof).

[0114] Step 702 includes determining whether to operate in sub-block mode or full block mode. In one embodiment, blocks in storage system 100 are operated in sub-block mode or full block mode for an extended period of time. For example, a block may undergo many program / erase cycles in one mode. However, the mode in which a given block operates may be switched between sub-block mode and full block mode. With respect to blocks in memory structure 202, it is possible that, at a certain point in time, all blocks operate in full block mode, all blocks operate in sub-block mode, or some operate in full block mode and some operate in sub-block mode.

[0115] Step 704 includes operating a block in the three-dimensional memory structure in a sub-block mode in which the group of reconfigurable word lines are used as dummy word lines that provide electrical isolation between the upper sub-block and the lower sub-block. Step 704 may include erasing the upper sub-block independently of the lower sub-block, in which case the group of reconfigurable word lines provides electrical isolation between the upper sub-block and the lower sub-block. In the sub-block mode, the group of reconfigurable word lines is not programmed.

[0116] Step 706 includes operating a block in the three-dimensional memory structure in a full block mode in which the group of reconfigurable word lines is used as a data word line. Step 704 may include erasing the entire block together. For example, memory cells connected to data word lines WL0-WL267 and memory cells connected to a group of reconfigurable word lines (e.g., WLRC1, WLRC2, WLRC3, WLRC4) may be erased as a unit. Step 704 may include programming the memory cells connected to the group of reconfigurable word lines.

[0117] In some embodiments of process 700, the blocks each have three levels with a first interface layer (IF1) and a second interface layer (IF2). In addition, the lower level 425 has a dummy WL adjacent to IF1, the middle level 423 has a lower dummy WL adjacent to IF1 and an upper dummy WL adjacent to IF2, and the upper level 421 has a dummy WL adjacent to IF2. These dummy word lines operate as dummy WLs in sub-block mode (step 704) and full block mode (step 706).

[0118] Now refer to Fig. 8A and Figure 8B , in order to discuss the advantages of operating with reconfigurable word lines in sub-block mode or full-block mode. Fig. 8A A full block mode example is depicted in which a memory system is provided to provide a user with 1 terabyte (1Tb) of available storage. The primary blocks 802 represent a number of blocks sufficient to provide 1Tb of storage when operating in full block mode. The memory system will also have some extended blocks 804. One use of the extended blocks is to provide for the possibility that some of the blocks in the primary blocks 802 may fail. Some of the blocks in the primary blocks 802 may be determined to be bad blocks during testing in the factory. Some of the blocks in the primary blocks 802 may fail during operation, which is referred to as growing bad blocks. Another possible use of the extended blocks is to consider using some of the blocks as SLC blocks, which have a lower storage capacity per block than the storage capacity per block of MLC blocks. Still another possible use of the extended blocks is to give more consideration to write amplification. As Fig. 8A As an example, the number of extended blocks 804 amounts to about 10% of the number of primary blocks 802 .

[0119] Figure 8BAn example of a sub-block mode is depicted. A sub-block can be twice as large as a full block. However, due to the fact that the reconfigurable word line is not used for data storage in the sub-block mode, the combined storage capacity of the two blocks in the sub-block is slightly smaller than the combined storage capacity of a single full block. Therefore, in the sub-block mode, several more blocks may be needed to provide a total user storage capacity of 1Tb. This is indicated by dividing the main sub-block 812 into a group of blocks that provide 0.98Tb and a group that provides the remaining 0.02Tb. In other words, the storage capacity provided by the same number of blocks in the sub-block mode is slightly smaller than the storage capacity provided in the full block mode. For example, the number of blocks in the main block 802 used in the full block mode can only provide about 0.98Tb of user storage in the sub-block mode. This 0.02Tb shortage can be compensated by using some of the blocks that may have been used as an extended sub-block pool. However, this reduces the number of blocks in the extended sub-block pool 814, which may be only about 8% of the number of blocks as main sub-blocks. However, due to the fact that a sub-block may be twice as large as a full block, the number of extended sub-blocks 814 may be much larger than the number of extended blocks 804 for full block mode. For example, there may be about 43 full blocks in the extended block 804, but there may be about 68 sub-blocks in the extended sub-block 814. This larger number of extended sub-blocks 814 allows the total storage of the extended sub-blocks 814 to be a smaller percentage of the storage of the main sub-block 814 than in full block mode.

[0120] In one embodiment, the memory controller 120 manages the blocks in the storage system 100 in full block mode and half block mode. In full block mode, there are x blocks to provide the target storage amount for the user, and in half block mode, there are more than 2x half blocks to provide the target storage amount for the user. However, the storage capacity of each half block is less than half of the storage capacity of the full block. For example, the full block mode main pool 802 of x blocks can provide the storage capacity of 1Tb for the user, and the half block mode main pool 812 of 2x+y half blocks can provide the storage capacity of 1Tb for the user (wherein y half blocks illustrate, for example, 0.02Tb is insufficient). In this example, x and y are integers greater than 0. In addition, the memory controller 120 manages the extended block pool in the storage system 100 in both full block mode and half block mode. The number of half blocks that the block pool 814 extended by the half block mode has can be less than twice the number of full blocks in the block pool 814 extended by the full block mode. However, the half block mode extended block pool 814 has more half blocks than the full blocks in the full block mode extended block pool 804. For example, there may be p full blocks in the full block mode extended block pool 804, but there may be p+q half blocks in the half block mode extended block pool 814. In this example, p and q are integers greater than 0. This is advantageous because a full block can replace a failed full block in the full block mode main block pool 802; however, a half block can replace a failed half block in the half block mode main block pool 812.

[0121] Fig. 9 Flow chart of one embodiment of process 900 for erasing NAND in sub-block mode or full block mode. Process 900 can be performed by one or more control circuits. In one embodiment, erasing of a memory cell includes applying an erase enable voltage (e.g., 0V) to the control gate of the memory cell while applying an erase voltage (e.g., about 20V) to the channel or body of the memory cell. The erase voltage is defined herein as a voltage that will erase the memory cell, provided that the erase enable voltage is also applied to different regions of the memory cell. The erase enable voltage is defined herein as a voltage that will enable erasing the memory cell, provided that the erase voltage is also applied to different regions of the memory cell. A memory cell to which an erase voltage has been applied to its channel (body) can be prohibited from being erased by applying an erase prohibition voltage (e.g., an erase voltage or about 20V) to its control gate. The erase prohibition voltage is defined herein as a voltage that will prohibit erasing the memory cell, despite the application of an erase voltage to different regions of the memory cell.

[0122] One technique for erasing memory cells is to bias the p-well substrate to a high voltage to charge the NAND channel. When the NAND channel is at a high voltage, an erase enable voltage is applied to the control gate of the memory cell to erase the memory cell. In one embodiment, p-well erasure is performed. In some cases, the NAND strings within a block can share a common well (e.g., a p-well). In p-well erasure, holes can be provided from the p-well located below the NAND string in the substrate. In one embodiment, the memory cell can be erased by raising the p-well to an erase voltage (e.g., 20 volts) for a sufficient period of time and grounding the word line connected to the memory cell to be erased. These erase bias conditions may cause electrons to transfer from the charge trapping layer or film 463 through the tunneling oxide 464, thereby reducing the threshold voltage of the memory cell in the selected block.

[0123] Another method of erasing a memory cell is to generate a gate induced drain leakage (GIDL) current to charge the NAND string channel. An erase enable voltage is applied to the control gate of the memory cell while maintaining the string channel potential to erase the memory cell. In one embodiment, the GIDL current is generated by causing a drain-gate voltage at the select transistor. The GIDL current can be generated when the select transistor drain voltage is significantly higher than the select transistor control gate voltage. The GIDL current is the result of carrier generation, that is, electron-hole pair generation and / or trap-assisted generation due to band-band tunneling. In one embodiment, the GIDL current can cause one type of carrier (e.g., hole) to move primarily into the NAND channel 465, thereby raising the potential of the channel 465. Another type of carrier (e.g., electron) is extracted from the channel 465 by an electric field in the direction of the bit line or in the direction of the source line. During erasure, holes can tunnel from the channel to the charge storage region 463 of the memory cell and recombine with electrons there to reduce the threshold voltage of the memory cell.

[0124] Step 902 includes selecting a block (or sub-block) to be erased. Step 904 is a branch depending on whether the erase is for full block mode or sub-block mode. Steps 906-914 describe an embodiment of a full block erase performed in full block mode. Step 906 includes setting the reconfigurable WL to the data WL. In one embodiment, the memory controller 120 sets the reconfigurable WL to the data WL by specifying the block for full block mode. Note that the block may have been previously specified for full block mode.

[0125] Step 908 includes applying an erase voltage to the channels of the NAND strings in the block. Step 910 includes applying an erase enable voltage to all data WLs (including reconfigurable WLs) in the block. Thus, the voltages applied in steps 908 and 910 will erase the memory cells in the block. Step 912 includes erase verification. The erase verification may apply, for example, VvEr (see Figure 5A-Figure 5C ). If the Vt of all memory cells on the NAND string is lower than VvEr, the NAND string will conduct a large current. In some embodiments, if the NAND string passes, the erasure of the NAND string can end at this time. Step 914 is to determine whether the erasure is complete. Then repeat steps 908-812. Optionally, the magnitude of the erase voltage can be increased at each iteration. When all NAND strings have passed, the erasure ends. In some embodiments, the erasure can end when several NAND strings have not passed the erasure. Steps 908-912 are performed in one embodiment of step 706 of process 700.

[0126] Steps 916-928 describe one embodiment of a sub-block erase performed in sub-block mode. Step 916 includes setting the reconfigurable WL to a dummy WL. In one embodiment, the memory controller 120 sets the reconfigurable WL to a dummy WL by specifying a block for sub-block mode. Note that the block may have been previously specified for sub-block mode.

[0127] Step 918 includes applying an erase voltage to the channel of the NAND string in the block. Step 920 includes applying an erase enable voltage to all data WLs in the selected sub-block. Step 922 includes applying an erase prohibition voltage to all data WLs in the unselected sub-block. Step 924 includes applying an erase isolation voltage to all reconfigurable WLs. The magnitude of the erase isolation voltage is between the magnitude of the erase enable voltage and the magnitude of the erase prohibition voltage. The erase isolation voltage can be about half of the erase enable voltage and the erase prohibition voltage. In one embodiment, the erase isolation voltage is about 8V less than the erase voltage (e.g., 20V-8V=12V). Therefore, the voltage applied in steps 908-924 will erase the memory cells in the selected sub-block while preventing any memory cells in the unselected sub-block from being erased. Step 926 includes erase verification. An erase verification voltage (e.g., VvEr) can be applied to each data WL in the selected sub-block. A read pass voltage can be applied to each data WL in the unselected sub-block. The read pass voltage is higher than the Vt of the highest data state, so that the read pass voltage will be higher than the Vt of any storage area cell in the memory cells in the unselected sub-block. If the Vt of all memory cells on a portion of the NAND string located in the selected sub-block is lower than VvEr, the NAND string will conduct a large current. In some embodiments, if the NAND string passes, the erase of the NAND string can end at this time. Optionally, if the erase has not passed (step 928 = no), the magnitude of the erase voltage can be increased, and then steps 918-926 are repeated. When all NAND strings in the selected sub-block have passed the erase (step 928 = yes), the process ends. In some embodiments, the erase can end when several NAND strings have not passed the erase. Steps 918-926 are performed in one embodiment of step 704 of process 700.

[0128] Fig.101 is a flow chart of an embodiment of a process 1000 for programming NAND cells in sub-block mode or full block mode. Process 1000 may be performed by one or more control circuits. Process 1000 may be used for SLC or MLC programming. Step 1002 includes selecting a block (or sub-block) to be programmed. Step 1004 is a branch depending on whether the erase is for full block mode or sub-block mode. In the case where the step is full block programming, step 1006 includes setting the reconfigurable WL to the data WL. In one embodiment, the memory controller 120 sets the reconfigurable WL to the data WL by specifying the block for full block mode. Note that the block may have been previously specified for full block mode.

[0129] Step 1008 includes programming all data WLs (including reconfigurable WLs). The phrase "programming data WLs" means programming the data memory cells connected to the data WLs to their corresponding target data states. Figure 6 The process in 1000 programs the data WL one WL at a time. The data WL can be programmed sequentially from the drain to the source of the NAND string or from the source to the drain of the NAND string. In one implementation of step 704 of process 700, step 1008 is performed.

[0130] In the case where the step is sub-block programming, then step 1010 includes setting the reconfigurable WL to the data WL. In one embodiment, the memory controller 120 sets the reconfigurable WL to the dummy WL by designating the block for sub-block mode. Note that the block may have been previously designated for sub-block mode.

[0131] Step 1012 includes programming all data WL in the upper sub-block. Figure 6 The process in the program programs the data WL one WL at a time. The data WLs in the upper sub-block can be programmed sequentially in the order of source to drain. For example, the upper sub-block can be programmed from WL134 to WL267.

[0132] Step 1014 includes programming all data WL in the lower sub-block. Figure 6 The process in 700 programs the data WL one WL at a time. The data WL in the lower sub-block can be programmed sequentially in the order of drain to source. For example, the lower sub-block can be programmed from WL133 to WL0. In one embodiment of step 706 of process 700, steps 1012 and 1014 are performed.

[0133] As combined Figure 6As discussed in step 604 of , programming the memory cell may have a channel precharge. In some embodiments, the direction of precharging the channel in the sub-block mode depends on whether the upper sub-block or the lower sub-block is being programmed. Fig.11A The NAND strings are shown being precharged during programming of the upper sub-block. Fig.11A An exemplary NAND string is shown connected to a bit line 411 at the drain terminal and to a source line (SL) at the source terminal. Fig.11A It is shown that when programming the upper sub-block, the NAND channel is precharged by Iprecgh starting from the bit line. In addition, in one embodiment, the word lines in the upper sub-block are programmed sequentially from WL134 to WL267. Therefore, when programming the memory cells connected to the selected word line in the upper sub-block, the memory cells connected to the word line located between the selected word line and the bit line will still be in an erased state, which promotes channel precharge.

[0134] Fig. 11B The NAND strings are shown being precharged during programming of the lower sub-block. Fig. 11B It is shown that when programming the lower sub-block, the NAND channel is precharged by Iprecgh starting from the source line. In addition, in one embodiment, the word lines in the lower sub-block are programmed sequentially from WL133 to WL0. Therefore, when programming the memory cells connected to the selected word line in the lower sub-block, the memory cells connected to the word line located between the selected word line and the source line will still be in an erased state, which promotes channel precharge.

[0135] In one embodiment of the full block mode, along Fig.11A The NAND channel is precharged in the direction depicted in FIG. 1 and the word lines are programmed in order from WL0 to WL267. In one embodiment of the full block mode, the word lines are programmed in the order from WL0 to WL267. Fig. 11B The NAND channel is precharged in the direction depicted in , and the word lines are programmed in order from WL267 to WL0.

[0136] One issue that needs to be noted is that in the case where the block is to be operated in a three-sub-block mode in which three sub-blocks correspond to three levels, there may be technical challenges in properly precharging the NAND channel in the middle sub-block. For example, in the case of programming a memory cell located in the upper level, there may be technical challenges in precharging the NAND channel starting from the bit line. Similarly, in the case of programming a memory cell located in the lower level, there may be technical challenges in precharging the NAND channel starting from the source line. Therefore, in the case of programming both the upper level and the lower level, there are technical challenges in precharging the NAND channel when programming the middle level. Therefore, the use of two sub-blocks helps to overcome this technical challenge. However, when the three-level block is divided into two sub-blocks, the dummy WL adjacent to the interface layer (IFDL1, IFDU1, IFDL1, IFDU1) is not in an appropriate position to provide electrical isolation between the upper sub-block and the lower sub-block. When in sub-block mode, the reconfigurable word lines can provide electrical isolation between the upper sub-block and the lower sub-block. In addition, the reconfigurable word lines can operate as data word lines in full block mode to increase the storage capacity for full block mode. In addition, because the number of sub-blocks in the sub-block extended pool 814 can be greater than the number of full blocks in the full block extended pool 804, the storage system 100 can be provided with fewer blocks and still meet user storage requirements in both full block mode and sub-block mode.

[0137] Fig.12 Depicted is a table 1200 describing bias conditions applied to word lines during programming in one embodiment of sub-block mode. Table 1200 lists exemplary bias conditions for eight different word lines (WL0, WL89, WL90, WL133, WL134, WL177, WL178, and WL267) that are programmed at different times. In one embodiment, WL0-WL133 are located in the lower sub-block. In one embodiment, WL134-WL257 are located in the upper sub-block. Table 1200 describes the bias conditions for the ... Figure 4D and Figure 4F The example in the example has a consistent three-level structure.

[0138] As depicted in Table 1200, when programming the memory cells in the lower sub-block connected to word line WL0, VPGM (e.g., 12V to 20V) is applied to WL0, while a boost voltage (e.g., Vpass1, Vpass2, Vpass3) is applied to the unselected word lines WL1 to WL267. A boost voltage is also applied to the reconfigurable word lines (WL_RC1, WL_RC2, WL_RC3, and WL_RC4) that operate as dummy word lines. The boost voltage will increase the potential of the disabled NAND string. The disabled NAND string is a NAND string in which the memory cells connected to the word line to which the program voltage is applied are prohibited from being programmed. The channel of the disabled NAND string is floating; therefore, the boost voltage will be paired with the channel potential, thereby inhibiting the programming of the memory cells connected to the word line to which the program voltage is applied. When programming the memory cells connected to other word lines, the bias conditions can be similar.

[0139] Fig.13A 1 is a flow chart of one embodiment of a process 1300 for programming memory cells in an upper sub-block. The process 1300 may be performed by one or more control circuits. Step 1302 includes setting the selected word line to WL 134. Step 1304 includes precharging the NAND channel starting with the bit line (see Fig.11A ). Step 1306 includes applying a boost voltage (e.g., Vpass) to the unselected WLs. Step 1308 includes applying a boost voltage (e.g., Vpass) to the reconfigurable WLs. The boost voltage may have different magnitudes depending on its position relative to the selected WL. For example, referring to Fig.12 , Vpass3 can be used for word lines adjacent to the selected word line, Vpass2 can be used for other word lines between the selected word line and the bit line, and Vpass1 can be used for other word lines between the selected word line and the source line. Step 1310 includes applying a program pulse to the selected WL. Voltages are applied to each WL simultaneously in 1306-1310. Step 1312 is to determine whether programming of the selected WL is complete. Step 1312 includes the following steps: Figure 6 Steps 1304-1310 are repeated until programming of the selected WL is complete. Step 1314 is to determine if there is another WL to be programmed in the upper sub-block. If so, then in step 1316, the number of the selected WL is incremented. Then, steps 1304-1312 are repeated for this selected WL. When all data word lines in the upper sub-block have been programmed, the process ends. Note that process 1300 is performed using Figure 4D and Figure 4F An exemplary number of word lines in a sub-block is described, but other numbers of word lines in a sub-block are contemplated.

[0140] Fig. 13B 13 is a flow chart of one embodiment of a process 1350 for programming memory cells in a lower sub-block. The process 1350 may be performed by one or more control circuits. Step 1352 includes setting the selected word line to WL133. Step 1354 includes precharging the NAND channel starting from the source line (see Fig. 11B ). Step 1356 includes applying a boost voltage (e.g., Vpass) to the unselected WLs. Step 1358 includes applying a boost voltage (e.g., Vpass) to the reconfigurable WLs. Step 1360 includes applying a program pulse to the selected WL. Voltages are applied to each WL simultaneously in 1356-1360. Step 1362 is to determine whether programming of the selected WL is complete. Step 1362 includes the following steps: Figure 6 Steps 1354-1360 are repeated until programming of the selected WL is complete. Step 1364 is to determine if there is another WL to be programmed in the lower sub-block. If so, then in step 1366, the number of selected WLs is decremented. Steps 1354-1362 are then repeated for this selected WL. When all data word lines in the lower sub-block have been programmed, the process ends. Note that process 1350 is performed using Figure 4D and Figure 4F An exemplary number of word lines in a sub-block is described, but other numbers of word lines in a sub-block are contemplated.

[0141] Fig.14A 14 is a flow chart of one embodiment of a process 1400 for programming memory cells in full block mode. The process 1400 may be performed by one or more control circuits. Step 1402 includes setting the selected word line to WL0. Step 1404 includes precharging the NAND channel starting with the bit line. Step 1406 includes applying a boost voltage (e.g., Vpass) to the unselected data WL. Step 1408 includes applying a boost voltage (e.g., Vpass) to the currently unselected reconfigurable WL. That is, when the reconfigurable WL is the selected word line, no boost voltage is applied to it. Fig.12 Similar to the scheme in , the boost voltage can have different magnitudes depending on its position relative to the selected WL. For example, Vpass3 can be used for word lines adjacent to the selected word line, Vpass2 can be used for other word lines located between the selected word line and the bit line, and Vpass1 can be used for other word lines between the selected word line and the source line. Step 1410 includes applying a program pulse to the selected WL. Voltages are applied to each WL simultaneously in 1406-1410. Step 1412 is to determine whether programming of the selected WL is complete. Step 1412 includes the following. Figure 6Steps 1404-1410 are repeated until programming of the selected WL is complete. Step 1414 is to determine if there is another WL to be programmed in the block. If so, then in step 1416, the selected WL is set to be the next WL in sequence. In one embodiment, the sequence proceeds from WL0 to WL133, then the reconfigurable WL, then WL134 to WL267. Steps 1404-1412 are then repeated for this selected WL. When all word lines in the block have been programmed, the process ends. Note that process 1400 is performed using Figure 4D and Figure 4F An exemplary number of word lines in a sub-block is described, but other numbers of word lines in a sub-block are contemplated.

[0142] Fig. 14B 14 is a flow chart of an embodiment of a process 1450 for programming memory cells in full block mode. Process 1450 can be performed by one or more control circuits. Step 1452 includes setting the selected word line to WL0. Step 1454 includes precharging the NAND channel starting from the source line. Step 1456 includes applying a boost voltage (e.g., Vpass) to an unselected data WL. Step 1458 includes applying a boost voltage (e.g., Vpass) to a reconfigurable WL that is not currently selected. Step 1460 includes applying a program pulse to the selected WL. Voltage is applied to each WL simultaneously in 1456-1460. Step 1462 is to determine whether the programming of the selected WL is completed. Repeat steps 1454-1460 until the programming of the selected WL is completed. Step 1464 is to determine whether there is another WL to be programmed in the block. If so, in step 1466, the selected WL is set to the next WL in sequence. In one embodiment, the order proceeds from WL267 to WL134, then the reconfigurable WL, then WL133 to WL0. Steps 1454-1462 are then repeated for this selected WL. When all word lines in the block have been programmed, the process ends. Note that process 1450 is performed using Figure 4D and Figure 4F An exemplary number of word lines in a sub-block is described, but other numbers of word lines in a sub-block are contemplated.

[0143] In view of the foregoing, a first embodiment includes a device for one or more three-dimensional memory structures. Each three-dimensional memory structure includes blocks having word lines and NAND strings. The NAND strings in the block include memory cells connected to the word lines of the block. The word lines include a first set of data word lines located in a first region of the block, a second set of data word lines located in a second region of the block, and reconfigurable word lines located between the first set and the second set. The device includes one or more control circuits that communicate with the one or more memory structures. The one or more control circuits are configured to operate the first block in a sub-block mode, in which the reconfigurable word lines in the first block are used as dummy word lines, which provide electrical isolation between the first region and the second region in the first block. In the sub-block mode, the first region includes an upper sub-block, and the second region includes a lower sub-block. The one or more control circuits are configured to operate the second block in the memory structure in a full block mode, in which the reconfigurable word lines in the second block are used as data word lines.

[0144] In a second embodiment, based on the first embodiment, the one or more control circuits are further configured to operate the memory cells connected to the reconfigurable word lines in the first block as dummy memory cells in the sub-block mode, which are not programmed. The one or more control circuits are further configured to operate the memory cells connected to the reconfigurable word lines in the second block as data memory cells in the full block mode, which are programmed.

[0145] In a third embodiment, on the basis of the first embodiment or the second embodiment, each block includes an upper level, an intermediate level and a lower level. Each block includes a first interface layer and a second interface layer, the first interface layer is located between the lower level and the intermediate level, and the second interface layer is located between the intermediate level and the upper level. The lower level includes a dummy word line adjacent to the first interface layer, the intermediate level includes a lower dummy word line adjacent to the first interface layer, the intermediate level includes an upper dummy word line adjacent to the second interface layer, and the upper level includes a dummy word line adjacent to the second interface layer. The reconfigurable word lines reside in the intermediate level, wherein the first plurality of data word lines in the first set of these data word lines are located between the reconfigurable word lines and the lower dummy word line of the intermediate level, and the second plurality of data word lines in the second set of these data word lines are located between the reconfigurable word lines and the upper dummy word line of the intermediate level.

[0146] In a fourth embodiment, based on any one of the first to third embodiments, the one or more control circuits are configured to independently erase the first memory cells connected to the first set of data word lines and the second memory cells connected to the second set of data word lines in the first block when in the sub-block mode, including operating the reconfigurable word lines as dummy word lines to provide electrical isolation between the first set and the second set of data word lines during erasure of the first memory cells and during erasure of the second memory cells in the sub-block mode. The one or more control circuits are configured to erase the memory cells in the second block connected to both the first set and the second set of data word lines and the memory cells in the second block connected to the reconfigurable word lines as a unit when in the full block mode.

[0147] In a fifth embodiment, based on any one of the fourth embodiments, the one or more control circuits are configured to perform the following operations in the sub-block mode: applying an erase voltage to the channels of the NAND strings of the first block; applying an erase enable voltage to the data word lines in a selected sub-block of the first block, wherein the selected sub-block includes the lower sub-block or the upper sub-block; applying an erase inhibit voltage to the data word lines in an unselected sub-block of the first block, wherein the unselected sub-block includes the other of the lower sub-block or the upper sub-block; and applying an erase isolation voltage to the reconfigurable word lines in the first block to provide electrical isolation between the selected sub-block and the unselected sub-block, wherein the magnitude of the erase isolation voltage is between the magnitude of the erase enable voltage and the magnitude of the erase inhibit voltage.

[0148] In a sixth embodiment, based on the fifth embodiment, the one or more control circuits are further configured to perform the following operations in the full block mode: apply the erase voltage to the channels of the NAND strings of the second block; and apply the erase enable voltage to the first set and the second set of these data word lines in the second block and the reconfigurable word lines in the second block.

[0149] In a seventh embodiment, based on any one of the first to sixth embodiments, the one or more control circuits are further configured to operate the second block in the sub-block mode, in which the reconfigurable word lines are used as dummy word lines that provide electrical isolation between the first set of data word lines and the second set of data word lines in the second block.

[0150] In an eighth embodiment, based on any one of the first to seventh embodiments, the first block is associated with a plurality of bit lines and one or more source lines. The one or more control circuits are further configured to precharge the channels of the NAND strings in the first block from the bit lines when programming the upper sub-block in the sub-block mode. The one or more control circuits are further configured to precharge the channels of the NAND strings in the first block from the one or more source lines when programming the lower sub-block in the sub-block mode.

[0151] In a ninth embodiment, based on the eighth embodiment, the one or more control circuits are further configured to program the first set of data word lines in the sub-block mode in a drain-to-source order, wherein the first set of data word lines resides in the lower sub-block. The one or more control circuits are further configured to program the second set of data word lines in the sub-block mode in a source-to-drain order, wherein the second set of data word lines resides in the upper sub-block.

[0152] In a tenth embodiment, based on any one of the first to ninth embodiments, the one or more control circuits are further configured to, in the sub-block mode, apply a boost voltage to the reconfigurable word lines in the first block and simultaneously apply a programming voltage to the selected word lines in the first block.

[0153] In an eleventh embodiment, based on any one of the first to tenth embodiments, the one or more control circuits are further configured to manage a full block master block pool having x full blocks in the full block mode, wherein the x full blocks provide a target storage amount. The one or more control circuits are further configured to manage a half block master block pool having 2x+y sub-blocks in the sub-block mode, wherein x and y are integers greater than 0, wherein the 2x+y sub-blocks provide the target storage amount.

[0154] In a twelfth embodiment, based on the eleventh embodiment, the one or more control circuits are further configured to manage a full block extended block pool with p full blocks in the full block mode. These x full blocks and the p full blocks include all blocks in the one or more memory structures. The one or more control circuits are further configured to manage a half block extended block pool with p+q sub-blocks in the sub-block mode, where p and q are integers greater than 0. These 2x+y sub-blocks and the p+q sub-blocks include all blocks in the one or more memory structures.

[0155] One embodiment includes a method for operating a non-volatile storage system. The method includes operating a block having NAND strings and word lines in a half NAND string mode, in which a group of word lines in the block provides electrical isolation between a first set of data word lines connected to memory cells located on a bottom segment of the NAND strings and a second set of data word lines connected to memory cells located on a top segment of the NAND strings, including erasing the memory cells connected to the first set of data word lines independently of erasing the memory cells connected to the second set of data word lines, while biasing the group of word lines to provide electrical isolation between the first set and the second set of data word lines. The method includes operating the block in a full NAND string mode, including erasing the memory cells connected to the first set of data word lines, the memory cells connected to the second set of data word lines, and the memory cells connected to the group of word lines as a unit.

[0156] One embodiment includes a non-volatile storage system. The system includes one or more three-dimensional memory structures, wherein each memory structure includes a block having a word line and a NAND string. The NAND strings in the block include memory cells connected to the word lines of the block. Each block includes three levels, wherein each level includes different sections of each NAND string, wherein the three levels include a lower level, an intermediate level, and an upper level. Each block includes a first interface layer and a second interface layer, the first interface layer having a first manufacturing joint, and the second interface layer having a second manufacturing joint. The first manufacturing joints are configured to electrically connect the channel of the section of the corresponding NAND string located in the lower level to the corresponding channel of the section of the corresponding NAND string located in the intermediate level. The second manufacturing joints are configured to electrically connect the channel of the section of the corresponding NAND string located in the intermediate level to the corresponding channel of the section of the corresponding NAND string located in the upper level. The system includes means for operating the one or more memory structures in a half-block mode, in which the group of word lines located in the middle level is used as a dummy word line. In the sub-block mode, the memory cells connected to the group are not programmed. A first plurality of data word lines resides between the group and the first manufacturing contacts, and a second plurality of data word lines resides between the group and the second manufacturing contacts. The system includes means for operating the one or more memory structures in a full-block mode, in which the group located in the middle level is used as a data word line, wherein the memory cells connected to the group are programmed in the full-block mode.

[0157] In one embodiment, the apparatus for operating the one or more three-dimensional memory structures in half-block mode includes one or more of a memory controller 120, a system control logic unit 206, a state machine 262, a column control circuit 210, a row control circuit 220, a processor, an FPGA, an ASIC, and / or an integrated circuit. In one embodiment, the apparatus for operating the one or more three-dimensional memory structures in half-block mode performs steps 916-926 of process 900. In one embodiment, the apparatus for operating the one or more three-dimensional memory structures in half-block mode performs steps 1010-1014 of process 1000. In one embodiment, the apparatus for operating the one or more three-dimensional memory structures in half-block mode performs process 1300. In one embodiment, the apparatus for operating the one or more three-dimensional memory structures in half-block mode performs process 1350.

[0158] In one embodiment, the apparatus for operating the memory structure in full block mode includes one or more of a memory controller 120, a system control logic unit 206, a state machine 262, a column control circuit 210, a row control circuit 220, a processor, an FPGA, an ASIC, and / or an integrated circuit. In one embodiment, the apparatus for operating the one or more three-dimensional memory structures in full block mode performs steps 906-912 of process 900. In one embodiment, the apparatus for operating the one or more three-dimensional memory structures in sub-block mode performs steps 1006-1008 of process 1000. In one embodiment, the apparatus for operating the one or more three-dimensional memory structures in full block mode performs process 1400. In one embodiment, the apparatus for operating the one or more three-dimensional memory structures in full block mode performs process 1450.

[0159] For the purposes of this document, references in the specification to "an embodiment," "one embodiment," "some embodiments," or "another embodiment" may be used to describe different embodiments or the same embodiment.

[0160] For the purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via one or more other parts). In some cases, when an element is referred to as being connected or coupled to another element, the element may be directly connected to the other element or indirectly connected to the other element via an intervening element. When an element is referred to as being directly connected to another element, there are no intervening elements between the element and the other element. Two devices are "in communication" if they are directly connected or indirectly connected, such that they are able to communicate electronic signals between them.

[0161] For the purposes of this document, the term "based on" may be understood as "based, at least in part, on."

[0162] For the purposes of this document, the use of numerical terms such as a "first" object, a "second" object, and a "third" object without additional context may not imply an ordering of the objects, but may be used for identification purposes to identify different objects.

[0163] For the purposes of this document, the term "group" of objects may refer to a "group" of one or more objects.

[0164] The above detailed description has been provided for the purpose of illustration and description. It is not intended to be exhaustive or to limit the precise form disclosed by the invention. Many modifications and variations are possible in light of the above teachings. The described embodiments are selected to best explain the principles of the proposed technology and its practical application, thereby enabling others skilled in the art to best utilize it in various embodiments and in various modifications suitable for the specific use contemplated. The scope of the invention is intended to be defined by the appended claims.

Claims

1. A device, comprising: one or more three-dimensional memory structures, each three-dimensional memory structure comprising a block having word lines and NAND strings, wherein the NAND strings in a block include memory cells connected to the word lines of the block, wherein the word lines include a first set of data word lines located in a first region of the block, a second set of data word lines located in a second region of the block, and a reconfigurable word line located between the first set and the second set; and one or more control circuits in communication with the one or more memory structures, wherein the one or more control circuits are configured to: operating the first block in a sub-block mode in which the reconfigurable word lines in the first block function as dummy word lines that provide electrical isolation between the first region and the second region in the first block, wherein in the sub-block mode, the first region includes an upper sub-block, and the second region includes a lower sub-block; as well as The second block is operated in a full block mode in which the reconfigurable word lines in the second block are used as data word lines.

2. The apparatus of claim 1 , wherein the one or more control circuits are configured to: In the sub-block mode, operating memory cells connected to the reconfigurable word lines in the first block as dummy memory cells, the dummy memory cells being unprogrammed; and In the full block mode, memory cells connected to the reconfigurable word lines in the second block are operated as data memory cells, and the data memory cells are programmed.

3. The device according to claim 1, wherein: Each block includes an upper level, a middle level, and a lower level; Each block includes a first interface layer and a second interface layer, the first interface layer is located between the lower level and the middle level, and the second interface layer is located between the middle level and the upper level; The lower level includes a dummy word line adjacent to the first interface layer, the middle level includes a lower dummy word line adjacent to the first interface layer, the middle level includes an upper dummy word line adjacent to the second interface layer, and the upper level includes a dummy word line adjacent to the second interface layer; and The reconfigurable word lines reside within the intermediate level, wherein a first plurality of data word lines of the first set of data word lines are located between the reconfigurable word lines and the lower dummy word lines of the intermediate level, and a second plurality of data word lines of the second set of data word lines are located between the reconfigurable word lines and the upper dummy word lines of the intermediate level.

4. The apparatus of claim 1 , wherein the one or more control circuits are configured to: independently erasing a first memory cell connected to the first set of data word lines and a second memory cell connected to the second set of data word lines in the first block while in the sub-block mode, including operating the reconfigurable word lines as dummy word lines in the sub-block mode to provide electrical isolation between the first set and the second set of data word lines during erasure of the first memory cells and during erasure of the second memory cells; and While in the full block mode, memory cells in both the first set and the second set of data word lines in the second block and memory cells in the second block connected to the reconfigurable word lines are erased as a unit.

5. The apparatus of claim 4, wherein the one or more control circuits are configured to perform the following operations in the sub-block mode: applying an erase voltage to a channel of the NAND string of the first block; applying an erase enable voltage to the data word line in a selected sub-block of the first block, wherein the selected sub-block includes the lower sub-block or the upper sub-block; applying an erase inhibit voltage to the data word lines in an unselected sub-block of the first block, wherein the unselected sub-block includes the other of the lower sub-block or the upper sub-block; as well as An erase isolation voltage is applied to the reconfigurable word line in the first block to provide electrical isolation between the selected sub-block and the unselected sub-blocks, wherein the erase isolation voltage has a magnitude between the magnitude of the erase enable voltage and the magnitude of the erase inhibit voltage.

6. The apparatus of claim 5, wherein the one or more control circuits are further configured to perform the following operations in the full block mode: applying the erase voltage to channels of the NAND strings in the second block; and The erase enable voltage is applied to the first and second sets of the data word lines in the second block and the reconfigurable word lines in the second block.

7. The apparatus of claim 1 , wherein the one or more control circuits are further configured to: The second block is operated in the sub-block mode in which the reconfigurable word lines function as dummy word lines that provide electrical isolation between the first set of data word lines and the second set of data word lines in the second block.

8. The device according to claim 1, wherein: The first block is associated with a plurality of bit lines and one or more source lines; The one or more control circuits are further configured to, in the sub-block mode, precharge channels of the NAND strings in the first block starting from the bit lines when programming the upper sub-block; and The one or more control circuits are further configured to, in the sub-block mode, precharge the channels of the NAND strings in the first block starting from the one or more source lines when programming the lower sub-block.

9. The apparatus of claim 8, wherein the one or more control circuits are further configured to: programming the first set of data word lines in drain to source order in the sub-block mode, wherein the first set of data word lines resides in the lower sub-block; and The second set of data word lines is programmed in source-to-drain order in the sub-block mode, wherein the second set of data word lines resides in the upper sub-block.

10. The apparatus of claim 1, wherein the one or more control circuits are further configured to: In the sub-block mode, a boost voltage is applied to the reconfigurable word lines in the first block, while a program voltage is applied to selected word lines in the first block.

11. The apparatus of claim 1 , wherein the one or more control circuits are further configured to: In the full block mode, managing a full block master block pool having x full blocks, wherein the x full blocks provide a target storage amount; and In the sub-block mode, a half-block main block pool having 2x+y sub-blocks is managed, where x and y are integers greater than 0, and the 2x+y sub-blocks provide the target storage amount.

12. The apparatus of claim 11, wherein the one or more control circuits are further configured to: In the full block mode, managing a block pool having a full block extension of p full blocks, wherein the x full blocks and the p full blocks include all blocks of the one or more memory structures; and In the sub-block mode, a half-block extended block pool having p+q sub-blocks is managed, where p and q are integers greater than 0, wherein the 2x+y sub-blocks and the p+q sub-blocks include all blocks in the one or more memory structures.

13. A method for operating a non-volatile storage system, the method comprising: operating a block having NAND strings and word lines in a half NAND string mode in which a group of word lines in the block provides electrical isolation between a first set of data word lines connected to memory cells located on a bottom segment of the NAND strings and a second set of data word lines connected to memory cells located on a top segment of the NAND strings, including erasing the memory cells connected to the first set of data word lines independently of erasing the memory cells connected to the second set of data word lines while biasing the group of word lines to provide electrical isolation between the first set and the second set of data word lines; as well as Operating the block in full NAND string mode includes erasing the memory cells of the first set connected to data word lines, the memory cells of the second set connected to data word lines, and the group of memory cells connected to the word lines as a unit.

14. The method according to claim 13, further comprising: programming user data into the memory cells of the group connected to the word line in the full NAND string mode; as well as In the half NAND string mode, the group of word lines is operated as dummy word lines, which are not programmed with data.

15. The method of claim 13 , wherein erasing the memory cells of the first set connected to data word lines, the memory cells of the second set connected to data word lines, and the memory cells of the group connected to the word lines as a unit comprises: An erase enable voltage is applied to the group of word lines while an erase voltage is applied to the channel of the NAND string.

16. The method of claim 13, wherein the block comprises an upper level, a middle level, and a lower level, wherein each level comprises a different segment of each NAND string in the block, wherein the group of word lines resides in the middle level, the block comprises a first interface layer and a second interface layer, the first interface layer being between the lower level and the middle level, the second interface layer being between the middle level and the upper level, the lower level comprising a first dummy word line adjacent to the first interface layer, the middle level comprising a second dummy word line adjacent to the first interface layer, the middle level comprising a third dummy word line adjacent to the second interface layer, the upper level comprising a fourth dummy word line adjacent to the second interface layer, and the method further comprising: The first dummy word line, the second dummy word line, the third dummy word line, and the fourth dummy word line are operated as dummy word lines in both the full NAND string mode and the half NAND string mode.

17. A non-volatile storage system, comprising: one or more three-dimensional memory structures, each memory structure comprising a block having word lines and NAND strings, wherein the NAND strings in a block comprise memory cells connected to the word lines of the block, wherein each block comprises three levels, wherein each level comprises a different segment of each NAND string, wherein the three levels comprise a lower level, a middle level, and an upper level, wherein each block comprises a first interface layer and a second interface layer, the first interface layer having a first manufacturing joint, the second interface layer having a second manufacturing joint, wherein the first manufacturing joint is configured to electrically connect a channel of a segment of a corresponding NAND string located in the lower level to a corresponding channel of a segment of a corresponding NAND string located in the middle level, wherein the second manufacturing joint is configured to electrically connect a channel of a segment of a corresponding NAND string located in the middle level to a corresponding channel of a segment of a corresponding NAND string located in the upper level; means for operating the one or more three-dimensional memory structures in a half-block mode, wherein a group of the word lines in the middle level functions as dummy word lines, wherein in the half-block mode memory cells connected to the group are not programmed, wherein a first plurality of data word lines reside between the group and the first fabrication tap, and wherein a second plurality of data word lines reside between the group and the second fabrication tap; and Means for operating the one or more three-dimensional memory structures in a full block mode in which the groups located in the middle level are used as data word lines, wherein in the full block mode the memory cells connected to the groups are programmed.

18. The non-volatile storage system of claim 17, wherein the means for operating the one or more three-dimensional memory structures in the half-block mode is configured to: Independently erasing memory cells in the upper and lower halves of a particular block includes applying an isolation voltage to the group of word lines while applying an erase voltage to the channels of the NAND strings to provide electrical isolation between the lower and upper halves.

19. The non-volatile storage system of claim 18, wherein the means for operating the one or more three-dimensional memory structures in the half-block mode is configured to: Erasing memory cells in selected ones of the upper half block and the lower half block while preventing erasing in unselected ones of the upper half block and the lower half block, comprising: applying an erase voltage to a channel of the NAND string; applying an erase enable voltage to the data word lines in the selected half block; applying an erase inhibit voltage to the data word lines in an unselected half block; as well as An isolation voltage is applied to the group of word lines while applying the erase voltage, the erase enable voltage, and the erase inhibit voltage to provide electrical isolation between the selected half-block and the unselected half-block, wherein the magnitude of the isolation voltage is between the magnitude of the erase enable voltage and the magnitude of the erase inhibit voltage.

20. The non-volatile storage system of claim 18, wherein the means for operating the one or more three-dimensional memory structures in the full block mode is configured to: Erasing the memory cells in the upper half block, the memory cells in the lower half block, and the group of memory cells connected to word lines as a unit includes applying an erase enable voltage to the group of word lines to erase the memory cells connected to the group of word lines.

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