Duty cycle correction device for large touch and display driver integrated system

Abstract

The invention discloses a duty cycle correction device. The duty cycle correction device comprises a duty cycle correction circuit based on a phase-locked loop, a bypass duty cycle correction circuit and a multiplexer. The duty cycle correction circuit based on the phase-locked loop is used for correcting a duty cycle of an input clock signal to generate a correction signal based on the phase-locked loop. The bypass duty cycle correction circuit is coupled to the phase-locked loop-based duty cycle correction circuit and is triggered by the input clock signal to sample a logic signal at an input end thereof and correct a duty cycle of the input clock signal, thereby generating a bypass correction signal. The multiplexer is coupled to the phase-locked loop-based duty cycle correction circuit and the bypass duty cycle correction circuit, and is configured to select one of the phase-locked loop-based correction signal, the bypass correction signal, and the input clock signal as the output clock signal.

Description

Technical Field

[0001] The present invention relates to duty cycle correction, and more particularly, to a duty cycle correction device for cascade circuits and related large touch and display driver integrated systems. Background Art

[0002] Touch and Display Driver Integration (TDDI) is a novel semiconductor design technology that integrates the touch controller and display driver into a single integrated circuit (IC). This technology is mainly used in touch screen display devices, such as smartphones and tablets. The main advantages of TDDI are that it can reduce manufacturing complexity, save space, and improve performance by reducing the need for separate touch controller and display driver ICs.

[0003] Large Touch and Display Driver Integration (LTDI) is an advanced development of TDDI technology, designed for large or very large touch display applications. LTDI embodies the same concept of integrating the touch controller and display driver into a single IC, but expands its functionality to accommodate larger, high-resolution touch display devices. Generally speaking, multiple LTDI ICs may need to be used in specific situations. For example, for larger or higher-resolution display devices, a single LTDI IC may not have enough driving power to effectively process all pixels. In this case, the display device can be divided into several regions, each of which is driven by a separate LTDI IC. In addition, in some designs, LTDI ICs may communicate using a serial peripheral interface (Serial Peripheral Interface, SPI). In the broadcast mode of SPI, multiple LTDI ICs are cascaded. All cascaded LTDI ICs will share the same SPI clock to broadcast data to all LTDI ICs.

[0004] However, when multiple ICs are connected in a cascade state, problems related to signal integrity may occur due to the physical limitations of the circuit board and components. One of the problems is the duty cycle distortion caused by the resistance-capacitance (RC) effect. The long traces on the printed circuit board are essentially transmission lines with intrinsic resistance and intrinsic capacitance, and their RC effect is usually an important factor causing duty cycle distortion of the clock signal. In particular, the propagation delay caused by the RC time constant of these traces may cause the high / low level duration of the clock signal to become wider or narrower, further distorting the duty cycle. This effect accumulates on the cascaded ICs and eventually causes significant duty cycle distortion on the last IC in the cascaded ICs, which will have an adverse effect on the operation of the circuit. Therefore, it is necessary to accurately manage the clock signal to prevent problems such as duty cycle distortion of the clock signal. Summary of the invention

[0005] In view of the above, the object of the present invention is to provide a duty cycle correction device with a dual duty cycle correction mechanism. The first of the dual duty cycle correction mechanisms is a duty cycle correction based on a phase-locked loop (PLL), which can effectively correct any distortion in the duty cycle of a clock signal. The second of the dual duty cycle correction mechanisms is a bypass duty cycle correction as an alternative. The bypass duty cycle correction mechanism is also designed to correct the distortion in the duty cycle of a clock signal, and this correction mechanism can be effective when the PLL-based duty cycle correction risks causing severe jitter accumulation. In this case, the bypass duty cycle correction will be set to replace the PLL-based duty cycle correction, thereby providing flexibility and improving efficiency.

[0006] An embodiment of the present invention provides a duty cycle correction device, characterized in that the duty cycle correction device includes: a duty cycle correction circuit based on a phase-locked loop, a bypass duty cycle correction circuit and a multiplexer. The duty cycle correction circuit based on the phase-locked loop is used to correct the duty cycle of an input clock signal to generate a correction signal based on a phase-locked loop. The bypass duty cycle correction circuit is coupled to the duty cycle correction circuit based on the phase-locked loop, and is triggered by the input clock signal to sample a logic signal at its input end, correct the duty cycle of the input clock signal, and thus generate a bypass correction signal. The multiplexer is coupled to the duty cycle correction circuit based on the phase-locked loop and the bypass duty cycle correction circuit, and is used to select one of the correction signal based on the phase-locked loop, the bypass correction signal and the input clock signal as the output clock signal.

[0007] An embodiment of the present invention provides a display and touch control system, characterized in that the display and touch control system comprises: a plurality of display and touch control circuits arranged in cascade. Each display and touch control circuit has a clock input terminal, a clock output terminal, a data input terminal and a data output terminal. Among them, the clock output terminal of a display and touch control circuit in the plurality of display and touch control circuits is coupled to the clock input terminal of a subsequent display and touch control circuit. Each display and touch control circuit includes a duty cycle correction device. The duty cycle correction device includes: a duty cycle correction circuit based on a phase-locked loop, a bypass duty cycle correction circuit and a multiplexer. The duty cycle correction circuit based on the phase-locked loop is used to correct the duty cycle of the input clock signal of the clock input terminal to generate a correction signal based on the phase-locked loop. The bypass duty cycle correction circuit is coupled to the duty cycle correction circuit based on the phase-locked loop and is triggered by the input clock signal to sample the logic signal of the input terminal, correct the duty cycle of the input clock signal, and thus generate a bypass correction signal. The multiplexer is coupled to the phase-locked loop-based duty cycle correction circuit and the bypass duty cycle correction circuit, and is used to select one of the phase-locked loop-based correction signal, the bypass correction signal and the input clock signal as the output clock signal at the clock output terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A cascaded arrangement of LTDIICs according to an embodiment of the present invention is shown.

[0009] Figure 2 A signal timing diagram within the LTDI IC according to an embodiment of the present invention is shown.

[0010] Figure 3 A schematic diagram showing the architecture of a duty cycle correction device according to an embodiment of the present invention is shown.

[0011] Figure 4 exhibit Figure 3 Signal timing diagram within the duty cycle correction device.

[0012] Figure 5 A schematic diagram showing a duty cycle correction device according to an embodiment of the present invention.

[0013] Figure 6 exhibit Figure 5 Signal timing diagram within the duty cycle correction device.

[0014] Figure 7 Demonstration of use Figure 6 The signal timing diagram of the duty cycle correction device within the LTDIIC.

[0015] The reference numerals are described as follows:

[0016] 10, 20, 30: Large touch and display driver ICs

[0017] 11, 21, 31: Duty cycle correction circuit based on phase-locked loop

[0018] 12, 22, 32: Bypass duty cycle correction circuit

[0019] 14, 24, 34: Automatic placement and routing

[0020] 100, 200: Clock correction device

[0021] 110, 210: Duty cycle correction circuit based on phase-locked loop

[0022] 112, 212: Phase-locked loop

[0023] 114, 214: Frequency divider

[0024] 120, 220: Bypass duty cycle correction circuit

[0025] 122, 230: D flip-flop

[0026] 140: OR gate

[0027] 130, 240: Multiplexer

[0028] 215: Counting circuit

[0029] 225: Full Adder DETAILED DESCRIPTION

[0030] In the following text, many specific details are described to provide readers with a thorough understanding of the embodiments of the present invention. However, those skilled in the art will understand how to implement the present invention without one or more specific details, or using other methods, components, materials, etc. In other cases, well-known structures, materials, or operations will not be shown or described in detail to avoid obscuring the core concepts of the present invention.

[0031] The reference to "an embodiment" in the specification means that the specific features, structures or characteristics described in the embodiment may be included in at least one embodiment of the present invention. Therefore, the "in an embodiment" that appears in various places in this specification does not necessarily mean the same embodiment. In addition, the aforementioned specific features, structures or characteristics may be combined in one or more embodiments in any suitable form.

[0032] Figure 1 The LTDI system of an embodiment of the present invention is shown. Figure 1As shown, the LTDI system includes multiple LTDIICs arranged in a cascade form. In one embodiment, the multiple LTDIICs include LTDIIC 10, LTDIIC 20 and LTDIIC 30. Please note that the number of LTDIICs included in a single LTDI system is not a limitation of the present invention. In multiple embodiments of the present invention, the number of LTDIICs included in an LTDI system can be more or less than 3. In this embodiment, LTDIIC 10, 20 and 30 communicate with each other using an SPI interface. In addition, LTDIIC 10, 20 and 30 operate in SPI broadcast mode. Among them, the clock output terminal of one LTDIIC (for example, LTDIIC 10 and LTDIIC 20) is coupled to the clock input terminal of a subsequent LTDIIC (for example, LTDIIC 20 and LTDIIC 30). Furthermore, a data output terminal of one LTDIIC (eg, LTDIIC 10 and LTDIIC 20 ) is coupled to a data input terminal of a subsequent LTDIIC (eg, LTDIIC 20 and LTDIIC 30 ).

[0033] Each of the LTDI ICs 10, 20, and 30 includes a duty cycle correction circuit based on a phase locked loop (PLL), namely, 11, 21, and 31, a bypass duty cycle correction circuit, namely, 12, 22, and 32, and auto-placement routing, namely, 14, 24, and 34. Each LTDI IC 10, 20, and 30 relies on the duty cycle correction circuit based on the PLL, namely, 11, 21, and 31, and the bypass duty cycle correction circuit, namely, 12, 22, and 32, to correct the duty cycle of the input clock signal SPI_CLK_IN at its clock input terminal, thereby generating an output clock signal SPI_CLK_OUT having a corrected duty cycle at its clock output terminal.

[0034] Figure 2A signal timing diagram in an LTDI IC according to an embodiment of the present invention is shown. As shown in the figure, in the SPI broadcast mode, an LTDI IC (e.g., LTDI ICs 10, 20, and 30) latches the signal Data_IN on the data input terminal at the falling edge of the output clock signal SPI_CLK_OUT having a corrected duty cycle. In addition, the latched data signal Data_OUT is transmitted to the subsequent LTDI IC through the data output terminal at the rising edge of the output clock signal SPI_CLK_OUT. Since the output clock signal SPI_CLK_OUT has a corrected duty cycle, each of the LTDI ICs 10, 20, and 30 can correctly receive and broadcast the data.

[0035] Please refer to Figure 3 , which illustrates a schematic diagram of the structure of a clock correction device according to an embodiment of the present invention. As shown in the figure, the clock correction device 100 includes a PLL-based duty cycle correction circuit 110, a bypass duty cycle correction circuit 120, and a multiplexer 130. The clock correction device 100 receives an input clock signal SPI_CLK_IN, and accordingly outputs an output clock signal SPI_CLK_OUT having a corrected duty cycle. .

[0036] The PLL-based duty cycle correction circuit 110 and the bypass duty cycle correction circuit 120 are both used to correct the duty cycle of the input clock signal SPI_CLK_IN. The PLL-based duty cycle correction circuit 110 is used to correct the duty cycle of the input clock signal SPI_CLK_IN, thereby providing a PLL-based correction signal PLL_FB_CLK. The bypass duty cycle correction circuit 120 is used to correct the duty cycle of the input clock signal SPI_CLK_IN to provide a bypass correction signal. The multiplexer 130 receives the input clock signal SPI_CLK_IN, the PLL-based correction signal PLL_FB_CLK and the bypass correction signal. Accordingly, the multiplexer 130 selects one of the input clock signal SPI_CLK_IN, the PLL-based correction signal PLL_FB_CLK and the bypass correction signal as the output clock signal SPI_CLK_OUT.

[0037] The duty cycle correction circuit 110 based on PLL includes a PLL circuit 112 and a frequency divider 114. In one embodiment, the PLL circuit 112 may include a phase detector, a loop filter, and an oscillator (not shown). The PLL circuit 112 is used to lock the frequency and phase of the input clock signal SPI_CLK_IN, thereby generating a PLL output signal. The PLL output signal can be aligned with the input clock signal SPI_CLK_IN on the rising edge. The PLL output signal of the PLL circuit 112 is also input to the frequency divider 114. The frequency divider 114 is used to divide the frequency of the PLL output signal by a factor N and correct the duty cycle of the PLL output signal. In this way, the frequency divider 214 can output a PLL-based correction signal PLL_FB_CLK with a corrected duty cycle.

[0038] Specifically, the PLL-based duty cycle correction circuit 110 utilizes a frequency divider 114 located in the feedback path of the PLL circuit 112. The frequency divider 114 has a duty cycle correction capability, which means that it can ensure a balanced distribution of the duration of the high level and the low level in the PLL-based correction signal PLL_FB_CLK. In addition, due to the frequency locking characteristic of the PLL circuit 112, the PLL-based correction signal PLL_FB_CLK can be synchronized with the input clock signal SPI_CLK_IN in frequency and aligned with the input clock signal SPI_CLK_IN at the rising edge. When the PLL-based correction signal PLL_FB_CLK is selected as the output clock signal SPI_CLK_OUT, the output clock signal SPI_CLK_OUT can be synchronized with the input clock signal SPI_CLK_IN in frequency, but has a corrected duty cycle (i.e., 50%-50% duty cycle).

[0039] The bypass duty cycle correction circuit 120 includes an OR gate 140 and a D flip-flop 122. The D flip-flop 122 receives a logic high signal (e.g., logic "1") at its input terminal D and is triggered by a pulse of the input clock signal SPI_CLK_IN to sample the logic high signal. Further, the D flip-flop 230 samples the logic high signal at the rising edge of the input clock signal SPI_CLK_IN. Accordingly, the D flip-flop 122 outputs the bypass correction signal to its output terminal Q. In addition, the OR gate 140 receives the PLL-based correction signal PLL_FB_CLK and a delayed version of the PLL-based correction signal PLL_FB_CLK (i.e., the delayed PLL-based correction signal FB_CLK_DLY), thereby generating a reset signal Rest.

[0040] Since the PLL-based correction signal PLL_FB_CLK has been duty cycle corrected, the falling edge of the PLL-based correction signal PLL_FB_CLK will be used to generate a reset pulse of the reset signal Rest, which helps to correct the duty cycle of the input clock signal SPI_CLK_IN. By using the reset pulse to control the input clock signal SPI_CLK_IN, the bypass correction signal is converted to a low level at the correct timing. Therefore, when the bypass correction signal is selected as the output clock signal SPI_CLK_OUT, the output clock signal SPI_CLK_OUT can be synchronized with the input clock signal SPI_CLK_IN in frequency, but has a corrected duty cycle (i.e., 50%-50% duty cycle).

[0041] The main advantage of the bypass duty cycle correction circuit 120 is that it can avoid the jitter accumulation problem that may occur when cascading multiple LTDI ICs when using PLL-based duty cycle correction. Since each PLL-based correction in the LTDI IC may introduce a time offset to the output clock signal, when multiple LTDI ICs are cascaded, this may cause significant jitter due to accumulation. Therefore, the bypass duty cycle correction provides a correction method to avoid this problem.

[0042] Figure 4 Draws Figure 3 The signal timing diagram of the duty cycle correction device of the embodiment of the present invention. Figure 3 As shown, the rising edges of the PLL-based correction signal PLL_FB_CLK and the output clock signal SPI_CLK_OUT are aligned with the rising edge of the input clock signal SPI_CLK_IN. In addition, at the falling edge of the PLL-based correction signal PLL_FB_CLK (which has a corrected duty cycle), the bypass correction signal is reset to a low level, thereby correcting the distorted duty cycle in the input clock signal SPI_CLK_IN.

[0043] See also Figure 5 , which is a schematic diagram of the architecture of a clock correction device according to an embodiment of the present invention. As shown in the figure, the clock correction device 200 includes a PLL-based duty cycle correction circuit 210 and a multiplexer 240. The clock correction device 200 receives an input clock signal SPI_CLK_IN and generates an output clock signal SPI_CLK_OUT accordingly.

[0044] The PLL-based duty cycle correction circuit 210 and the bypass duty cycle correction circuit 220 are both used to correct the duty cycle of the input clock signal SPI_CLK_IN. The PLL-based duty cycle correction circuit 210 is used to correct the duty cycle of the input clock signal SPI_CLK_IN, thereby providing a PLL-based correction signal PLL_FB_CLK. The bypass duty cycle correction circuit 220 is used to correct the duty cycle of the input clock signal SPI_CLK_IN, thereby providing a bypass correction signal SPI_BYPASS_CLK. The multiplexer 240 receives the input clock signal SPI_CLK_IN, the PLL-based correction signal PLL_FB_CLK, and the bypass correction signal SPI_BYPASS_CLK. Accordingly, the multiplexer 240 selects one of the input clock signal SPI_CLK_IN, the PLL-based correction signal PLL_FB_CLK, and the bypass correction signal SPI_BYPASS_CLK as the output clock signal SPI_CLK_OUT.

[0045] The duty cycle correction circuit 210 based on PLL includes a PLL circuit 212 and a frequency divider 214. In one embodiment, the PLL circuit 112 may include a phase detector, a loop filter, and an oscillator (not shown). The PLL circuit 212 is used to lock the frequency and phase of the input clock signal SPI_CLK_IN, thereby generating a PLL output signal PLL_CLK, which can be aligned with the input clock signal SPI_CLK_IN on the rising edge. The PLL output signal PLL_CLK is also output to the frequency divider 214. The frequency divider 214 is used to divide the frequency of the PLL output signal PLL_CLK by a factor N, and also corrects the duty cycle of the PLL output signal PLL_CLK. In this way, the frequency divider 214 will output a PLL-based correction signal PLL_FB_CLK with a corrected duty cycle.

[0046] The bypass duty cycle correction circuit 220 includes a counting circuit 215 (having a full adder 225) and a D flip-flop 230. The D flip-flop 230 receives the input clock signal SPI_CLK_IN and is triggered by a pulse of the input clock signal SPI_CLK_IN to sample a high logic signal (e.g., logic "1") at the input terminal D. Specifically, the D flip-flop 230 samples the high logic signal at the rising edge of the input clock signal SPI_CLK_IN. Accordingly, the D flip-flop 230 outputs the bypass correction signal SPI_BYPASS_CLK at its output terminal Q.

[0047] On the other hand, the PLL output signal PLL_CLK is input to a counting circuit 215 having a full adder 225. The counting circuit 215 is used to count the number of cycles of the PLL output signal PLL_CLK within a single cycle of the input clock signal SPI_CLK_IN by using the full adder 225. The counting circuit 215 generates a reset signal Rest according to the count value representing the number of cycles of the PLL output signal PLL_CLK.

[0048] See also Figure 6 , which is Figure 5 The signal timing diagram in the duty cycle correction device is shown in FIG. Figure 6 As shown, within a single cycle of the input clock signal SPI_CLK_IN, the PLL output signal PLL_CLK has 8 cycles, which means that the value of N is 8. In addition, the counting circuit 215 having the full adder 225 is used to generate the reset signal Rest according to the count value. Once the count value reaches N / 2 (for example, 8 / 2=4), the counting circuit 215 will increase the reset signal Rest so that the bypass correction signal SPI_BYPASS_CLK is converted to a low logic level. On the other hand, once the count value reaches N, the counting circuit 215 will lower the reset signal Rest. In this way, the bypass correction signal SPI_BYPASS_CLK will be synchronized with the input clock signal SPI_CLK_IN, but with a corrected duty cycle.

[0049] Figure 7 Depicted using Figure 5 The signal timing diagram in the LTDIIC of the duty cycle correction device of the present invention. As shown in the figure, when the count value reaches N / 2 within one cycle of the input clock signal SPI_CLK_IN, the output clock signal SPI_CLK_OUT (i.e., when the bypass correction signal SPI_BYPASS_CLK is selected) will be changed to a low level. When the count value reaches N, the output clock signal SPI_CLK_OUT (i.e., when the bypass correction signal SPI_BYPASS_CLK is selected) will be changed to a high level due to the reset signal Rest being triggered. And, the high logic signal is sampled by the D flip-flop 230 again at the rising edge of the input clock signal SPI_CLK_IN. In addition, at the falling edge of the output clock signal SPI_CLK_OUT, the data signal Data_IN is latched. At the rising edge of the output clock signal SPI_CLK_OUT, the latched data signal Data_OUT is transmitted.

[0050] In one embodiment, the strategy used by multiplexers 130 and 240 to determine the output clock signal SPI_CLK_OUT is related to the number of LTDI ICs included in the LTDI system. Specifically, if the LTDI system contains a minimum number of LTDI ICs, multiplexers 130 and 240 can both choose to use the input clock signal SPI_CLK_IN as the output clock signal SPI_CLK_OUT (without correction). In the case where the LTDI system contains a medium or large number of LTDI ICs, multiplexers 130 and 240 can select the bypass correction signal SPI_BYPASS_CLK as the output clock signal SPI_CLK_OUT, thereby mitigating possible jitter accumulation (caused by the PLL circuit). However, in the case where the jitter accumulation is not severe, multiplexers 130 and 240 can select the PLL-based correction signal PLL_FB_CLK as the output clock signal SPI_CLK_OUT.

[0051] In summary, when multiple ICs are connected in a cascaded arrangement and share the same clock signal, each IC may add a certain amount of load to the clock signal, resulting in a distortion in the duty cycle of the clock signal. Due to the cumulative effect of the load, this distortion may become severe when the clock signal reaches the last IC in the cascade arrangement, causing the clock signal to almost disappear or be severely distorted. This distortion may affect the setup time, hold time, and various parameters of the data signal determined by the rising / falling edge of the clock signal. Any change in the position of the rising / falling edge of the clock signal may cause errors during the setup or hold time of the data signal, which may disrupt the normal operation of the entire system. In order to solve this problem, the present invention proposes a duty cycle correction device, characterized by a dual duty cycle correction mechanism. The first is a PLL-based duty cycle correction, which can effectively correct any distortion of the duty cycle of the clock signal. In addition, the present invention also combines bypass duty cycle correction as an alternative. The bypass duty cycle correction mechanism is also used to correct the distortion of the duty cycle of the clock signal, but the bypass duty cycle correction mechanism is particularly beneficial when the PLL-based duty cycle correction has the risk of serious jitter accumulation caused by the PLL circuit. In this case, the bypass duty cycle correction can be set to replace the PLL-based duty cycle correction, thereby providing flexibility and improving efficiency.

[0052] The embodiments of the present invention may be specifically implemented as an apparatus, method or computer program product. Accordingly, the embodiments of the present invention may take the form of an entity implemented entirely by hardware, an entity implemented entirely by software (including firmware, resident software, microcode, etc.), or an entity combining software and hardware aspects, which may be generally referred to as a "module" or "system". In addition, the embodiments of the present invention may take the form of a computer program product embodied in any tangible expression medium, and the medium has a computer-usable program code embodied in the medium. In terms of hardware, the present invention may be implemented by applying any of the following technologies or related combinations: separate operating logic of a logic gate capable of executing a logic function according to a data signal, and an application specific integrated circuit (ASIC), a programmable gate array (PGA) or a field programmable gate array (FPGA) with appropriate combinational logic.

[0053] The flow chart and block diagram illustrate the architecture, function and operation of the system, method and computer program product of different possible implementation methods of the embodiment of the present invention. In this regard, each box in the flow chart or block diagram may represent a module, segment or part of the program code, including one or more executable instructions to implement a specific logic function. It should also be noted that each box in the block diagram and / or flow chart, and the combination of boxes in the block diagram and / or flow chart can be implemented by a special-purpose hardware base system, or a combination of special hardware and computer program instructions. These computer program instructions can be stored in a readable computer medium to command a computer or other programmable data processing device to operate in a specific manner so that the instructions stored in the readable computer medium generate functions / operations specified in the boxes or box combinations that implement the flow chart and / or block diagram.

[0054] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A duty cycle correction device, characterized in that: The duty cycle correction device comprises: A duty cycle correction circuit based on a phase-locked loop, used to correct the duty cycle of an input clock signal to generate a correction signal based on a phase-locked loop; a bypass duty cycle correction circuit, coupled to the phase-locked loop-based duty cycle correction circuit, triggered by the input clock signal to sample a logic signal at its input terminal, correct the duty cycle of the input clock signal, and thereby generate a bypass correction signal; and A multiplexer is coupled to the phase-locked loop-based duty cycle correction circuit and the bypass duty cycle correction circuit, and is used to select one of the phase-locked loop-based correction signal, the bypass correction signal and the input clock signal as the output clock signal.

2. The duty cycle correction device according to claim 1, characterized in that: The duty cycle correction circuit based on a phase-locked loop comprises: A phase-locked loop circuit, configured to generate a phase-locked loop output signal according to the input clock signal; and A frequency divider is coupled to the phase-locked loop circuit and is used for dividing the frequency of the phase-locked loop output signal by a factor N to generate the phase-locked loop-based correction signal.

3. The duty cycle correction device according to claim 1, characterized in that: The bypass duty cycle correction circuit comprises: an OR gate for performing an OR operation on the phase-locked loop-based correction signal and a delayed version of the phase-locked loop-based correction signal to generate a reset signal; and The D flip-flop is coupled to the OR gate and the multiplexer, is triggered by the input clock signal to sample a high logic signal, and is reset by the reset signal to generate the bypass correction signal.

4. The duty cycle correction device according to claim 2, characterized in that: The bypass duty cycle correction circuit comprises: a counting circuit, coupled to the phase-locked loop circuit, for counting the number of cycles of the phase-locked loop output signal within one cycle of the input clock signal, and generating a reset signal according to the count value; and The D flip-flop is coupled to the counting circuit and the multiplexer, is triggered by the input clock signal to sample a high logic signal, and is reset by the reset signal to generate the bypass correction signal.

5. The duty cycle correction device according to claim 4, characterized in that: When the count value indicates that the number of cycles of the phase-locked loop output signal received by the counting circuit within one cycle of the input clock signal reaches N / 2, the counting circuit is used to increase the reset signal; and when the count value indicates that the number of cycles of the phase-locked loop output signal received by the counting circuit within one cycle of the input clock signal reaches N, the counting circuit is used to decrease the reset signal.

6. A display and touch control system, characterized in that: The display and touch control system comprises: A plurality of display and touch control circuits arranged in cascade, each display and touch control circuit having a clock input terminal, a clock output terminal, a data input terminal and a data output terminal, wherein the clock output terminal of one display and touch control circuit among the plurality of display and touch control circuits is coupled to the clock input terminal of a subsequent display and touch control circuit, and each display and touch control circuit comprises: A duty cycle correction device, comprising: A duty cycle correction circuit based on a phase-locked loop, used for correcting the duty cycle of the input clock signal at the clock input terminal to generate a correction signal based on a phase-locked loop; a bypass duty cycle correction circuit, coupled to the phase-locked loop-based duty cycle correction circuit, triggered by the input clock signal to sample a logic signal at its input terminal, correct the duty cycle of the input clock signal, and thereby generate a bypass correction signal; and A multiplexer is coupled to the phase-locked loop-based duty cycle correction circuit and the bypass duty cycle correction circuit, and is used to select one of the phase-locked loop-based correction signal, the bypass correction signal and the input clock signal to be used as an output clock signal at the clock output terminal.

7. The display and touch control system according to claim 6, characterized in that: Each of the multiple display and touch control circuits is used to latch the data signal on the data input terminal at the falling edge of the output clock signal, and transmit the latched data signal to a subsequent display and touch control circuit at the rising edge of the output clock signal.

8. The display and touch control system according to claim 6, characterized in that: The duty cycle correction circuit based on a phase-locked loop comprises: A phase-locked loop circuit, configured to generate a phase-locked loop output signal according to the input clock signal; and A frequency divider is coupled to the phase-locked loop circuit and is used to divide the frequency of the phase-locked loop output signal by a factor N to generate the PLL-based correction signal.

9. The display and touch control system according to claim 6, characterized in that: The bypass duty cycle correction circuit comprises: an OR gate for performing an OR operation on the phase-locked loop-based correction signal and a delayed version of the phase-locked loop-based correction signal to generate a reset signal; and The D flip-flop is coupled to the OR gate and the multiplexer, is triggered by the input clock signal to sample a high logic signal, and is reset by the reset signal to generate the bypass correction signal.

10. The display and touch control system according to claim 8, characterized in that: The bypass duty cycle correction circuit comprises: a counting circuit, coupled to the phase-locked loop circuit, for counting the number of cycles of the phase-locked loop output signal within one cycle of the input clock signal, and generating a reset signal according to the count value; and The D flip-flop is coupled to the counting circuit and the multiplexer, is triggered by the input clock signal to sample a high logic signal, and is reset by the reset signal to generate the bypass correction signal.

11. The display and touch control system according to claim 10, characterized in that: When the count value indicates that the number of cycles of the phase-locked loop output signal received by the counting circuit within one cycle of the input clock signal reaches N / 2, the counting circuit is used to increase the reset signal; and when the count value indicates that the number of cycles of the phase-locked loop output signal received by the counting circuit within one cycle of the input clock signal reaches N, the counting circuit is used to decrease the reset signal.

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