Post-silicon verification system and post-silicon verification method

Abstract

The invention provides a post-silicon verification system and a post-silicon verification method. The post-silicon verification system comprises a first chip, a second chip and an off-chip memory bank, the first chip comprises a first on-chip network, a target module needing to be verified in a post-silicon verification stage, and a first inter-chip high-speed interface; a debugging interface is configured in the target module and is used for summarizing all debugging signals needing to be verified in the post-silicon verification stage in the target module; the first inter-chip high-speed interface is connected with a debugging interface of each target module through the first network-on-chip; the second chip comprises a second inter-chip high-speed interface and a second on-chip network; the second inter-chip high-speed interface is connected with the first inter-chip high-speed interface, and the second inter-chip high-speed interface is also connected with the off-chip memory bank through the second on-chip network; wherein the first chip is used for sending a debugging signal of each target module to the off-chip memory bank for storage through the second chip in a post-silicon verification stage.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a post-silicon verification system and a post-silicon verification method. Background Art

[0002] In integrated circuit design, post-silicon verification (also called post-silicon verification in some literature) refers to the stage after the sample has been taped out but the decision to go into mass production has not yet been made. Often at this stage, a large number of test cases need to be built to verify the functions of the sample. However, unlike the RTL (Register Transfer Level) or netlist simulation based on EDA (Electronics Design Automation) tools before tape-out, post-silicon verification cannot detect the jumps and logic values ​​of specific signals. Therefore, it is difficult for post-silicon verification engineers to debug the problems that occur, and thus it is impossible to count and analyze the code coverage of the netlist in the post-silicon stage.

[0003] Therefore, during the chip design phase, design engineers need to design additional debug logic to assist post-silicon verification. Common debug logic includes setting the state of the signal to be verified as a register value for software to read. However, since registers consume a large amount of area resources, only a small number of signal states can be set as register values. In addition, since it takes time for software to read registers, once the state of the register changes during the software reading process, it will result in reading an incorrect value and debug failure. Summary of the invention

[0004] The purpose of the embodiments of the present application is to provide a post-silicon verification system and a post-silicon verification method to solve the above-mentioned problems.

[0005] An embodiment of the present application provides a post-silicon verification system, comprising a first chip, a second chip and an off-chip memory; the first chip comprises: a first on-chip network, a target module to be verified in the post-silicon verification stage, and a first inter-chip high-speed interface; the target module is configured with a debugging interface for summarizing the debugging signals in the target module to be verified in the post-silicon verification stage; the first inter-chip high-speed interface is connected to the debugging interface of each target module through the first on-chip network; the second chip comprises: a second inter-chip high-speed interface and a second on-chip network; the second inter-chip high-speed interface is connected to the first inter-chip high-speed interface, and the second inter-chip high-speed interface is also connected to the off-chip memory through the second on-chip network; wherein, the first chip is used to: send the debugging signals of each target module to the off-chip memory for storage through the second chip in the post-silicon verification stage.

[0006] In the above implementation scheme, each target module to be verified in the post-silicon verification stage of the chip is configured with a debug interface for summarizing the debug signals to be verified in the target module in the post-silicon verification stage, and the debug interface is connected to the first inter-chip high-speed interface through the first on-chip network. When such a chip is undergoing post-silicon verification, the debug signals to be verified in the post-silicon verification stage can be forwarded to the first inter-chip high-speed interface through the debug interface, and then sent to the off-chip storage body for storage through the second chip. In this way, compared with the prior art, since the debug signals are specially summarized and output by the debug interfaces configured by each target module in the chip, the integrity and timing of the debug signals summarized and stored in the off-chip storage body are better. By outputting and saving the debug signals, the demand for debug signals in the post-silicon verification stage can be met, and the code coverage of the netlist in the post-silicon verification stage can also be counted and analyzed, that is, the statistics of the netlist coverage can be realized in the post-silicon verification stage. At the same time, since the debug signal is stored in an off-chip memory bank, there is no need to borrow an on-chip memory bank. Therefore, there will be no situation where the debug signal competes with the normal data generated when the chip is operating normally for the memory bank, that is, there will be no situation where the normal data generated when the chip is operating normally cannot use the corresponding memory bank, and thus the performance test indicators will not be damaged. In addition, by using the chip's inter-chip high-speed interface to export debug data, compared to the method of exporting using pins or interface bandwidth, it is possible not to occupy the on-chip data bandwidth, thereby not damaging the performance test indicators. At the same time, the bandwidth of the inter-chip high-speed interface is higher, and the number is easier to increase or decrease, which can match the data bandwidth within the chip, and the debug signal can be quickly and completely exported to the off-chip memory bank.

[0007] Furthermore, there are multiple target modules, and the first on-chip network includes: a first arbitration circuit, the input ports of the first arbitration circuit are respectively connected to the debugging interfaces of the target modules, and the output ports of the first arbitration circuit are respectively connected to the first inter-chip high-speed interfaces.

[0008] In the above implementation scheme, by setting a first arbitration circuit in the first on-chip network, the first arbitration circuit can be used to arbitrate the debug signals sent by multiple target modules, and determine which specific target module's debug signal is currently exported to the off-chip storage body through the first inter-chip high-speed interface, thereby avoiding the debug signals of multiple target modules competing for the first inter-chip high-speed interface, causing signal loss and other problems.

[0009] Furthermore, the number of the first inter-chip high-speed interfaces is N, where N is an integer greater than or equal to 2; the first on-chip network includes: an N-mode address distribution circuit, the input port of the N-mode address distribution circuit is connected to the output port of the first arbitration circuit, and the output ports of the first arbitration circuit are respectively connected to each of the first inter-chip high-speed interfaces; the N-mode address distribution circuit is configured to distribute the received debug signal to the first inter-chip high-speed interface corresponding to the remainder value of the address of the debug signal and N.

[0010] In the above implementation scheme, the debug signal transmitted from the first arbitration circuit is distributed to the first inter-chip high-speed interface according to the address of the data and the remainder value of N through the N-mode address distribution circuit. In this way, the debug signal can be evenly distributed to each first inter-chip high-speed interface, thereby fully utilizing the bandwidth of each first inter-chip high-speed interface and improving data transmission efficiency.

[0011] Furthermore, the chip also includes: a selector, a first input port of the selector is connected to the first on-chip network, and a second input port of the selector is configured to receive functional data generated when the chip is running; and an output end of the selector is connected to the first inter-chip high-speed interface.

[0012] In the above implementation scheme, by setting the selector, the first inter-chip high-speed interface can be reused by both the normal operation data of the chip and the debugging signal of the post-silicon verification stage, thereby reducing the number of interfaces required to be set in the chip and reducing the chip area.

[0013] Furthermore, the debug interfaces of the target modules are respectively configured with different debug signal base addresses and debug signal initial offset addresses; the debug interfaces are configured to: assign addresses to the debug signals in turn based on the debug signal base addresses and the debug signal initial offset addresses, and send the debug signals; wherein the addresses of the debug signals are obtained by combining the debug signal base addresses of the debug interfaces and the debug signal offset addresses corresponding to the debug signals; and the debug signal offset addresses of the debug signals are obtained by sequentially adding the debug signal initial offset addresses of the debug interfaces in the order in which the debug signals are received.

[0014] In the above implementation scheme, by configuring different debug signal base addresses and debug signal initial offset addresses for the debug interface of each target module, and when sending a debug signal, an address is allocated to each debug signal in turn based on the debug signal base address and the debug signal initial offset address, and the debug signal is sent. In this way, the address of the debug signal received by the debug interface can be automatically determined, thereby improving the accuracy of the debug signal address each time the debug signal is sent.

[0015] Furthermore, the first on-chip network is an on-chip network dedicated to connecting the debug interface of the target module with the first inter-chip high-speed interface.

[0016] In the above implementation scheme, the debug signal is forwarded by using an on-chip network connected to the debug interface dedicated to the target module and the first inter-chip high-speed interface. In this way, the debug signals used for post-silicon verification and the functional signals generated by the normal operation of the chip do not interfere with each other, thereby avoiding affecting the normal operation of the chip.

[0017] Furthermore, the first inter-chip high-speed interface is configured to: have the ability to read signals from the second inter-chip high-speed interface while sending the debug signal to the second inter-chip high-speed interface when post-silicon verification and the first chip and the second chip work together.

[0018] In the above implementation scheme, when the first chip is post-silicon verified, the first chip will only occupy the data writing function of the second inter-chip high-speed interface, and will not occupy the data reading function of the second inter-chip high-speed interface. Correspondingly, when the first chip is post-silicon verified, the post-silicon verification only uses the first inter-chip high-speed interface for write operations, and will not perform read operations. Then, in the case where the first chip and the second chip work together, there will be a need for data interaction between the chips. To this end, the first inter-chip high-speed interface is configured to have the ability to read signals from the second inter-chip high-speed interface while sending debug signals to the second inter-chip high-speed interface when the post-silicon verification and the first chip and the second chip work together are performed at the same time. In this way, while the first chip is post-silicon verified, the first chip can complete at least part of the collaborative operation tasks, thereby improving the chip operation capability when the chip is post-silicon verified.

[0019] Furthermore, the structures of the first chip and the second chip are completely consistent.

[0020] In the above implementation scheme, by reusing the same chip for transfer, the collection and storage of debugging signals in the post-silicon verification stage of the chip can be realized without the need to establish a special debugging network, which is more applicable.

[0021] Furthermore, the first inter-chip high-speed interface and the second inter-chip high-speed interface are P2P interfaces.

[0022] In the above implementation scheme, the P2P interface is used as the first inter-chip high-speed interface and the second inter-chip high-speed interface, and the single P2P interface can reach a rate of tens of GByte / s or even hundreds of GByte / s. Therefore, the P2P interface can better match the data bandwidth within the chip and meet the export requirements of the debug signal. At the same time, the protocol used by the P2P interface can be customized, which is also convenient for chip design manufacturers to design and modify the upper-layer software for post-silicon verification, thereby facilitating post-silicon verification.

[0023] An embodiment of the present application also provides a post-silicon verification method, which is applied to any of the above-mentioned post-silicon verification systems, and the method includes: the debug interface of each target module in the first chip aggregates the debug signals in the corresponding target module, and sends the debug signals to the first inter-chip high-speed interface through the first on-chip network; the first inter-chip high-speed interface sends the debug signal to the second inter-chip high-speed interface of the second chip; the second inter-chip high-speed interface sends the debug signal to the off-chip storage body through the second on-chip network for storage, so that the upper-layer device can obtain the debug signal from the off-chip storage body for post-silicon verification.

[0024] In the above implementation scheme, the debug interface of each target module in the first chip aggregates the debug signals in the target module to which it belongs and transmits them to the second chip through the first inter-chip high-speed interface, so that the off-chip storage stores the debug signals of the first chip, so that the upper-layer device can obtain the debug signals from the off-chip storage when needed to perform post-silicon verification. Compared with the prior art, the above implementation scheme does not need to borrow the on-chip storage, so the working scene of the first chip can be unaffected by the debug (debugging) in the post-silicon verification stage, so that normal data cannot use the corresponding storage, and thus will not damage the performance test index. In addition, by using the inter-chip high-speed interface of the chip to export the debug data, compared with the method of exporting using the pin or interface bandwidth, the on-chip data bandwidth can be not occupied, thereby not damaging the performance test index. At the same time, the bandwidth of the inter-chip high-speed interface is higher, and the number is also easier to increase or decrease, which can match the data bandwidth in the chip, and the debug signal can be quickly and completely exported to the off-chip storage. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0026] Figure 1A basic structural diagram of a post-silicon verification system provided in an embodiment of the present application;

[0027] Figure 2 A schematic diagram of the structure of a post-silicon verification system provided with a first arbitration circuit according to an embodiment of the present application;

[0028] Figure 3 A schematic diagram of the structure of a post-silicon verification system provided with an N-mode address distribution circuit provided in an embodiment of the present application;

[0029] Figure 4 A schematic diagram of the structure of a post-silicon verification system provided by an embodiment of the present application, which is provided with a first arbitration circuit and an N-mode address distribution circuit;

[0030] Figure 5 A schematic diagram of a first chip structure provided with a selector provided in an embodiment of the present application;

[0031] Figure 6 A schematic diagram of a more specific post-silicon verification system provided in an embodiment of the present application;

[0032] Figure 7 A schematic diagram of a storage format of debug signals of each target module in a storage body provided in an embodiment of the present application;

[0033] Figure 8 A schematic diagram of the structure of an optional post-silicon verification system composed of three chips provided in an embodiment of the present application;

[0034] Fig. 9 A schematic diagram of the structure of another optional post-silicon verification system composed of three chips provided in an embodiment of the present application;

[0035] Fig.10 A schematic diagram of a post-silicon verification method provided in an embodiment of the present application;

[0036] Fig.11 A schematic diagram of the structure of a specific post-silicon verification system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0037] In order to be able to understand the features and technical contents of the embodiments of the present application in more detail, the implementation of the embodiments of the present application is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present application. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0038] The terms "first", "second", etc. in the specification and claims of the embodiments of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the embodiments of the present application described here. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0039] Unless otherwise stated, the term "plurality" means two or more.

[0040] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.

[0041] The present application provides a post-silicon verification system, which can be found in Figure 1 As shown, the post-silicon verification system includes a first chip, a second chip and an off-chip memory bank.

[0042] The first chip includes: a first on-chip network, a target module to be verified in the post-silicon verification phase, and a first inter-chip high-speed interface; the first inter-chip high-speed interface is connected to the debugging interface of each target module through the first on-chip network.

[0043] In the embodiment of the present application, the target modules to be verified in the post-silicon verification stage can be determined by engineers. In addition, considering that the engineers in the chip design stage and the engineers in the post-silicon verification stage are often different, in some implementations of the embodiment of the present application, in order to count the post-silicon verification coverage as much as possible, all functional modules can be used as target modules.

[0044] In the embodiments of the present application, a functional module refers to a collection of circuits in a chip that implement a certain function, such as a convolution operation circuit that implements a convolution operation, a multiplication operation circuit that implements a multiplication operation, and so on.

[0045] In the embodiments of the present application, Figure 1 As shown, the target module is configured with a debug interface for summarizing the debug signals in the target module that need to be verified in the post-silicon verification stage. It can be understood that the debug signal can be a signal output by the hardware (such as a register) required for verification in the post-silicon verification stage in the target module. For example, the debug signal can be a signal output by the hardware in the target module that needs to count the coverage. The debug interface is connected to the output end of the hardware required for verification in the post-silicon verification stage in the target module, thereby summarizing the debug signals generated in the target module.

[0046] In an embodiment of the present application, the debug signal may be a coverage signal used to perform netlist coverage statistics in the post-silicon stage, or may be debug data for functional verification and debugging, or may be other signals required for post-silicon stage verification.

[0047] In the embodiment of the present application, the second chip includes: a second inter-chip high-speed interface and a second on-chip network, wherein the second inter-chip high-speed interface is connected to the first inter-chip high-speed interface of the first chip, and the second inter-chip high-speed interface is also connected to the off-chip storage through the second on-chip network.

[0048] In the embodiment of the present application, the debug interface of the target module in the first chip can convert the collected debug signal into a NOC bus signal, and transmit the debug signal to the bus of the first on-chip network. The first on-chip network can transmit the debug signal on the bus to the first inter-chip high-speed interface, thereby sending the debug signal of each target module to the second inter-chip high-speed interface of the second chip through the first inter-chip high-speed interface, and then transmitting it to the off-chip storage body through the second on-chip network of the second chip for storage.

[0049] In this way, when such a chip is undergoing post-silicon verification, the debug signals to be verified in the post-silicon verification stage can be forwarded to the first inter-chip high-speed interface through the debug interface, and then sent to the off-chip storage body for storage through the second chip. In this way, compared with the prior art, since the debug signals are specially summarized and output by the debug interfaces configured by each target module in the chip, the integrity and timing of the debug signals summarized and stored in the off-chip storage body are better. By outputting and saving the debug signals, the demand for debug signals in the post-silicon verification stage can be met, and the code coverage of the netlist in the post-silicon verification stage can also be counted and analyzed, that is, the statistics of the netlist coverage can be realized in the post-silicon verification stage. At the same time, since the debug signals are stored in the off-chip storage body, there is no need to borrow the on-chip storage body, so there will be no situation where the debug signals and the normal data generated when the chip is operating normally compete for the storage body, that is, there will be no situation where the normal data generated when the chip is operating normally cannot use the corresponding storage body, and thus the performance test indicators will not be damaged. In addition, by using the chip's inter-chip high-speed interface to export debug data, compared to using pin or interface bandwidth to export, it does not occupy the on-chip data bandwidth, thus not damaging the performance test indicators. At the same time, the bandwidth of the inter-chip high-speed interface is higher, and the number is easier to increase or decrease, which can match the data bandwidth within the chip, and can quickly and completely export debug signals to off-chip storage.

[0050] In the embodiment of the present application, the off-chip storage body can be a storage body in other chips, or it can be an independently set storage body. In the embodiment of the present application, the off-chip storage body can adopt HBM (High Bandwidth Memory), DDR (Double Data Rate Synchronous Dynamic Random Access Memory), DDR2 (Second Generation Double Data Rate Synchronous Dynamic Random Access Memory), DDR3 (Third Generation Double Data Rate Synchronous Dynamic Random Access Memory), DDR4 (Fourth Generation Double Data Rate Synchronous Dynamic Random Access Memory), DDR5 (Fifth Generation Double Data Rate Synchronous Dynamic Random Access Memory), LPDDR (Low Power Double Data Rate SDRAM), SRAM (Static Random-Access Memory), DRAM (Dynamic Random Access Memory), memory, hard disk, floppy disk, optical disk, flash memory, U disk and other storage bodies, but not as a limitation.

[0051] In the embodiment of the present application, the debugging interface can arrange the debugging signals in sequence to obtain a group of data that meets the set bit width requirement, and then send the group of data at one time. Figure 1 As shown, usually a debug signal is 1 bit. Assuming that the bit width is required to be n+1, debug signal 0, debug signal 1, debug signal 2...debug signal n can be arranged in sequence to obtain a group of data with a bit width of n+1.

[0052] In the embodiment of the present application, an address can be assigned to the debug interface, and then after the debug interface is aggregated to each debug signal, each debug signal can obtain a corresponding address bit by bit. For example, the debug signal starting address A can be assigned to the debug interface, such as Figure 1 As shown, the debug signal 0 received by the debug interface can be assigned the corresponding address A, the debug signal 1 received by the debug interface can be assigned the corresponding address A+1, the debug signal 2 received by the debug interface can be assigned the corresponding address A+2... and so on, the address of each debug signal can be obtained.

[0053] When sending a debug signal, the debug interface may carry the address of the debug signal together with the send, so that the off-chip storage body can store the debug signal according to the corresponding address. It can be understood that when sending the address of the debug signal, only the debug signal start address can be sent, so that the address of each debug signal can be obtained according to the above address allocation logic. Of course, the corresponding address can also be sent independently for each debug signal.

[0054] Optionally, in an embodiment of the present application, one or more address registers may be configured for each debug interface to record the debug signal start address assigned to each debug interface, or to record the address of the debug signal collected by each debug interface.

[0055] In the embodiment of the present application, there may be one or more target modules. When there are multiple target modules, a first arbitration circuit may be configured in the first on-chip network. Figure 2 As shown, the input ports of the first arbitration circuit are respectively connected to the debugging interfaces of the target modules, and the output ports of the first arbitration circuit are respectively connected to the first inter-chip high-speed interfaces.

[0056] When the debug interfaces of multiple target modules output debug signals to the first on-chip network, the first arbitration circuit can perform arbitration, thereby selecting the debug signal of one target module from the debug signals of the multiple target modules and sending it to the first inter-chip high-speed interface for external transmission. When the debug signal of one target module is completely transmitted, the debug signal of one target module is continuously selected from the debug signals of the target modules that have not been transmitted and sent to the first inter-chip high-speed interface for external transmission. This process is repeated in this way until the debug signals of all target modules are completely transmitted.

[0057] In this way, by setting up the first arbitration circuit in the first on-chip network, the first arbitration circuit can be used to arbitrate the debug signals sent by multiple target modules, and determine which target module's debug signal is currently exported to the off-chip storage through the first inter-chip high-speed interface.

[0058] In the embodiment of the present application, the first arbitration circuit can use but is not limited to arbitration mechanisms such as polling arbitration for arbitration. In the embodiment of the present application, the specific structure of the first arbitration circuit can be implemented by various existing arbitration circuit structures, and the present application does not limit it.

[0059] Exemplarily, assuming that the debug interface of target module 0 to target module n sends a debug signal to the first on-chip network, the first arbitration circuit can send the received debug signals of each target module to the first inter-chip high-speed interface for external transmission in a polling manner. For example, the polling order can be set to target module 0 to target module n, then the first arbitration circuit can first query the debug signal of target module 0, and send it to the first inter-chip high-speed interface for external transmission. Then, the first arbitration circuit can first query the debug signal of target module 1, and send it to the first inter-chip high-speed interface for external transmission. Similarly, after the first arbitration circuit queries the debug signal of target module n and sends it to the first inter-chip high-speed interface for external transmission, it queries the debug signal of target module 0 again. In this process, if a target module is polled and it is found that the debug signal of the target module does not exist, the target module can be skipped and the debug signal of the next target module can be queried.

[0060] In the embodiment of the present application, the number of the first inter-chip high-speed interface can be one or more. Optionally, the number of the first inter-chip high-speed interface can be determined by the bandwidth of the first inter-chip high-speed interface and the data bandwidth inside the chip (i.e., the on-chip bandwidth). For example, a suitable number of first inter-chip high-speed interfaces can be set so that the total bandwidth of the first inter-chip high-speed interface can be greater than or equal to the on-chip bandwidth of the chip, thereby better meeting the export requirements of the debug signal.

[0061] In some implementations of the embodiments of the present application, see Figure 3 As shown, when the number of the first inter-chip high-speed interfaces is multiple, for example, N (N is an integer greater than or equal to 2), the first on-chip network may include an N-mode address distribution circuit. The input port of the N-mode address distribution circuit is connected to the debug interface of the target module, and the N output ports of the N-mode address distribution circuit are respectively connected to the N first inter-chip high-speed interfaces.

[0062] The N-module address distribution circuit is configured to distribute the received debug signal to the first inter-chip high-speed interface corresponding to the remainder value of the address of the debug signal and N according to the remainder value of the address of the debug signal and N.

[0063] Exemplarily, assume that N is 4, that is, there are 4 first inter-chip high-speed interfaces in the chip, which are respectively recorded as the first inter-chip high-speed interface 0, the first inter-chip high-speed interface 1, the first inter-chip high-speed interface 2 and the first inter-chip high-speed interface 3. The N-mode address distribution circuit is a 4-mode address distribution circuit, and the operation performed is: for any debug signal, the address of the debug signal is divided by 4 to obtain a remainder value. For example, for address 0000, the remainder value after division by 4 is 0, and the debug signal corresponding to address 0000 can be allocated to the first inter-chip high-speed interface 0. Similarly, for address 0001, the remainder value after division by 4 is 1, and the debug signal corresponding to address 0001 can be allocated to the first inter-chip high-speed interface 1. For address 0002, the remainder value after division by 4 is 2, and the debug signal corresponding to address 0002 can be allocated to the first inter-chip high-speed interface 2. For address 0003, the remainder value after division by 4 is 3, and the debug signal corresponding to address 0003 can be allocated to the first inter-chip high-speed interface 3. By analogy, the received debug signals of the target modules can be evenly distributed to each first inter-chip high-speed interface.

[0064] In this way, the debug signal transmitted from the first arbitration circuit is distributed to the first inter-chip high-speed interface according to the address of the data and the remainder value of N through the N-mode address distribution circuit. The debug signal can be evenly distributed to each first inter-chip high-speed interface, thereby fully utilizing the bandwidth of each first inter-chip high-speed interface and improving data transmission efficiency.

[0065] It can be understood that in the above embodiment, the N-mode address distribution circuit can be implemented by using a division operation circuit, but this is not a limitation.

[0066] It can also be understood that in the embodiment of the present application, in addition to using the above-mentioned N-module address distribution circuit to distribute debug signals based on the address of the debug signal and the remainder value of N, other data distribution circuits can also be used to distribute debug signals to each first inter-chip high-speed interface.

[0067] Exemplarily, for the debug signal of any target module, it can be evenly divided into N segments, and then a segment of the debug signal is allocated to each first inter-chip high-speed interface. At this time, a shift circuit can be used as a data distribution circuit, but is not limited to it, to achieve the equal distribution of the debug signal of the target module. For example, assuming that N is 4, that is, there are 4 first inter-chip high-speed interfaces in the chip, which are respectively recorded as first inter-chip high-speed interface 0, first inter-chip high-speed interface 1, first inter-chip high-speed interface 2 and first inter-chip high-speed interface 3. Assume that the address of the debug signal sent by a certain debug interface is from address 000000000 to address 111111111 (i.e., from 0 to 511). At this time, the debug signal corresponding to address 000000000 to 001111111 (i.e., 0 to 127) can be divided into one section and distributed to the first inter-chip high-speed interface 0, the debug signal corresponding to address 010000000 to 011111111 (i.e., 128 to 255) can be divided into one section and distributed to the first inter-chip high-speed interface 1, the debug signal corresponding to address 100000000 to 101111111 (i.e., 256 to 383) can be divided into one section and distributed to the first inter-chip high-speed interface 2, and the debug signal corresponding to address 110000000 to 111111111 (i.e., 384 to 511) can be divided into the last section and distributed to the first inter-chip high-speed interface 3.

[0068] In the embodiment of the present application, when there are multiple target modules and multiple first inter-chip interfaces, the above Figure 2 and Figure 3 The solutions shown can be implemented in combination, for example Figure 4 As shown. At this time, the input port of the N-mode address distribution circuit is connected to the output port of the first arbitration circuit, and the output port of the first arbitration circuit is respectively connected to each first inter-chip high-speed interface. Correspondingly, the N-mode address distribution circuit is configured to distribute the received debug signal to the first inter-chip high-speed interface corresponding to the remainder value according to the address of the debug signal and the remainder value of N. At this time, the working logic of the first arbitration circuit and the N-mode address distribution circuit is consistent with the above, except that the debug signal of the target module needs to be arbitrated by the first arbitration circuit before it can reach the N-mode address distribution circuit for debug signal distribution.

[0069] In an embodiment of the present application, the debug interface of each target module is respectively configured with different debug signal base addresses and debug signal initial offset addresses. Each debug interface is configured as follows: based on the debug signal base address and the debug signal initial offset address (the combination of the two is the debug signal starting address when each debug interface sends a debug signal each time), an address is assigned to each debug signal in turn, and the debug signal is sent. Wherein, the address of each debug signal is obtained by combining the debug signal base address of the debug interface and the debug signal offset address corresponding to each debug signal. The debug signal offset address of each debug signal is obtained by the debug interface being accumulated on the debug signal initial offset address in turn according to the receiving order of each debug signal.

[0070] For example, assuming that the debug interface is configured as follows: the debug signal base address is base address, and the debug signal initial offset address is offset addr0, then the debug interface will assign addresses to each debug signal in the following order: baseaddress+offset addr0, base address+offset addr1, base address+offset addr2, ..., base address+offset addrn, where offset addrn is the address after offset addr0 is accumulated by n.

[0071] Considering that each time the first chip sends a debug signal to the off-chip storage through the inter-chip high-speed interface, the address of the next debug signal sent to the off-chip storage should be updated to avoid data overwriting in the off-chip storage. To this end, the outgoing debug signal of each debug interface and the updating of the debug signal start address of each debug interface can be controlled based on the clock signal. For example, when the rising edge of the clock signal arrives, the collected debug signal can be sent to the first on-chip network once, and the debug signal start address of each debug interface can be updated.

[0072] In the embodiment of the present application, each time a debug signal is sent to an off-chip storage body through an inter-chip high-speed interface, the bit width used is the total bit width of all debug signals sent out. Therefore, each time the debug signal start address of each debug interface is updated, the total bit width of the debug signal sent this time can be added to the original debug signal start address of each debug interface to obtain the latest debug signal start address of each debug interface.

[0073] Exemplarily, the debug signal base address can be kept unchanged, and the debug signal initial offset address can be added to the total bit width of the debug signal sent this time to obtain a new debug signal initial offset address. For example, if the total bit width of the debug signal sent this time is 512 bits, and the original debug signal initial offset address is offset addr0, then the new debug signal initial offset address is offset addr0+512 bits.

[0074] In an embodiment of the present application, an address self-adding circuit can be configured for each debug interface, so that when the debug signal starting address of each debug interface is updated, the address self-adding circuit of each debug interface is used to automatically add the debug signal starting address of the debug interface according to the total bit width of the debug signal sent this time.

[0075] In an embodiment of the present application, after the debug interface sends a debug signal once, the upper-layer software may also update the debug signal start address of the debug interface and reallocate the updated debug signal start address to the debug interface to replace the original debug signal start address.

[0076] In this way, the addresses of the debug signals received by the debug interface can be automatically accumulated, thereby improving the accuracy of the debug signal addresses each time the debug signal is sent.

[0077] In an embodiment of the present application, each debug interface can be specifically configured to: send a debug signal according to the bus width of the first on-chip network, and update its own debug signal start address according to the bus width of the first on-chip network after sending the debug signal.

[0078] In the embodiment of the present application, considering that there may be collaborative work between chips, the first inter-chip interface can be used for interconnection and information exchange between chips, thereby realizing collaborative work between chips. Then, in order to meet the use requirements of the first inter-chip interface when the chip is working normally, such as Figure 5 As shown, the first chip may also include a selector. The first input port of the selector is connected to the first on-chip network, and the second input port of the selector is configured to receive functional data generated when the chip is running; the output end of the selector is connected to the first inter-chip high-speed interface. In this way, when post-silicon verification is not performed, the control selector is controlled to select the functional data generated when the chip is running and the first inter-chip interface, and when post-silicon verification is performed, the control selector is controlled to select the debug signal output by the debug interface and the first inter-chip interface. In this way, the first inter-chip high-speed interface can be reused by the normal operating data of the chip and the debug signal in the post-silicon verification stage at the same time, thereby reducing the number of interfaces required to be set in the chip and reducing the chip area.

[0079] It is understandable that for a chip, an on-chip network needs to be set up to meet the instruction distribution and data interaction requirements when the chip is operating normally. Then, in a feasible implementation, the first on-chip network for implementing the debug signal distribution in the embodiment of the present application can be directly implemented by using the on-chip network in the chip that is used to meet the instruction distribution and data interaction requirements when the chip is operating normally.

[0080] In other implementations, in addition to the on-chip network used to meet the instruction distribution and data interaction requirements when the chip is operating normally, a separate on-chip network dedicated to the debug interface of the target module connected to the first inter-chip high-speed interface can be set to realize the distribution of debug signals. In this way, by using the on-chip network dedicated to the debug interface of the target module connected to the first inter-chip high-speed interface to forward debug signals, the debug signals used for post-silicon verification and the functional signals generated by the normal operation of the chip can be prevented from interfering with each other, thereby avoiding affecting the normal operation of the chip.

[0081] In an embodiment of the present application, the first inter-chip high-speed interface and the second inter-chip high-speed interface can be implemented using a P2P interface. The protocol used by the P2P interface can be customized, so that the chip design manufacturer can design and modify the upper-layer software for post-silicon verification, and adjust the number of the first inter-chip interface, so as to facilitate post-silicon verification. In addition, a single P2P interface can reach a rate of tens of GByte / s or even hundreds of GByte / s, so the use of a P2P interface can also better match the data bandwidth within the chip and meet the export requirements of the debug signal.

[0082] In some optional implementations of the embodiments of the present application, the second inter-chip high-speed interface of the second chip is of the same type as the first inter-chip high-speed interface of the first chip. For example, if the first inter-chip high-speed interface is a P2P interface, the second inter-chip high-speed interface is also a P2P interface. In addition, the number of the second inter-chip high-speed interfaces of the second chip is equal to the number of the first inter-chip high-speed interfaces to ensure that the debug signal transmitted from the first chip can be fully obtained. For example, if there are 4 first inter-chip high-speed interfaces on the first chip, there should be 4 second inter-chip high-speed interfaces on the second chip.

[0083] In the embodiment of the present application, the second on-chip network of the second chip can be implemented by using an on-chip network within the chip that is used to meet the instruction distribution and data interaction requirements during normal operation of the chip.

[0084] In the embodiments of the present application, Figure 6 As shown, the second chip may also include a high-speed cache connected between the off-chip memory and the second on-chip network, and used for caching the debugging signal transmitted from the first chip.

[0085] In the embodiments of the present application, Figure 6 As shown, a second arbitration circuit may be provided in the second on-chip network of the second chip. An input end of the second arbitration circuit is connected to a second inter-chip high-speed interface of the second chip, and an output end of the second arbitration circuit is connected to a cache, so that after a debug signal is transmitted from each second inter-chip high-speed interface, the debug signal may be sequentially stored in the cache.

[0086] In the embodiment of the present application, the second arbitration circuit may adopt, but is not limited to, a polling strategy based on the second inter-chip high-speed interface, or perform arbitration based on the order in which the debug signals are received.

[0087] It should be noted that in the embodiment of the present application, the off-chip storage body can have a unified address encoding with the debug interface of the first chip, and when the first chip sends a debug signal, it also sends the address of the debug signal to the second signal, so that the second chip can store the debug signal at the corresponding address location according to the address of the received debug signal.

[0088] Exemplarily, the debug signals of the target modules (assuming there are target modules 0 to m) in the first chip can be as follows: Figure 7 The form shown is stored in off-chip memory.

[0089] In the embodiment of the present application, as described above, the chips can use the inter-chip high-speed interface to achieve collaborative work. When the first chip is post-silicon verified, the first chip will only occupy the data writing function of the second inter-chip high-speed interface, and will not occupy the data reading function of the second inter-chip high-speed interface. Correspondingly, when the first chip is post-silicon verified, the post-silicon verification only uses the first inter-chip high-speed interface for write operations, and will not perform read operations. Then, in some implementations of the embodiment of the present application, the first inter-chip high-speed interface can be configured as: when the post-silicon verification and the first chip and the second chip work together at the same time, while sending a debug signal to the second inter-chip high-speed interface, it has the ability to read signals from the second inter-chip high-speed interface. In this way, while the first chip is post-silicon verified, the first chip can complete at least part of the collaborative work tasks, thereby improving the chip operation capability when the chip is post-silicon verified.

[0090] Optionally, in the embodiment of the present application, the structures of the first chip and the second chip may be consistent. That is, the second chip may also have the target module, debug interface, first arbitration circuit, etc. in the first chip. Similarly, the first chip may also have a second on-chip network, cache, second arbitration circuit, etc.

[0091] In the embodiment of the present application, the post-silicon verification system may also include upper-layer devices, such as fixed terminals (such as desktop computers, etc.), mobile terminals (such as smart phones, smart wearable devices, etc.), servers, etc. The upper-layer devices may access the off-chip storage through a PCIE (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) bus, etc., and obtain the debugging signal therefrom, so as to prepare waveforms according to the debugging signal, or perform operations such as statistical coverage, etc.

[0092] In the embodiment of the present application, the first chip and the second chip can be but are not limited to a CPU (Central Processing Unit) chip, a GPU (Graphics Processing Unit) chip, an AI (Artificial Intelligence) chip, an MCU (Microcontroller Unit), a GPGPU (General-Purpose Computing On Graphics Processing Unit) chip, etc., but are not limited thereto.

[0093] In the embodiment of the present application, there may be a third chip or even more chips. For example, the chips have the same structure. When there is a third chip, see Figure 8 and Fig. 9 As shown, the chips can be connected sequentially through the inter-chip high-speed interface, the chips can be connected in a star shape through the inter-chip high-speed interface, or the chips can be connected through other topological structures, which is not limited in the embodiments of the present application.

[0094] When there are three or more chips, multiple chips can be used as chips for post-silicon verification, and the remaining chips connected to them can be used as transfers to access the off-chip memory to store debug signals. The implementation method is similar to that of two chips, and will not be repeated here.

[0095] For example, Figure 8 In the above solution, the first chip and the third chip can use the second chip as a transfer to realize the storage of the debugging signal to the off-chip memory. Fig. 9 In the solution, the first chip uses the third chip and the second chip as transfer to realize the storage of the debug signal in the off-chip memory; the third chip uses the second chip as transfer to realize the storage of the debug signal in the off-chip memory.

[0096] Based on the same inventive concept, the embodiment of the present application also provides a post-silicon verification method, which can be applied to the above-mentioned post-silicon verification system. Fig.10 As shown, the post-silicon verification method may include:

[0097] S101: The debug interface of each target module in the first chip aggregates the debug signals in the target module, and sends the debug signals to the first inter-chip high-speed interface through the first on-chip network.

[0098] S102: The first inter-chip high-speed interface sends the debugging signal to the second inter-chip high-speed interface of the second chip.

[0099] S103: The second inter-chip high-speed interface sends the debug signal to an off-chip storage body through a second on-chip network for storage, so that an upper-layer device can obtain the debug signal from the storage body for post-silicon verification.

[0100] It can be understood that in the above method, the relevant operations performed in the first chip can refer to the description in the aforementioned chip embodiment, and the corresponding operations are performed according to the functions of the corresponding devices in the chip to complete the transmission of the debug signal to the second chip, which will not be repeated here.

[0101] To facilitate understanding of the solution of the embodiment of the present application, Fig.11 Taking the system shown as an example, the scheme of the embodiment of the present application is exemplified.

[0102] like Fig.11 As shown in the figure, a debug interface is designed in each target module. The debug interface takes the hardware signal of the chip target module that needs to be covered as the main input. The debug interface is responsible for converting the hardware signal into a NOC bus signal and transmitting the address to the NOC bus according to the register configuration address. In each clock cycle, the address is automatically aligned with the bit width of the NOC bus for self-addition. The address uses the physical address, and the physical addresses of the two chips are uniformly addressed.

[0103] A dedicated first on-chip network is designed, rather than a multiplexed on-chip network within the chip that is used to meet the instruction distribution and data interaction requirements during normal operation of the chip, to ensure that the performance of the debug signal and the performance of the functional data generated by the normal operation of the chip do not interfere with each other. At the same time, the introduction of a dedicated first on-chip network can ensure that multiple target modules are stimulated at the same time and jointly perform coverage statistics. When multiple target modules perform joint coverage statistics, the first arbitration circuit in the first on-chip network can use a polling strategy to arbitrate the debug signals of multiple target modules. For the scenario of coverage statistics of a single target module, the debug signal of a single target module can always obtain an arbitration token. The debug signal after arbitration is evenly distributed to the four P2P interfaces of the chip through the 4-mode address distribution circuit operation to make full use of the bandwidth of the four P2P interfaces.

[0104] Selectors are deployed in front of the four P2P interfaces, and can be configured to send functional data or debug signals. In coverage data transmission mode (i.e., in the case of post-silicon verification), there are only write operations on the P2P interface, and no read operations. Chip 0 can still read functional data from chip 1 for data processing.

[0105] The second on-chip network of chip 1 uses only the functional path, receives the debugging signal sent by chip 0 through the P2P interface, and writes it into the storage body after polling arbitration of the second on-chip network.

[0106] When performing post-silicon verification, configure the debug signal start address of each target module, set the selector to the coverage data transmission mode, and run the verification test case on chip 0. After that, the upper-layer device reads the debug signal from the memory bank of chip 1 through the PCIE bus, and prepares a waveform or counts the coverage based on the debug signal.

[0107] In the present application, the various embodiments and implementation modes provided above can be freely combined to obtain new embodiments without conflict.

[0108] In the embodiments provided in the present application, it should be understood that the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some communication interface, device or unit, which may be electrical, mechanical or other forms.

[0109] In this document, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0110] As used herein, a plurality refers to two or more than two.

[0111] The above description is only an embodiment of the present application and is not intended to limit the protection scope of the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A post-silicon verification system, characterized in that: It includes a first chip, a second chip and an off-chip storage body; The first chip includes: a first on-chip network, a target module to be verified in a post-silicon verification phase, and a first inter-chip high-speed interface; the target module is configured with a debug interface for summarizing debug signals in the target module to be verified in a post-silicon verification phase; the first inter-chip high-speed interface is connected to the debug interfaces of the target modules through the first on-chip network; The second chip includes: a second inter-chip high-speed interface and a second on-chip network; the second inter-chip high-speed interface is connected to the first inter-chip high-speed interface, and the second inter-chip high-speed interface is also connected to the off-chip storage through the second on-chip network; The first chip is used to send the debugging signals of each target module to the off-chip storage body for storage via the second chip in the post-silicon verification stage.

2. The post-silicon verification system according to claim 1, characterized in that: There are multiple target modules, and the first network on chip includes: A first arbitration circuit, wherein input ports of the first arbitration circuit are respectively connected to the debugging interfaces of the target modules, and output ports of the first arbitration circuit are respectively connected to the first inter-chip high-speed interfaces.

3. The post-silicon verification system according to claim 2, characterized in that: The number of the first inter-chip high-speed interfaces is N, where N is an integer greater than or equal to 2; and the first on-chip network includes: an N-mode address distribution circuit, wherein an input port of the N-mode address distribution circuit is connected to an output port of the first arbitration circuit, and the output ports of the first arbitration circuit are respectively connected to each of the first inter-chip high-speed interfaces; The N-mode address distribution circuit is configured to distribute the received debug signal to the first inter-chip high-speed interface corresponding to the remainder value of the address of the debug signal and N according to the remainder value of the address of the debug signal and N.

4. The post-silicon verification system according to claim 1, wherein: The chip further comprises: A selector, wherein a first input port of the selector is connected to the first on-chip network, and a second input port of the selector is configured to receive functional data generated when the chip is running; and an output end of the selector is connected to the first inter-chip high-speed interface.

5. The post-silicon verification system according to claim 1, characterized in that: The debugging interface of each target module is respectively configured with a different debugging signal base address and a debugging signal initial offset address; Each of the debug interfaces is configured to: assign an address to each of the debug signals in sequence based on the debug signal base address and the debug signal initial offset address, and send the debug signal; wherein the address of each of the debug signals is obtained by combining the debug signal base address possessed by the debug interface and the debug signal offset address corresponding to each debug signal; and the debug signal offset address of each of the debug signals is obtained by sequentially accumulating the debug signal initial offset address according to the order in which each of the debug signals is received by the debug interface.

6. The post-silicon verification system according to claim 1, wherein: The first on-chip network is a network on chip dedicated to connecting the debug interface of the target module with the first inter-chip high-speed interface.

7. The post-silicon verification system according to claim 1, characterized in that: The first inter-chip high-speed interface is configured to have the ability to read signals from the second inter-chip high-speed interface while sending the debug signal to the second inter-chip high-speed interface when post-silicon verification is performed and the first chip and the second chip work together.

8. The post-silicon verification system according to any one of claims 1 to 7, characterized in that: The structures of the first chip and the second chip are completely consistent.

9. The post-silicon verification system according to any one of claims 1 to 7, characterized in that: The first inter-chip high-speed interface and the second inter-chip high-speed interface are P2P interfaces.

10. A post-silicon verification method, characterized in that: Applied to the post-silicon verification system according to any one of claims 1 to 9, the method comprises: The debug interface of each target module in the first chip aggregates the debug signals in the target module, and sends the debug signals to the first inter-chip high-speed interface through the first on-chip network; The first inter-chip high-speed interface sends the debug signal to a second inter-chip high-speed interface of the second chip; The second inter-chip high-speed interface sends the debugging signal to the off-chip storage body through the second on-chip network for storage, so that an upper-layer device can obtain the debugging signal from the off-chip storage body for post-silicon verification.

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