PCIe asset information generation method and device and program product

Abstract

The embodiment of the invention provides a PCIe asset information generation method and device and a program product, and is applied to the technical field of computers. The method comprises the following steps: for each PCIe slot position on a mainboard of the electronic equipment, determining a first bandwidth allocated for the PCIe slot position according to PCIe equipment accessed into the PCIe slot position; determining a second bandwidth of each RC according to a preset first mapping relationship between the RC and the PCIe slot and the first bandwidth allocated for each PCIe slot; and generating PCIe asset information of the electronic equipment according to the second bandwidth of each RC. The method is used for achieving the effect of improving the asset information generation accuracy of the computer system.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a method, device and program product for generating PCIe asset information. Background Art

[0002] With the development of computer technology, the functions of computer systems are constantly increasing, so the complexity of computer system structures is also increasing. In view of the complex hardware architecture in computer systems, it is necessary to collect hardware information in computer systems and perform operation monitoring and management on the hardware information.

[0003] In the prior art, hardware information management in a computer system is mainly divided into two stages: when the computer starts, the basic input / output system is first started, and the hardware device information in the computer system is collected based on the basic input / output system, and bandwidth configuration in the computer system and generation of hardware device topology information are performed based on the hardware device information; the basic input / output system synchronizes the hardware device information and topology information to the management controller of the computer system, and the generation and management of hardware device asset information are implemented based on the management controller.

[0004] Since the basic input and output system in the prior art needs to rely on the preset configuration file of the hardware device to implement the configuration when configuring the bandwidth, the prior art has the problem of low accuracy in generating asset information of the computer system. Summary of the invention

[0005] The embodiments of the present application provide a method, device and program product for generating PCIe asset information, so as to improve the accuracy of generating asset information of a computer system.

[0006] In a first aspect, an embodiment of the present application provides a method for generating PCIe asset information, which is applied to an electronic device, and the method includes:

[0007] For each PCIe slot on a motherboard of the electronic device, determining a first bandwidth allocated to the PCIe slot according to a PCIe device connected to the PCIe slot;

[0008] Determine a second bandwidth of each RC according to a preset first mapping relationship between the RC and the PCIe slot and a first bandwidth allocated to each PCIe slot;

[0009] PCIe asset information of the electronic device is generated according to the second bandwidth of each RC.

[0010] In a possible implementation, for each PCIe slot on a motherboard of an electronic device, determining a first bandwidth allocated to the PCIe slot according to a PCIe device connected to the PCIe slot includes:

[0011] Determine the bandwidth of each PCIe channel based on the PCIe version;

[0012] According to the number of PCIe channels in each PCIe slot and the bandwidth of each PCIe channel, determine the maximum bandwidth that can be allocated to each PCIe slot;

[0013] For each PCIe slot, if the total bandwidth of the PCIe devices connected to the PCIe slot is less than or equal to the maximum bandwidth that can be allocated to the PCIe slot, the total bandwidth of the PCIe devices connected to the PCIe slot is determined as the first bandwidth of the PCIe slot;

[0014] If the total bandwidth of the PCIe devices connected to the PCIe slot is greater than the maximum bandwidth that can be allocated to the PCIe slot, determining an available PCIe device among the PCIe devices connected to the PCIe slot;

[0015] The total bandwidth of available PCIe devices connected to the PCIe slot is determined as the first bandwidth of the PCIe slot.

[0016] In a possible implementation, determining an available PCIe device among PCIe devices connected to a PCIe slot includes:

[0017] If the number of PCIe devices connected to the PCIe slot is greater than 1, the PCIe devices connected to the PCIe slot are combined to obtain multiple PCIe device groups;

[0018] Calculate the total bandwidth of each PCIe device group;

[0019] A PCIe device group whose total bandwidth is less than or equal to the maximum bandwidth allocatable to the PCIe slot among the multiple PCIe device groups includes PCIe devices that are determined as available PCIe devices.

[0020] In a possible implementation manner, before generating PCIe asset information of the electronic device according to the second bandwidth of each RC, the method further includes:

[0021] After the electronic device is powered on, a second mapping relationship between the PCIe slot and the processor logic slot is obtained, as well as PCIe device information of the PCIe device connected to the motherboard of the electronic device, wherein the PCIe device information includes a PCIe device identifier and a PCIe slot connected to the PCIe device.

[0022] In a possible implementation, the method further includes:

[0023] Determine an identifier of each PCIe slot according to the second bandwidth of each RC, the first mapping relationship, and the first bandwidth allocated to each PCIe slot;

[0024] The identifier of each processor logical slot is determined according to the second mapping relationship and the identifier of each PCIe slot.

[0025] In a possible implementation, generating PCIe asset information of the electronic device according to the second bandwidth of each RC includes:

[0026] PCIe asset information of the electronic device is generated according to the second bandwidth of each RC, the first mapping relationship, the second mapping relationship, the PCIe device information, the identifier of each PCIe slot and the identifier of each processor logic slot.

[0027] In a possible implementation, the method further includes:

[0028] Obtain PCIe device error information, where the PCIe device error information includes an identifier of a target PCIe slot;

[0029] According to the identifier of the target PCIe slot, determining a target PCIe device connected to the target PCIe slot corresponding to the identifier of the target PCIe slot;

[0030] Get the PCIe device information of the target PCIe device.

[0031] In a second aspect, an embodiment of the present application provides a device for generating PCIe asset information, which is applied to an electronic device, including:

[0032] A first processing module is used to determine, for each PCIe slot on a motherboard of the electronic device, a first bandwidth allocated to the PCIe slot according to a PCIe device connected to the PCIe slot;

[0033] A second processing module, configured to determine a second bandwidth of each RC according to a preset first mapping relationship between the RC and the PCIe slot and a first bandwidth allocated to each PCIe slot;

[0034] The third processing module is used to generate PCIe asset information of the electronic device according to the second bandwidth of each RC.

[0035] In a possible implementation manner, the first processing module is further configured to:

[0036] Determine the bandwidth of each PCIe channel based on the PCIe version;

[0037] According to the number of PCIe channels in each PCIe slot and the bandwidth of each PCIe channel, determine the maximum bandwidth that can be allocated to each PCIe slot;

[0038] For each PCIe slot, if the total bandwidth of the PCIe devices connected to the PCIe slot is less than or equal to the maximum bandwidth that can be allocated to the PCIe slot, the total bandwidth of the PCIe devices connected to the PCIe slot is determined as the first bandwidth of the PCIe slot;

[0039] If the total bandwidth of the PCIe devices connected to the PCIe slot is greater than the maximum bandwidth that can be allocated to the PCIe slot, determining an available PCIe device among the PCIe devices connected to the PCIe slot;

[0040] The total bandwidth of available PCIe devices connected to the PCIe slot is determined as the first bandwidth of the PCIe slot.

[0041] In a possible implementation manner, the first processing module is further configured to:

[0042] If the number of PCIe devices connected to the PCIe slot is greater than 1, the PCIe devices connected to the PCIe slot are combined to obtain multiple PCIe device groups;

[0043] Calculate the total bandwidth of each PCIe device group;

[0044] A PCIe device group whose total bandwidth is less than or equal to the maximum bandwidth allocatable to the PCIe slot among the multiple PCIe device groups includes PCIe devices that are determined as available PCIe devices.

[0045] In a possible implementation manner, the third processing module is further configured to:

[0046] After the electronic device is powered on, a second mapping relationship between the PCIe slot and the processor logic slot is obtained, as well as PCIe device information of the PCIe device connected to the motherboard of the electronic device, wherein the PCIe device information includes a PCIe device identifier and a PCIe slot connected to the PCIe device.

[0047] In a possible implementation manner, the third processing module is further configured to:

[0048] Determine an identifier of each PCIe slot according to the second bandwidth of each RC, the first mapping relationship, and the first bandwidth allocated to each PCIe slot;

[0049] The identifier of each processor logical slot is determined according to the second mapping relationship and the identifier of each PCIe slot.

[0050] In a possible implementation manner, the third processing module is further configured to:

[0051] PCIe asset information of the electronic device is generated according to the second bandwidth of each RC, the first mapping relationship, the second mapping relationship, the PCIe device information, the identifier of each PCIe slot and the identifier of each processor logic slot.

[0052] In a possible implementation, the device further includes a fourth processing module, and the fourth processing module is used to:

[0053] Obtain PCIe device error information, where the PCIe device error information includes an identifier of a target PCIe slot;

[0054] Determine, according to the identifier of the target PCIe slot, a target PCIe device connected to the target PCIe slot corresponding to the identifier of the target PCIe slot;

[0055] Get the PCIe device information of the target PCIe device.

[0056] In a third aspect, an embodiment of the present application provides an electronic device, including: a memory, a processor;

[0057] Memory stores computer-executable instructions;

[0058] The processor executes the computer-executable instructions stored in the memory, so that the processor executes the above first aspect and / or various possible implementations of the first aspect.

[0059] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, they are used to implement the first aspect above and / or various possible implementations of the first aspect.

[0060] In a fifth aspect, an embodiment of the present application provides a computer program product, including a computer program, which, when executed by a processor, implements the above first aspect and / or various possible implementation methods of the first aspect.

[0061] The PCIe asset information generation method, device and program product provided in the embodiment of the present application determine the first bandwidth to be allocated to each PCIe slot in the current electronic device through the PCIe slot applicable to the electronic device motherboard and the PCIe device connected to each PCIe slot; based on the first bandwidth of each PCIe slot and the first mapping relationship between the RC on the motherboard and the PCIe slot, determine the second bandwidth of each RC; thereby generating the PCIe asset information of the electronic device based on the second bandwidth of each RC. Compared with the bandwidth configuration method based on the preset bandwidth configuration file in the prior art, the present application uses the information of the PCIe device and the PCIe slot connected in the computer system to realize accurate bandwidth determination, and can generate corresponding asset information based on the bandwidth information; avoids the situation where the preset configuration file and the PCIe device do not match after the PCIe device is changed, resulting in inaccurate bandwidth information allocation; thereby achieving the effect of improving the accuracy of asset information generation of the computer system. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0063] Figure 1 An architectural diagram of a server out-of-band PCIe asset information generation system provided for this application;

[0064] Figure 2 PCIe asset information generation system architecture diagram provided for this application;

[0065] Figure 3 Schematic diagram of the process of generating PCIe asset information provided in this application Figure 1 ;

[0066] Figure 4 Schematic diagram of the process of generating PCIe asset information provided in this application Figure 2 ;

[0067] Figure 5 A flowchart of a method for locating a PCIe device error provided in an embodiment of the present application;

[0068] Figure 6 A schematic diagram of a process for locating a server hardware device error provided in an embodiment of the present application;

[0069] Figure 7 A schematic diagram of the structure of a device for generating PCIe asset information provided in this application;

[0070] Figure 8 A schematic diagram of the structure of the electronic device provided in this application.

[0071] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0072] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0073] First, the terms involved in this application are explained:

[0074] Peripheral Component Interconnect Express (PCIe): is a high-speed serial computer expansion bus standard (or interface) that is widely used to connect motherboards and various external devices (such as graphics cards, storage devices, network interfaces, etc.) to achieve high-bandwidth and low-latency data transmission.

[0075] PCIe device: is an external or internal hardware component that connects to the computer motherboard via the PCIe bus standard.

[0076] PCIe channel: PCIe uses a "channel" mechanism for data transmission, and each channel can transmit data in both directions at the same time; each PCIe link consists of one to sixteen channels, usually expressed in the form of "xN", such as x1, x4, x8, x16, etc. This represents the bandwidth of the link, and x16 provides higher data transmission capacity than x1.

[0077] PCIe topology: refers to the connection method and structure between PCIe devices and between them and the motherboard in a computer system. PCIe topology determines how devices communicate with each other and how data is transmitted between these devices.

[0078] Basic Input / Output System (BIOS): A type of firmware that is responsible for starting and initializing hardware devices when the computer is turned on, and provides a basic operating environment for the operating system. BIOS is the lowest-level software in a computer system, and it is usually stored in non-volatile memory on the motherboard.

[0079] Baseboard Management Controller (BMC): is a specialized microcontroller commonly used in servers and high-performance computing systems. It is responsible for managing and monitoring the status of computer hardware and provides remote management capabilities, enabling system administrators to perform maintenance and troubleshooting without physical access to the server.

[0080] Root Complex (RC): The RC in the briefing document refers to the root complex in the PCIe topology, which is the starting point of the PCIe network and is usually integrated in the processor or chipset. It is the connection point for all PCIe devices, which is responsible for connecting the CPU and PCIe devices and managing data flow.

[0081] Complex Programmable Logic Device (CPLD): A digital integrated circuit used to implement complex logic functions. It is a flexible and programmable solution used to replace traditional logic gate arrays and fixed-function logic devices in hardware design.

[0082] SBDF: In the PCIe architecture, the device address consists of multiple parts, including Segment Number, Bus Number, Device Number and Function Number, referred to as SBDF. These parameters together define the unique identification of a PCIe device in the system. Among them, Segment Number is used to distinguish different PCIe segments. A PCIe system can contain multiple segments, each of which usually corresponds to a different bus or a different logical device group; Bus Number represents the number of the PCIe bus. All devices are connected through the bus, so the Bus Number is used to identify a specific PC Ie bus; Device Number is used to identify the specific device connected to the specified Bus. Each Bus can support up to 32 devices; Function Number is used to identify different functions in the same device. Each PCIe device can support up to 8 functions (function numbers from 0 to 7), but not all devices use multiple functions.

[0083] NVMe Backplane: A circuit board or device used to connect multiple NVMe SSDs. It is usually used in servers or storage systems to integrate multiple NVMe SSDs in a unified architecture to provide high-speed data transmission and redundancy support.

[0084] Serial communication protocol (Inter-Integrated Circuit, I2C): is a widely used serial communication protocol designed to achieve simple and efficient communication between microcontrollers and various external devices. I2C is a simple and efficient serial communication protocol suitable for connections between various low-speed devices; its two-wire design and flexible master-slave architecture make it the preferred solution in many electronic systems. Although there are certain limitations in speed and distance, its ease of use and popularity make I2C play an important role in embedded development.

[0085] Figure 1 This is an architecture diagram of a server out-of-band PCIe asset information generation system provided in this application. Figure 1 As shown, the system includes: a BIOS subsystem 101, a BMC subsystem 102, a PCIe bus 103, a plurality of PCIe devices 104 connected to the PCIe bus, and an I2C bus 105. The BIOS subsystem 101 is connected to the PCIe device 104 via the PCIe bus 103, and the BIOS subsystem 101 is connected to the BMC subsystem 102 via the I2C bus 105.

[0086] When the server starts, the BIOS subsystem 101 is activated, and scans the PCIe bus 103 to identify multiple PCIe devices 104 in the current server; thereby obtaining the device information of each PCIe device 104. The BIOS subsystem 101 determines the bandwidth information corresponding to each PCIe device 104 based on the device information of the PCIe device 104 and the preset bandwidth configuration file; determines the RC bandwidth configuration information of the server in combination with the bandwidth information of the PCIe device 104 and the connection relationship between the PCIe device 104 and the PCIe bus 103, and performs corresponding bandwidth configuration. After the BIOS subsystem 101 implements the bandwidth configuration, it determines the PCIe topology information in the server based on the device information of the PCIe device 104 and the connection relationship with the PCIe bus 103. The BIOS subsystem 101 sends the PCIe topology information and the device information of the PCIe device 104 to the BMC subsystem 102 through the I2C bus 105, and the BMC subsystem 102 generates the out-of-band PCIe asset information of the server based on the device information and the PCIe topology information, and stores it.

[0087] In the prior art, the generation of PCIe topology information requires correct bandwidth configuration, and the generation of out-of-band PCIe asset information depends on device information and PCIe topology information generated by the BIOS subsystem. Specifically, BIOS performs bandwidth configuration based on device information and generates PCIe topology information; the SBDF number of each PCIe device is determined based on the PCIe topology information, and the BIOS subsystem is used to send the SBDF number and device information to the BMC subsystem, and the BMC subsystem is used to generate asset information and store it in the server database.

[0088] However, in actual server asset management, bandwidth configuration based on the BIOS subsystem needs to be implemented based on a preset bandwidth configuration file, and the generation of asset information needs to rely on information transmission between the BIOS subsystem and the BMC subsystem. Due to the update of hardware devices or PCIe devices, the fixed bandwidth configuration in the preset bandwidth configuration file is inconsistent with the bandwidth configuration actually required by the current updated PCIe device; when the BIOS subsystem allocates bandwidth, it configures the bandwidth according to the preset bandwidth configuration file, and the obtained bandwidth allocation information is inaccurate, thereby affecting the generation of PCIe topology information; which in turn affects the generation of asset information of the BMC subsystem. It can be seen that there is a coupling relationship between the preset bandwidth configuration file and the BIOS subsystem, and there is also a coupling relationship between the BIOS subsystem and the BMC subsystem. Therefore, it can be known that there is a technical problem of low accuracy in the generation of asset information of computer systems in the prior art.

[0089] In view of the above technical problems, the present application proposes the following technical concept: the reason for the low accuracy of asset information generation in the prior art is that the BIOS subsystem occupies most of the information collection and processing work, and the bandwidth allocation method adopted depends on the preset bandwidth configuration file; in order to solve the problem of excessive dependence between bandwidth configuration and preset bandwidth configuration file, accurate bandwidth configuration can be achieved by obtaining the bandwidth requirements of each PCIe device in real time. At the same time, in order to reduce the workload of the BIOS subsystem, the work of the BIOS subsystem can be distributed to reduce the coupling degree between various working modules. Specifically: complex programmable logic devices implement the collection of device information in the server and related information on the mapping relationship between the device and the motherboard, and generate bandwidth configuration information based on the collected information. The BI OS subsystem is used to obtain bandwidth configuration information, and bandwidth configuration and PCIe topology information are generated. The BMC subsystem is used to obtain bandwidth configuration information and device information to generate corresponding asset information, and the asset information also includes the SBDF number in the PCIe topology information. The same SBDF encoding rules and bandwidth configuration information are used in the BIOS subsystem and the BMC subsystem, so that the SBDF numbers of the two are consistent. Therefore, the BMC subsystem does not need to obtain topology information from the BIOS subsystem; it does not need to use the fixed bandwidth configuration in the preset bandwidth configuration file, and can flexibly implement accurate bandwidth configuration based on the specific bandwidth requirements in the current computer system; thereby ensuring the accuracy of the computer system asset information generation.

[0090] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0091] Figure 2 The PCIe asset information generation system architecture diagram provided for this application is as follows: Figure 2 As shown, the system includes: a CPLD subsystem 201, multiple PCIe devices 202, a BMC subsystem 203, a BIOS subsystem 204, and a communication bus 205. The CPLD subsystem 201 is connected to multiple daughter card devices 202, the BMC subsystem 203, and the BIOS subsystem 204 based on the communication bus 205.

[0092] Among them, the CPLD subsystem 201 senses multiple PCIe devices 202, obtains the device information of each PCIe device 202 and the PCIe slot information corresponding to each PCIe device 202; and generates the bandwidth allocation information of each PCIe slot based on the device information and the PCIe slot information, and generates the RC bandwidth allocation information based on the preset mapping relationship between RC and PCIe slot. The BIOS subsystem 204 obtains the RC bandwidth allocation information generated by the CPLD subsystem 201 based on the communication bus 205 to perform bandwidth configuration, and generates PCIe topology information at the same time. Among them, the BIOS subsystem 204 is used to perform bandwidth configuration, and assigns the SBDF number corresponding to each device in the generated PCIe topology information to each PCIe device, so that the identification information of each PCIe device in the system is displayed as the SBDF number. The BMC subsystem 203 obtains the RC bandwidth allocation information and device information generated by the CPLD subsystem 201 based on the communication bus 205, and generates PCIe asset information; wherein the PCIe asset information includes the SBDF number of each PCIe device, and is consistent with the SBDF number assigned to the PCIe device by the BIOS.

[0093] based on Figure 2 The PCIe asset information generation system shown, the embodiment of the present application also provides a method for generating PCIe asset information. Figure 3 Schematic diagram of the process of generating PCIe asset information provided in this application Figure 1 ,like Figure 3 As shown, the method includes:

[0094] S301. For each PCIe slot on a motherboard of an electronic device, determine a first bandwidth allocated to the PCIe slot according to a PCIe device connected to the PCIe slot.

[0095] In this step, the PCIe slot refers to the slot on the motherboard used to connect the PCIe device; the PCIe device refers to various hardware components connected to the computer motherboard through the PCIe bus standard; the first bandwidth refers to the bandwidth allocated to the PCIe slot when it is ultimately used for information transmission; the first bandwidth is not equivalent to the maximum bandwidth supported by the PCIe slot.

[0096] Optionally, a possible implementation manner of determining the first bandwidth is:

[0097] a1. Determine the bandwidth requirement of the PCIe device based on the PCIe device;

[0098] a2. Determine the maximum bandwidth supported by each PCIe slot based on the PCIe slot;

[0099] a3. Determine a first bandwidth that is less than or equal to the maximum bandwidth based on the number of PCIe devices connected to the PCIe slot, the bandwidth requirement, and the maximum bandwidth.

[0100] Exemplarily, there are two PCIe slots, namely the first slot and the second slot, wherein the maximum bandwidth supported by the first slot is 4 Gbps, and the maximum bandwidth supported by the second slot is 12 Gbps; the first slot is connected to a PCIe device, and the bandwidth requirement of the device is 4 Gbps, then it can be determined that the final first bandwidth of the first slot is 4 Gbps; the second slot is connected to a PCIe device with a bandwidth requirement of 8 Gbps, then the first bandwidth of the second slot is 8 Gbps, which is less than the corresponding maximum bandwidth of the second slot.

[0101] S302: Determine a second bandwidth of each RC according to a preset first mapping relationship between RC and PCIe slot and a first bandwidth allocated to each PCIe slot.

[0102] In this step, the first mapping relationship refers to how the RC is associated and managed with each PCIe slot on the motherboard, which ensures that the connected PCIe device can correctly communicate with the main system and optimize performance and resource utilization.

[0103] Exemplarily, the preset RCs are RC0 and RC1, and the PCIe slots corresponding to RC0 are slot 1 and slot 2; the slots corresponding to RC1 are slot 3 and slot 4. Then the method for determining the second bandwidth of RC is:

[0104] b1. Obtain the first bandwidth of slots 1 to 4.

[0105] b2. Calculate the sum of the first bandwidths of slot 1 and slot 2, and determine the sum as the second bandwidth of RC0.

[0106] b3. Calculate the sum of the first bandwidths of slots 3 and 4, and determine it as the second bandwidth of RC1.

[0107] S303: Generate PCIe asset information of the electronic device according to the second bandwidth of each RC.

[0108] In this step, the PCIe asset information of the electronic device includes: the SBDF number of each PCIe device, the connection information between the device and the motherboard, and the device information. The SBDF number refers to the system operation number obtained by the PCIe device after the electronic device is started, which is used to uniquely identify each PCIe device in the electronic device.

[0109] It should be noted that in this step, after the BMC subsystem generates the PCIe asset information of the electronic device, it is necessary to store the PCIe asset information in a database or storage device corresponding to the electronic device to facilitate the location processing of errors inside the electronic device.

[0110] Optionally, before generating the PCIe asset information of the electronic device according to the second bandwidth of each RC, the method further includes:

[0111] c1. After the electronic device is powered on, a second mapping relationship between the PCIe slot and the processor logic slot, and PCIe device information of a PCIe device connected to a mainboard of the electronic device are obtained.

[0112] Optionally, the PCIe device information includes a PCIe device identifier and a PCIe slot connected to the PCIe device.

[0113] In this step, the PCIe device information may also include: device type, device code, device manufacturer code, device function, driver version required by the device, device temperature monitoring, device power usage, and firmware version installed on the device. PCIe slot refers to a physical slot on the motherboard of an electronic device for connecting a PCIe device, a processor logical slot refers to a logical representation of a slot position in the system, and the second mapping relationship refers to a mapping relationship between the two.

[0114] It should be noted that based on Figure 2 When the generation system shown implements the method of this embodiment, the information collected based on the CPLD subsystem includes: a second mapping relationship between the PCIe slot and the processor logic slot, and PCIe device information of the PCIe device connected to the mainboard of the electronic device.

[0115] c2. Determine an identifier of each PCIe slot according to the second bandwidth of each RC, the first mapping relationship, and the first bandwidth allocated to each PCIe slot.

[0116] In this step, the first bandwidth allocated to each PCIe slot is related to the RC to which the slot belongs and the PCIe channel occupied by itself. Based on the PCIe channel corresponding to the first bandwidth of each slot and the number of the channel itself, the identification of each PCIe slot can be determined.

[0117] Exemplarily, there is an RC0, the second bandwidth of RC0 is 16Gbps, the corresponding PCIe channels are 0-15, RC0 connects three PCIe slots, namely slot one, slot two and slot three; the first bandwidth allocated to slot one is 4Gbps, the channels used for communication are 4 channels, and the corresponding PCIe channels are 0-3 channels; the first bandwidth allocated to slot two is 8Gbps, the channels used for communication are 8 channels, and the corresponding PCIe channels are 4-11; the first bandwidth allocated to slot three is 4Gbps, the channels used for communication are 4 channels, and the corresponding PCIe channels are 12-15. According to the first bandwidth corresponding to the above slots and the corresponding numbering of the channels used to provide bandwidth support, each slot is numbered in the order of the channels, and the final identification of slot one is R0-0, slot two is R0-1, and slot three is R0-2.

[0118] c3. Determine the identifier of each processor logical slot according to the second mapping relationship and the identifier of each PCIe slot.

[0119] In this step, the second mapping relationship refers to the mapping relationship between the physical slot and the logical slot. After determining the identifier of each PCIe slot, the identifier of the logical slot used to identify the physical slot in the system can be determined.

[0120] Exemplarily, the identifier of the PCIe slot can be encoded to determine the identifier of a unique corresponding processor logic slot. For example, there are three PCIe slot identifiers, namely R0-0, R0-1, and R0-2; using binary encoding to perform conversion calculation, the identifiers of the three processor logic slots are determined to be: 00-00, 00-01, and 00-10.

[0121] Optionally, a possible implementation manner of generating PCIe asset information of the electronic device according to the second bandwidth of each RC is:

[0122] PCIe asset information of the electronic device is generated according to the second bandwidth of each RC, the first mapping relationship, the second mapping relationship, the PCIe device information, the identifier of each PCIe slot and the identifier of each processor logic slot.

[0123] Optionally, a possible implementation manner of generating PCIe asset information is:

[0124] d1. Determine the correspondence between the RC and the PCIe slot based on the first mapping relationship, and determine the Segment number in the SBDF number corresponding to the PCIe device.

[0125] For example, two RCs are deployed in the electronic device, namely RC0 and RC1, and the Segment number of the PCIe device connected to the PCIe slot having a first mapping relationship with RC0 is the identifier or number of RC0. The Segment number of the PCIe device connected to the PCIe slot having a first mapping relationship with RC1 is the identifier or number of RC1.

[0126] d2. Based on the first mapping relationship and the second bandwidth of the RC, determine the PCIe channel information occupied by each RC-connected PCIe slot, and determine the identifier of each PCIe slot based on the PCIe channel information; the PCIe slot identifier corresponds to the Segment number and Bus number in the SBDF number, which is used to identify the bus used by the PCIe device and the RC to which the PCIe device belongs.

[0127] d3. Based on the identifier of each PCIe slot and the second mapping relationship, the identifier of the processor logic slot can be determined. The segment number and the bus number are encoded to obtain the encoded segment number and bus number.

[0128] d4. Set the Device code and Function in the SBDF number of the PCIe device to the default value 0. The SBDF number can then be used to identify a unique slot.

[0129] d5. Each SBDF number and its corresponding PCIe device information are combined into the asset information of a PCIe device.

[0130] d6. Generate PCIe asset information of the electronic device based on the second bandwidth of RC, the first mapping relationship, the second mapping relationship, the identifier of each PCIe slot, the identifier of each processor logic slot, and the asset information of each PCIe device.

[0131] The method for generating PCIe asset information provided in the embodiment of the present application determines the first bandwidth that should be allocated to each PCIe slot in the current electronic device through the PCIe slot applicable to the electronic device motherboard and the PCIe device connected to each PCIe slot; based on the first bandwidth of each PCIe slot and the first mapping relationship between the RC on the motherboard and the PCIe slot, the second bandwidth of each RC is determined; thereby generating the PCIe asset information of the electronic device based on the second bandwidth of each RC. Compared with the method of configuring bandwidth based on a preset bandwidth configuration file in the prior art, the present application uses the information of the PCIe device and the PCIe slot connected in the computer system to achieve accurate bandwidth determination, and can generate corresponding asset information based on the bandwidth information. It avoids the situation where the preset configuration file and the PCI e device do not match after the PCIe device is changed, resulting in inaccurate bandwidth information allocation, thereby achieving the effect of improving the accuracy of asset information generation of the computer system.

[0132] Figure 4 Schematic diagram of the process of generating PCIe asset information provided in this application Figure 2 ,like Figure 4 As shown, in this embodiment Figure 3 Based on the embodiment, the determination of the first bandwidth of the PCIe slot in S301 is described in detail. The method includes:

[0133] S401. Determine the bandwidth of each PCIe channel according to the PCIe version.

[0134] In this step, the bandwidths allowed by the PCIe versions used by the electronic device are inconsistent. Exemplarily, the bandwidth per channel corresponding to the first version of PCIe is 2.5 Gbps, the bandwidth per channel corresponding to the second version of PCIe is 5.0 Gbps, the bandwidth per channel corresponding to the third version of PCIe is 8.0 Gbps, the bandwidth per channel corresponding to the fourth version of PCIe is 16.0 Gbps, and the bandwidth per channel corresponding to the fifth version of PCIe is 32.0 Gbps.

[0135] S402: Determine a maximum bandwidth that can be allocated to each PCIe slot according to the number of PCIe channels of each PCIe slot and the bandwidth of each PCIe channel.

[0136] In this step, the maximum bandwidth that can be allocated to each PCIe slot is equal to the sum of the bandwidths of each PCIe channel. The sum of the maximum bandwidth that can be allocated to the PCIe slot is related to the number of channels in the slot itself, and is different from the actual allocation situation.

[0137] Exemplarily, there is a PCIe slot with 8 PCIe channels and the PCIe version used is the second version, then the bandwidth of each channel is 5.0 Gbps; the maximum allocatable bandwidth is 40 Gbps, that is, 2 GB / s.

[0138] S403: For each PCIe slot, if the total bandwidth of the PCIe devices connected to the PCIe slot is less than or equal to the maximum bandwidth that can be allocated to the PCIe slot, determine the total bandwidth of the PCIe devices connected to the PCIe slot as the first bandwidth of the PCIe slot.

[0139] In this step, each PCIe slot can only be connected to one PCIe device. If the PCIe device is an expansion device for expanding a slot, the device group expanded and connected to the same PCIe slot will be regarded as a logical PCIe device.

[0140] Exemplarily, there is a PCIe slot using the first version of PCIe; an NVME backplane is connected to expand the PCIe slot, and two slots supporting 4-channel devices are distributed on the backplane, and each slot is connected to a PCIe device. At this time, both devices need to be allocated 10Gbps of bandwidth corresponding to 4 channels, and the maximum bandwidth supported by the PCIe slot is greater than 20Gbps. Then the bandwidth finally allocated to the slot is the bandwidth required by the actual device, that is, the first bandwidth is 20Gbps.

[0141] S404: If the total bandwidth of the PCIe devices connected to the PCIe slot is greater than the maximum bandwidth that can be allocated to the PCIe slot, determine available PCIe devices among the PCIe devices connected to the PCIe slot.

[0142] In this step, the bandwidth allocation of the PCIe slot needs to consider the maximum bandwidth corresponding to the number of PCIe channels of the slot itself. Therefore, when the bandwidth of the PCIe device exceeds the maximum bandwidth, it is necessary to perform available device analysis to maximize the use of the PCIe slot while ensuring the availability of the PCIe slot.

[0143] Optionally, a possible implementation manner of determining available PCIe devices is:

[0144] e1. If the number of PCIe devices connected to the PCIe slot is greater than 1, the PCIe devices connected to the PCIe slot are combined to obtain multiple PCIe device groups.

[0145] In this step, the PCIe devices are combined to obtain multiple PCIe device groups by performing subset calculation on the multiple PCIe devices and determining them as multiple PCIe device groups.

[0146] For example, there is a PCIe slot, and the number of connected PCIe devices is 3, namely device one, device two, and device three; the multiple PCIe device groups obtained by self calculation are: {device one}, {device two}, {device three}, {device one, device two}, {device one, device three}, {device two, device three}, {device one, device two, device three}.

[0147] e2. Calculate the total bandwidth of each PCIe device group.

[0148] In this step, the total bandwidth of each PCIe device group is calculated according to the PCIe devices included in the PCIe device group.

[0149] For example, referring to the example in e1, the bandwidth of device 1 is 10 Gbps, the bandwidth of device 2 is 20 Gbps, and the bandwidth of device 3 is 30 Gbps. Then the total bandwidth of each PCIe device group is: {device 1} is 10 Gbps, {device 2} is 20 Gbps, {device 3} is 30 Gbps, {device 1, device 2} is 30 Gbps, {device 1, device 3} is 40 Gbps, {device 2, device 3} is 50 Gbps, {device 1, device 2, device 3} is 60 Gbps.

[0150] e3. Determine the PCIe devices included in the PCIe device group whose total bandwidth is less than or equal to the maximum bandwidth that can be allocated to the PCIe slot among the multiple PCIe device groups as available PCIe devices.

[0151] Exemplarily, if the maximum bandwidth that can be allocated to a PCIe slot is 50 Gbps, then the devices in the PCIe device group of {device two, device three} can be determined as available PCIe devices.

[0152] S405: Determine the total bandwidth of available PCIe devices connected to the PCIe slot as the first bandwidth of the PCIe slot.

[0153] Exemplarily, referring to the PCIe device group and available PCIe devices obtained by example in step e3, it can be determined that the first bandwidth of the PCIe slot is 50 Gbps.

[0154] It should be noted that the bandwidth parameters and the distance of the PCIe device in this embodiment are only illustrative descriptions, and no limitation is imposed on the specific PCIe version, PCIe device, PCIe slot, and related bandwidth.

[0155] In this embodiment, the first bandwidth of the PCIe slot is calculated through the PCIe slot and the connected PCIe device; based on the premise of maximizing utilization, the PCIe available device is determined on the basis of not exceeding the supported range of the PCIe slot, thereby obtaining a more accurate first bandwidth of the PCIe slot. Compared with the prior art, the present application uses the CPLD subsystem to calculate and allocate the PCIe slot bandwidth, which can adapt to the change scenario of the PCIe device, so that the accuracy of the PCIe asset management of the electronic device is improved.

[0156] Based on the above embodiments, the present application also provides a method for locating a PCIe device error. Figure 5 A flow chart of a method for locating a PCIe device error provided in an embodiment of the present application is shown in FIG. Figure 5 As shown, the method includes:

[0157] S501, obtaining PCIe device error information.

[0158] In this step, the PCIe device error information includes the identifier of the target PCIe slot.

[0159] In this step, when the electronic device is running, the internal system will monitor the running status of the PCIe device in real time and generate error information in a timely manner. Generally, such error information will be stored in the operation log of the electronic device, and this application does not limit the storage location of the error information.

[0160] For example, an error message of a PCIe device is detected in the operation log of the electronic device, and the error message includes: the SBDF number of the PCIe device, the error time and the specific error type. The first two numbers of the SBDF number refer to the identifier of the PCIe slot, so that the PCIe slot to which the current PCIe device reporting the error belongs can be determined.

[0161] S502: Determine, according to the identifier of the target PCIe slot, a target PCIe device connected to the target PCIe slot corresponding to the identifier of the target PCIe slot.

[0162] In this step, the PCIe device connected to each PCIe slot is regarded as a whole, regardless of whether there are other PCIe devices extended to the PCIe device.

[0163] For example, there is a PCIe slot connected to a daughter card expansion device, and two available PCIe devices are connected to the daughter card expansion device; since the present application sets the Device and Function numbers in the SBDF numbering to the default values, when the default values ​​are 0; the SBDF numbers of the two available PCIe devices are both 00-01-00-00. Then, when an error occurs in either of the two available PCIe devices, the final location queried according to the error information is the PCIe slot rather than the device itself. Therefore, the target PCIe device actually determined is the daughter card expansion device.

[0164] S503: Obtain PCIe device information of the target PCIe device.

[0165] In this step, the PCIe asset information stored in the electronic device is matched with the SBD F number in step S502 to obtain the corresponding PCIe device information.

[0166] In this embodiment, the present application utilizes the error information of the PCIe device and the PCIe asset information to locate the error inside the electronic device, and specifically can locate the PCIe slot of the multi-link of the device with the error, thereby achieving error processing.

[0167] Based on the above embodiments, the present application also provides a method for locating server hardware device errors. Figure 6 A flow chart of a method for locating a server hardware device error provided in an embodiment of the present application is shown in FIG. Figure 6 As shown, the method includes:

[0168] f1. The CPLD subsystem senses the PCIe device information on the server, the connection relationship between the PCIe device and the PCIe slot, the mapping relationship between the PCIe slot and the RC, and the mapping relationship between the PCIe slot and the processor logic slot.

[0169] f2. The CPLD subsystem determines the allocated bandwidth of each PCIe slot and the allocated bandwidth of each RC based on the PCIe device information, the connection relationship between the PCIe device and the PCIe slot, and the mapping relationship between the PCIe slot and the RC.

[0170] f3. The BIOS subsystem obtains the allocated bandwidth of each PCIe slot and each RC from the CPLD subsystem during the server startup phase; based on the allocated bandwidth of each PCIe slot and each RC, the SBDF number of each device in each slot is calculated, and the PCIe device topology information starting from RC in the server is generated. The BIOS subsystem assigns the SBDF number to each PCIe device and the bandwidth to each PCIe slot and RC.

[0171] f4. During the server startup phase, the BMC subsystem obtains the allocated bandwidth of each PCIe slot, the allocated bandwidth of each RC, the device information of each PCIe, the connection relationship between the PCIe device and the PCIe slot, the mapping relationship between the PCIe slot and the RC, and the mapping relationship between the PCIe slot and the processor logic slot from the CPLD subsystem.

[0172] f5. The BMC subsystem calculates the SBDF number of each device in each slot based on the allocated bandwidth of each PCIe slot and the allocated bandwidth of each RC. The BMC subsystem generates the PCIe asset information of the server based on the SBDF number and the information obtained from the CPLD, and stores it in the database.

[0173] f6. When a PCIe device alarm is detected, the PCIe slot and the corresponding PCIe device are located based on the SBDF number in the alarm information, and the device in the slot can be replaced or removed.

[0174] In this embodiment, it is described how to use the system and method provided by the present application in a server to realize PCIe asset information generation and realize error device location based on asset information. By determining bandwidth allocation and collecting PCIe device information through the CPLD subsystem, the obtained information can be transmitted to the BIOS subsystem and the BMC subsystem at the same time. The BIOS subsystem and the BMC subsystem can achieve consistency in the SBDF numbering information of the PCIe device without the need for communication, which is conducive to the location of the error and reduces the coupling between the two subsystems.

[0175] Figure 7 A schematic diagram of the structure of the device for generating PCIe asset information provided in this application, such as Figure 7 As shown, the PCIe asset information generation device 70 provided in this embodiment includes:

[0176] The first processing module 701 is used to determine, for each PCIe slot on the motherboard of the electronic device, a first bandwidth allocated to the PCIe slot according to a PCIe device connected to the PCIe slot;

[0177] The second processing module 702 is used to determine the second bandwidth of each RC according to the preset first mapping relationship between the RC and the PCIe slot and the first bandwidth allocated to each PCIe slot;

[0178] The third processing module 703 is used to generate PCIe asset information of the electronic device according to the second bandwidth of each RC.

[0179] In a possible implementation manner, the first processing module 701 is further configured to:

[0180] Determine the bandwidth of each PCIe channel based on the PCIe version;

[0181] According to the number of PCIe channels in each PCIe slot and the bandwidth of each PCIe channel, determine the maximum bandwidth that can be allocated to each PCIe slot;

[0182] For each PCIe slot, if the total bandwidth of the PCIe devices connected to the PCIe slot is less than or equal to the maximum bandwidth that can be allocated to the PCIe slot, the total bandwidth of the PCIe devices connected to the PCIe slot is determined as the first bandwidth of the PCIe slot;

[0183] If the total bandwidth of the PCIe devices connected to the PCIe slot is greater than the maximum bandwidth that can be allocated to the PCIe slot, determining an available PCIe device among the PCIe devices connected to the PCIe slot;

[0184] The total bandwidth of available PCIe devices connected to the PCIe slot is determined as the first bandwidth of the PCIe slot.

[0185] In a possible implementation manner, the first processing module 701 is further configured to:

[0186] If the number of PCIe devices connected to the PCIe slot is greater than 1, the PCIe devices connected to the PCIe slot are combined to obtain multiple PCIe device groups;

[0187] Calculate the total bandwidth of each PCIe device group;

[0188] A PCIe device group whose total bandwidth is less than or equal to a maximum bandwidth allocatable to a PCIe slot among the multiple PCIe device groups includes PCIe devices that are determined as available PCIe devices.

[0189] In a possible implementation manner, the third processing module 703 is further configured to:

[0190] After the electronic device is powered on, a second mapping relationship between the PCIe slot and the processor logic slot is obtained, as well as PCIe device information of the PCIe device connected to the motherboard of the electronic device, wherein the PCIe device information includes a PCIe device identifier and a PCIe slot connected to the PCIe device.

[0191] In a possible implementation manner, the third processing module 703 is further configured to:

[0192] Determine an identifier of each PCIe slot according to the second bandwidth of each RC, the first mapping relationship, and the first bandwidth allocated to each PCIe slot;

[0193] The identifier of each processor logical slot is determined according to the second mapping relationship and the identifier of each PCIe slot.

[0194] In a possible implementation manner, the third processing module 703 is further configured to:

[0195] PCIe asset information of the electronic device is generated according to the second bandwidth of each RC, the first mapping relationship, the second mapping relationship, the PCIe device information, the identifier of each PCIe slot and the identifier of each processor logic slot.

[0196] In a possible implementation manner, the device further includes a fourth processing module 704, and the fourth processing module 704 is configured to:

[0197] Obtain PCIe device error information, where the PCIe device error information includes an identifier of a target PCIe slot;

[0198] Determine, according to the identifier of the target PCIe slot, a target PCIe device connected to the target PCIe slot corresponding to the identifier of the target PCIe slot;

[0199] Get the PCIe device information of the target PCIe device.

[0200] The device for generating PCIe asset information provided in this embodiment can execute the method provided in the above method embodiment, and its implementation principle and technical effect are similar, which will not be described in detail in this embodiment.

[0201] Figure 8 This is a schematic diagram of the structure of the electronic device provided in this application. Figure 8 As shown, the electronic device 80 provided in this embodiment includes: at least one processor 801 and a memory 802. Optionally, the device 80 also includes a communication component 803. The processor 801, the memory 802 and the communication component 803 are connected via a bus 804.

[0202] In a specific implementation process, at least one processor 801 executes the computer-executable instructions stored in the memory 802, so that at least one processor 801 executes the above method.

[0203] The specific implementation process of the processor 801 can be found in the above method embodiment, and its implementation principle and technical effect are similar, so this embodiment will not be repeated here.

[0204] In the above embodiments, it should be understood that the processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), etc. A general-purpose processor may be a microprocessor or any conventional processor. The steps of the method disclosed in the invention may be directly implemented as being executed by a hardware processor, or may be executed by a combination of hardware and software modules in the processor.

[0205] The memory may include a high-speed memory (Random Access Memory, RAM), and may also include a non-volatile memory (Non-volatile Memory, NVM), such as at least one disk memory.

[0206] The bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, the bus in the drawings of the present application is not limited to only one bus or one type of bus.

[0207] The present application also provides a computer program product, including a computer program, which implements the above method when executed by a processor.

[0208] The present application also provides a computer-readable storage medium, in which computer-executable instructions are stored. When a processor executes the computer-executable instructions, the above method is implemented.

[0209] The above-mentioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk. The readable storage medium can be any available medium that can be accessed by a general or special-purpose computer.

[0210] An exemplary readable storage medium is coupled to a processor so that the processor can read information from the readable storage medium and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can be located in an application specific integrated circuit (Application Specific Integrated Circuits, referred to as: ASIC). Of course, the processor and the readable storage medium can also exist in the device as discrete components.

[0211] The division of units is only a logical function division, and there may be other divisions in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interface, device or unit, which can be electrical, mechanical or other forms.

[0212] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0213] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0214] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods of each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0215] Those skilled in the art can understand that all or part of the steps of implementing the above-mentioned method embodiments can be completed by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, the steps of the above-mentioned method embodiments are executed; and the aforementioned storage medium includes: ROM, RAM, disk or optical disk and other media that can store program codes.

[0216] Finally, it should be noted that those skilled in the art will readily conceive of other embodiments of the present invention after considering the specification and practicing the invention disclosed herein. The present invention is intended to cover any variations, uses or adaptations of the present invention, which follow the general principles of the present invention and include common knowledge or customary technical means in the art not disclosed by the present invention, are not limited to the precise structure described above and shown in the drawings, and may be modified and changed in various ways without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.

Claims

1. A method for generating PCIe asset information, characterized in that: Used in electronic equipment, including: For each high-speed serial computer expansion bus standard PCIe slot on the motherboard of the electronic device, according to the PCIe device connected to the PCIe slot, determine a first bandwidth allocated to the PCIe slot; Determine a second bandwidth of each RC according to a preset first mapping relationship between the root complex RC and the PCIe slot and a first bandwidth allocated to each PCIe slot; The PCIe asset information of the electronic device is generated according to the second bandwidth of each RC.

2. The method according to claim 1, characterized in that The step of determining, for each PCIe slot on the motherboard of the electronic device, a first bandwidth allocated to the PCIe slot according to a PCIe device connected to the PCIe slot, includes: Determine the bandwidth of each PCIe channel based on the PCIe version; According to the number of PCIe channels in each PCIe slot and the bandwidth of each PCIe channel, determine the maximum bandwidth that can be allocated to each PCIe slot; For each PCIe slot, if the total bandwidth of the PCIe devices connected to the PCIe slot is less than or equal to the maximum bandwidth that can be allocated to the PCIe slot, the total bandwidth of the PCIe devices connected to the PCIe slot is determined as the first bandwidth of the PCIe slot; If the total bandwidth of the PCIe devices connected to the PCIe slot is greater than the maximum bandwidth that can be allocated to the PCIe slot, determining an available PCIe device among the PCIe devices connected to the PCIe slot; The total bandwidth of available PCIe devices connected to the PCIe slot is determined as the first bandwidth of the PCIe slot.

3. The method according to claim 2, characterized in that The determining of available PCIe devices among the PCIe devices connected to the PCIe slot comprises: If the number of PCIe devices connected to the PCIe slot is greater than 1, the PCIe devices connected to the PCIe slot are combined to obtain multiple PCIe device groups; Calculate the total bandwidth of each PCIe device group; The PCIe device groups whose total bandwidth is less than or equal to the maximum bandwidth allocatable to the PCIe slots among the multiple PCIe device groups include PCIe devices that are determined as the available PCIe devices.

4. The method according to any one of claims 1 to 3, characterized in that: Before generating the PCIe asset information of the electronic device according to the second bandwidth of each RC, the method further includes: After the electronic device is turned on, a second mapping relationship between the PCIe slot and the processor logic slot, as well as PCIe device information of the PCIe device connected to the motherboard of the electronic device are obtained, wherein the PCIe device information includes a PCIe device identifier and a PCIe slot connected to the PCIe device.

5. The method according to claim 4, characterized in that The method further comprises: Determine an identifier of each PCIe slot according to the second bandwidth of each RC, the first mapping relationship, and the first bandwidth allocated to each PCIe slot; According to the second mapping relationship and the identifier of each PCIe slot, the identifier of each processor logical slot is determined.

6. The method according to claim 5, characterized in that Generating PCIe asset information of the electronic device according to the second bandwidth of each RC includes: The PCIe asset information of the electronic device is generated according to the second bandwidth of each RC, the first mapping relationship, the second mapping relationship, the PCIe device information, the identifier of each PCIe slot and the identifier of each processor logic slot.

7. The method according to claim 6, characterized in that The method further comprises: Obtain PCIe device error information, where the PCIe device error information includes an identifier of a target PCIe slot; Determine, according to the identifier of the target PCIe slot, a target PCIe device connected to the target PCIe slot corresponding to the identifier of the target PCIe slot; Obtain PCIe device information of the target PCIe device.

8. A device for generating PCIe asset information, characterized in that: Used in electronic equipment, including: A first processing module, configured to determine, for each PCIe slot on the motherboard of the electronic device, a first bandwidth allocated to the PCIe slot according to a PCIe device connected to the PCIe slot; A second processing module, configured to determine a second bandwidth of each RC according to a preset first mapping relationship between the RC and the PCIe slot and a first bandwidth allocated to each PCIe slot; The third processing module is used to generate PCIe asset information of the electronic device according to the second bandwidth of each RC.

9. An electronic device, characterized in that: include: Memory, processor; The memory stores computer-executable instructions; The processor executes the computer-executable instructions stored in the memory, so that the processor performs the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, which are used to implement the method according to any one of claims 1 to 7 when executed by a processor.

11. A computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

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