Storage device

Abstract

The invention relates to a storage device. The storage device includes: a memory-arithmetic unit including a storage circuit and an arithmetic circuit; and a request processing circuit configured to process a storage request and an operation request transmitted from the software domain to transmit a storage command and an address corresponding to the storage request and an operation command and an address corresponding to the operation request to the memory-operator unit. The request processing circuitry is configured to schedule processing of the storage request and the operation request based on a state of the storage request remaining in the request processing circuitry when the operation request is transmitted from the software domain to the request processing circuitry.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0092070, filed on Jul. 14, 2023, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure relate generally to a storage device, and more particularly, to a storage device that is identified as two separate devices, a memory and an operator. Background Art

[0004] Recently, interest in artificial intelligence has rapidly increased not only in the information technology (IT) industry, but also in entire industries such as finance and healthcare. As a result, the introduction of artificial intelligence (more precisely, deep learning) is being considered and prototyped in multiple fields. In general, deep learning refers to the technology of effectively learning deep neural networks (DNNs) or deep networks with more layers than existing neural networks, and using deep neural networks (DNNs) or deep networks for pattern recognition or reasoning.

[0005] One of the backgrounds and reasons for such widespread interest in deep learning may be the performance improvement of processors that perform operations. In order to improve the performance of artificial intelligence, neural networks with up to hundreds of layers need to be accumulated and learned. This trend has continued in recent years, and as a result, the amount of operations required for the hardware that actually performs the operations has increased exponentially. In addition, in the case of existing hardware systems in which the memory and the processor are separated, the performance improvement of artificial intelligence hardware is hindered due to the limitation of the amount of data communication between the memory and the processor. Recently, in order to solve this problem, a device that integrates the processor and the memory in the semiconductor chip itself has been used as a neural network computing device. Summary of the invention

[0006] A storage device according to an embodiment of the present disclosure may include: a memory-operator unit including a storage circuit and an operation circuit; and a request processing circuit configured to process a storage request and an operation request sent from a software domain to send a storage command and an address corresponding to the storage request and an operation command and an address corresponding to the operation request to the memory-operator unit. The request processing circuit may be configured to schedule the processing of the storage request and the operation request based on the state of the remaining storage request in the request processing circuit when the operation request is sent from the software domain to the request processing circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram illustrating a software domain and a storage device according to an embodiment of the present disclosure.

[0008] Figure 2 Shows Figure 1 An example of a memory-operator unit included in a storage device.

[0009] Figure 3 It is shown Figure 1 A block diagram of an example of a storage preparation circuit of a request processing circuit included in a storage device.

[0010] Figure 4 It is shown Figure 3 Flowchart of the operation of the storage preparation circuit.

[0011] Figure 5 It is shown Figure 1 A block diagram of an example of an operation preparation circuit of a request processing circuit included in a storage device.

[0012] Figure 6 It is shown Figure 5 A flowchart of the operation of the operation preparation circuit.

[0013] Figure 7 Shows from Figure 1 An example of a storage queue status signal output by a storage request queue of a request processing circuit included in a storage device.

[0014] Figure 8 Shows from Figure 1 An example of an operation queue status signal output by an operation request queue of a request processing circuit included in a storage device.

[0015] Fig. 9 It is shown Figure 1 A block diagram of an example of a mode control circuit of a request processing circuit included in a storage device.

[0016] Fig.10 It is shown Fig. 9 Flowchart of the operation of the first queue flag signal generating circuit included in the mode control circuit of FIG.

[0017] Fig.11 It is shown Fig. 9 Flowchart of the operation of the second queue flag signal generating circuit included in the mode control circuit of FIG.

[0018] Fig.12 It is shown Fig. 9 Flowchart of the operation of the mode signal generating circuit included in the mode control circuit.

[0019] Fig.13 is a block diagram illustrating a software domain and a storage device according to an embodiment of the present disclosure.

[0020] Fig.14 It is shown Fig.13A block diagram of an example of a storage preparation circuit of a request processing circuit included in a storage device.

[0021] Fig.15 It is shown Fig.14 Flowchart of the operation of the storage preparation circuit.

[0022] Fig.16 Shows from Fig.13 An example of a storage queue status signal output by a storage request queue of a request processing circuit included in a storage device.

[0023] Fig.17 It is shown Fig.13 A block diagram of an example of a mode control circuit of a request processing circuit included in a storage device.

[0024] Fig.18 It is shown Fig.17 Flowchart of the operation of the mode signal generating circuit included in the mode control circuit. DETAILED DESCRIPTION

[0025] In the description of the following embodiments, it should be understood that the terms "first" and "second" are intended to identify elements, but are not used to define a specific number or sequence of elements. In addition, when an element is referred to as being "on", "above", "above", "below" or "below" another element, it is intended to represent a relative positional relationship, rather than being used to limit certain situations where an element directly contacts another element or there is at least one intermediate element between two elements. Therefore, the terms such as "on", "above", "above", "below", "below", "below" etc. used herein are only for the purpose of describing a specific embodiment, rather than being intended to limit the scope of the present disclosure. In addition, when an element is referred to as being "connected" or "coupled" to another element, the element may be directly electrically or mechanically connected or coupled to another element, or may be indirectly electrically or mechanically connected or coupled to another element, with one or more additional elements between the two elements.

[0026] Furthermore, when a parameter is referred to as "predetermined", it may be intended to mean that the value of the parameter is determined in advance when the parameter is used in a process or algorithm. The value of the parameter may be set at the start of the process or algorithm, or may be set during the execution of the process or algorithm.

[0027] Logical "high" levels and logical "low" levels can be used to describe the logical levels of electrical signals. A signal with a logical "high" level can be distinguished from a signal with a logical "low" level. For example, when a signal with a first voltage corresponds to a signal with a logical "high" level, a signal with a second voltage can correspond to a signal with a logical "low" level. In an embodiment, the voltage level of the logical "high" level can be set to a voltage level higher than the voltage level of the logical "low" level. In addition, according to an embodiment, the logic level of the signal can be set to be different or opposite. For example, a signal with a logical "high" level in one embodiment can be set to have a logical "low" level in another embodiment.

[0028] Various embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. However, the embodiments described herein are only for illustrative purposes and are not intended to limit the scope of the present disclosure.

[0029] In various embodiments described below, dynamic random access memory (DRAM) devices are used as examples of storage devices, but it is clear that the present disclosure is not limited thereto. For example, the present disclosure is also applicable to static random access memory (SRAM) devices, synchronous DRAM (SDRAM) devices, double data rate synchronous DRAM (DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, etc.) devices, graphic double data rate synchronous DRAM (GDDR, GDDR2, GDDR3, etc.) devices, quad data rate DRAM (QDRDRAM) devices, RAMBUS XDR DRAM (XDR DRAM) devices, fast page mode DRAM (FPM DRAM) devices, video DRAM (VDRAM) devices, extended data output DRAM (EDO DRAM) devices, burst EDO DRAM (BEDO DRAM) devices, multi-bank DRAM (MDRAM) devices, synchronous graphic RAM (SGRAM) devices, and / or other types of DRAM devices.

[0030] Figure 1 is a block diagram illustrating a software domain 10 and a storage device 100 according to an embodiment of the present disclosure.

[0031] refer to Figure 1, the storage device 100 may include a memory-operator unit 200 and a request processing circuit 300. The memory-operator unit 200 may include a storage circuit and an operation circuit. The request processing circuit 300 may process a storage request M_REQ and an operation request OP_REQ sent from the software domain 10. The request processing circuit 300 may send a storage command M_CMD and an address ADDR corresponding to the storage request M_REQ to the memory-operator unit 200. In addition, the request processing circuit 300 may send an operation command OP_CMD and / or an address ADDR corresponding to the operation request OP_REQ to the memory-operator unit 200. The request processing circuit 300 may send data DATA to the memory-operator unit 200, or receive data DATA from the memory-operator unit 200. Although Figure 1 Although not shown in the figure, the request processing circuit 300 may include a request decoder, which decodes the storage request M_REQ and the operation request OP_REQ to generate a storage command M_CMD and an operation command OP_CMD, respectively.

[0032] The software domain 10 may include applications 11, operating systems (OS) 12, and drivers 13. Figure 1 Although not shown in the figure, the software domain 10 may include a framework, a runtime library, etc. The application 11 may include various types of application programs driven by a host device (e.g., a central processing unit (CPU)). The operating system 12 may manage resources of the entire system including the host device and the storage device 100. The driver 13 may refer to a hardware device driver constituting the entire system, and includes software for controlling the storage device 100.

[0033] In the software domain 10, the storage device 100 may be identified as an independent device as a memory or an operator. Therefore, a storage request M_REQ for identifying the storage device 100 as a memory and requesting a memory operation of the storage device 100 may be sent from the operating system 12 of the software domain 10 to the storage device 100. On the other hand, an operation request OP_REQ for identifying the storage device 100 as an operator and requesting an operator operation of the storage device 100 may be sent from the driver 13 of the software domain 10 to the storage device 100. In an embodiment, the memory operation of the storage device 100 may include a data read operation and a data write operation to a storage circuit constituting the storage device 100. The operating system 12 of the software domain 10 may access the storage device 100 as a storage device through "load" and "store" commands. The operator operation of the storage device 100 may include an operation of sending operation data from the storage circuit to the operation circuit, an operation of performing an operation in the operation circuit using the operation data, and an operation of outputting operation result data generated by the operation in the operation circuit from the operation circuit. The driver 13 of the software domain 10 can drive the storage device 100 to operate as an operator in the form of an operation code (OP code) corresponding to the operation of the operator. According to the storage device 100 of this example, the storage device 100 can be used as a general storage device excluding the operation of the operator. In addition, the storage of data used in the operator can be performed by a general memory write operation, and the reading of data generated by the operator can be performed by a general memory read operation. The memory write operation of the data used in the operator and the memory read operation of the data generated by the operator can be performed by the operating system 12 without going through the driver 13 in the software domain 10.

[0034] The request processing circuit 300 of the storage device 100 may include a storage preparation circuit 310 , an operation preparation circuit 320 , a storage request queue 330 , an operation request queue 340 , a mode control circuit 350 , and an arbiter 360 .

[0035] The storage preparation circuit 310 may receive a storage request M_REQ requesting a memory operation of the memory-operator unit 200 from the operating system 12 of the software domain 10. The storage preparation circuit 310 may receive a first queue flag signal Q_FLAG1 from the mode control circuit 350. The storage preparation circuit 310 may allow or prevent the output of the storage request M_REQ based on the first queue flag signal Q_FLAG1. In an example, when the first queue flag signal Q_FLAG1 has a first logic level (e.g., a binary value of "1"), the storage preparation circuit 310 may allow the storage request M_REQ to be sent to the storage request queue 330. On the other hand, when the first queue flag signal Q_FLAG1 has a second logic level (e.g., a binary value of "0"), the storage preparation circuit 310 may prevent the storage request M_REQ from being sent to the storage request queue 330.

[0036] The operation preparation circuit 320 may receive an operation request OP_REQ requesting an operator operation of the memory-operator unit 200 from the driver 13 of the software domain 10. The operation preparation circuit 320 may receive a second queue flag signal Q_FLAG2 from the mode control circuit 350. The operation preparation circuit 320 may allow or prevent the output of the operation request OP_REQ based on the second queue flag signal Q_FLAG2. In an example, when the second queue flag signal Q_FLAG2 has a first logic level (e.g., a binary value of "1"), the operation preparation circuit 320 may allow the operation request OP_REQ to be sent to the operation request queue 340. On the other hand, when the second queue flag signal Q_FLAG2 has a second logic level (e.g., a binary value of "0"), the operation preparation circuit 320 may prevent the operation request OP_REQ from being sent to the operation request queue 340.

[0037] The storage request queue 330 may store the storage request M_REQ sent by the storage preparation circuit 310. To this end, the storage request queue 330 may include a plurality of storage areas capable of storing the storage request M_REQ. The storage request queue 330 may output the storage request M_REQ (out of the queue) located in the storage area indicated by the front pointer among the plurality of storage areas. The storage request queue 330 may store the input storage request M_REQ in the storage area indicated by the back pointer among the plurality of storage areas. The storage request queue 330 may output the storage request M_REQ stored in the plurality of storage areas in the order determined by the scheduling. In an example, the storage request queue 330 may output the storage request M_REQ in the order determined by the reordering method (e.g., the first-ready first-come first-served (FR-FCFS) method). In this case, in an embodiment, the storage request queue 330 may search for the storage request M_REQ from the oldest entry among the storage requests M_REQ stored in the storage area, while outputting the storage request M_REQ in the order in which the number of row activations of the storage circuit of the memory-operator unit 200 is minimized. The memory request queue 330 may send a memory request M_REQ to the arbiter 360 .

[0038] The storage request queue 330 may generate a storage queue status signal MQ_STAT including status information of the storage request queue 330 to send the storage queue status signal MQ_STAT to the mode control circuit 350. The storage request queue 330 may output the storage queue status signal MQ_STAT in synchronization with a time point when the storage request M_REQ is sent from the storage preparation circuit 310 and a time point when the storage request M_REQ is output. The storage queue status signal MQ_STAT may include information about whether the storage request M_REQ is sent to the storage request queue 330. The storage queue status signal MQ_STAT may include information about whether the storage request M_REQ is output from the storage request queue 330. In addition, the storage queue status signal MQ_STAT may include information about the status of the storage area of ​​the storage request queue 330, for example, whether all the storage areas of the storage request queue 330 are filled with the storage request M_REQ, that is, whether the storage request queue 330 is in a "full state", and whether all the storage areas of the storage request queue 330 are empty, that is, whether the storage request queue 330 is in an "empty state".

[0039] The operation request queue 340 may store the operation request OP_REQ sent by the operation preparation circuit 320. To this end, the operation request queue 340 may include a plurality of storage areas capable of storing the operation request OP_REQ. The operation request queue 340 may output the operation request OP_REQ (out of the queue) located in the storage area indicated by the front pointer among the plurality of storage areas. The operation request queue 340 may store the operation request OP_REQ input to the storage area indicated by the rear pointer in the plurality of storage areas. The operation request queue 340 may output the operation request OP_REQ stored in the plurality of storage areas according to a reordering method (e.g., according to a first-in-first-out (FIFO) method). Therefore, the operation request queue 340 may output the operation request OP_REQ in the order in which the operation request OP_REQ is sent to the operation request queue 340 for the operation request OP_REQ stored in the storage area. That is, the operation request OP_REQ first sent to the operation request queue 340 may be output from the operation request queue 340 before the operation request OP_REQ sent to the operation request queue 340 later. The operation request queue 340 may send an operation request OP_REQ to the arbiter 360 .

[0040] The operation request queue 340 may generate an operation queue status signal OPQ_STAT including status information of the operation request queue 340 to send the operation queue status signal OPQ_STAT to the mode control circuit 350. The operation request queue 340 may output the operation queue status signal OPQ_STAT in synchronization with the time point when the operation request OP_REQ is sent from the operation preparation circuit 320 and the time point when the operation request OP_REQ is output. The operation queue status signal OPQ_STAT may include information about whether the operation request OP_REQ is sent to the operation request queue 340. The operation queue status signal OPQ_STAT may include information about whether the operation request OP_REQ is output from the operation request queue 340. In addition, the operation queue status signal OPQ_STAT may include information about the status of the storage area of ​​the operation request queue 340, such as whether all the storage areas of the operation request queue 340 are filled with the operation request OP_REQ, that is, whether the operation request queue 340 is in a full state, and whether all the storage areas of the operation request queue 340 are empty, that is, whether the operation request queue 340 is in an empty state.

[0041] The mode control circuit 350 may receive a storage queue status signal MQ_STAT from the storage request queue 330, and receive an operation queue status signal OPQ_STAT from the operation request queue 340. The mode control circuit 350 may generate and output a first queue flag signal Q_FLAG1, a second queue flag signal Q_FLAG2, and a mode signal MODE based on the storage queue status signal MQ_STAT and the operation queue status signal OPQ_STAT. The mode control circuit 350 may send the first queue flag signal Q_FLAG1 to the storage preparation circuit 310. The mode control circuit 350 may send the second queue flag signal Q_FLAG2 to the operation preparation circuit 320. The mode control circuit 350 may send the mode signal MODE to the arbiter 360.

[0042] When the storage request queue 330 satisfies all three conditions according to the state of the storage queue state signal MQ_STAT and the operation request queue 340 satisfies all three conditions according to the state of the operation queue state signal OPQ_STAT, the mode control circuit 350 may send a first queue flag signal Q_FLAG1 having a first logic level (i.e., a binary value of "1") to the storage preparation circuit 310. Here, when the storage request queue 330 is not in a full state, the first condition of the three conditions may be satisfied. When the operation request OP_REQ is not input to the operation request queue 340, the second condition of the three conditions may be satisfied. When the operation request queue 340 is in an empty state, the third condition of the three conditions may be satisfied. When the first queue flag signal Q_FLAG1 having a first logic level (i.e., a binary value of "1") is sent, the storage preparation circuit 310 may send a storage request M_REQ to the storage request queue 330.

[0043] When the storage request queue 330 satisfies one of the three conditions according to the state of the storage queue state signal MQ_STAT and the operation request queue 340 satisfies the state of the operation queue state signal OPQ_STAT, the mode control circuit 350 may send a first queue flag signal Q_FLAG1 having a second logic level (i.e., a binary value of "0") to the storage preparation circuit 310. Here, when the storage request queue 330 is in a full state, the first condition of the three conditions may be satisfied. When the operation request OP_REQ is input to the operation request queue 340, the second condition of the three conditions may be satisfied. When the operation request queue 340 is not in an empty state, the third condition of the three conditions may be satisfied. When the first queue flag signal Q_FLAG1 having a second logic level (i.e., a binary value of "0") is sent, the storage preparation circuit 310 may not send the storage request M_REQ to the storage request queue 330. In this case, the untransmitted memory request M_REQ may be transmitted to the memory request queue 330 after a point in time when the first queue flag signal Q_FLAG1 having the first logic level (ie, binary value “1”) is transmitted from the mode control circuit 350 to the memory preparation circuit 310 .

[0044] When the operation request queue 340 is not in a full state according to the operation queue state signal OPQ_STAT, the mode control circuit 350 may transmit the second queue flag signal Q_FLAG2 having a first logic level (i.e., a binary value of “1”) to the operation preparation circuit 320. When the second queue flag signal Q_FLAG2 having a first logic level (i.e., a binary value of “1”) is transmitted, the operation preparation circuit 320 may transmit the operation request OP_REQ transmitted from the driver 13 of the software domain 10 to the operation request queue 340. When the operation request queue 340 is in a full state according to the operation queue state signal OPQ_STAT, the mode control circuit 350 may transmit the second queue flag signal Q_FLAG2 having a second logic level (i.e., a binary value of “0”) to the operation preparation circuit 320. When the second queue flag signal Q_FLAG2 having a second logic level (i.e., a binary value of “0”) is transmitted, the operation preparation circuit 320 may not transmit the operation request OP_REQ transmitted from the driver 13 of the software domain 10 to the operation request queue 340. In this case, the untransmitted operation request OP_REQ may be transmitted to the operation request queue 340 after a point in time when the second queue flag signal Q_FLAG2 having the first logic level (ie, binary “1”) is transmitted from the mode control circuit 350 to the operation preparation circuit 320 .

[0045] When the operation request queue 340 is in an empty state according to the operation queue state signal OPQ_STAT, the mode control circuit 350 may generate a memory mode signal as the mode signal MODE to send the memory mode signal to the arbitrator 360. Even when the storage request queue 330 is not in an empty state according to the storage queue state signal MQ_STAT, even when the operation request queue 340 is not in an empty state according to the operation queue state signal OPQ_STAT, the mode control circuit 350 may generate a memory mode signal as the mode signal MODE to send the memory mode signal to the arbitrator 360. On the other hand, when the operation request queue 340 is not in an empty state according to the operation queue state signal OPQ_STAT and the storage request queue 330 is in an empty state according to the storage queue state signal MQ_STAT, the mode control circuit 350 may generate an operator mode signal as the mode signal MODE to send the operator mode signal to the arbitrator 360.

[0046] The arbitrator 360 may receive the storage request M_REQ output from the storage request queue 330 and the operation request OP_REQ output from the operation request queue 340. The arbitrator 360 may receive the mode signal MODE from the mode control circuit 350. The arbitrator 360 may output the storage request M_REQ or the operation request OP_REQ based on the mode signal MODE. When the mode signal MODE is a memory mode signal, the arbitrator 360 may output the storage request M_REQ before the operation request OP_REQ. On the other hand, when the mode signal MODE is an operator mode signal, the arbitrator 360 may output the operation request OP_REQ before the storage request M_REQ.

[0047] Figure 2 Shows Figure 1 An example of a memory-operator unit 200 included in a storage device 100.

[0048] refer to Figure 2 , the memory-operator unit 200 may include a plurality of storage circuits (e.g., the first to sixteenth storage circuits BK0-BK15 and the global buffer GB) and a plurality of operation circuits (e.g., the first to sixteenth operation circuits AC0-AC15). In an example, the first to sixteenth storage circuits BK0-BK15 may be a memory bank constituting a DRAM device. In an example, the first to sixteenth operation circuits AC0-AC15 may be an accumulation and multiplication (MAC) circuit. However, this is only an example, and the plurality of storage circuits and the plurality of operation circuits may be configured in a variety of ways.

[0049] The memory-operator unit 200 may include a command / address decoder 210, which receives a command from a request processing circuit ( Figure 1300) sends a command CMD and an address ADDR to decode and generate and output a control signal CTRL and a storage body address / row address / column address BA / RA / CA. Figure 1 As described, the command CMD may include a storage command ( Figure 1 M_CMD) and operation commands ( Figure 1 The memory-operator unit 200 may include a data input / output (I / O) circuit 220, which utilizes a request processing circuit ( Figure 1 300) performs data sending operation and data receiving operation. Figure 2 Although not shown in the figure, the control signal CTRL and the bank address / row address / column address BA / RA / CA outputted from the command / address decoder 210 may be transmitted to the first to sixteenth storage circuits BK0-BK15, the global buffer GB, and the first to sixteenth operation circuits AC0-AC15 through the control signal transmission line. The data input / output circuit 220 may transmit data DATA to or receive data DATA from the first to sixteenth storage circuits BK0-BK15, the global buffer GB, and the first to sixteenth operation circuits AC0-AC15 through a global input / output (hereinafter referred to as "GIO") line.

[0050] The first to sixteenth storage circuits BK0-BK15 can be combined with the first to sixteenth operation circuits AC0-AC15 in a 1:1 manner. For example, the first storage circuit BK0 can be combined with the first operation circuit AC0. The second storage circuit BK1 can be combined with the second operation circuit AC1. Similarly, the sixteenth storage circuit BK15 can be combined with the sixteenth operation circuit AC15. On the other hand, the global buffer GB can be combined with the first to sixteenth operation circuits AC0-AC15. However, this is only an example, and in another example, at least two storage circuits can be combined with one operation circuit.

[0051] Despite Figure 2, but the first to sixteenth storage circuits BK0-BK15 can perform data transmission operations through the GIO line. The data transmission operations of the first to sixteenth storage circuits BK0-BK15 can be divided into memory operations and operator operations. The memory operations of the first to sixteenth storage circuits BK0-BK15 may include data write operations for storing data sent through the data input / output circuit 220 and the GIO line and data read operations for outputting the stored data through the GIO line and the data input / output circuit 220. The first to sixteenth storage circuits BK0-BK15 can store the operation data transmitted through the data input / output circuit 220 and the GIO line, such as the first to sixteenth weight data W1-W16, through the data write operation.

[0052] The operator operation of the first to sixteenth storage circuits BK0-BK15 can be performed by providing operation data (e.g., first to sixteenth weight data W1-W16) to the first to sixteenth operation circuits AC0-AC15 via the GIO line. In this case, the storage circuit can provide the weight data to the corresponding operation circuit combined with the storage circuit. For example, the first storage circuit BK0 can send the first weight data W1 to the first operation circuit AC0 via the GIO line. The second storage circuit BK1 can send the second weight data W2 to the second operation circuit AC1 via the GIO line. Similarly, the sixteenth storage circuit BK15 can send the sixteenth weight data W16 to the sixteenth operation circuit AC15 via the GIO line. The operator operation of the first to sixteenth storage circuits BK0-BK15 can be performed by receiving and storing the operation result data output from the first to sixteenth operation circuits AC0-AC15 via the GIO line.

[0053] The global buffer GB may also perform a data transfer operation through the GIO line. Therefore, the global buffer GB may store operation data, such as vector data V transmitted through the data input / output circuit 220 and the GIO line. The global buffer GB may provide operation data, such as vector data V, to the first to sixteenth operation circuits AC0-AC15 through the GIO line. The vector data V output from the global buffer GB may be sent to the first to sixteenth operation circuits AC0-AC15 in common through the GIO line.

[0054] The first to sixteenth operation circuits AC0-AC15 can perform operations using the first to sixteenth weight data W1-W16 sent from the first to sixteenth storage circuits BK0-BK15 and the vector data V sent from the global buffer GB. For example, the first operation circuit AC0 can perform a first operation on the first weight data W1 and the vector data V sent from the first storage circuit BK0 and the global buffer GB, respectively. The second operation circuit AC1 can perform a second operation on the second weight data W2 and the vector data V sent from the second storage circuit BK1 and the global buffer GB, respectively. Similarly, the sixteenth operation circuit AC15 can perform a sixteenth operation on the sixteenth weight data W16 and the vector data V sent from the sixteenth storage circuit BK15 and the global buffer GB, respectively. The first to sixteenth operation circuits AC0-AC15 can send the operation result data generated due to the operation to the first to sixteenth storage circuits BK0-BK15 or to the data input / output circuit 220.

[0055] Figure 3 It is shown Figure 1 1 is a block diagram of an example of a storage preparation circuit 310 of a request processing circuit 300 included in a storage device 100. In addition, Figure 4 It is shown Figure 3 Flowchart of the operation of the storage preparation circuit 310.

[0056] First refer to Figure 3 The storage preparation circuit 310 may include a first flag register 311 and a first request output selection circuit 312. The first flag register 311 may store the slave mode control circuit ( Figure 1 350). The first flag register 311 may send the stored first queue flag signal Q_FLAG1 to the first request output selection circuit 312. In an example, the first flag register 311 may send the first queue flag signal Q_FLAG1 to the first request output selection circuit 312 at a time point when the storage request M_REQ is input to the storage preparation circuit 310. In another example, when the first queue flag signal Q_FLAG1 is sent to the first flag register 311, the first flag register 311 may send the first queue flag signal Q_FLAG1 to the first request output selection circuit 312 regardless of whether the storage request M_REQ is input. The first request output selection circuit 312 may be selected from the software domain ( Figure 1 10) Operating System ( Figure 112) receives the storage request M_REQ. The first request output selection circuit 312 may allow the output of the storage request M_REQ or prevent the output of the storage request M_REQ based on the logic level (or value) of the first queue flag signal Q_FLAG1 sent from the first flag register 311.

[0057] For more details, refer to Figure 4 Combined with Figure 3 , in operation 411, the first request output selection circuit 312 may determine whether the storage request M_REQ is input. The determination in operation 411 may continue until the storage request M_REQ is input to the first request output selection circuit 312. When the storage request M_REQ is input to the first request output selection circuit 312, in operation 412, the first request output selection circuit 312 may determine whether the first queue flag signal Q_FLAG1 has a first logic level (i.e., a binary value of "1"). In the determination of operation 412, when the first queue flag signal Q_FLAG1 has a first logic level (i.e., a binary value of "1"), in operation 413, the first request output selection circuit 312 may output the storage request M_REQ. In the determination of operation 412, when the first queue flag signal Q_FLAG1 has a second logic level (i.e., a binary value of "0"), in operation 414, the first request output selection circuit 312 may block the output of the storage request M_REQ.

[0058] Figure 5 It is shown Figure 1 1 is a block diagram of an example of an operation preparation circuit 320 of a request processing circuit 300 included in a storage device 100. In addition, Figure 6 It is shown Figure 5 Flowchart of the operation of the operation preparation circuit 320.

[0059] refer to Figure 5 The operation preparation circuit 320 may include a second flag register 321 and a second request output selection circuit 322. The second flag register 321 may store the slave mode control circuit ( Figure 1The second flag register 321 may send the stored second queue flag signal Q_FLAG2 to the second request output selection circuit 322. In an example, the second flag register 321 may send the second queue flag signal Q_FLAG2 to the second request output selection circuit 322 at a time point when the operation request OP_REQ is input to the operation preparation circuit 320. In another example, when the second queue flag signal Q_FLAG2 is sent to the second flag register 321, the second flag register 321 may send the second queue flag signal Q_FLAG2 to the second request output selection circuit 322 regardless of whether the operation request OP_REQ is input. The second request output selection circuit 322 may be selected from the software domain ( Figure 1 10) Driver ( Figure 1 13) receives the operation request OP_REQ. The second request output selection circuit 322 can allow the output of the operation request OP_REQ or prevent the output of the operation request OP_REQ based on the logic level (or value) of the second queue flag signal Q_FLAG2 sent from the second flag register 321.

[0060] For more details, refer to Figure 6 Combined with Figure 5 , in operation 421, the second request output selection circuit 322 may determine whether the operation request OP_REQ is input. The determination in operation 421 may be continuously performed until the operation request OP_REQ is input to the second request output selection circuit 322. When the operation request OP_REQ is input to the second request output selection circuit 322, in operation 422, the second request output selection circuit 322 may determine whether the second queue flag signal Q_FLAG2 has a first logic level, that is, a binary value of "1". In the determination of operation 422, when the second queue flag signal Q_FLAG2 has the first logic level (that is, the binary value of "1"), in operation 423, the second request output selection circuit 322 may output the operation request OP_REQ. In the determination of operation 422, when the second queue flag signal Q_FLAG2 has the second logic level (that is, the binary value of "0"), in operation 424, the second request output selection circuit 322 may prevent the output of the operation request OP_REQ.

[0061] Figure 7 Shows from Figure 1 00 includes an example of a storage queue state signal MQ_STAT output by a storage request queue 330 of a request processing circuit 300 included in the storage device 100. Figure 7 The storage queue status signal MQ_STAT shown is only an example, and the storage queue status signal MQ_STAT may include multiple pieces of information as required.

[0062] Reference Figure 7 , in the storage request queue ( Figure 1 330) and sent to the control mode circuit ( Figure 1 The storage queue status signal MQ_STAT of 350) may be composed of a first binary stream, and the first binary stream may be composed of a plurality of binary bits. The first binary stream constituting the storage queue status signal MQ_STAT may include four bits. The first bit, i.e., the least significant bit (LSB) of the first binary stream constituting the storage queue status signal MQ_STAT, may indicate that the storage request queue ( Figure 1 More specifically, when the storage request queue ( Figure 1 When the storage area of ​​the storage request queue (330) is completely empty, that is, when the storage request queue ( Figure 1 When there is no storage request M_REQ in the storage area of ​​the storage queue ( 330 ), the first bit of the first binary stream constituting the storage queue state signal MQ_STAT may have a first logic level, that is, a binary value of “1”. On the other hand, when the storage request queue ( Figure 1 330) is not in an empty state, that is, when at least one storage request M_REQ remains in the storage request queue ( Figure 1 When the storage area 330) is in the storage area, the first bit of the first binary stream constituting the storage queue status signal MQ_STAT can have a second logic level, that is, a binary value "0".

[0063] The second bit of the first binary stream constituting the storage queue status signal MQ_STAT may indicate the storage request queue ( Figure 1 More specifically, when the storage request queue ( Figure 1 When all storage areas of the storage request queue ( 330 ) are filled with storage requests M_REQ, the second bit of the first binary stream constituting the storage queue state signal MQ_STAT may have a first logic level, that is, a binary value “1”. On the other hand, when the storage request queue ( Figure 1 330) is not in a full state, that is, when the storage request queue ( Figure 1 When there is at least one empty storage area without a storage request M_REQ in 330), the second bit of the first binary stream constituting the storage queue status signal MQ_STAT may have a second logic level, that is, a binary value “0”.

[0064] The third bit of the first binary stream constituting the storage queue status signal MQ_STAT may indicate whether the storage request M_REQ is received from the storage request queue ( Figure 1More specifically, when the storage request M_REQ is not output from the storage request queue ( Figure 1 When the storage request queue ( 330 ) is output, the third bit of the first binary stream constituting the storage queue status signal MQ_STAT may have a first logic level, that is, a binary value of “1”. On the other hand, when the storage request queue ( Figure 1 330) output storage request queue ( Figure 1 When a storage request M_REQ is stored in the storage area pointed to by the front pointer in the storage area 330), the third bit of the first binary stream constituting the storage queue status signal MQ_STAT may have a second logic level, that is, a binary value "0".

[0065] The fourth bit, i.e., the most significant bit (MSB) of the first binary stream constituting the storage queue status signal MQ_STAT, may indicate whether the storage request M_REQ is input (entered) into the storage request queue ( Figure 1 More specifically, when the storage request M_REQ is not input into the storage request queue ( Figure 1 330), the fourth bit of the first binary stream constituting the storage queue state signal MQ_STAT may have a first logic level, that is, a binary value of "1". On the other hand, when the storage request M_REQ is sent to the storage request queue ( Figure 1 When the storage area pointed to by the back pointer in the storage area 330) of the storage queue status signal MQ_STAT, the fourth bit of the first binary stream constituting the storage queue status signal MQ_STAT can have a second logic level, that is, a binary value "0".

[0066] Figure 8 Shows from Figure 1 1. An example of an operation queue state signal OPQ_STAT output by the operation request queue 340 of the request processing circuit 300 in the storage device 100. Figure 8 The operation queue status signal OPQ_STAT shown is only an example, and the operation queue status signal OPQ_STAT may include multiple pieces of information as required.

[0067] Reference Figure 8 , in the operation request queue ( Figure 1 340) and sent to the mode control circuit ( Figure 1 The operation queue status signal OPQ_STAT of 350) may be composed of a second binary stream, the second binary stream including a plurality of binary bits. The second binary stream constituting the operation queue status signal OPQ_STAT may include four bits. The first bit, i.e., the least significant bit (LSB) of the second binary stream constituting the operation queue status signal OPQ_STAT, may indicate that the operation request queue ( Figure 1 More specifically, when the operation request queue ( Figure 1 When the storage area of ​​340) is completely empty, that is, when the operation request queue ( Figure 1 When there is no operation request OP_REQ in the storage area of ​​the operation queue state signal OPQ_STAT, the first bit of the operation queue state signal OPQ_STAT may have a first logic level, that is, a binary value of "1". On the other hand, when the operation request queue ( Figure 1 340) is not in an empty state, that is, when at least one operation request OP_REQ remains in the operation request queue ( Figure 1 When the storage area 340) is in the storage area 340), the first bit of the second binary stream of the operation queue status signal OPQ_STAT can have a second logic level, that is, a binary value "0".

[0068] The second bit of the second binary stream constituting the operation queue state signal OPQ_STAT may indicate the operation request queue ( Figure 1 More specifically, when the operation request queue ( Figure 1 340) is in the operation request queue ( Figure 1 When all storage areas of the operation request queue ( 340 ) are filled with the full state of the operation request OP_REQ, the second bit of the second binary stream constituting the operation queue state signal OPQ_STAT may have a first logic level, that is, a binary value “1”. On the other hand, when the operation request queue ( Figure 1 340) is not full, that is, when the operation request queue ( Figure 1 When there is at least one empty storage area without an operation request OP_REQ in 340), the second bit of the second binary stream constituting the operation queue status signal OPQ_STAT may have a second logic level, that is, a binary value “0”.

[0069] The third bit of the second binary stream constituting the operation queue status signal OPQ_STAT may indicate whether a request is received from the operation request queue ( Figure 1 More specifically, when the operation request queue ( 340 ) is not dequeued, Figure 1 When the storage request M_REQ is output from the operation request queue ( 340 ), the third bit of the second binary stream constituting the operation queue state signal OPQ_STAT may have a first logic level, that is, a binary value of “1”. On the other hand, when the storage request M_REQ is output from the operation request queue ( Figure 1 340) output operation request queue ( Figure 1When the operation request OP_REQ stored in the storage area pointed to by the front pointer in the storage area 340) of the operation queue, the third bit of the second binary stream constituting the operation queue status signal OPQ_STAT can have a second logic level, that is, a binary value "0".

[0070] The fourth bit, that is, the most significant bit (MSB) of the second binary stream constituting the operation queue status signal OPQ_STAT may indicate whether the operation request OP_REQ is input (entered) into the operation request queue ( Figure 1 More specifically, when the operation request OP_REQ is not input into the operation request queue ( Figure 1 340), the fourth bit of the second binary stream constituting the operation queue state signal OPQ_STAT may have a first logic level, that is, a binary value of "1". On the other hand, when the operation request OP_REQ is input to the operation request queue ( Figure 1 When the storage area pointed to by the back pointer in the storage area 340) of the operation queue state signal OPQ_STAT, the fourth bit of the second binary stream constituting the operation queue state signal OPQ_STAT may have a second logic level, that is, a binary value "0".

[0071] Fig. 9 It is shown Figure 1 1 is a block diagram of an example of a mode control circuit 350 of a request processing circuit 300 in a storage device 100.

[0072] Reference Fig. 9 The mode control circuit 350 may include a first queue flag signal generating circuit 351, a second queue flag signal generating circuit 352, and a mode signal generating circuit 353. Each of the first queue flag signal generating circuit 351 and the mode signal generating circuit 353 may receive a request from the storage request queue ( Figure 1 330) sends the storage queue status signal MQ_STAT and the slave operation request queue ( Figure 1 On the other hand, the second queue flag signal generating circuit 352 can receive the operation queue status signal OPQ_STAT sent from the operation request queue ( Figure 1 The first queue flag signal generating circuit 351 can generate the first queue flag signal Q_FLAG1 based on the storage queue status signal MQ_STAT and the operation queue status signal OPQ_STAT to send a signal to the storage preparation circuit ( Figure 1 The second queue flag signal generating circuit 352 can generate a second queue flag signal Q_FLAG2 based on the operation queue state signal OPQ_STAT to send a first queue flag signal Q_FLAG1 to the operation preparation circuit ( Figure 1 The mode signal generating circuit 353 can generate a mode signal MODE based on the storage queue state signal MQ_STAT and the operation queue state signal OPQ_STAT to send a second queue flag signal Q_FLAG2 to the arbiter ( Figure 1 360) sends mode signal MODE.

[0073] Fig.10 It is shown Fig. 9 Flow chart of the operation of the first queue flag signal generating circuit 351 included in the mode control circuit 350 of FIG. In the following example, it is assumed that the configurations of the storage queue state signal MQ_STAT and the operation queue state signal OPQ_STAT are respectively the same as those of the reference Figure 7 and Figure 8 The configuration described is the same.

[0074] Reference Fig.10 Combined with Fig. 9 In operation 431, the first queue flag signal generating circuit 351 of the mode control circuit 350 may receive the storage queue status signal MQ_STAT and the operation queue status signal OPQ_STAT. In operation 432, the first queue flag signal generating circuit 351 may determine the storage request queue ( Figure 1 330) is in a full state. When the storage request queue ( Figure 1 330) is in full state, that is, as shown in reference Figure 7 As described above, when the second bit of the first binary stream constituting the storage queue state signal MQ_STAT has a first logic level (i.e., a binary value of "1"), in operation 433, the first queue flag signal generating circuit 351 may generate and output a first queue flag signal Q_FLAG1 having a second logic level (i.e., having a binary value of "0"). As described above with reference to Figure 3 and Figure 4 As described above, when the first queue flag signal Q_FLAG1 having the second logic level (ie, the binary value “0”) is transmitted, the storage preparation circuit 310 may prevent the storage request queue ( Figure 1 330) sends a storage request M_REQ).

[0075] In the determination of operation 432, when the storage request queue ( Figure 1 330) is not in full state, that is, as shown in reference Figure 7As described above, when the second bit of the first binary stream constituting the storage queue status signal MQ_STAT has a second logic level (i.e., a binary value of "0"), in operation 434, the first queue flag signal generating circuit 351 may determine whether the operation request OP_REQ is input (entered) into the operation request queue ( Figure 1 In the determination of operation 434, when the operation request OP_REQ is input into the operation request queue ( Figure 1 340), that is, as referenced Figure 8 As described above, when the fourth bit of the second binary stream constituting the operation queue status signal OPQ_STAT has a second logic level (i.e., binary value "0"), the first queue flag signal generating circuit 351 can generate and output a first queue flag signal Q_FLAG1 having a second logic level (i.e., binary value "0").

[0076] In the determination of operation 434, when the operation request OP_REQ is not input into the operation request queue ( Figure 1 340), that is, as referenced Figure 8 As described above, when the fourth bit of the second binary stream constituting the operation queue state signal OPQ_STAT has a first logic level (ie, a binary value of “1”), in operation 435, the first queue flag signal generating circuit 351 may determine that the operation request queue ( Figure 1 340) is in an empty state. When the operation request queue ( Figure 1 340) is not in an empty state, that is, as shown in reference Figure 8 As described above, when the first bit of the second binary stream constituting the operation queue state signal OPQ_STAT has a second logic level (i.e., a binary value of "0"), the first queue flag signal generating circuit 351 may generate and output a first queue flag signal Q_FLAG1 having a second logic level (i.e., a binary value of "0") in operation 433. In the determination of operation 435, when the operation request queue ( Figure 1 340) is in an empty state, that is, as shown in reference Figure 8 As described above, when the first bit of the second binary stream constituting the operation queue status signal OPQ_STAT has a first logic level (i.e., binary value "1"), the first queue flag signal generating circuit 351 can generate and output a first queue flag signal Q_FLAG1 having a first logic level (i.e., binary value "1") in operation 436.

[0077] As mentioned above, when the storage request queue ( Figure 1 330) is not in full state, and the operation request OP_REQ is not input into the operation request queue ( Figure 1 340), and the operation request queue ( Figure 1 When the first queue flag signal generating circuit 351 is in an empty state, the first queue flag signal generating circuit 351 may generate a first queue flag signal Q_FLAG1 having a first logic level (ie, a binary value of “1”) and send the first queue flag signal Q_FLAG1 to the storage preparation circuit ( Figure 1 In this case, the storage request M_REQ can be received from the storage preparation circuit ( Figure 1 310) is sent to the storage request queue ( Figure 1 On the other hand, when the storage request queue ( Figure 1 330) is in full state, and the operation request OP_REQ is input into the operation request queue ( Figure 1 340), or the operation request queue ( Figure 1 When the first queue flag signal generating circuit 351 is not in the empty state, the first queue flag signal generating circuit 351 may generate a first queue flag signal Q_FLAG1 having a second logic level (ie, a binary value of “0”), and send the first queue flag signal Q_FLAG1 to the storage preparation circuit ( Figure 1 In this case, the storage request M_REQ is sent from the storage preparation circuit ( Figure 1 310) to the storage request queue ( Figure 1 The transmission of 330) can be blocked.

[0078] Fig.11 It is shown Fig. 9 Flow chart of the operation of the second queue flag signal generating circuit 352 included in the mode control circuit 350 of FIG. In the following example, it is assumed that the configurations of the storage queue state signal MQ_STAT and the operation queue state signal OPQ_STAT are respectively the same as those of the reference Figure 7 and Figure 8 The configuration described is the same.

[0079] refer to Fig.11 as well as Fig. 9 In operation 441, the second queue flag signal generating circuit 352 of the mode control circuit 350 may receive the operation queue status signal OPQ_STAT. In operation 442, the second queue flag signal generating circuit 352 may determine the operation request queue ( Figure 1 In the determination of operation 442, when the operation request queue ( Figure 1 340) is in full state, that is, as shown in reference Figure 8As described above, when the second bit of the second binary stream constituting the operation queue state signal MQ_STAT has a first logic level (i.e., a binary value of "1"), in operation 443, the second queue flag signal generating circuit 352 may generate and output a second queue flag signal Q_FLAG2 having a second logic level (i.e., a binary value of "0"). Figure 5 and Figure 6 As described above, when the second queue flag signal Q_FLAG2 having a second logic level (ie, a binary value of “0”) is transmitted, the operation preparation circuit 320 may prevent the operation request OP_REQ from being transmitted to the operation request queue ( Figure 1 of 340).

[0080] In the determination of operation 442, when the operation request queue ( Figure 1 340) is not in full state, that is, as shown in reference Figure 8 As described above, when the second bit of the second binary stream constituting the operation queue state signal OPQ_STAT has a second logic level (i.e., a binary value of "0"), in operation 444, the second queue flag signal generating circuit 352 may generate and output a second queue flag signal Q_FLAG2 having a first logic level (i.e., a binary value of "1"). Figure 5 and Figure 6 As described above, when the second queue flag signal Q_FLAG2 having the first logic level (ie, the binary value “1”) is transmitted, the operation preparation circuit 320 may send a request to the operation request queue ( Figure 1 340) sends an operation request OP_REQ.

[0081] Fig.12 It is shown Fig. 9 Flowchart of the operation of the mode signal generating circuit 353 included in the mode control circuit 350 of FIG. 1. In the following example, it is assumed that the configurations of the storage queue state signal MQ_STAT and the operation queue state signal OPQ_STAT are respectively as described in FIG. Figure 7 and Figure 8 The configuration described is the same.

[0082] Reference Fig.12 Combined with Fig. 9 In operation 451, the mode signal generation circuit 353 of the mode control circuit 350 may receive the storage queue status signal MQ_STAT and the operation queue status signal OPQ_STAT. In operation 452, the mode signal generation circuit 353 may determine the operation request queue ( Figure 1 In the determination of operation 452, when the operation request queue ( Figure 1340) is in an empty state, that is, as shown in reference Figure 8 As described above, when the first bit of the second binary stream constituting the operation queue state signal OPQ_STAT has a first logic level (i.e., a binary value of “1”), in operation 453, the mode signal generating circuit 353 may generate a memory mode signal as the mode signal MODE and send the memory mode signal to the arbiter ( Figure 1 360) sends a memory mode signal. In the determination of operation 452, when the operation request queue ( Figure 1 340) is not in an empty state, that is, as shown in reference Figure 8 As described above, when the first bit of the second binary stream constituting the operation queue state signal OPQ_STAT has a second logic level (ie, a binary value of “0”), in operation 454, the mode signal generating circuit 353 may determine that the storage request queue ( Figure 1 330) is in an empty state.

[0083] When the request queue ( Figure 1 330) is not in an empty state, that is, as shown in reference Figure 8 As described above, when the first bit of the first binary stream constituting the storage queue status signal MQ_STAT has a second logic level (i.e., a binary value of “0”), in operation 453, the mode signal generating circuit 353 may generate a memory mode signal as the mode signal MODE and send the memory mode signal to the arbiter ( Figure 1 360). When the request queue is stored in operation 454 ( Figure 1 330) is in an empty state, that is, as shown in reference Figure 8 As described above, when the first bit of the first binary stream constituting the storage queue state signal MQ_STAT has a first logic level (i.e., a binary value of “1”), in operation 455, the mode signal generating circuit 353 may generate an operator mode signal as the mode signal MODE and send the operator mode signal to the arbiter ( Figure 1 of 360).

[0084] Fig.13 is a block diagram showing the software domain 10 and the storage device 500 according to an embodiment of the present disclosure. Fig.13 In, with Figure 1 The same reference numerals as in the figure denote the same components, and repeated descriptions will be omitted below.

[0085] Reference Fig.13, the storage device 500 may include a memory-operator unit 200 and a request processing circuit 600. The request processing circuit 600 may include a storage preparation circuit 610, an operation preparation circuit 320, a storage request queue 630, an operation request queue 340, a mode control circuit 650 and an arbiter 360. Figures 1 to 12 The description may be equally applied to the operation preparation circuit 320 , the operation request queue 340 , and the arbiter 360 .

[0086] The storage preparation circuit 610 of the request processing circuit 600 may receive a storage request M_REQ requesting a memory operation of the memory-operator unit 200 from the operating system 12 of the software domain 10. The storage preparation circuit 610 may receive a first queue flag signal Q_FLAG1 from the mode control circuit 650. The storage preparation circuit 610 may output the storage request M_REQ or output the blocking request B_REQ based on the first queue flag signal Q_FLAG1. In an example, when the first queue flag signal Q_FLAG1 has a first logic level (e.g., a binary value of "1"), the storage preparation circuit 610 may send the storage request M_REQ to the storage request queue 630. On the other hand, when the first queue flag signal Q_FLAG1 has a second logic level (e.g., a binary value of "0"), the storage preparation circuit 610 may send the blocking request B_REQ to the storage request queue 630. The blocking request B_REQ may be stored in the storage preparation circuit 610 and include information requesting the storage request queue 630 to stop outputting the storage request M_REQ.

[0087] The storage request queue 630 may store the storage request M_REQ or the blocking request B_REQ sent from the storage preparation circuit 610. The storage request queue 630 may output the storage request M_REQ (out of the queue) located in the storage area indicated by the front pointer among the multiple storage areas of the storage request queue 630. When the blocking request B_REQ is stored in the storage area pointed to by the front pointer among the multiple storage areas of the storage request queue 630, the storage request queue 630 may process the blocking request B_REQ by removing the blocking request B_REQ from the storage area indicated by the front pointer without outputting the blocking request B_REQ. After removing the blocking request B_REQ, the storage request queue 630 may stop outputting other storage requests M_REQ. The storage request queue 630 may store the input storage request M_REQ or the blocking request B_REQ in the storage area pointed to by the back pointer among the multiple storage areas. The storage request queue 630 may output the storage request M_REQ stored in the multiple storage areas in the order determined by the schedule. In an example, the storage request queue 330 may output the storage requests M_REQ in an order determined by a reordering method (e.g., a first-ready-first-come-first-served (FR-FCFS) method). On the other hand, the storage request queue 630 may process the blocking requests B_REQ in the reordering method. That is, the blocking requests B_REQ may be processed in the storage request queue 630 in the same order as the order in which they are input to the storage request queue 630.

[0088] The storage request queue 630 may generate a storage queue status signal MQ_STAT including status information of the storage request queue 630 to send the storage queue status signal MQ_STAT to the mode control circuit 650. The storage request queue 630 may output the storage queue status signal MQ_STAT in synchronization with the time point when the storage request M_REQ and the blocking request B_REQ are sent from the storage preparation circuit 610, the time point when the storage request M_REQ is output, and the time point when the blocking request B_REQ is removed. The storage queue status signal MQ_STAT may include information about whether the storage request M_REQ or the blocking request B_REQ is sent to the storage request queue 630. The storage queue status signal MQ_STAT may include information about whether the blocking request B_REQ is removed from the storage request. In addition, the storage queue status signal MQ_STAT may include information about the state of the storage request queue 630, for example, information about whether all storage areas of the storage request queue 630 are filled (i.e., full state) and information about whether all storage areas of the storage request queue 630 are empty (i.e., empty state).

[0089] The mode control circuit 650 may receive a storage queue status signal MQ_STAT from the storage request queue 630 and an operation queue status signal OPQ_STAT from the operation request queue 340. The operation queue status signal OPQ_STAT may be configured to be consistent with the reference signal. Figure 8 The mode control circuit 650 may generate and output a first queue flag signal Q_FLAG1, a second queue flag signal Q_FLAG2, and a mode signal MODE based on the storage queue state signal MQ_STAT and the operation queue state signal OPQ_STAT. The mode control circuit 650 may send the first queue flag signal Q_FLAG1 to the storage preparation circuit 610. The mode control circuit 650 may send the second queue flag signal Q_FLAG2 to the operation preparation circuit 320. The mode control circuit 650 may send the mode signal MODE to the arbiter 360.

[0090] When the storage request queue 630 satisfies all three conditions according to the state of the storage queue state signal MQ_STAT and the operation request queue 340 satisfies all three conditions according to the state of the operation queue state signal OPQ_STAT, the mode control circuit 650 may send a first queue flag signal Q_FLAG1 having a first logic level (i.e., a binary value of "1") to the storage preparation circuit 610. When the storage request queue 630 is not in a full state, the first condition of the three conditions may be satisfied. When the operation request OP_REQ is not input to the operation request queue 340, the second condition of the three conditions may be satisfied. When the operation request queue 340 is in an empty state, the third condition of the three conditions may be satisfied. When the first queue flag signal Q_FLAG1 having a first logic level (i.e., a binary value of "1") is sent, the storage preparation circuit 610 may send a storage request M_REQ to the storage request queue 630.

[0091] When the storage request queue 630 satisfies one of the three conditions according to the state of the storage queue state signal MQ_STAT and the operation request queue 340 satisfies the state of the operation queue state signal OPQ_STAT, the mode control circuit 650 may send a first queue flag signal Q_FLAG1 having a second logic level (i.e., a binary value of "0") to the storage preparation circuit 610. When the storage request queue 630 is in a full state, the first condition of the three conditions may be satisfied. When the operation request OP_REQ is input to the operation request queue 340, the second condition of the three conditions may be satisfied. When the operation request queue 340 is not in an empty state, the third condition of the three conditions may be satisfied. When the first queue flag signal Q_FLAG1 having a second logic level (i.e., a binary value of "0") is sent, the storage preparation circuit 610 may send a blocking request B_REQ to the storage request queue 630.

[0092] When the operation request queue 340 is not in a full state according to the operation queue state signal OPQ_STAT, the mode control circuit 650 may send a second queue flag signal Q_FLAG2 having a first logic level (i.e., a binary value of “1”) to the operation preparation circuit 320. When the second queue flag signal Q_FLAG2 having a first logic level (i.e., a binary value of “1”) is sent, the operation preparation circuit 320 may send the operation request queue OP_REQ sent from the driver 13 of the software domain 10 to the operation request queue 340. When the operation request queue 340 is in a full state according to the operation queue state signal OPQ_STAT, the mode control circuit 650 may send a second queue flag signal Q_FLAG2 having a second logic level (i.e., a binary value of “0”) to the operation preparation circuit 320. When the second queue flag signal Q_FLAG2 having a second logic level (i.e., a binary value of “0”) is sent, the operation preparation circuit 320 may not send the operation request OP_REQ sent from the driver 13 of the software domain 10 to the operation request queue 340. In this case, the untransmitted operation request OP_REQ may be transmitted to the operation request queue 340 after a point in time when the second queue flag signal Q_FLAG2 having the first logic level (ie, binary value “1”) is transmitted from the mode control circuit 650 to the operation preparation circuit 320 .

[0093] When the operation request queue 340 is in an empty state according to the operation queue state signal OPQ_STAT, the mode control circuit 650 may generate a memory mode signal as the mode signal MODE to send the memory mode signal to the arbiter 360. Even if the operation request queue 340 is not in an empty state according to the operation queue state signal OPQ_STAT, the mode control circuit 650 may generate a memory mode signal as the mode signal MODE to send the memory mode signal to the arbiter 360 until the blocking request B_REQ is removed from the storage request queue 630 according to the storage queue state signal MQ_STAT. On the other hand, when the operation request queue 340 is not in an empty state according to the operation queue state signal OPQ_STAT and the blocking request B_REQ is removed from the storage request queue 630 according to the storage queue state signal MQ_STAT, the mode control circuit 650 may generate an operator mode signal as the mode signal MODE to send the operator mode signal to the arbiter 360.

[0094] Fig.14 It is shown Fig.13 5 is a block diagram of an example of a storage preparation circuit 610 of a request processing circuit 600 included in a storage device 500. In addition, Fig.15 It is shown Fig.14 Flowchart of the operation of the storage preparation circuit 610.

[0095] First refer to Fig.14 The storage preparation circuit 610 may include a first flag register 611 and a first request output selection circuit 612. The first flag register 611 may store the slave mode control circuit ( Fig.13 650). The first flag register 611 may send the stored first queue flag signal Q_FLAG1 to the first request output selection circuit 612. In an example, the first flag register 611 may send the first queue flag signal Q_FLAG1 to the first request output selection circuit 612 at a time point when the storage request M_REQ is input to the storage preparation circuit 610. In another example, when the first queue flag signal Q_FLAG1 is sent to the first flag register 611, the first flag register 611 may send the first queue flag signal Q_FLAG1 to the first request output selection circuit 612 regardless of whether the storage request M_REQ is input. The first request output selection circuit 612 may be selected from the software domain ( Fig.13 10) Operating System ( Fig.1312) receives the storage request M_REQ. The first request output selection circuit 612 may include the blocking request B_REQ itself. The first request output selection circuit 612 may output the storage request M_REQ or the blocking request B_REQ based on the logic level (or binary value) of the first queue flag signal Q_FLAG1 sent from the first flag register 611.

[0096] For more details, refer to Fig.15 Combined with Fig.14 , in operation 711, the first request output selection circuit 612 may determine whether the storage request M_REQ is input. The determination of operation 711 may continue until the storage request M_REQ is input to the first request output selection circuit 612. When the storage request M_REQ is input to the first request output selection circuit 612, in operation 712, the first request output selection circuit 612 may determine whether the first queue flag signal Q_FLAG1 has a first logic level, that is, a binary value of "1". In the determination of operation 712, when the first queue flag signal Q_FLAG1 has the first logic level (that is, a binary value of "1"), the first request output selection circuit 612 may output the storage request M_REQ in operation 713. In the determination of operation 712, when the first queue flag signal Q_FLAG1 has a second logic level (that is, a binary value of "0"), in operation 714, the first request output selection circuit 612 may block the output of the storage request M_REQ and output the blocking request B_REQ.

[0097] Fig.16 Shows from Fig.13 00 includes an example of a storage queue state signal MQ_STAT output by a storage request queue 630 of a request processing circuit 600 included in a storage device 500. Fig.16 The storage queue status signal MQ_STAT shown is only an example, and the storage queue status signal MQ_STAT may include multiple pieces of information as required.

[0098] refer to Fig.16 , in the storage request queue ( Fig.13 630) and sent to the mode control circuit ( Fig.13 The storage queue status signal MQ_STAT of 650) may be composed of a first binary stream, and the first binary stream may be composed of a plurality of binary bits. The first binary stream constituting the storage queue status signal MQ_STAT may include four bits. The first bit, i.e., the least significant bit (LSB) of the first binary stream constituting the storage queue status signal MQ_STAT may indicate the storage request queue ( Fig.13 More specifically, when the storage request queue ( Fig.13630) is in an empty state, that is, the storage request queue ( Fig.13 When the storage area of ​​630) is completely empty, that is, when the storage request queue ( Fig.13 When there is no storage request M_REQ and no blocking request B_REQ in the storage queue state signal MQ_STAT, the first bit of the first binary stream constituting the storage queue state signal MQ_STAT may have a first logic level, that is, a binary value of "1". On the other hand, when the storage request queue ( Fig.13 630) is not in an empty state, that is, when at least one storage request M_REQ or blocking request B_REQ remains in the storage request queue ( Fig.13 When the storage area 630 is in the storage area, the first bit of the storage queue status signal MQ_STAT can have a second logic level, that is, a binary value "0".

[0099] The second bit of the first binary stream constituting the storage queue status signal MQ_STAT may indicate the storage request queue ( Fig.13 More specifically, when the storage request queue ( Fig.13 630) is full, that is, when the storage request queue ( Fig.13 When the storage area of ​​the storage queue (630) is completely filled with storage requests M_REQ (which may include blocking requests B_REQ), the second bit of the storage queue state signal MQ_STAT may have a first logic level, that is, a binary value "1". On the other hand, when the storage request queue ( Fig.13 630) is not in a full state, that is, the storage request queue ( Fig.13 When there is at least one empty storage area without a storage request M_REQ or a blocking request B_REQ in 630), the second bit of the storage queue status signal MQ_STAT may have a second logic level, ie, a binary value “0”.

[0100] The third bit of the first binary stream constituting the storage queue status signal MQ_STAT may indicate whether the blocking request B_REQ is removed from the storage request queue ( Fig.13 More specifically, when the blocking request B_REQ is not removed from the storage request queue ( Fig.13 630), the third bit of the first binary stream constituting the storage queue state signal MQ_STAT may have a first logic level, that is, a binary value of "1". On the other hand, when the blocking request B_REQ is removed from the storage request queue ( Fig.13 When the storage area indicated by the front pointer among the storage areas of 630) is removed, the third bit of the storage queue status signal MQ_STAT may have a second logic level, that is, a binary value “0”.

[0101] The fourth bit, i.e., the most significant bit (MSB) of the first binary stream constituting the storage queue status signal MQ_STAT, may indicate whether the storage request M_REQ or the blocking request B_REQ is input (enqueued) to the storage request queue ( Fig.13 More specifically, when the storage request M_REQ or the blocking request B_REQ is not input into the storage request queue ( Fig.13 630), the fourth bit of the first binary stream constituting the storage queue state signal MQ_STAT may have a first logic level, that is, a binary value of "1". On the other hand, when a storage request M_REQ or a blocking request B_REQ is input to the storage request queue ( Fig.13 When the storage area indicated by the rear pointer is among the storage areas of 630), the fourth bit of the storage queue status signal MQ_STAT can have a second logic level, that is, a binary value "0".

[0102] Fig.17 It is shown Fig.13 1 is a block diagram of an example of a mode control circuit 650 of a request processing circuit 600 included in a storage device 500 of FIG.

[0103] refer to Fig.17 The mode control circuit 650 may include a first queue flag signal generating circuit 651, a second queue flag signal generating circuit 652 and a mode signal generating circuit 653. The first queue flag signal generating circuit 651 and the mode signal generating circuit 653 may jointly receive a request from the storage request queue ( Fig.13 630) sends a storage queue status signal MQ_STAT and a request queue ( Fig.13 On the other hand, the second queue flag signal generating circuit 652 can receive the operation queue status signal OPQ_STAT sent from the operation request queue ( Fig.13 The first queue flag signal generating circuit 651 can generate a first queue flag signal Q_FLAG1 based on the storage queue status signal MQ_STAT and the operation queue status signal OPQ_STAT to send the first queue flag signal Q_FLAG1 to the storage preparation circuit ( Fig.13 The second queue flag signal generating circuit 652 may generate a second queue flag signal Q_FLAG2 based on the operation queue state signal OPQ_STAT to send the second queue flag signal Q_FLAG2 to the operation preparation circuit ( Fig.13The mode signal generating circuit 653 can generate the mode signal MODE based on the storage queue state signal MQ_STAT and the operation queue state signal OPQ_STAT to send the mode signal MODE to the arbiter ( Fig.13 The operations of the first queue flag signal generating circuit 651 and the second queue flag signal generating circuit 652 can be respectively as described in reference to Fig.10 and Fig.11 The operations described are the same.

[0104] Fig.18 It is shown Fig.17 Flowchart of the operation of the mode signal generating circuit 653 included in the mode control circuit 650 of FIG. 1. In the following example, it is assumed that the storage queue state signal MQ_STAT and the operation queue state signal OPQ_STAT are configured to be respectively connected to the reference Fig.16 and Figure 8 Same as described.

[0105] Reference Fig.18 Combined with Fig.17 In operation 751, the mode signal generation circuit 653 of the mode control circuit 650 may receive the storage queue status signal MQ_STAT and the operation queue status signal OPQ_STAT. In operation 752, the mode signal generation circuit 653 may determine the operation request queue ( Fig.13 In the determination of operation 752, when the operation request queue ( Fig.13 640) is in an empty state, that is, as shown in reference Figure 8 As described above, when the first bit of the second binary stream constituting the operation queue state signal OPQ_STAT has a first logic level (i.e., has a binary value of “1”), in operation 753, the mode signal generating circuit 653 may generate a memory mode signal as the mode signal MODE to send the memory mode signal to the arbiter ( Fig.13 360). In the determination of operation 752, when the operation request queue ( Fig.13 640) is not in an empty state, that is, as shown in reference Figure 8 As described above, when the first bit of the second binary stream constituting the operation queue status signal OPQ_STAT has a second logic level (i.e., a binary value of “0”), in operation 754, the mode signal generating circuit 653 may determine whether the blocking request B_REQ is received from the storage request queue ( Fig.13 630) was removed.

[0106] In operation 754, when the blocking request B_REQ is not removed from the storage request queue ( Fig.13 630) is removed, that is, as referenced Fig.16 As described above, when the third bit of the first binary stream constituting the storage queue status signal MQ_STAT has a second logic level (i.e., a binary value of "0"), the mode signal generating circuit 653 may generate a memory mode signal as the mode signal MODE to send the memory mode signal to the arbiter ( Fig.13 360). In operation 754, when the storage request queue ( Fig.13 630) removes the blocking request B_REQ, that is, as shown in reference Fig.16 As described above, when the third bit of the first binary stream constituting the storage queue status signal MQ_STAT has a first logic level (i.e., a binary value of "1"), in operation 755, the mode signal generating circuit 653 may generate an operator mode signal as the mode signal MODE to send the operator mode signal to the arbitrator ( Fig.13 of 360).

[0107] For illustrative purposes, a limited number of possible embodiments of the present teachings have been presented above. It will be appreciated by those skilled in the art that various modifications, additions and substitutions are possible. Although this patent document contains many details, these details should not be interpreted as limitations on the scope of the present teachings or the scope that may be claimed, but rather as descriptions of features that may be specific to a particular embodiment. Certain features described in the context of a separate embodiment in this patent document may also be implemented in combination in a single embodiment. On the contrary, the various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. In addition, although the features may be described as working in certain combinations, even initially claimed as such, in some cases, one or more features in the combination may be deleted from the claimed combination, and the claimed combination may involve a variant of a sub-combination or a sub-combination.

Claims

1. A storage device, comprising: A memory-operator unit, which includes a storage circuit and an operation circuit; as well as a request processing circuit that processes a storage request and an operation request sent from the software domain to send a storage command and an address corresponding to the storage request and an operation command and an address corresponding to the operation request to the memory-operator unit, When the operation request is sent from the software domain to the request processing circuit, the request processing circuit schedules the processing of the storage request and the operation request based on the status of the remaining storage requests in the request processing circuit.

2. The storage device according to claim 1, wherein: The request processing circuit processes the operation request after processing the storage request received before the operation request.

3. The storage device according to claim 1, wherein: When the operation request is sent from the software domain, the request processing circuit stops receiving the storage request.

4. The storage device according to claim 3, wherein: The request processing circuit resumes receiving the storage request from the software domain after the operation request is processed.

5. The storage device according to claim 1, wherein: When the operation request is sent from the software domain, the request processing circuit generates a blocking request for stopping the processing of the storage request.

6. The storage device according to claim 1, wherein: The request processing circuit receives the storage request from the operating system of the software domain, and receives the operation request from the driver of the software domain.

7. The storage device according to claim 6, wherein: The request processing circuit comprises: a storage preparation circuit that performs an output operation of the storage request sent from the operating system based on a first queue flag signal; a storage request queue that stores the storage request output from the storage preparation circuit and outputs a storage queue state signal indicating a storage state of the storage request; an operation preparation circuit that performs an output operation of the operation request sent from the driver based on a second queue flag signal; an operation request queue that stores the operation request output from the operation preparation circuit and outputs an operation queue state signal indicating a storage state of the operation request; a mode control circuit that generates and outputs the first queue flag signal, the second queue flag signal, and a mode signal based on the storage queue status signal and the operation queue status signal; and An arbiter, which: receives the storage request output from the storage request queue and the operation request output from the operation request queue; outputs the storage request when the mode signal is a memory mode signal; and outputs the operation request when the mode signal is an operator mode signal.

8. The storage device according to claim 7, in, The storage preparation circuit includes a first request output selection circuit, the first request output selection circuit performs a selective output operation of the storage request, and the operation preparation circuit includes a second request output selection circuit, the second request output selection circuit performs a selective output operation of the operation request, wherein when the first queue flag signal has a first logic level, the first request output selection circuit allows output of the storage request, and when the first queue flag signal has a second logic level, the first request output selection circuit blocks output of the storage request, wherein when the second queue flag signal has the first logic level, the second request output selection circuit allows output of the operation request, and when the second queue flag signal has the second logic level, the second request output selection circuit prevents output of the operation request, and The first logic level is different from the second logic level.

9. The storage device according to claim 8, wherein: The mode control circuit: initially setting the logic level of each of the first queue flag signal and the second queue flag signal to the first logic level; When at least one of the following conditions is satisfied, changing the logic level of the first queue flag signal from the first logic level to the second logic level, the conditions comprising: a condition that the storage request queue is in a full state, a condition that the operation request is sent to the operation request queue, and a condition that the operation request queue is not in an empty state; as well as When a condition that the operation request queue is in the full state is satisfied, the logic level of the second queue flag signal is changed from the first logic level to the second logic level.

10. The storage device according to claim 8, in, Whenever the storage request is input or the storage request is output, the storage request queue outputs the storage queue status signal, and Wherein, whenever the operation request is input or the operation request is output, the operation request queue outputs the operation queue status signal.

11. The storage device according to claim 10, in, the storage queue status signal includes information on whether the storage request queue is in an empty state, whether the storage request queue is in a full state, whether the storage request is output from the storage request queue, and whether the storage request is input to the storage request queue, and The operation queue status signal includes information about the following situations: whether the operation request queue is in the empty state, whether the operation request queue is in the full state, whether the operation request is output from the operation request queue, and whether the operation request is input to the operation request queue.

12. The storage device according to claim 8, wherein: The mode control circuit comprises: a first queue flag signal generating circuit, which receives the storage queue status signal and the operation queue status signal, and generates and outputs the first queue flag signal; a second queue flag signal generating circuit, which receives the operation queue status signal, and generates and outputs the second queue flag signal; and A mode signal generating circuit receives the storage queue status signal and the operation queue status signal, and generates and outputs the memory mode signal or the operator mode signal as the mode signal.

13. The storage device according to claim 12, wherein: The first queue flag signal generating circuit: When the storage request queue is not in the full state, the operation request queue is in the empty state, and no operation request is input to the operation request queue, outputting the first queue flag signal of the first logic level; as well as When the storage request queue is in the full state, when the operation request is input to the operation request queue, or when the operation request queue is not in the empty state, the first queue flag signal of the second logic level is output.

14. The storage device according to claim 12, wherein: The second queue flag signal generating circuit: When the operation request is not in the full state, outputting the second queue flag signal of the first logic level; as well as When the operation request is in the full state, the second queue flag signal of the second logic level is output.

15. The storage device according to claim 12, wherein: The mode signal generating circuit: When the operation request queue is in the empty state, or when the operation request queue is not in the empty state and the storage request queue is in the empty state, outputting the memory mode signal as the mode signal; as well as When the operation request queue is not in the empty state and the storage request queue is in the empty state, the operator mode signal is output as the mode signal.

16. The storage device according to claim 8, in, The storage preparation circuit includes a first request output selection circuit, the first request output selection circuit performs an operation of outputting the storage request, and the operation preparation circuit includes a second request output selection circuit, the second request output selection circuit performs an operation of outputting the operation request, wherein, when the first queue flag signal has the first logic level, the first request output selection circuit allows outputting the storage request, and when the first queue flag signal has the second logic level, the first request output selection circuit outputs a blocking request, wherein when the second queue flag signal has the first logic level, the second request output selection circuit allows output of the operation request, and when the second queue flag signal has the second logic level, the second request output selection circuit prevents output of the operation request, and The first logic level is different from the second logic level.

17. The storage device according to claim 16, in, When the storage request or the blocking request is input, the blocking request is removed from the storage request queue, or the storage request is output, the storage request queue outputs the storage queue state signal, and Wherein, whenever the operation request is input or the operation request is output, the operation request queue outputs the operation queue status signal.

18. The storage device according to claim 17, in, the storage queue status signal includes information on whether the storage request queue is in an empty state, whether the storage request queue is in a full state, whether the blocking request is removed from the storage request queue, and whether the storage request or the blocking request is input to the storage request queue, and The operation queue status signal includes information about the following situations: whether the operation request queue is in the empty state, whether the operation request queue is in the full state, whether the operation request is output from the operation request queue, and whether the operation request is input to the operation request queue.

19. The storage device according to claim 18, wherein: The mode control circuit comprises: a first queue flag signal generating circuit, which receives the storage queue status signal and the operation queue status signal, and generates and outputs the first queue flag signal; a second queue flag signal generating circuit, which receives the operation queue status signal, and generates and outputs the second queue flag signal; and A mode signal generating circuit receives the storage queue status signal and the operation queue status signal, and generates and outputs the memory mode signal or the operator mode signal as the mode signal.

20. The storage device according to claim 19, wherein: The mode signal generating circuit: when the operation request queue is in the empty state, or when the operation request queue is not in the empty state and the blocking request is removed from the storage request queue, outputting the memory mode signal as the mode signal, and When the operation request queue is not in the empty state and the blocking request is not removed from the storage request queue, the operator mode signal is output as the mode signal.

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