A logic gate equivalence determination method based on a graph neural network

Abstract

The present application belongs to the field of electronic design automation (EDA), and specifically provides a logic gate equivalence determination method based on a graph neural network, to improve the speed improvement effect of GNN on SAT solving. The present application provides a logic gate equivalence determination method based on a graph neural network, which effectively represents the function information of the logic gate by constructing a logic gate characteristic value through a truth table, and on this basis, the characteristic value is sorted, and the characteristic serial number is taken as the training target of the graph neural network model, reducing the number of nodes of the full connection layer, thereby improving the circuit representation ability of the graph neural network model while reducing the model parameters, improving the training speed, and in terms of logic gate equivalence determination, using the graph neural network model to predict the similarity between logic gates, improving the variable search strategy and improving the SAT solving speed.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of Electronic Design Automation (EDA), and specifically provides a logic gate equivalence determination method based on a graph neural network. BACKGROUND

[0002] Logic gate equivalence refers to the equivalence of two logic gates in terms of logic function, and logic gate equivalence determination is a main step of equivalence circuit checking, and plays an important role in electronic design automation.

[0003] There are various methods for determining logic gate equivalence, and common methods include truth table comparison, logic expression comparison, and Boolean satisfiability problem (SAT) solving; among them, the truth table comparison method determines equivalence by comparing the truth tables of the outputs of two logic gates; the logic expression comparison method uses Boolean algebra simplification to compare the simplified logic expressions to determine equivalence; and the Boolean satisfiability problem solving method converts the logic equivalence problem into a Boolean satisfiability problem, and determines the equivalence by using a SAT solver. The mainstream SAT solver is based on the Conflict-Driven Clause Learning (CDCL) algorithm, which has the advantages of large problem size and the disadvantages of significant dependence on problem difficulty and high computational complexity for difficult clause solving. In recent years, graph neural networks (GNNs) have been introduced into SAT solvers to improve the time efficiency of solving, such as using GNNs to preprocess logic formulas to identify potential conflicts and structural features to guide the search process, or using GNNs to generate or improve heuristic search strategies based on node features.

[0004] Although GNNs improve the speed of SAT solving, the current graph neural network model still has insufficient representation ability for circuit logic functions due to the complex and variable structure of circuits, resulting in the need for further improvement in the speed improvement effect of GNNs on SAT solving. SUMMARY

[0005] The present application aims to address the shortcomings of the prior art and provides a logic gate equivalence determination method based on a graph neural network to improve the speed improvement effect of GNNs on SAT solving.

[0006] To achieve the above-mentioned purpose, the technical solution adopted by the present application is as follows:

[0007] A logic gate equivalence determination method based on a graph neural network, characterized by comprising the following steps:

[0008] A1. Generating a feature sequence number:

[0009] A1-1. By simulating input, obtaining the truth table of each logic gate of the circuit;

[0010] A1-2. For each logic gate, the characteristic value of the logic gate is calculated respectively;

[0011] A1-3. According to the characteristic value of the logic gate, the logic gate is sorted in descending order, and the logic gate with the same characteristic value has the same sequence number. The sequence number obtained after sorting is taken as the feature sequence number of the logic gate;

[0012] A2. Construct and train a graph neural network model:

[0013] A2-1. Construct a graph neural network model, including: a graph convolution layer and a fully connected layer;

[0014] The graph convolution layer contains nodes and edges of the graph network, and the construction process is: for each logic gate in the circuit, a logic gate node is created, and the initial value of the data vector of the logic gate node is a random number; for each pair of logic gates in the circuit, an edge from the input logic gate node to the output logic gate node is created;

[0015] The fully connected layer contains the same number of nodes as the logic gate nodes, and the nodes are connected to the logic gate nodes of the graph convolution layer in a fully connected manner;

[0016] A2-2. Train the graph neural network model: set the loss function, and use the back propagation algorithm to complete the training of the graph neural network model to obtain the data vector of each logic gate node;

[0017] A3. Construct SAT: define a Boolean variable for each logic gate in the circuit, and set the variables corresponding to the two logic gates to be determined as u1 and u2, and construct the output logic expressions of the two logic gates and Then define the SAT: the logic expression whether it is satisfiable, where represents the exclusive or of the logic expressions and All variables in the logic expression are added to the initially empty set V, and the initial value of the reference variable is set to 1;

[0018] A4. Fast solution of SAT:

[0019] A4-1. Define a backup Boolean variable t, and backup the value of the reference variable to t;

[0020] A4-2. Determine if set V is empty: If it is empty, end the current SAT solution;

[0021] A4-3. Select variable v from set V, update the reference variable to variable v, and delete variable v from set V; if the current selection is the first selection, then select randomly; otherwise, calculate the graphical distance between each variable in set V and the current reference variable, and select the variable with the smallest graphical distance.

[0022] A4-4. Let the value of variable v be the logical inverse of the backup Boolean variable t, and then perform a simplified recursive solution;

[0023] A4-5. Let the value of variable v be the logical value of the backup Boolean variable t, and then perform a simplified recursive solution;

[0024] A4-6. Result returned: The current SAT score is unsatisfactory;

[0025] A5. Logic gate equivalence determination: For SAT: logical expression If the condition is not met, output that the two logic gates to be judged are equivalent; otherwise, output that the two logic gates to be judged are not equivalent.

[0026] Furthermore, in step A1-2, the eigenvalue calculation process is as follows: For the i-th logic gate, let the output value sequence of its truth table be {z}. i,1 ,z i,2 ,z i,3 …z i,M} Calculate the eigenvalue f of the i-th logic gate. i :

[0027]

[0028] Where i = 1, 2, ..., I, I is the number of logic gates, M is the number of rows in the truth table, and z i,j This represents the j-th output value of the i-th logic gate.

[0029] Furthermore, in step A2-2, the loss function is expressed as:

[0030]

[0031] in, N is the predicted feature index value of the i-th logic gate. i Let i be the feature number of the i-th logic gate.

[0032] Furthermore, in step 4-3, the graph representation distance is the Euclidean distance between the data vectors of the graph convolutional layer logic gate nodes corresponding to the two variables.

[0033] Further, in steps A4-4 and A4-5, the recursive solving process is simplified as:

[0034] According to the variable assignment and the logical constraint, the logical expression of the current SAT is simplified to the simplest expression or the logical value Y;

[0035] If the logical expression of the current SAT is simplified to the simplest expression, denoted as Then, according to step A4, the new SAT: the logical expression is solved to determine whether it is satisfiable;

[0036] If the logical expression of the current SAT is simplified to the logical value Y, the logical value Y is determined: if Y=0, the current SAT solving is ended; if Y=1, the entire SAT solving is ended, and the result: the logical expression is returned.

[0037] Based on the above technical solutions, the present application has the following beneficial effects:

[0038] The present application provides a logic gate equivalence determination method based on a graph neural network, which effectively represents the functional information of the logic gate by constructing a truth table to obtain a logic gate characteristic value, and sorts the characteristic value on this basis, taking the characteristic serial number as the training target of the graph neural network model, thereby reducing the number of nodes in the full connection layer, improving the circuit representation capability of the graph neural network model, reducing the model parameters, improving the training speed, and improving the variable search strategy and the SAT solving speed in the aspect of logic gate equivalence determination by using the graph neural network model to predict the similarity between the logic gates. BRIEF DESCRIPTION OF DRAWINGS

[0039] Figure 1 FIG. 1 is a flowchart of the logic gate equivalence determination method based on the graph neural network in the present application. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solutions and beneficial effects of the present application clearer, the present application will be further described in detail below with reference to the drawings and examples.

[0041] The present embodiment provides a logic gate equivalence determination method based on a graph neural network, and the flowchart thereof is shown in FIG. 1, which aims to determine the equivalence of the first and second logic gates of a given digital circuit, and the digital circuit is given in the form of a circuit netlist. Figure 1

[0042] The specific steps of the logic gate equivalence determination method are as follows:

[0043] A1. Generating a characteristic serial number:

[0044] ​A1-1. Obtain the truth table of each logic gate of the circuit through the simulation input;

[0045] A1-2. Calculate the characteristic value of each logic gate, specifically: for the i-th logic gate, let the output value sequence of the truth table be {z i,1 ,z i,2 ,z i,3 …z i,M}, calculate the characteristic value f i of the i-th logic gate:

[0046]

[0047] wherein i = 1, 2, …, I, I is the number of logic gates, M is the number of rows of the truth table, z i,j represents the j-th output value of the i-th logic gate;

[0048] In this embodiment, the number of logic gates I = 36, the number of rows of the truth table M = 32, and the characteristic values of each logic gate are calculated. Taking the first and second logic gates as examples, the characteristic value of the first logic gate f1 = 792058851, and the characteristic value of the second logic gate f2 = 894254013;

[0049] A1-3. According to the size of the characteristic value of the logic gate, the logic gates are sorted in descending order, and the logic gates with the same characteristic value have the same serial number. The serial number obtained after sorting is taken as the characteristic serial number of the logic gate, and the characteristic serial number of the i-th logic gate is denoted as N i .

[0050] In this embodiment, taking the first and second logic gates as examples, the characteristic serial number of the first logic gate N1 = 10, and the characteristic serial number of the second logic gate N2 = 19;

[0051] A2. Construct and train a graph neural network model:

[0052] A2-1. Construct a graph neural network model, including: a graph convolution layer and a fully connected layer;

[0053] The graph convolution layer includes nodes and edges of the graph network, and the construction process is as follows: for each logic gate in the circuit, create a logic gate node, and the data of the logic gate node is a vector with dimension w, whose initial value is a random number; for each pair of logic gates in the circuit, create an edge from the input logic gate node to the output logic gate node;

[0054] In this embodiment, the graph convolution layer includes 36 logic gate nodes and 45 edges, and the initial data of each node is a 64-dimensional vector (w = 64);

[0055] The full connection layer comprises I=36 nodes which are connected to the logical gate nodes of the graph convolution layer in a full connection manner;

[0056] A2-2. Training the graph neural network model: performing graph convolution on the graph convolution layer, forward propagating the obtained logical gate node data to the full connection layer, calculating the loss, and updating the model parameters using the back propagation algorithm, and iterating until the training is completed;

[0057] The loss function is:

[0058]

[0059] Wherein, is the data of the i-th node of the full connection layer, i.e. the predicted feature sequence number;

[0060] In this embodiment, taking the first and second logical gates as examples, the feature sequence number of the first logical gate is The feature sequence number of the second logical gate is Then the loss corresponding to the first and second logical gates is and The final loss of the entire network L=306 is calculated;

[0061] A3. Constructing SAT: defining a Boolean variable for each logical gate in the circuit, and setting the variables corresponding to the first and second logical gates to be determined as u1 and u2 respectively, constructing the output logical expression of logical gate u1 Constructing the output logical expression of logical gate u2 Defining SAT as: the logical expression whether it is satisfiable, wherein, represents the logical expression and the logical expression XOR; add all variables in the logical expression to an initially empty set V, and set the reference variable to a Boolean variable with an initial value of 1;

[0062] In this embodiment, 36 variables u1, u2, u3, …, u 36 are defined, corresponding to 36 logical gates, and the obtained logical expression The SAT defined is: the logical expression whether it is satisfiable, and adding u3, u4, u8, etc. 3 variables in to the set V, i.e. V={u3, u4, u8}, defining a new Boolean variable q, and setting q=1, and setting q as the initial reference variable;

[0063] A4. Fast solution of SAT:

[0064] A4-1. Define a backup Boolean variable t, backup the value of the reference variable into t;

[0065] In this embodiment, let t = q, i.e., t = 1;

[0066] A4-2. Determine whether the set V is empty: if it is empty, end the current SAT solving, otherwise, continue to execute the subsequent steps of the current SAT solving;

[0067] In this embodiment, taking the first round of iteration of solving SAT: logical expression is satisfiable as an example, since the set V is not empty, the subsequent steps of the current SAT solving are continued to be executed;

[0068] A4-3. Select a variable v from the set V, and update the reference variable to the variable v, while deleting the variable v from the set V; if the current selection is the first selection, it is randomly selected; otherwise, calculate the graph representation distance of each variable in the set V and the current reference variable, and select the variable with the smallest graph representation distance; the graph representation distance is the Euclidean distance between the data vectors of the logical gate nodes of the graph convolution layer corresponding to the two variables;

[0069] In this embodiment, in the first selection, the variable u8 is randomly selected, and the reference variable is updated to the variable u8, while it is deleted from V, obtaining V = {u3, u4};

[0070] A4-4. Let the value of v be the logical negation value of t, and perform a simplified recursive solving;

[0071] In this embodiment, taking the first round of iteration of solving SAT: logical expression is satisfiable as an example, let u8 be the logical negation value of t, i.e., u8 = 0;

[0072] The simplified recursive solving specifically includes:

[0073] According to the existing variable assignment and logical constraint, simplify the logical expression to obtain the simplest expression Solve a new SAT: logical expression is satisfiable according to step A4;

[0074] Further, taking a round of iteration of solving SAT: logical expression is satisfiable as an example for illustration:

[0075] According to step A4-1. Define a backup Boolean variable t', let t' = u8, i.e., t' = 0;

[0076] According to step A4-2. Determine whether the set V is empty, since the set V is not empty, the subsequent steps of the current SAT solving are continued to be executed;

[0077] According to step A4-3, the variable is selected, because it is not the first time to select, the graph representation distance of u3, u4 and u8 in V is calculated, the variable u4 with the minimum distance is selected, u4 is set as the reference variable, and is deleted from V, and V={u3} is obtained;

[0078] According to step A4-4, u4 is the logical negation value of t', that is, u4=1;

[0079] The recursive simplification specifically includes:

[0080] According to the existing variable assignment and logical constraint, the logical expression is simplified If the logical value Y=1 is obtained, the whole SAT solving is ended, and the result is returned: the logical expression is satisfiable;

[0081] A5. Logic gate equivalence determination: for SAT: logical expression whether it is satisfiable, if not, two logic gates are equivalent, otherwise, two logic gates are not equivalent;

[0082] In this embodiment, because the logical expression is satisfiable, it is determined that the first logic gate and the second logic gate are not equivalent;

[0083] As can be seen from the above flow, in the SAT solving, the graph representation information obtained by the graph neural network is used to calculate the graph representation distance of the variable to be selected and the reference variable, the variable with the minimum distance is preferentially selected, and the logical value opposite to the reference variable is preferentially assigned to it, so that the SAT solving process is accelerated.

[0084] The above is only a specific embodiment of the present application, any feature disclosed in the specification can be replaced by other equivalent or similar purpose alternative features, unless specifically described; all features disclosed, or steps in all methods or processes, except for mutually exclusive features and / or steps, can be combined in any way.

Claims

1. A method for determining logical gate equivalence based on a graph neural network, characterized in that, The method comprises the following steps: A1. Generating a feature sequence number: A1-1. Obtaining a truth table of each logic gate of the circuit through analog input; A1-2. Calculating the feature value of each logic gate; A1-3. According to the feature value of the logic gate, the logic gate is sorted in descending order, and the logic gate with the same feature value has the same sequence number, and the sequence number obtained after sorting is taken as the feature sequence number of the logic gate; A2. Constructing and training a graph neural network model: A2-1. Constructing a graph neural network model, including: a graph convolution layer and a fully connected layer; The graph convolution layer includes nodes and edges of the graph network, and the construction process is: for each logic gate in the circuit, a logic gate node is created, and the initial value of the data vector of the logic gate node is a random number; for each pair of logic gates in the circuit, an edge from the input logic gate node to the output logic gate node is created; The fully connected layer includes the same number of nodes as the logic gate nodes, and the nodes are connected to the logic gate nodes of the graph convolution layer in a fully connected manner; A2-2. Training the graph neural network model: setting a loss function, and using a back propagation algorithm to complete the training of the graph neural network model to obtain the data vector of each logic gate node; A3. Construct SAT: define a Boolean variable for each logic gate in the circuit, and let the variables corresponding to the two logic gates to be judged be u1 and u2, and construct the output logic expressions of the two logic gates and Then define SAT: the logic expression is satisfiable, where denotes the logic expression and the XOR of the logic expressions Add all variables in the logic expression to the initially empty set V, and set the initial value of the reference variable to 1; A4. Fast solving SAT: A4-1. Defining a backup Boolean variable t, and backing up the value of the reference variable into t; A4-2. Judging whether the set V is empty: if it is empty, ending the current SAT solving; A4-3. Selecting a variable v from the set V, and updating the reference variable to the variable v, and deleting the variable v from the set V; if the current selection is the first selection, it is randomly selected; otherwise, calculating the graph representation distance of each variable in the set V and the current reference variable, and selecting the variable with the minimum graph representation distance; A4-4. Letting the value of the variable v be the logical negation value of the backup Boolean variable t, and performing a simplified recursive solving; A4-5. Letting the value of the variable v be the logical value of the backup Boolean variable t, and performing a simplified recursive solving; A4-6. Returning the result: the current SAT is not satisfiable; A5. Logic gate equivalence determination: for SAT: logical expression whether satisfiable, if not, output the two logic gates to be determined equivalence, otherwise, output the two logic gates to be determined not equivalent.

2. The method of claim 1, wherein the method further comprises: In step A1-2, the eigenvalue calculation process is as follows: for the i-th logic gate, let the output value sequence of its truth table be {z i,1 ,z i,2 ,z i,3 …z i,M}, and the eigenvalue f i of the i-th logic gate is calculated as follows: where i = 1, 2,..., I, I is the number of logic gates, M is the number of rows of the truth table, z i,j represents the jth output value of the ith logic gate.

3. The method of claim 1, wherein the method further comprises: In step A2-2, the loss function is represented as: wherein, is the feature number prediction value for the i-th logic gate, N i is the feature number of the i-th logic gate.

4. The method of claim 1, wherein the method further comprises: In step 4-3, the graph representation distance is the Euclidean distance between the data vectors of the logic gate nodes of the graph convolution layer corresponding to the two variables.

5. The method of claim 1, wherein the method further comprises: In steps A4-4 and A4-5, the simplified recursive solving process is: According to the variable assignment and the logic constraint, the logic expression of the current SAT is simplified to the simplest expression or the logic value Y; If the logical expression of the current SAT is reduced to the simplest expression, denoted as Then solve the new SAT according to step A4: whether the logical expression is satisfiable. If the logic expression of the current SAT is simplified to the logic value Y, judging the logic value Y: if Y=0, ending the current SAT solving; If Y = 1, then the entire SAT solution process ends, and the result is returned: logical expression. This is acceptable.

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