A flow control module and chip integrated circuit for optimizing data flow control timing

Abstract

The application provides a flow control module and a chip integrated circuit for optimizing data flow control timing, comprising a receiving unit, a data processing unit, a data flow control unit, and a sending unit, wherein the receiving unit is used for receiving external data and transmitting the external data to the data processing unit; the data processing unit receives data from the receiving unit, performs data processing inside the data processing unit, obtains a data processing result, and transmits the data processing result to the sending unit; the sending unit is used for receiving the data processing result from the data processing unit and outputting the data processing result according to a clock cycle; and the data flow control unit communicates with the receiving unit and the sending unit and is used for controlling the receiving unit to control data transmission. According to the technical scheme of the application, data flow control can be realized at the same time, additional time consumption is reduced, transmission efficiency is improved, and timing requirements are more easily met.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip design, and particularly relates to a flow control module for optimizing data flow control timing and a chip integrated circuit. BACKGROUND

[0002] Flow control is a measure for controlling data transmission by using software or hardware. Data flow means that a large amount of data is transmitted continuously like water. For example, network processing equipment receives network data from one network port, and outputs the data from other network ports after complex routing processing. From the outside of the equipment, the network data appears to flow into and out of the equipment continuously. If the sending speed of the source equipment is faster than the receiving speed of the destination equipment, the destination equipment will inevitably receive excessive data, which will be discarded or processed incorrectly if the speed difference is not controlled. In this example, if the destination equipment is to correctly receive all data, an effective way is to reduce the average sending speed of the source equipment, for example, to pause for a period of time after sending part of the data, so that the total amount of data sent by the source equipment does not exceed the carrying capacity of the destination equipment. This is flow control. For a large amount of continuous data transmission, flow control is essential.

[0003] Figure 1 An existing flow control architecture is shown in the diagram.

[0004] Data transmission in a chip is usually implemented in the form of a bus. One widely used bus architecture is the Advanced Microcontroller Bus Architecture (AMBA) of ARM. Taking the AXI bus interface of AMBA as an example, see Figure 1 , its flow control function is realized by two signals in opposite directions, namely valid and ready. Valid and data are sent by the sending end, so their directions are the same, both from the sending end to the receiving end. Data is the data to be transmitted, and the valid signal is 1, indicating that the current data is valid data, which must be ensured to be correct during transmission. The valid signal is 0, indicating that the current data is invalid data, which can be ignored. Ready is sent by the receiving end, so its direction is opposite to that of valid / data, and ready is 1, indicating that the receiving end can (or has the ability to) receive data, and ready is 0, indicating that the receiving end cannot (or has no ability to) receive data. As shown in Figure 1 , the diagram shows the direction relationship of valid / data / ready, and valid and ready are both single-bit signals.

[0005] The flow control needs to comply with the following rules:

[0006] 1. Data data uses valid as an indication of validity.

[0007] 2. The only condition for the receiving end to accept data is that both `valid` and `ready` are 1. This is because `valid` being 1 indicates that the data is valid and must be transmitted, while `ready` being 1 indicates that the receiving end is capable of accepting the data. If `valid` is 0, it means the data is invalid, and the receiving end obviously has no need to accept it. If `ready` is 0, it means the receiving end is unable to accept data at this time, for example, because its limited storage space has been filled by previously received data.

[0008] 3. When valid is 1, if ready remains 0, valid must remain 1 and cannot change to 0 on its own. Data must also remain unchanged. This state must be maintained until valid data is received. Only when ready also becomes 1, at which point both valid and ready are 1 (the receiver has received the data), can the sender update valid and data. Because the sender must maintain valid data unchanged when ready is 0 and cannot arbitrarily introduce new data, flow control is achieved. Clearly, both the receiver and sender must detect the ready signal.

[0009] In digital logic, every operation must meet timing requirements. Simply put, meeting timing requirements means that the physical connection path from the transmitter to the receiver cannot be too long or too short. Too long a path leads to excessive delay (delay is the time it takes for data to travel through the connection path), while too short a path leads to insufficient delay. Both excessive and insufficient delays will cause timing violations (technically called timing inconsistencies), preventing the receiver from correctly receiving (sampling) the data. For example, if the transmitter sends data as 1234, due to a timing violation, the receiver will actually receive 1220 after sampling.

[0010] Figure 2 A schematic diagram of a flow control model in the prior art is shown.

[0011] See Figure 2 To simplify understanding, Figure 2Taking the simplest synchronous transmit / receive model as an example, the data flow control timing is described, using the rising edge of the clock for operation. Both the transmitter and receiver operate on the same clock, and the clock delay at both ends is consistent (meaning that the transmitter uses the rising edge of the clock at a certain moment, and the receiver does the same). The transmitter sends valid / data at the rising edge of the clock, and the receiver sends ready at the rising edge of the clock. The transmitter samples valid / data at the rising edge of the clock, and the receiver also samples valid / data / ready at the rising edge of the clock.

[0012] Figure 3 Showing satisfaction Figure 2 The timing diagram for the timing requirements of the flow control model in the example.

[0013] Figure 4 Showing non-satisfaction Figure 2 The timing diagram for the timing requirements of the flow control model in the example.

[0014] See Figure 3 The figure shows for Figure 2 The timing diagram of the flow control model described above, which meets the timing requirements, is shown in the figure. At the rising edge of clock T0, the transmitter outputs "valid" and "data 8'ha5" as 1, and the receiver outputs "ready" as 1. Due to physical delay, the dashed line under T0 in the figure is not aligned with the rising edge of "valid". This misalignment indicates a delay. Since the transmitter sends "valid" and "data" simultaneously, it can be simply assumed that the output delays of "valid" and "data" are the same. Similarly, the rising edge of "ready" is not aligned with the rising edge of clock T0. At the rising edge of clock T1, the receiver samples "valid / data" and "ready". At this time, both "valid" and "ready" are stable 1s, so the receiver can correctly sample "data 8'ha5". At this time, the transmitter also samples "valid" and "ready", both of which are 1s. The transmitter can then update its output with new data, continuing to send "valid" as 1 and new "data". If there is no new data to send, "valid" is changed to 0.

[0015] For comparison, see Figure 4 The figure shows for Figure 2The timing diagram in which the flow control model does not meet the timing requirement. As shown in the figure, the sending end still sends valid / data at the rising edge of T0, but the valid / data path between the sending end and the receiving end is long, resulting in a large delay, and the valid / data only reaches the receiving end at T1. For the receiving end, the valid at T1 is in the change from 0 to 1, and the receiving end cannot sample a stable 0 or 1, so there is a high probability that the receiving end cannot correctly receive the data at this time. This example shows that too large signal delay is easy to cause timing violation.

[0016] Figure 5 Another flow control model in the prior art is shown in the schematic diagram.

[0017] Figure 2 The simple model in the prior art only includes one sending and one receiving, but the entire data chain inside the actual chip includes many intermediate components, and most of the intermediate components such as registers can both receive and send. For example, Figure 5 In order to simplify understanding, it is assumed in the prior art that Figure 5 The sending end in the prior art can only send, and the receiving end can only receive. Referring to Figure 5 The three registers reg1 / reg2 / reg3 in the middle can both receive data coming from the left and send data to the right. The data sent by the sending end is transmitted through the three registers and finally reaches the receiving end. In order to maximize transmission efficiency and make the data of the sending end reach the receiving end as soon as possible, the ready signal of the receiving end needs to be directly connected to the sending end and the three registers, trying to make them receive the ready signal at the same time. Only by directly connecting the ready signal can the data of the sending end reach the receiving end with the shortest total time, but this may cause the timing violation problem of the ready signal. Because the physical positions of the sending end and the three registers are far away from the receiving end, the delay of the ready signal from the receiving end to the sending end and the three registers is inconsistent, and the delay to reg3 may be the smallest and the delay to the sending end may be the largest. From the timing requirement, too large delay is easy to cause timing violation, resulting in abnormal work of the entire system.

[0018] For long-distance signal transmission, pipeline registers are typically inserted between components, a process known as "tipping." For example, assuming there's no reg2 between reg1 and reg3 in the diagram above, and the signals are directly connected and far apart, the delay from reg1 to reg3 would be significant. In this case, reg2 can be inserted to transform a long-distance connection into two short-distance connections. The timing requirement for reg1->reg3 becomes the timing requirement for reg1->reg2 and reg2->reg3, with reg2 acting as the tipping mechanism. However, the ready signal used in flow control is special. It only indicates whether the receiver can receive data at the next moment (usually the rising edge of the clock). For example, if the receiver outputs 1 for ready at time T0 in the diagram, it means it can receive data at time T1. If the receiver outputs 0 for ready at time T1, it means it cannot receive data at the next moment. Ready only indicates the receiver's state, so it can be changed arbitrarily by the receiver and is completely unrelated to valid / data. Therefore, this type of flow control tipping cannot be done directly like regular unidirectional signals. Taking conventional in-direction signal transmission as an example, if a timing violation occurs in a signal within the valid / data stream, simply adding one or more clock cycles to both valid and data (the valid stream is added for the same number of clock cycles as the data stream, maintaining a consistent number of clock cycles) is sufficient—it's very simple. However, this clocking method is incorrect for reverse valid / ready flow control due to the inherent characteristics of the ready state.

[0019] Figure 6 This diagram illustrates another flow control model in the prior art.

[0020] The timing mechanism eliminates excessive delays by inserting registers, but it cannot simply timing the valid / ready data. Therefore, the conventional approach for this type of flow control is to have the receiver of the ready data regenerate a new ready data and send the new ready data to the upstream data sender. For example... Figure 6 As shown in the flow control model, the rightmost receiver emits a "ready" signal. "Ready" only indicates whether the receiver can receive data; the receiver samples "data4" based on "valid4" and "ready". The intermediate component 3 (typically a FIFO-type memory) emits a "ready1" signal. "Ready1" only indicates whether the intermediate component 3 can receive data; the intermediate component 3 samples "data3" based on "valid3" and "ready1", and updates its output "valid4" and "data4" based on "valid4" and "ready". The same logic applies to other components. Whether it's "ready", or "ready1 / 2 / 3", they are only connected to adjacent components, resulting in short distances and making it easier to meet timing requirements.

[0021] But there are also disadvantages, one is that the intermediate component generates a new ready signal, which is directly connected to the same ready, and needs to consume additional time compared to multiple components, reducing data transmission efficiency; two is that although the insertion of intermediate components can improve timing, but still need to use valid / ready flow control frequently, which is not as simple and easy to use as the conventional ready-free unidirectional beat, and is more likely to meet the timing requirements.

[0022] Therefore, a technical solution is needed to achieve data flow control while reducing additional time consumption, improving transmission efficiency, and more easily meeting timing requirements. SUMMARY

[0023] The application aims to provide a flow control module and chip integrated circuit for optimizing data flow control timing, which can achieve data flow control while reducing additional time consumption, improving transmission efficiency, and more easily meeting timing requirements.

[0024] According to one aspect of the application, a flow control module for optimizing data flow control timing is provided, comprising a receiving unit, a data processing unit, a data flow control unit, and a sending unit, wherein,

[0025] The receiving unit is configured to receive external data and transmit the external data to the data processing unit.

[0026] The data processing unit receives data from the receiving unit and performs data processing inside the data processing unit to obtain data processing results and transmit them to the sending unit.

[0027] The sending unit is configured to receive the data processing results from the data processing unit and output the data processing results according to the clock cycle.

[0028] The data flow control unit communicates with the receiving unit and the sending unit and controls the receiving unit to control data transmission.

[0029] According to some embodiments, the receiving unit is configured to receive external first data signals and first valid signals, and first flow control signals from the data flow control unit, store the first data signals according to the first valid signals, send first storage feedback signals to the data flow control unit according to external data reception conditions, and output second data signals and second valid signals to the data processing unit according to the first flow control signals from the data flow control unit.

[0030] The data processing unit is configured to receive the second data signal and the second valid signal from the receiving unit, perform data processing on the second data signal according to the second valid signal inside the data processing unit, and transmit the data processing result to the sending unit as a third data signal and a third valid signal.

[0031] The sending unit is configured to receive the third data signal and the third valid signal from the data processing unit and a data reading signal from outside, store the third data signal according to the third valid signal, and output a fourth data signal and a fourth valid signal to outside according to a clock cycle.

[0032] According to some embodiments, the data flow control unit is configured to output the first flow control signal to the receiving unit according to a first storage feedback signal from the receiving unit, the fourth valid signal from the sending unit, and the data reading signal from outside.

[0033] According to some embodiments, the data flow control unit comprises a counter, and when the count value of the counter is not zero, outputs a valid read request signal to the receiving unit.

[0034] According to some embodiments, the counter is configured to:

[0035] The counter is configured according to a clock cycle, and the value of the counter in the next cycle is the value of the counter in the current cycle minus the level value of the first flow control signal.

[0036] According to some embodiments, the counter is further configured to:

[0037] When the output fourth valid signal of the sending unit and the data reading signal are both high, the counter is configured according to a clock cycle, and the value of the counter in the next cycle is the value of the counter in the current cycle minus the level value of the first flow control signal, and then plus 1.

[0038] According to some embodiments, the sending unit is configured to:

[0039] When the receiving unit is in an empty state, the first storage feedback signal outputs a high level.

[0040] According to some embodiments, the data flow control unit is configured to:

[0041] When the first storage feedback signal outputs a low level and the read request signal is valid, the data flow control unit outputs the first flow control signal to control the receiving unit to output the stored data.

[0042] According to some embodiments, the sending unit capacity size is at least the sum of the maximum delay between the receiving unit and the sending unit of the flow control module and the readout delay of the receiving unit and the write-readout delay of the sending unit.

[0043] According to another aspect of the present application, there is provided a chip integrated circuit, characterized by comprising the flow control module according to any one of the preceding aspects.

[0044] According to embodiments of the present application, the data flow control part and the data processing part are separated by additionally adding the data flow control unit, which is responsible for controlling the timing of the transmission interface data, and the data processing unit, which is responsible for calculation or service protocol processing, etc., facilitating independent development and timing optimization. The receiving unit and the sending unit interface both use valid / ready flow control, and the data processing unit only uses valid and does not use ready. This can reduce the time consumption caused by signal identification, improve data processing efficiency, simplify design, and be more friendly to timing.

[0045] It should be understood that the above general description and the following detailed description are only exemplary and do not limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced as follows.

[0047] Figure 1 An existing flow control architecture is shown.

[0048] Figure 2 An existing flow control model is shown.

[0049] Figure 3 A timing diagram that meets the flow control model timing requirements in the example is shown. Figure 2 A timing diagram that meets the flow control model timing requirements in the example is shown.

[0050] Figure 4 A timing diagram that does not meet the flow control model timing requirements in the example is shown. Figure 2 A timing diagram that does not meet the flow control model timing requirements in the example is shown.

[0051] Figure 5 Another existing flow control model is shown.

[0052] Figure 6 Another existing flow control model is shown.

[0053] Figure 7 A flow control module device timing diagram for optimizing data flow control timing according to an example embodiment is shown.

[0054] Figure 8 A timing diagram showing the flow control module timing requirements being met according to an example.

[0055] Figure 9 A flow diagram showing the application flow of the flow control module according to an example embodiment. DETAILED DESCRIPTION

[0056] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings. Example embodiments, however, can be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the several views and the description of the figures.

[0057] Moreover, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the application. One skilled in the relevant art will recognize, however, that the

[0058] The block diagrams in the drawings show only the functionality of the embodiments and do not imply any particular physical or architectural arrangement of the devices, systems, or methods. No inference should be drawn regarding the implementational aspects of the embodiments as a result of their diagrams illustrating only a selective view of the functionality of the embodiments. That is, all

[0059] The flow diagrams depicted herein are merely illustrative examples, and are not necessarily meant to include all of the steps or operations, or the order in which the operations / steps are performed. For example, some operations / steps can be combined, or further broken down into sub-operations / steps, and thus the actual order of execution can vary from that which is depicted.

[0060] It should be understood that although the terms first, second, third, etc. can be used herein to describe various components, these components should not be limited by these terms. These terms are used only to distinguish one component from another. Thus, a first component discussed below could be termed a second component without departing from the teachings of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0061] The user information (including but not limited to user equipment information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in the present application are all information and data authorized by the user or authorized by all parties, and the collection, use and processing of related data need to comply with relevant laws, regulations and standards of relevant countries and regions, and provide corresponding operation portal for user to choose authorization or refusal.

[0062] Those skilled in the art can understand that the drawings are only schematic diagrams of example embodiments, and the modules or flows in the drawings are not necessarily required for implementing the present application, and therefore cannot be used to limit the protection scope of the present application.

[0063] Timing control is an important aspect of digital circuit design, especially in synchronous circuits. It involves ensuring that data is correctly transmitted between different parts of the circuit, avoiding problems such as clock skew, race conditions, glitches, and ensuring that data arrives at the destination at the correct time. Timing control techniques are crucial for high-performance processors, communication systems, storage systems, and other fields.

[0064] In complex SoC designs, ensuring timing convergence of the entire system is a challenge. Designers must balance performance, power consumption, and area to achieve optimal timing results.

[0065] To this end, the present application proposes a flow control module and chip integrated circuit for optimizing data flow timing, which can achieve data flow control while reducing additional time consumption, improving transmission efficiency, and more easily meeting timing requirements. According to the embodiment, the data flow control part and data processing are separated, the data flow control unit part is responsible for controlling the timing of the transmission interface data, and the data processing unit is responsible for calculation or service protocol processing, etc., which facilitates independent development and timing optimization. If you want to improve the internal timing of the flow control module, you can insert the pipeline by hitting the valid / data, which is very convenient and effective with less iteration.

[0066] According to some embodiments, valid / ready flow control is used for both receiving and sending unit interfaces, and the data processing unit only needs to use valid, not ready. This can reduce time consumption caused by signal recognition, improve data processing efficiency, simplify design, and be more friendly to timing.

[0067] The example embodiments of the present application will be described below with reference to the accompanying drawings.

[0068] Figure 7 An apparatus diagram of a flow control module for optimizing data flow timing according to an example embodiment is shown.

[0069] Referring to Figure 7According to an example embodiment, a flow control module for optimizing data flow timing includes a receiving unit 01, a data processing unit 02, a data flow control unit 03, and a sending unit 04. The receiving unit 01 is configured to receive external data and transmit the external data to the data processing unit 02. The data processing unit 02 receives data from the receiving unit and performs data processing inside the data processing unit 02 to obtain a data processing result and transmit the data processing result to the sending unit 04. The sending unit 04 is configured to receive the data processing result from the data processing unit 02 and output the data processing result according to a clock cycle. The data flow control unit 03 communicates with the receiving unit 01 and the sending unit 04 and controls the receiving unit 01 to control data transmission.

[0070] According to some embodiments, the receiving unit 01 and the sending unit 04 use an active / ready flow control protocol, and the data input / output interface of the data processing unit 02 only includes active signals and data signals in the same direction.

[0071] According to some embodiments, referring to Figure 7 , the receiving unit 01 is configured to receive a first data signal (data1) and a first active signal (valid1) from outside and a first flow control signal (read) from the data flow control unit 03, store the first data signal (data1) according to the first active signal (valid1), send a first storage feedback signal (empty) to the data flow control unit 03 according to external data reception, and output a second data signal (data2) and a second active signal (valid2) to the data processing unit 02 according to the first flow control signal (read) from the data flow control unit 03.

[0072] According to some embodiments, the data processing unit 02 is configured to receive the second data signal (data2) and the second active signal (valid2) from the receiving unit 01, perform data processing on the second data signal (data2) according to the second active signal (valid2) inside the data processing unit 02, and convert the data processing result into a third data signal (data3) and a third active signal (valid3) and transmit the third data signal (data3) and the third active signal (valid3) to the sending unit 04.

[0073] According to some embodiments, the sending unit 04 is configured to receive the third data signal (data3) and the third valid signal (valid3) from the data processing unit 02, and a data read signal (ready4) from outside, store the third data signal (data3) according to the third valid signal (valid3), and output a fourth data signal (data4) and a fourth valid signal (valid4) according to a clock cycle.

[0074] According to some embodiments, the data flow control unit 03 is configured to include a counter 0301, output the first flow control signal (read) to the receiving unit 01 according to a first storage feedback signal (empty) from the receiving unit 01, a fourth valid signal (valid4) from the sending unit 04, and the data read signal (ready4) from outside.

[0075] According to some embodiments, referring to Figure 7 , the receiving unit 01 and the sending unit 04 of the flow control module both use valid / ready flow control, the receiving unit 01 on the left is responsible for receiving data, and the sending unit 04 on the right is responsible for sending data. The receiving unit 01 and the sending unit 04 can be random access memories (RAMs). The flow control module coordinates the receiving RAM and the sending RAM on both sides to achieve the flow control function together.

[0076] According to some embodiments, the data processing module 02 is used to implement business requirements, and its function does not need to be concerned in the design scheme. The focus is that the data interface of this module only contains valid / data in the same direction, without ready in the opposite direction. That is, the flow control module has a data interface using valid / ready flow control outside, and only uses valid inside. The data flow cannot be paused in the internal data processing. Such an architecture separates the data flow control part and the data business part, the data flow control unit 03 is only responsible for controlling the timing of the transmission interface data, and the data processing unit 02 is responsible for calculation or business protocol processing, etc., which facilitates independent development and timing optimization of each part. If the internal timing of the flow control module needs to be improved, it is very convenient to insert a pipeline to hit valid / data, the effect is good, and the iteration is less.

[0077] According to some embodiments, in the prior technical solutions, the flow control part and the actual service part are not separated, and the service part will always bring in valid / ready flow control. Any processing needs to detect the state of valid and ready, and it can also be said that any processing may appear timing violation of ready, resulting in service error. In the present application, the data processing unit 02 part has no ready, compared with the service processing with ready, the need to generate many new readies step by step is reduced, the design is simpler, the resource consumption is less, and any processing cannot appear timing violation of ready, reducing the probability of timing error. Using valid / ready for flow control needs to always check the timing of the valid and ready signals, but without ready, only the timing of the valid signal needs to be checked. Obviously, the condition is more relaxed and easier to meet the requirements, which can reduce the data processing time and further improve the data processing efficiency.

[0078] According to some embodiments, the counter 0301 is configured to output a valid read request signal to the receiving unit 01 when the count value of the counter 0301 is not zero. The flow control module 03 has a counter 0301 inside, denoted as cnt, which is not 0 by default. As long as cnt is not 0, a valid read request signal (rd_req) is generated, and 1 represents valid. When cnt is 0, rd_req is 0. Therefore, rd_req is the or result of each bit of cnt, that is, rd_req = |cnt, and the initial value of rd_req is obviously 1.

[0079] According to some embodiments, the sending unit 04 is configured to output a high level of the first storage feedback signal (empty) when the receiving unit 01 is in an empty state. Assuming the initial state, the system has not started data transmission, and the receiving unit 01 has not stored any data, and is in an empty state (the empty state means that there is no data in the ram, and after all the data is read out, it is also in an empty state. Corresponding to the empty signal in Figure 7 , when the ram is empty, empty is 1, otherwise it is 0). Therefore, only when the receiving unit 01 is not empty, a valid first storage feedback signal (empty) is generated and output to the data flow control unit 03.

[0080] According to some embodiments, the data flow control unit 03 is configured such that when the first storage feedback signal (empty) is low and the read request signal is valid, the data flow control unit 03 outputs the first flow control signal (read) to control the receiving unit 01 to output the stored data, that is, let read = rd_req & (~empty). In other words, when cnt is not 0 and the receiving RAM is not empty, the data flow control unit 03 reads the receiving RAM and allows the receiving RAM to output data.

[0081] According to some embodiments, the storage capacity of the receiving unit 01 is at least two data entries to ensure a continuous data stream. To guarantee continuous output from the receiving RAM while minimizing hardware resource consumption, the receiving RAM capacity is at least two data entries, enabling ping-pong output.

[0082] Figure 8 A timing diagram is shown that satisfies the timing requirements of the flow control module according to the example.

[0083] See Figure 8 The diagram illustrates a timing sequence that meets the timing requirements of the flow control module according to an example embodiment. The maximum capacity stores at least two data items, allowing for continuous data flow. For example, at time T0, data 1 enters the receiving RAM (at this time, the RAM contains one data item, i.e., data 1). At time T1, data 2 enters the receiving RAM (at this time, the RAM contains two data items, i.e., data 1 and data 2, reaching the maximum capacity limit and is full). Simultaneously, at time T1, the receiving RAM outputs data 1, so at time T2, data 3 can enter the receiving RAM (at this time, the RAM contains two data items, i.e., data 2 and data 3, reaching the maximum capacity limit and is full. Data 3 can be stored because data 1 was already output at the previous time T1), and at this time, the receiving RAM can output data 2, allowing the RAM to receive data 4 at the next time step. In this way, the receiving RAM continuously inputs and outputs data.

[0084] According to some embodiments, the capacity of the sending unit 04 is at least the sum of the maximum delay between the receiving unit 01 and the sending unit 04 of the flow control module, the read delay of the receiving unit 01, and the write read delay of the sending unit 04. See also Figure 7 as well as Figure 8 From the output of the receiving RAM to the input of the sending RAM, there is no reverse readiness in this path. Once data is output from the receiving RAM, it can only be transmitted sequentially without stopping midway. Therefore, the sending RAM must be able to store all the data output from the receiving RAM, including data still in the data processing module. The capacity of the sending RAM must be large enough to cover the maximum delay of this data path between the two RAMs.

[0085] According to some embodiments, referring to Figure 8 At T0, cnt is X (X is not equal to 0), rd_req is 1, and empty is 1. Assuming that only one data enters the receiving ram, empty changes from 1 to 0, and a valid read signal is generated at T1. At this time, read reads the only one data in the receiving ram, and empty changes from 0 to 1, so the following read is 0 and no longer reads the ram. Because the read signal is generated at T1, the receiving ram outputs valid2 and data2 at T2 (only data is shown in the figure to show how to calculate the delay, and data does not need to be drawn). Assuming that the data processing module needs 4 cycles at the slowest to output, valid3 is output at T6. The sending ram is read at T7, and valid4 is output at T8. Therefore, the maximum delay from reading the receiving ram to outputting valid from the sending ram is delay1+delay2+delay3+delay4 in the figure, that is, 8. From the perspective of saving resources, the sending ram can store 8 data.

[0086] According to some embodiments, the counter 0301 is configured to: configure the counter 0301 according to a clock cycle, and configure the value of the counter 0301 in the next cycle to be the value of the counter 0301 in the current cycle minus the level value of the first flow control signal (read). Assuming that ready4 is always 0, the 8 data in the sending ram cannot be truly output, which means that the receiving ram must stop outputting after outputting 8 data, that is, under this condition, the receiving ram can be read at most 8 times, and after reading the receiving ram 8 times, rd_req must be 0, so the default value of cnt can be X=8, and cnt(new value)=cnt(old value)-read.

[0087] According to some embodiments, the counter 0301 is further configured to: when the fourth valid signal of the output of the sending unit 04 and the data reading signal are both high, configure the counter 0301 according to a clock cycle, and the value of the counter 0301 in the next cycle is the value of the counter 0301 in the current cycle minus the level value of the first flow control signal (read) and then plus 1. With the increase of read, let cnt decrease in turn until 0, and rd_req also stops reading and receiving ram. But cnt is 0, which means that the flow control module no longer reads and receives ram, and this ram does not output, so the whole data flow stops, so cnt cannot only decrease but not increase. From the valid / ready flow control background knowledge, when the valid4 / ready4 of the sending ram are both valid, it means that the sending ram really outputs data. Therefore, cnt (new value) = cnt (old value) - read + (valid4 & ready4) can be allowed to make the data flow continuously enter and exit the component. The function of reducing read is to make cnt small until 0, so as to prevent the default value of cnt from being too large to read too much data exceeding the capacity limit of the sending ram. The function of adding (valid4 & ready4) is to make cnt larger, so as to prevent the data flow from stopping when cnt is always 0. In summary, the meaning of cnt (new value) = cnt (old value) - read + (valid4 & ready4) is that reducing a read is to output a data from the receiving ram, and adding a (valid4 & ready4) is to output a data from the sending ram. The addition and subtraction functions offset each other to make the data flow continuously pass through the component.

[0088] Figure 9 The application flowchart of the flow control module according to the example embodiment is shown.

[0089] Referring to Figure 9 , the application flowchart of the flow control module is shown, first, the flow control module is divided into three parts, which are the receiving and sending interfaces responsible for input and output at both ends and the data processing unit 02. Among them, the receiving and sending interfaces use valid / ready flow control, and the data processing unit 02 in the middle only needs to transmit valid / data and does not use ready. Simplify the design and optimize the timing. The capacity of the receiving side ram is set to at least 2 data, which can ensure the continuous data flow through the ping-pang output. Then, the maximum delay of the input to output of the business processing of the flow control module is determined, which is assumed to be A. Then, the capacity of the sending side ram is set to A + constant B, and this constant B depends on the readout delay of the receiving ram and the write and readout delay of the sending ram.

[0090] According to some embodiments, the default value of the counter is the sum of the maximum delay between the receiving unit and the sending unit of the flow control module and the readout delay of the receiving unit and the write-readout delay of the sending unit. Generally, the readout delay of the receiving RAM and the write-readout delay of the sending RAM are fixed once the design is completed, and thus are considered as constants. Finally, the flow control timer in the flow control module is configured, the default value of the flow control counter 0301 cnt is A+B, and the next time cnt = current time cnt-read+(valid & ready). The read is the read enable signal of the receiving RAM, and the valid and ready are the output flow control interface signals of the sending RAM.

[0091] According to some embodiments, the design scheme of the application can be applied to the design of a chip integrated circuit, which comprises a flow control module as described above, used for the flow control of data flow in the chip, so that the data flow can be processed efficiently and quickly.

[0092] According to some embodiments, in the design scheme of the application, the data flow control part and the data service part are separated, the data flow control unit part is responsible for controlling the timing of the transmission interface data, and the data processing unit is responsible for calculation or service protocol processing, etc., which facilitates independent development and timing optimization of each other. If the internal timing of the flow control module needs to be improved, it is only necessary to insert the pipeline by tapping the valid / data, which is very convenient, has good effect, and requires less iteration. The valid / ready flow control is used for the interface of the receiving unit and the sending unit, and the data processing unit only needs to use valid and does not use ready, which can reduce the time consumption caused by signal recognition, improve the data processing efficiency, simplify the design, and be more friendly to the timing.

[0093] Those skilled in the art can clearly understand that the technical scheme of the application can be realized by means of software and / or hardware. The "unit" and "module" in the specification refer to software and / or hardware that can independently complete or cooperate with other components to complete a specific function, and the hardware may, for example, be a field programmable gate array, an integrated circuit, etc.

[0094] It should be noted that, for each of the foregoing method embodiments, in order to simply describe, it is expressed as a series of action combinations, but those skilled in the art should know that the application is not limited by the described action sequence, because according to the application, certain steps can be performed in other order or simultaneously. Secondly, those skilled in the art should know that the embodiments described in the specification all belong to preferred embodiments, and the actions and modules involved are not necessarily necessary for the application.

[0095] In the above-described embodiments, the description of each embodiment focuses on different aspects, and the parts not described in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0096] In several embodiments provided by the present application, it should be understood that the disclosed apparatus can be implemented in other manners. For example, the embodiments of the apparatus described above are merely schematic; for example, the division of the units is only a logical function division; there can be another division manner for the actual implementation; for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections between different parts can be indirect couplings or communication connections through some interfaces, devices or units, and can be electrically, mechanically or in other forms.

[0097] The units described as separate parts can or can not be physically separate, and parts displayed as units can or can not be physical units; that is, they can be located in one place or distributed on a plurality of network units. In actual implementation, some or all of the units can be selected according to the actual needs to achieve the purposes of the embodiments of the present application.

[0098] In addition, each functional unit in the various embodiments of the present application can be integrated in a processing unit, or each unit can exist physically as a separate unit, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

[0099] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on such an understanding, the technical solutions of the present application essentially or the part that contributes to the prior art or all or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes a number of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods in the various embodiments of the present application.

[0100] In the above-described embodiments, the description of each embodiment focuses on different aspects, and the parts not described in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0101] The exemplary embodiments of the present application are specifically shown and described above. It should be understood that the present application is not limited to the detailed structure, arrangement or implementation method described herein; on the contrary, the present application is intended to cover various modifications and equivalent arrangements included in the spirit and scope of the appended clauses.

Claims

1. A flow control module for optimizing data stream flow control timing, characterized in that, include: The unit comprises a receiving unit, a data processing unit, a data flow control unit, and a transmitting unit. The receiving unit is used to receive external data and transmit the external data to the data processing unit; The data processing unit receives data from the receiving unit, performs data processing within the data processing unit, obtains data processing results, and transmits them to the sending unit. The sending unit is used to receive the data processing result from the data processing unit and output the data processing result according to the clock cycle; The data flow control unit communicates with the receiving unit and the sending unit, and controls the receiving unit to perform flow control on data transmission. The receiving unit is configured to: receive an external first data signal and a first valid signal, as well as a first flow control signal from the data flow control unit; store the first data signal based on the first valid signal; send a first storage feedback signal to the data flow control unit based on the external data reception status; and output a second data signal and a second valid signal to the data processing unit based on the first flow control signal from the data flow control unit. The data processing unit is configured to: receive the second data signal and the second valid signal from the receiving unit; perform data processing on the second data signal based on the second valid signal within the data processing unit; and convert the data processing result into a third data signal and a third valid signal, which are then transmitted to the sending unit. The transmitting unit is configured to: receive the third data signal and the third valid signal from the data processing unit, and a data read signal from an external source; store the third data signal based on the third valid signal; and output a fourth data signal and a fourth valid signal according to a clock cycle. The data flow control unit is configured to output the first flow control signal to the receiving unit based on the first storage feedback signal from the receiving unit, the fourth valid signal from the sending unit, and the data read signal from the outside.

2. The flow control module according to claim 1, characterized in that, The data flow control unit includes a counter, which outputs a valid read request signal to the receiving unit when the counter value is non-zero.

3. The flow control module according to claim 2, characterized in that, The counter is configured as follows: The counter is configured according to the clock cycle, and the value of the counter in the next cycle is configured to be the value of the counter in the current cycle minus the level value of the first flow control signal.

4. The flow control module according to claim 2, characterized in that, The counter is also configured to: When the fourth valid signal output by the transmitting unit and the data reading signal are both high, the counter is configured according to the clock cycle. The value of the counter in the next cycle is configured to be the value of the counter in the current cycle minus the level value of the first flow control signal, and then incremented by 1.

5. The flow control module according to claim 1, characterized in that, The sending unit is configured as follows: When the receiving unit is in an empty state, the first storage feedback signal outputs a high level.

6. The flow control module according to claim 2, characterized in that, The data flow control unit is configured as follows: When the first storage feedback signal is low and the read request signal is valid, the data flow control unit outputs the first flow control signal to control the receiving unit to output the stored data.

7. The flow control module according to claim 1, characterized in that, The capacity of the sending unit is at least the sum of the maximum delay between the receiving unit and the sending unit of the flow control module, the read delay of the receiving unit, and the write read delay of the sending unit.

8. A chip integrated circuit, characterized in that, include: The flow control module as described in any one of claims 1-7.

Images