Memory operation method, memory and memory system

Abstract

The invention provides a memory operation method, a memory and a memory system, and relates to the technical field of memories. The method comprises the following steps of: performing reading operation on a memory bank of the memory; obtaining error correction detection result information of the memory bank, the error correction detection result information being obtained based on an error correction operation on the memory bank, and the error correction operation being performed based on the reading operation; and judging whether at least one bit of the memory bank is subjected to error correction or not in the error correction operation according to the error correction detection result information of the memory bank, so that a controller coupled with the memory obtains a judgment result.

Description

Technical Field

[0001] The present disclosure relates to the field of memory technology, and in particular to a memory operation method, a memory, and a storage system. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a volatile memory. DRAM often has data errors during data storage. Error detection and correction technology can be used to ensure the correctness of data storage. For example, Error Correction Code (ECC) technology uses a certain length of data bits to add supervision bits to detect and correct erroneous data.

[0003] The information stored in the storage unit of the DRAM may be lost, so the storage information of the storage unit needs to be refreshed within a certain period of time. Summary of the invention

[0004] The purpose of the present disclosure is to provide a memory operation method, a memory and a storage system.

[0005] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by the practice of the present disclosure.

[0006] According to one aspect of the present disclosure, a memory operation method is provided, comprising: performing a read operation on a storage body of the memory; obtaining error correction detection result information of the storage body, the error correction detection result information being obtained based on an error correction operation on the storage body, the error correction operation being performed based on the read operation; judging whether error correction has been performed on at least one bit of the storage body in the error correction operation according to the error correction detection result information of the storage body, so that a controller coupled to the memory obtains a judgment result.

[0007] According to one embodiment of the present disclosure, the memory includes an on-chip error correction code module and an information storage module coupled thereto, the error correction operation is performed by the on-chip error correction code module and target information is obtained accordingly, the error correction detection result information is obtained according to the target information and stored in the information storage module; obtaining the error correction detection result information of the storage body includes: performing a read operation on the information storage module to obtain the error correction detection result information of the storage body.

[0008] According to an embodiment of the present disclosure, the target information is a plurality of bit codes characterizing whether the plurality of bits of the storage body have been error corrected in the error correction operation; the error correction detection result information is a one-bit code obtained by performing an XOR operation on the plurality of bit codes.

[0009] According to an embodiment of the present disclosure, the information storage module includes multiple storage bits, and the error correction detection result information is stored in the storage bits corresponding to the storage body in the information storage module; performing a read operation on the information storage module to obtain the error correction detection result information of the storage body includes: reading multiple storage bits of the information storage module to obtain the error correction detection result information of the storage body.

[0010] According to an embodiment of the present disclosure, it further includes: performing an operation of writing target data to the storage body; performing a reading operation on the storage body of the memory, including: performing an operation of reading the target data from the storage body.

[0011] According to an embodiment of the present disclosure, in response to determining, based on error correction detection result information of the storage body, that error correction is performed on at least one bit of the storage body in the error correction operation, the storage body is rewritten with the target data.

[0012] According to an embodiment of the present disclosure, a self-refresh operation is performed on the memory, wherein erroneous data is stored in at least one bit of the memory bank during the self-refresh operation.

[0013] According to another aspect of the present disclosure, a memory is provided, comprising: a memory cell array, comprising at least one memory body; a peripheral circuit coupled to the memory cell array, the peripheral circuit comprising an on-chip error correction code module and an information storage module coupled thereto, wherein: the on-chip error correction code module is configured to perform an error correction operation based on a read operation on the memory body to obtain error correction detection result information of the memory body; the information storage module is configured to receive and store the error correction detection result information, so that a controller coupled to the memory determines whether error correction is performed on at least one bit of the memory body in the error correction operation according to the error correction detection result information.

[0014] According to one embodiment of the present disclosure, the on-chip error correction code module is also configured to obtain target information of the error correction operation, and the target information is a plurality of bit codes that characterize whether multiple bits of the storage body have been error corrected in the error correction operation; the peripheral circuit also includes an XOR operation module coupled between the on-chip error correction code module and the information storage module, and is configured to perform an XOR operation on the multiple bit codes to obtain a one-bit code to obtain the error correction detection result information.

[0015] According to one embodiment of the present disclosure, the peripheral circuit includes a control logic unit coupled to the on-chip error correction code module, the control logic unit includes the information storage module, and the control logic unit is configured to control reading the information storage module to obtain the error correction detection result information, and send the error correction detection result information to the controller.

[0016] According to one embodiment of the present disclosure, the information storage module includes multiple storage bits, which are configured to store error correction detection result information of the corresponding storage body; the control logic unit is also configured to control the reading of the multiple storage bits of the information storage module to obtain the error correction detection result information of the storage body.

[0017] According to an embodiment of the present disclosure, the control logic unit is further configured to write target data to the storage body; the control logic unit is further configured to read the target data from the storage body.

[0018] According to one embodiment of the present disclosure, the control logic unit is also configured to rewrite the target data on the storage body in response to a write command sent by the controller, and the write command is sent by the controller in response to determining that error correction was performed on at least one bit of the storage body in the error correction operation based on error correction detection result information of the storage body.

[0019] According to an embodiment of the present disclosure, the control logic unit is further configured to perform a self-refresh operation on the memory, wherein erroneous data is stored in at least one bit of the memory bank during the self-refresh operation.

[0020] According to another aspect of the present disclosure, a storage system is provided, comprising a memory and a controller coupled to the memory, the controller being configured to: send a read command to the memory to perform a read operation on a storage body of the memory; receive error correction detection result information of the storage body sent by the memory, the error correction detection result information being obtained based on an error correction operation on the storage body, the error correction operation being performed based on the read operation; and determine whether error correction has been performed on at least one bit of the storage body in the error correction operation according to the error correction detection result information of the storage body.

[0021] According to one embodiment of the present disclosure, the memory includes an on-chip error correction code module and an information storage module coupled thereto, the error correction operation is performed by the on-chip error correction code module and target information is obtained accordingly, the error correction detection result information is obtained according to the target information and stored in the information storage module; the controller is also configured to send a storage information read command to the memory to obtain the error correction detection result information of the storage body from the information storage module.

[0022] According to one embodiment of the present disclosure, the controller is also configured to send a first write command to the memory to write target data to the storage body; the controller is also configured to send the read command to the memory to read the target data from the storage body of the memory.

[0023] According to one embodiment of the present disclosure, the controller is also configured to send a second write command to the memory to rewrite target data to the storage body in response to determining that error correction has been performed on at least one bit of the storage body during the error correction operation based on error correction detection result information of the storage body.

[0024] According to an embodiment of the present disclosure, the controller is further configured to send a self-refresh command to the memory to perform a self-refresh operation on the memory, wherein erroneous data is stored in at least one bit of the memory bank during the self-refresh operation.

[0025] It is to be understood that the foregoing general description and the following detailed description are exemplary only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other objects, features and advantages of the present disclosure will become more apparent by describing in detail example embodiments thereof with reference to the attached drawings.

[0027] Figure 1A A block diagram of an exemplary system 100A having a memory according to an embodiment of the present disclosure is shown.

[0028] Figure 1B FIG. 1 is a block diagram of another exemplary system 100B having a memory according to an embodiment of the present disclosure.

[0029] Figure 2 A schematic circuit diagram of an exemplary memory 200 including peripheral circuits is shown according to an exemplary embodiment.

[0030] Figure 3 A schematic diagram of a peripheral circuit provided in an embodiment of the present disclosure.

[0031] Figure 4 It is a schematic block diagram showing a chip arrangement according to an embodiment of the present disclosure.

[0032] Figure 5 according to Figure 4 An example is shown in which the information registering module stores error correction detection result information of a plurality of memory banks in some embodiments.

[0033] Figure 6 A schematic diagram showing a flow chart of an on-chip error correction code module of a memory bank outputting corrected data of a read operation of the memory bank in some embodiments.

[0034] Figure 7 according to Figure 6 A schematic diagram of a process for obtaining error correction detection result information of a storage body in an embodiment of the present disclosure is shown.

[0035] Figure 8 The figure is a flow chart showing a memory operation method according to an exemplary embodiment.

[0036] Fig. 9 is a flowchart showing another memory operation method according to an exemplary embodiment.

[0037] Fig.10 according to Fig. 9 The command execution flow of the memory operation method provided by the embodiments of the present disclosure is shown in some embodiments.

[0038] Fig.11 Shows Fig.10 The timing diagram of the command execution flow in . DETAILED DESCRIPTION

[0039] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the disclosure will be more comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The accompanying drawings are only schematic illustrations of the disclosure and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and thus their repeated description will be omitted.

[0040] In addition, the described features, structures or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or other methods, devices, steps, etc. may be adopted. In other cases, well-known structures, methods, devices, implementations or operations are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0041] In addition, the terms "first", "second", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. The symbol " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0042] In this disclosure, unless otherwise clearly specified and limited, terms such as "connection" should be understood in a broad sense, for example, it can be an electrical connection or can communicate with each other; it can be directly connected or indirectly connected through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0043] Figure 1AA block diagram of an exemplary system 100A with a memory according to an embodiment of the present disclosure is shown. System 100A may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. As shown in FIG. 1 , system 100B may include a host 108 and a memory system 102 having one or more memories 104 and a memory controller 106. Host 108 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. In some embodiments, host 108 may be configured to send data to memory 104 or receive data from memory 104. In some embodiments, the host may be a user logic unit or a user interface, so that a user may issue instructions to the host and transmit instructions to a storage device or a storage array.

[0044] The memory 104 may be any storage device in the embodiments of the present disclosure. As disclosed in detail below, according to some embodiments, the memory 104 such as a PCRAM, a DRAM, or a NAND flash memory device may include a clock input, a command bus, an address bus, a data input, a plurality of storage bodies, a plurality of interface modules, and a plurality of FSM modules. In the embodiments of the present disclosure, the memory 104 is described as a DRAM, but is not limited thereto.

[0045] According to some embodiments, the memory controller 106 is coupled to the memory 104 and the host 108 and is configured to control the memory 104. The memory controller 106 can manage the data stored in the memory 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices (e.g., personal computers, digital cameras, mobile phones, etc.). In other embodiments, the memory controller 106 is designed to operate in a high duty cycle environment, such as an SSD or an embedded multimedia card (eMMC) used as a data storage device for mobile devices such as smartphones, tablets, laptops, etc., and an enterprise storage array. The memory controller 106 can be configured to control the operation of the memory 104, such as write, read, and other operations. The memory controller 106 may also be configured to manage various functions related to data stored or to be stored in the memory 104, for example, in some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) on data read from or written to the memory 104. The memory controller 106 may also perform any other suitable functions, for example, formatting the memory 104. The memory controller 106 may communicate with an external device (e.g., the host 108) according to a specific communication protocol. For example, the memory controller 106 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer mini interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0046] Figure 1B FIG. 1 is a block diagram of another exemplary system 100B having a memory according to an embodiment of the present disclosure. Figure 1B As shown, the system 100B may include a host 108 and a plurality of memories ( Figure 1B 100B) and a memory system 102 of a memory controller 106. Exemplary implementations of the host 108, the memory controller 106, and the memory system 102 in the system 100B may refer to Figure 1AIn the system 100B, the memory 1062 may be a random access memory (RAM) in the memory controller 106, which is used to directly exchange data with the host 108, so that the memory controller 106 controls the memory to execute instructions transmitted by the host 108 to achieve corresponding functions.

[0047] Figure 2 A schematic circuit diagram of an exemplary memory 200 including a peripheral circuit is shown according to an exemplary embodiment. The memory 200 may be Figure 1A Memory 104 in, or Figure 1B 1062 in an example. The memory 200 may include a memory cell array 201 and a peripheral circuit 202 coupled to the memory cell array 201. The memory cell array 201 may include one or more memory banks 204. Each memory bank 204 includes a word line 214, a bit line 216, and a cross-point device 208 formed between the word line 214 and the bit line 216. In some embodiments, each cross-point device 208 may include a DRAM cell of a pair of transistors and capacitors. In order to operate each memory bank 204 of the memory cell array 201, a word line voltage (V WL ), and a bit line voltage (V BL ).

[0048] Figure 3 A schematic diagram of a peripheral circuit provided in an embodiment of the present disclosure. Figure 3 An exemplary memory 300 (eg, corresponding to Figure 1A 104 or Figure 1B 1062), the exemplary memory 300 includes a memory cell array 301 (eg, corresponding to Figure 2 201) and peripheral circuit 202. Figure 3 As shown, the peripheral circuit 202 may include a row decoder / word line (WL) driver 302, a page buffer / sense amplifier 304, a column decoder / bit line (BL) driver 306, an address register 308, a control logic unit 310, and an input / output (I / O) circuit 312, etc. It should be understood that in some embodiments, the peripheral circuit 202 may also include Figure 4 Additional peripheral circuits not shown.

[0049] The row decoder / word line (WL) driver 302 may be configured to be controlled by the control logic unit 310 and the selected bank 204 and the word line 214 of the selected bank 204 of the memory cell array 301. The row decoder / word line driver 302 may also be configured to drive the selected word line 214.

[0050] The page buffer / sense amplifier 304 may be configured to read data from the memory cell array 301 and program (write) data to the memory cell array 301 according to a control signal from the control logic unit 310. In some embodiments, the page buffer / sense amplifier 304 may store a page of programming data (write data) to be programmed into the memory cell array 301. In other embodiments, the page buffer / sense amplifier 304 may perform a program verification operation to ensure that the data has been correctly programmed into the cross-point device 208 coupled to the selected word line 214. In yet other embodiments, the page buffer / sense amplifier 304 may also sense a low-power signal from the bit line 216 (which represents a data bit stored in the cross-point device 208) in a read operation and amplify the small voltage swing to a recognizable logic level.

[0051] The column decoder / bit line (BL) driver 306 may be configured to be controlled by the control logic unit 310 and select one or more cross point devices 208. The input / output (I / O) circuit 312 may be coupled to the page buffer / sense amplifier 304 and / or the column decoder / bit line driver 306 and may be configured to receive and receive data from the bus ( Figure 3 The data input by the memory cell array 301 is directed (routed) to a desired memory cell region (e.g., Figure 3 One or more memory banks 204 among memory bank 0, memory bank 1 ... memory bank 15), and direct (route) data output from a desired memory cell area to a bus.

[0052] The peripheral circuit 202 may further include an on-chip error correction code (ECC) module 303 coupled to the memory cell array 301. The on-chip ECC module 303 may be configured to perform an error correction operation when a (e.g., one-bit) error occurs during a read operation of the corresponding memory bank 204, so as to store correct data on the corresponding memory bank 204. In some embodiments, one on-chip ECC module may be provided for each memory bank. Figure 4 This situation is exemplarily shown, where 16 memory banks correspond one to one with 16 on-chip ECC modules. In other embodiments, multiple memory banks may share one on-chip ECC module, for example, 2, 3 or 4 memory banks may be grouped as a group and share one on-chip ECC module.

[0053] The control logic unit 310 may include a mode register 305 coupled to the on-chip ECC module 303. The mode register 305 may be configured to store the error correction detection result information sent by the on-chip ECC module 303 as an information storage module, and the error correction detection result information may be obtained by the on-chip ECC module 303 according to the target information of performing the error correction operation. In some embodiments, the target information may be a plurality of bit codes representing whether the plurality of bits of the storage body have been error corrected in the error correction operation, and the error correction detection result information may be a one-bit code obtained by performing an XOR operation on the plurality of bit codes. The memory controller 106 may obtain the error correction detection result information by reading the mode register 305, thereby knowing whether the at least one bit of the storage body has been error corrected in the error correction operation.

[0054] According to the memory provided by the embodiment of the present disclosure, the memory controller can obtain the error correction detection result of the on-chip ECC module through the information storage module, so that the memory controller can know the defect location in the storage cell array and perform corresponding operations, thereby improving the reliability of the memory and the storage system.

[0055] Figure 4 It is a schematic block diagram showing a chip arrangement according to an embodiment of the present disclosure. Figure 4 Taking a memory cell array including 16 memory banks as an example, the arrangement of the corresponding on-chip ECC module and mode register on the chip is shown. Figure 4 As shown, 16 memory banks BK0, BK1, BK2...BK15 (i.e. Figure 3 In the memory bank 0, memory bank 1, memory bank 2 ... memory bank 15), each corresponding to an on-chip ECC module 303 is set, and the output of each on-chip ECC module 303 is transmitted to the mode register (Mode Register, MR) 305 after passing through the XOR operation module 402. The XOR operation module 402 may include at least one XOR gate.

[0056] According to the memory provided by the embodiment of the present disclosure, by respectively setting an on-chip ECC module for each storage body of the storage cell array, and transmitting the output of each on-chip ECC module to the information storage module through the XOR operation module, the controller can obtain from the information storage module whether a one-bit error occurs in the reading operation of each storage body of the storage cell array, so that corresponding operations can be performed on the storage body where the one-bit error occurs.

[0057] In some embodiments, the MR may include multiple register bits, and a one-bit code obtained by performing an XOR operation on the target information output by the on-chip ECC module 303 corresponding to each storage body may be stored in a corresponding register bit in one or more MRs. Figure 5 according to Figure 4 An example is shown in which the information storage module stores error correction detection result information of multiple storage banks in some embodiments. Figure 4 and Figure 5 Still taking the example that each of the 16 memory banks BK0, BK1, BK2, ... BK15 corresponds to an on-chip ECC module 303, the one-bit code obtained by performing an XOR operation on the target information output by the on-chip ECC module 303 of the 16 memory banks has a total of 16 bits. The 16-bit data can be represented as ecc_det<15:0>, Figure 5 In the example of ecc_det<15:0>, [0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,1,0], if an MR has 8 data bits, then MR 305 may include MR1 and MR2, and MR1 and MR2 each store 8 bits of data, for example Figure 5 Among them, MR1 stores the one-bit code [0,0,0,1,0,0,0,0] of BK0, BK1...BK7, and MR2 stores the one-bit code [0,0,0,0,0,0,1,0] of BK8, BK9...BK15.

[0058] Figure 6 A schematic diagram showing a flow chart of an on-chip error correction code module of a memory bank outputting corrected data of a read operation of the memory bank in some embodiments. Figure 6 Shows Figure 4 The ECC module 303 outputs the process of reading the corrected data of a data column (e.g., a BL of the storage body 204) of a data row (row) (e.g., a WL of the storage body 204) of its corresponding storage body. In the embodiment of the present disclosure, a data column is described as 128 bits, but the present invention is not limited to this.

[0059] like Figure 6 As shown, the on-chip ECC module 303 may include a decoding generation module 3032 and an error coding module 3034. Figure 4, the 128-bit data lbdl<127:0> and ECC supervision bit data (8 bits are used as an example in the disclosed embodiment, but not limited to this) lbecc<7:0> of the current data column of the selected WL read from the storage body BK1 are transmitted to the decoding generation module 3032 in the ECC module 303 for decoding, and 8-bit data lbdl_ecc<7:0> for representing the association between the 8-bit ECC supervision bit data and the 128-bit read data is generated. The lbdl_ecc<7:0> is then encoded by the error coding module 3034 to generate data gda_ecc_ecd<127:0> corresponding to the 128-bit data lbdl<127:0> one by one, representing whether each bit of data has been error corrected by the ECC supervision bit data. In some embodiments, it can be configured as follows: if the data of the corresponding bit is not error-corrected, the corresponding data in gda_ecc_ecd<127:0> is 0; if the data of the corresponding bit is error-corrected, the corresponding data in gda_ecc_ecd<127:0> is 1. Taking the error correction of one bit of the storage body as an example, there is only one data in gda_ecc_ecd<127:0> that is 1, and the rest are 0. Then the read 128-bit data lbdl<127:0> and gda_ecc_ecd<127:0> are XORed through XOR gate 602 to obtain the correct data gdal<127:0> of the current data column of the selected WL to be read after correction.

[0060] According to the on-chip ECC module provided by the embodiment of the present disclosure, the read data and ECC supervision bit data are encoded through the decoding generation module to generate data representing the association between the ECC supervision bit data and the read data, and then the data is encoded through the error coding module to generate data representing whether each bit of data has been error-corrected as recorded by the ECC supervision bit data, and then the data is XOR-ed with the read data to obtain the correct data after correction, so that automatic error correction of the read data can be achieved.

[0061] Figure 7 according to Figure 6 FIG. 1 is a schematic diagram showing a process of obtaining error correction detection result information of a storage body in an embodiment of the present disclosure. Figure 7 As shown, Figure 6 For example, refer to the read data error correction process Figure 6, the data gda_ecc_ecd<127:0> which indicates whether each bit of data has been error-corrected through the ECC supervision bit data can be used as the target information, and it can be passed through the XOR operation module 402. For example, the 128-bit data in gda_ecc_ecd<127:0> can be XORed with the next bit of data through the XOR gate in the XOR operation module 402 in sequence. Then, when only one of the data in gda_ecc_ecd<127:0> is 1 and the rest are 0, the one-bit data ecc_det output by the XOR operation module 402 for indicating whether a one-bit error has occurred in BK1 <0> is 1, indicating that a bit error occurs in BK1.

[0062] According to the method provided by the embodiment of the present disclosure, by using the on-chip ECC module to perform an XOR operation on the data in the error correction process of reading data of the corresponding storage body, the data used to characterize whether each bit of data has been recorded through the ECC supervision bit data for error correction is operated through the XOR operation module, and a single bit of data used to characterize whether a single-bit error has occurred in the storage body is obtained, so that it is convenient to know whether a single-bit error has occurred in the storage body.

[0063] Figure 8 FIG. 1 is a flow chart of a memory operation method according to an exemplary embodiment. Figure 8 The method shown can be applied, for example, to Figure 2 The method 80 provided in the embodiment of the present disclosure may be executed by a memory controller, or may be executed by a control logic unit in a peripheral circuit of the memory. In the embodiment of the present disclosure, the method 80 is described by taking the memory controller as an example, but is not limited thereto.

[0064] refer to Figure 8 , method 80 may include the following steps S802 to S806.

[0065] In step S802, a read operation is performed on a storage bank of the memory.

[0066] In some embodiments, the read operation performed on a memory bank of the memory may be an operation of reading target data, and the target data may be, for example, data of a selected data column of a selected WL of the target memory bank. Figure 4 This is an example of performing a read operation on the memory bank BK1 , in which the target data to be read is 128 bits of data in a data column of the selected WL.

[0067] In some embodiments, before performing a read operation on a memory bank of the memory, a self-refresh operation may be performed on the memory. The self-refresh operation may be performed at a predetermined frequency. The self-refresh operation includes read and rewrite operations, and activation, precharge, and other operations performed before and after these operations may cause erroneous data to be written into the memory, such as a one-bit error.

[0068] In step S804, error correction detection result information of the storage bank is obtained, the error correction detection result information is obtained based on an error correction operation on the storage bank, and the error correction operation is performed based on a read operation.

[0069] In some embodiments, after performing a read operation on a memory bank of the memory, the on-chip ECC module of the memory may automatically perform an error correction operation on the corresponding memory bank. The error correction operation of the on-chip ECC module may correct errors in the read data and output correct read data. The implementation of the on-chip ECC module in some embodiments may refer to Figure 6 .

[0070] In some embodiments, the on-chip ECC module may generate target information for characterizing whether each bit of the target data has been error-corrected in the error correction operation during the error correction operation. Error correction detection result information for characterizing whether at least one bit of the target data has been error-corrected in the error correction operation may be obtained according to the target information. An exemplary implementation of this in some embodiments may refer to Figure 7 .

[0071] In some embodiments, the error correction detection result information of the storage body is stored in the corresponding information storage module, and the information storage module can be, for example, a mode register. A mode register read (MRR) command can be executed to obtain the error correction detection result information from the corresponding mode register. For example, the exemplary implementation can refer to Figure 4 and Figure 5 .

[0072] In step S806, it is determined whether error correction is performed on at least one bit of the memory bank in the error correction operation according to the error correction detection result information of the memory bank, so that a controller coupled to the memory obtains the determination result.

[0073] In some embodiments, the target information may be a plurality of bit codes representing whether a plurality of bits of a storage body have been error corrected in an error correction operation, and the error correction detection result information may be a one-bit code obtained by performing an XOR operation on the plurality of bit codes. It may then be determined whether a bit of the storage body has been error corrected in the error correction operation based on the one-bit code.

[0074] In the case where the method provided by the embodiment of the present disclosure is executed by a memory controller, the memory controller can directly obtain the judgment result after judging whether error correction has been performed on at least one bit of the storage body in the error correction operation based on the error correction detection result information of the storage body; in the case where the method provided by the embodiment of the present disclosure is executed by the control logic unit of the peripheral circuit, the control logic unit can send the judgment result to the memory controller after judging whether error correction has been performed on at least one bit of the storage body in the error correction operation based on the error correction detection result information of the storage body.

[0075] In some embodiments, after the memory controller obtains the result of determining that error correction is performed on at least one bit of the memory bank in the error correction operation, it may execute the re-write command.

[0076] According to the memory operation method provided by the embodiment of the present disclosure, after performing a read operation on a storage body of the memory, error correction detection result information obtained based on an error correction operation performed on the read operation of the storage body is obtained, and whether error correction has been performed on at least one bit of the storage body in the error correction operation is judged according to the error correction detection result information of the storage body, so that a controller coupled to the memory obtains the judgment result, thereby enabling the memory controller to know the defect location in the storage cell array and perform corresponding operations, thereby avoiding the accumulation of erroneous data in the memory and improving the reliability of the memory and the storage system.

[0077] Fig. 9 is a flow chart showing another memory operation method according to an exemplary embodiment. Fig. 9 , the method 90 provided in the embodiment of the present disclosure may include the following steps S902 to S910. Fig. 9 and Figure 8 The association lies in that steps S906 to S910 are exemplary implementations of steps S802 to S806, and steps S902 and S904 are exemplary implementations of operations performed on the memory before step S802.

[0078] In step S902, an operation of writing target data into the storage body is performed.

[0079] In some embodiments, an activation operation may be performed before the write operation, for example, an instruction that triggers a data write operation to the memory may be executed.

[0080] In some embodiments, the target data may be data of a selected data column of a selected WL of a target storage body, and the row where the selected WL is located will be opened during a write operation. A precharge operation may be performed after writing the target data, and the row opened during the write operation is closed during the precharge operation.

[0081] In step S904, a self-refresh operation is performed on the memory, wherein erroneous data is stored in at least one bit of the memory bank during the self-refresh operation.

[0082] In some embodiments, the self-refresh operation includes read and rewrite operations, and activation, precharge and other operations may be performed before and after these operations. The operation of the page buffer / sense amplifier during the activation, precharge and other processes may cause a bit of erroneous data to be written into the memory.

[0083] In step S906, an operation of reading target data from the storage body is performed.

[0084] In some embodiments, a read command may be executed to read target data previously written in a corresponding storage body.

[0085] In step S908, multiple register bits of the information register module are read to obtain error correction detection result information of the storage body, the error correction detection result information is obtained based on an error correction operation on the storage body, and the error correction operation is performed based on an operation of reading target data.

[0086] In some embodiments, the information storage module may include one or more mode registers, and the mode register may include multiple register bits. The error correction detection result information obtained according to the target information output by the on-chip ECC module corresponding to each storage body may be stored in the corresponding register bits in the one or more mode registers. For example, the exemplary implementation can refer to Figure 4 and Figure 5 .

[0087] In step S910, in response to determining, according to the error correction detection result information of the storage bank, that error correction is performed on at least one bit of the storage bank in the error correction operation, an operation of rewriting target data is performed on the storage bank.

[0088] In some embodiments, after determining that error correction is performed on a bit of the memory bank in an error correction operation according to error correction detection result information of the memory bank, the memory controller may execute a command to rewrite target data on the memory bank according to the obtained determination result.

[0089] In other embodiments, the control logic unit may send the determination result to the memory controller after determining whether error correction has been performed on at least one bit of the memory bank in the error correction operation according to the error correction detection result information of the memory bank. If the memory controller determines that the determination result is that error correction has been performed on one bit of the memory bank in the error correction operation, the memory controller executes a command to rewrite the target data to the memory bank.

[0090] According to the memory operation method provided by the embodiment of the present disclosure, in the case where a one-bit error is introduced by a self-refresh operation between a write operation and a read operation, the memory controller can be informed of whether a one-bit error has occurred in the read operation of each storage body of the memory cell array by reading the error correction detection result information stored on the corresponding bit position in the information register module, so that the memory controller can re-write the storage body where the one-bit error has occurred.

[0091] Fig.10 according to Fig. 9 FIG. 2 shows a command execution flow of the memory operation method provided by the embodiment of the present disclosure in some embodiments. Fig. 9 The process shown may include the following steps S1002 to S1020.

[0092] Step S1002, executing the activation command.

[0093] In some embodiments, the activation command may include two sub-commands ACT1 and ACT2. The completion of both commands ACT1 and ACT2 indicates the completion of the activation operation, ie, opening the row address of the storage body corresponding to the target data.

[0094] Step S1004, executing a write command (WR).

[0095] In some embodiments, after a column address strobe command (CAS) corresponding to the target data is executed, a command to write the target data is executed.

[0096] Step S1006, executing a precharge command (PRE).

[0097] Step S1008 , executing a self-refresh command (Self_ref) of the memory.

[0098] Step S1010, executing the activation command.

[0099] In some embodiments, the activation command may include two sub-commands ACT1 and ACT2. The completion of both commands ACT1 and ACT2 indicates the completion of the activation operation, ie, opening the row address of the storage body corresponding to the target data.

[0100] Step S1012, execute the read command.

[0101] In some embodiments, after a column address strobe command (CAS) corresponding to the target data is executed, a command to read the target data is executed.

[0102] Step S1014, executing a command to read the mode register (MRR).

[0103] In some embodiments, after executing a column address strobe command (CAS) corresponding to the target data, a command of a mode register coupled to an on-chip ECC module corresponding to the memory bank where the target data is located is executed.

[0104] Step S1016, determining whether the data read from the mode register includes "1".

[0105] In step S1018, if the data read from the mode register includes "1", it can be determined that a one-bit error has occurred in the corresponding storage bank, and the process can return to step S1004 to execute a command to rewrite the target data.

[0106] In step S1020, if the data read from the mode register does not include "1", it can be determined that the corresponding memory bank does not have a one-bit error, and the process ends.

[0107] Fig.11 Shows Fig.10 In some embodiments, the command execution process may be responsive to Fig.11 The signal execution of the timing diagram Fig.10 Describes the memory operation flow. Fig.11 2 shows the command (CMD) executed according to the clock pulse signal io_ck_t in the time periods t1, t2, ..., t7 in chronological order, as well as the corresponding memory input / output data io_dq and the data mon_det stored in the mode register monitored by the memory controller. Fig.11 In the description, io_dq and mon_det are both 16 bits representing hexadecimal data as an example, but the present invention is not limited to this.

[0108] Reference Fig.10 and Fig.11 , in the first time period t1, the memory can respond to the CAS command and the WR command to perform an operation of writing the target data in BK0 (S1004). In the second time period t2, the memory inputs the target data 16'h1234. In the third time period t3, the memory can respond to the Self_ref command to perform a self-refresh operation (S1008). In the fourth time period t4, the memory can respond to the ACT1 and ACT2 commands to perform an activation operation (S1010). In the fifth time period t5, the memory can respond to the CAS command and the RD command to perform an operation of reading the target data in BK0 (S1012). During t1 to t5, the data stored in the mode register corresponding to BK0 monitored by the memory controller is 16'h0.

[0109] In the sixth time period t6, the memory can respond to the CAS command and the MRR command to perform an operation of reading the data stored in the mode register corresponding to BK0 (S1014). In the seventh time period t7, the memory outputs the data 16'h1 of the read mode register. The memory controller monitors that the data stored in the mode register corresponding to BK0 is updated to 16'h1 during the period from t6 to t7. If the data of the register bit corresponding to BK0 in 16'h1 is "1", the memory controller can determine that a 1-bit error has occurred in the read operation of t5.

[0110] According to the method provided in the embodiment of the present disclosure, after a read operation is performed on a storage body of the memory, error correction detection result information obtained by an on-chip ECC module based on an error correction operation performed on the read operation of the storage body is obtained through the information storage module, and it is determined whether error correction has been performed on at least one bit of the storage body in the error correction operation based on the error correction detection result information of the storage body. By only adding an information storage module, an XOR operation module and a control command for reading the information registration module, it is possible to implement a memory controller that can know the defect location in the storage cell array and perform corresponding operations.

[0111] The exemplary embodiments of the present disclosure are specifically shown and described above. It should be understood that the present disclosure is not limited to the detailed structures, configurations or implementations described herein; on the contrary, the present disclosure is intended to cover various modifications and equivalent configurations included in the spirit and scope of the appended claims.

Claims

1. A memory operation method, characterized in that: include: Performing a read operation on a storage body of the memory; Acquire error correction detection result information of the storage body, wherein the error correction detection result information is obtained based on an error correction operation on the storage body, wherein the error correction operation is performed based on the read operation; It is determined whether error correction is performed on at least one bit of the memory bank in the error correction operation according to the error correction detection result information of the memory bank, so that a controller coupled to the memory obtains the determination result.

2. The method according to claim 1, characterized in that The memory includes an on-chip error correction code module and an information storage module coupled thereto, the error correction operation is performed by the on-chip error correction code module and target information is obtained accordingly, and the error correction detection result information is obtained according to the target information and stored in the information storage module; Acquiring error correction detection result information of the storage bank, including: A read operation is performed on the information storage module to obtain error correction detection result information of the storage body.

3. The method according to claim 1 or 2, characterized in that: The target information is a plurality of bit codes representing whether the plurality of bits of the storage body have been error corrected in the error correction operation; The error correction detection result information is a one-bit code obtained by performing an XOR operation on the multiple bit codes.

4. The method according to claim 2, characterized in that: The information storage module includes a plurality of storage bits, and the error correction detection result information is stored in the storage bits corresponding to the storage body in the information storage module; Performing a read operation on the information storage module to obtain error correction detection result information of the storage body includes: A plurality of register bits of the information register module are read to obtain error correction detection result information of the storage body.

5. The method according to any one of claims 1 to 4, characterized in that: Also includes: Writing target data into the storage body; Performing a read operation on a storage body of the memory includes: An operation of reading the target data is performed on the storage body.

6. The method according to claim 5, characterized in that Also includes: In response to determining, according to the error correction detection result information of the storage bank, that error correction is performed on at least one bit of the storage bank in the error correction operation, an operation of rewriting the target data is performed on the storage bank.

7. The method according to claim 6, characterized in that Also includes: A self-refresh operation is performed on the memory, wherein erroneous data is stored in at least one bit of the memory bank during the self-refresh operation.

8. A memory, characterized in that: include: A memory cell array including at least one memory bank; A peripheral circuit coupled to the memory cell array, the peripheral circuit comprising an on-chip error correction code module and an information storage module coupled thereto, wherein: The on-chip error correction code module is configured to perform an error correction operation based on a read operation on the memory bank to obtain error correction detection result information of the memory bank; The information storage module is configured to receive and store the error correction detection result information, so that a controller coupled to the memory determines whether error correction is performed on at least one bit of the storage body in the error correction operation according to the error correction detection result information.

9. The memory according to claim 8, characterized in that: The on-chip error correction code module is further configured to obtain target information of the error correction operation, wherein the target information is a plurality of bit codes representing whether the plurality of bits of the storage body are error corrected in the error correction operation; The peripheral circuit also includes an XOR operation module coupled between the on-chip error correction code module and the information storage module, and is configured to perform an XOR operation on the multiple bit codes to obtain a one-bit code to obtain the error correction detection result information.

10. The memory according to claim 8 or 9, characterized in that: The peripheral circuit includes a control logic unit coupled to the on-chip error correction code module, the control logic unit includes the information storage module, and the control logic unit is configured to control reading of the information storage module to obtain the error correction detection result information and send the error correction detection result information to the controller.

11. The memory according to claim 10, characterized in that: The information storage module includes a plurality of storage bits, and the storage bits are configured to store error correction detection result information of corresponding storage bodies; The control logic unit is further configured to control reading of a plurality of register bits of the information register module to obtain error correction detection result information of the storage body.

12. The memory according to any one of claims 8 to 11, characterized in that: The control logic unit is further configured to write target data into the storage body; The control logic unit is further configured to perform an operation of reading the target data from the storage body.

13. The memory according to claim 12, characterized in that: The control logic unit is also configured to rewrite the target data to the storage body in response to a write command sent by the controller, wherein the write command is sent by the controller in response to determining that error correction has been performed on at least one bit of the storage body in the error correction operation based on error correction detection result information of the storage body.

14. The memory according to claim 13, characterized in that: The control logic unit is further configured to perform a self-refresh operation on the memory, wherein erroneous data is stored in at least one bit of the memory bank during the self-refresh operation.

15. A storage system, characterized in that: The invention comprises a memory and a controller coupled to the memory, wherein the controller is configured to: Sending a read command to the memory to perform a read operation on a storage body of the memory; receiving error correction detection result information of the storage body sent by the memory, wherein the error correction detection result information is obtained based on an error correction operation on the storage body, and the error correction operation is performed based on the read operation; It is determined whether error correction is performed on at least one bit of the memory bank in the error correction operation according to the error correction detection result information of the memory bank.

16. The storage system according to claim 15, characterized in that: The memory includes an on-chip error correction code module and an information storage module coupled thereto, the error correction operation is performed by the on-chip error correction code module and target information is obtained accordingly, and the error correction detection result information is obtained according to the target information and stored in the information storage module; The controller is further configured to send a registered information read command to the memory to obtain error correction detection result information of the storage body from the information registration module.

17. The storage system according to claim 15 or 16, characterized in that: The controller is further configured to send a first write command to the memory to write target data to the storage body; The controller is further configured to send the read command to the memory to perform an operation of reading the target data on a storage bank of the memory.

18. The storage system according to claim 17, characterized in that: The controller is further configured to send a second write command to the memory to rewrite target data to the memory in response to determining, based on error correction detection result information of the memory, that error correction is performed on at least one bit of the memory in the error correction operation.

19. The storage system according to claim 17, characterized in that: The controller is further configured to send a self-refresh command to the memory to perform a self-refresh operation on the memory, wherein erroneous data is stored in at least one bit of the memory bank during the self-refresh operation.

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