Bus training for interconnected memory dies

Abstract

The invention relates to bus training of interconnected memory dies. Test data associated with a command bus training CBT can be individually received at the interconnected memory die. Feedback data output from the plurality of interconnected memory dies in response to the test data can be randomly combined such that the combined feedback data is returned as if the feedback data was sent from a single memory die. This provides a flexible and scalable architecture that can accommodate a range of memory densities (e.g., several interconnected memory dies).

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor memory and methods, and more particularly to apparatus, systems, and methods associated with bus training of interconnected memory dies. Background Art

[0002] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic systems. There are many different types of memory, including volatile memory and non-volatile memory. Volatile memory may require power to maintain its data (e.g., host data, error data, etc.) and includes random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), and thyristor random access memory (TRAM), etc. Non-volatile memory can provide persistent data by retaining stored data when not powered and can include NAND flash memory, NOR flash memory, ferroelectric random access memory (FeRAM), and resistance variable memory, such as phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), such as spin torque transfer random access memory (STT RAM), etc.

[0003] A memory device may be coupled to a host (e.g., a host computing device) to store data, commands, and / or instructions for use by the host when a computer or electronic system is operating. For example, during operation of a computing or other electronic system, data, commands, and / or instructions may be transferred between the host and the memory device(s). A controller may be used to manage the transfer of data, commands, and / or instructions between the host and the memory device. Summary of the invention

[0004] One aspect of the present disclosure discloses a method for bus training of interconnected memory dies, comprising: in response to receiving a bus training command and test data associated with the bus training command and having a first number of bits, generating a first number of random pointer bits having the first number of bits; in response to determining that the first number of random pointer bits has a second number of bits with a first binary value, generating combined feedback data based on the first number of random pointer bits by randomly combining first feedback data corresponding to the first test data received at a first memory die and second feedback data corresponding to the first test data received at a second memory die to generate combined feedback data, the combined feedback data comprising: a portion of the first feedback data having the second number of bits; and a portion of the second feedback data having a third number of bits; and sending the feedback data on an external data bus coupled to the first memory die or the second memory die as a response to the bus training command.

[0005] Another aspect of the present disclosure discloses an apparatus for bus training of interconnected memory dies, comprising: a first memory die coupled to a substrate via an external data bus and a command / address (CA) bus; and a second memory die coupled to the CA bus and internally coupled to the first memory die; the first memory die being configured to: in response to receiving a first bus training command including first test data having a first number of bits, generate a first number of random pointer bits having the first number of bits; in response to the first number of random pointer bits being determined to have a second number of bits with a first binary value, generate first combined feedback data based on the first number of random pointer bits, the first combined feedback data including a portion of the first feedback data having the second number of bits and a portion of the second feedback data having a third number of bits, wherein: the first feedback data corresponds to the first test data received at the first memory die; and the second feedback data corresponds to the first test data received at the first memory die; and send the first combined feedback data on the external data bus.

[0006] Another aspect of the present disclosure discloses an apparatus for bus training of interconnected memory dies, comprising: a first memory die coupled to a substrate via a first external data bus and a command / address (CA) bus; the first memory die configured to send first feedback data in response to receiving test data having a first number of bits via the CA bus; and a second memory die coupled to the CA bus and internally coupled to the first memory die, the second memory die configured to send second feedback data in response to receiving the test data via the CA bus; the first memory die comprising bus training logic, the bus training logic configured to: in response to receiving the test data via the CA bus to a bus training command containing the test data, continuously generating a sequence of a plurality of random pointer bits until it is determined that a number of random pointer bits of the sequence have a second or third number of bits with a first binary value; generating combined feedback data, which includes: a portion of the first feedback data at bit positions of the combined feedback data, the bit positions respectively corresponding to the bit positions of the one number of random pointer bits with the first binary value; and a portion of the second feedback data at corresponding bit positions of the combined feedback data, the corresponding bit positions respectively corresponding to the bit positions of the one number of random pointer bits with a second binary value; and transmitting the combined feedback data on the external data bus. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram of a computing system according to several embodiments of the present disclosure.

[0008] Figure 2 A block diagram illustrating a link architecture between interconnected memory dies according to several embodiments of the present disclosure.

[0009] Figures 3A to 3B A portion of one memory die of interconnected memory dies including pseudo-random combination pointers according to several embodiments of the present disclosure is illustrated.

[0010] Figure 4 A timing diagram illustrating performing a bus training operation on interconnected memory dies according to several embodiments of the present disclosure.

[0011] Figures 5A to 5C A sequence of example output bits generated from a pseudo-random combined pointer is illustrated according to several embodiments of the present disclosure. DETAILED DESCRIPTION

[0012] Systems, devices, and methods related to bus training of interconnected memory dies are described. Establishing timing parameters for correctly receiving signaling via a bus is referred to as "bus training" (BT). Bus training for training a command bus, such as a command / address (CA) bus, is referred to as "command bus training" (CBT). CBT can be initiated by sending one or more signals indicating a plurality of bits (or "test data") on the CA bus (from a controller). In response to the test data, the memory die sends feedback data detected on the CA bus back to the controller. The feedback data is sent on a data bus (e.g., a DQ bus) according to specific timing parameters. The controller determines whether the two (e.g., the test data sent on the CA bus and the feedback data received via the DQ bus) match. If there is a match, the controller instructs the memory die to lock the timing parameters for receiving data on the command bus. However, if there is no match (the bit phase of the two data differs by any number of bits), the controller repeats the CBT process until there is a match between the two and until the appropriate timing parameters are determined.

[0013] In some approaches, multiple interconnected memory dies may be individually trained with respect to a bus (e.g., a command bus) by excluding one or more other dies from the training process. As used herein, the term "interconnected memory dies" refers to memory dies that are interconnected together to have at least one shared signal bus to which multiple memory dies are commonly coupled to receive signals. Individual training of each memory die of the interconnected memory dies may be achieved by masking another die (or dies) to prevent it from receiving incoming training communications or to cause it to refuse to respond to training communications. Masking instructions may be implemented using a multi-purpose command (MPC) or other suitable means.

[0014] The memory controller may send an MPC to the memory die to indicate that at least one die is shadowed. However, some memory systems or standards may not support MPC, or it may not be available in certain operating modes or scenarios. For example, during initialization, the physical (PHY) layer or PHY chip may not support the issuance of MPC. In addition, training multiple memory dies in a sequential manner may incur increased latency compared to training the memory dies jointly and / or substantially simultaneously.

[0015] Aspects of the present disclosure address the above and other challenges of memory systems that include interconnected memory dies. For example, embodiments of the present disclosure relate to the execution of bus training (e.g., CBT) in which interconnected memory dies are trained jointly and substantially simultaneously without relying on MPC. In embodiments of the present disclosure, memory dies are "interconnected" such that the interconnected memory dies are internally connected to each other, while some memory dies may be externally connected to a substrate. An externally connected memory die (referred to as an "interface memory die") may act as an interface die for other memory dies (often referred to as "link memory dies") that are internally connected to it. As used herein, an interface die that is externally connected to a substrate may be referred to as a "primary memory die," while a link memory die may be referred to as an "auxiliary memory die." In some embodiments, the external connection is used to transmit signals indicating data to and / or from the interconnected memory dies, while the memory dies are internally connected by cascade connections (e.g., formed via wire bonding) for transmitting other signals such as commands, addresses, power, ground, etc.

[0016] By receiving test data over a shared bus (e.g., a shared CA bus), memory dies that are interconnected together can be trained substantially simultaneously. Feedback data generated at each memory die can be combined and then sent on the DQ bus so that the combined feedback data can be sent from the interface memory die as if the feedback data was sent from a single memory die. For example, if the test data received at each of the two interconnected memory dies includes 7 bits, the combined feedback data can also include 7 bits (rather than 14 bits = 7 bits / memory die*two memory dies). This eliminates the need to mask other memory dies and / or sequentially access the interconnected memory dies to obtain corresponding feedback data.

[0017] As used herein, the singular forms "a", "an", and "the" include singular and plural referents unless the context clearly dictates otherwise. In addition, the word "may" is used throughout this application in a permissive sense (i.e., likely to, able to) rather than in a mandatory sense (i.e., must). The term "include" and its derivatives are derived to mean "including (but not limited to)". The term "coupled" means connected directly or indirectly.

[0018] The figures herein follow a numbering convention in which the first digit or digits correspond to the figure number and the remaining digits identify the element or component in the figure. Similar elements or components between different figures may be identified by using similar numerals. For example, 109 may refer to Figure 1 Component "09" in , and similar components in Figure 3A Or it can be marked as 309 in 3B.

[0019] Similar elements within the figures may be referenced by a hyphen and an additional number or letter. For example, see Figure 1 110-1, ..., 110-N in the drawings. Such similar elements may be generally referenced without hyphens and additional numbers or letters. For example, elements 110-1, ..., 110-N may be collectively referred to as 110. As used herein, the indicator "N" particularly with respect to the element symbols in the drawings indicates that several specific features so specified may be included. As should be understood, the elements shown in various embodiments herein may be added, exchanged and / or eliminated in order to provide several additional embodiments of the present disclosure. In addition, as should be understood, the proportions and relative scales of the elements provided in the drawings are intended to illustrate certain embodiments of the present disclosure and should not be understood in a limiting sense.

[0020] Figure 1 is a block diagram of a computing system 100 according to several embodiments of the present disclosure. The computing system 100 includes a host 102, a controller 104, and memory devices 110-1, ..., 110-N, which may also be individually considered as "devices."

[0021] The host 102 may include a host memory and a central processing unit (not illustrated). The host 102 may be a host system, such as a personal laptop computer, a desktop computer, a digital camera, a smart phone, a memory card reader, and / or a device supporting the Internet of Things, as well as various other types of hosts, and may include a memory access device (such as a processor and / or a processing device). Those skilled in the art will appreciate that a "processor" may refer to one or more processors, such as a parallel processing system, a number of coprocessors, etc.

[0022] Host 102 may include a system motherboard and / or backplane and may include a number of processing resources (e.g., one or more processors, microprocessors, or some other type of control circuitry). System 100 may include separate integrated circuits, or host 102, memory controller 104, and memory device 110 may be on the same integrated circuit. System 100 may be, for example, a server system and / or a high performance computing (HPC) system and / or a portion thereof.

[0023] like Figure 1As illustrated, the host 102 may be coupled to the controller 104 via an interface 103. The interface 103 may be any type of communication path, bus, or the like that allows information to be transferred between the host 102 and the controller 104. Non-limiting examples of the interface may include a peripheral component interconnect (PCI) interface, a peripheral component interconnect express (PCIe) interface, a serial advanced technology attachment (SATA) interface, and / or a micro serial advanced technology attachment (mSATA) interface, etc. However, in at least one embodiment, the interface 103 is a PCIe 5.0 interface that is compatible with the Compute Express Link (CXL) protocol standard. Thus, in some embodiments, the interface 103 may include a flexible bus interconnect and use CXL protocol layers including CXL.io and CXL.mem, and may support transfer speeds of at least 32 gigatransfers per second.

[0024] The controller 104 may control the execution of a memory operation for an access command received from the host 102. The memory operation may be a memory operation of reading data from one or more memory devices 110 (in response to a read request from the host) or an operation of writing data to one or more memory devices 110 (in response to a write request from the host).

[0025] In some embodiments, the controller 104 may be a Compute Express Link (CXL) compatible controller. The host interface (e.g., the front-end portion of the controller 104) may be managed with the CXL protocol and coupled to the host 102 via an interface configured for the Peripheral Component Interconnect Express (PCIe) protocol. CXL is a high-speed central processing unit (CPU) to device and CPU to memory interconnect designed to accelerate next-generation data center performance. CXL technology maintains memory consistency between the CPU memory space and the memory on the attached device, which allows resource sharing to achieve higher performance, reduced software stack complexity, and lower overall system cost. CXL is designed as an industry open standard interface for high-speed communications, as accelerators are increasingly used to supplement CPUs to support emerging applications such as artificial intelligence and machine learning. CXL technology is built on the PCIe infrastructure, thereby utilizing the PCIe physical and electrical interface to provide advanced protocols in several areas, such as input / output (I / O) protocols, memory protocols (e.g., initially allowing hosts and accelerators to share memory), and consistency interfaces.

[0026] Controller 104 may be coupled to memory device 110 via channels 108-1, ..., 108-N, which may be collectively referred to as channels 108. Channels 108 may include various types of data buses, such as a 16-pin data bus and a 2-pin data mask inversion (DMI) bus, among other possible buses. In some embodiments, channel 108 may be part of a physical (PHY) layer. As used herein, the term "PHY layer" generally refers to a physical layer in an open systems interconnection (OSI) model of a computing system. The PHY layer may be the first (e.g., lowest) layer of the OSI model and may be used to transmit data via a physical data transmission medium.

[0027] The memory device 110 may provide main memory for the computing system 100, or may be used as an additional memory or storage device for the entire computing system 100. The memory device 110 may be various / different types of memory devices. For example, the memory device may include RAM, ROM, DRAM, SDRAM, PCRAM, RRAM, and flash memory, etc. In an embodiment where the memory device 110 includes a persistent or non-volatile memory, the memory device 110 may be a flash memory device, such as a NAND or NOR flash memory device. However, the embodiments are not so limited, and the memory device 110 may include other non-volatile memory devices, such as non-volatile random access memory devices (e.g., non-volatile RAM (NVRAM), ReRAM, ferroelectric RAM (FeRAM), MRAM, PCRAM), "emerging" memory devices such as ferroelectric RAM devices including ferroelectric capacitors that may exhibit hysteresis characteristics, memory devices having resistive, phase change or similar memory cells, etc., or a combination thereof.

[0028] For example, a FeRAM device may include a ferroelectric capacitor and may perform bit storage based on a voltage or amount of charge applied thereto. In such examples, relatively small and relatively large voltages allow the ferroelectric RAM device to exhibit properties similar to normal dielectric materials (e.g., dielectric materials with relatively high dielectric constants), but at various voltages between such relatively small and large voltages, the ferroelectric RAM device may exhibit polarization reversal that produces nonlinear dielectric behavior.

[0029] As another example, an array of nonvolatile memory cells (e.g., resistive, phase change, or similar memory cells) can be combined with a stackable crossbar grid data access array to perform bit storage based on changes in bulk resistance. Additionally, in contrast to many flash memory based memories, nonvolatile memories can perform write-in-place operations, where nonvolatile memory cells can be programmed without previously being erased.

[0030] One example of the memory device 110 is a dynamic random access memory (DRAM) operating according to a protocol such as low power double data rate (LPDDRx), which may be referred to herein as an LPDDRx DRAM device, LPDDRx memory, etc. The "x" in LPDDRx refers to any of several generations of protocols (e.g., LPDDR5). In at least one embodiment, at least one of the memory devices 110-1 is operated as an LPDDRx DRAM device with low power features enabled, and at least one of the memory devices 110-N is operated as an LPDDRx DRAM device with at least one low power feature disabled. In some embodiments, although the memory device 110 is an LPDDRx memory device, the memory device 110 does not include circuitry configured to provide low power functionality for the memory device 110, such as a dynamic voltage frequency scaling core (DVFSC), a subthreshold current reduction circuit (SCRC), or other low power functionality providing circuitry. Providing the LPDDRx memory device 110 without such circuitry can advantageously reduce the cost, size, and / or complexity of the LPDDRx memory device 110. For example, a LPDDRx memory device 110 with reduced low-power functionality providing circuitry may be used in applications other than mobile applications (eg, if the memory is not desired for use in mobile applications, some or all low-power functionality may be sacrificed to reduce the cost of producing the memory).

[0031] The memory devices 110 may each include a number of memory dies (eg, Figure 2 220-1 and 220-2 described in the example above). These memory dies may be interconnected memory dies. Figure 2 As further described, when memory dies are connected internally, one or more memory dies (e.g., Figure 2 The memory die 220-1) illustrated in FIG. 2 may be externally connected to the substrate to act as an interface die for other memory dies that are internally connected to the substrate. In some embodiments, these interconnected memory dies may be "stacked" memory dies.

[0032] The controller 104 may further include a bus training component 105. Although not shown in the figure to avoid obscuring the diagram, Figure 1 1, but the bus training component 105 may include various circuit systems to facilitate the performance of the operations described herein. For example, the bus training component 105 may cause each memory device 110 to perform those operations associated with bus training. As used herein, the term "bus training" (or "bus training operation", "bus training process", etc.) refers to the process of establishing timing parameters for correctly receiving signaling via a bus. In addition, the command bus (e.g., Figure 2The bus training operation performed by the CA bus 212 described in the figure may be referred to as command bus training (CBT).

[0033] The bus training component 105 may initiate bus training by issuing commands (eg, mode register set and / or write commands) to the memory devices 110 and then sending (eg, transmitting) test data to one or more memory devices 110 via a bus (eg, CA bus 212).

[0034] Test data may be received at the memory dies (e.g., corresponding to one or more ranks) of the memory device 110 according to the first timing parameters. Upon receiving, each memory die may return (e.g., send) the received test data (or "feedback data") back to the controller 104. If the feedback data matches the test data sent from the controller 104, the controller 104 may instruct the memory device 110 to lock the first timing parameters for receiving on the command bus. On the other hand, if the two (e.g., the test data and the feedback data) do not match, the controller 104 may repeat the test and feedback process with respect to the memory device using different second timing parameters and one or more test data. The bus training operation may continue until the appropriate timing parameters are determined.

[0035] The memory devices 110 may include bus training circuits 109-1, . . . , 109-N that may coordinate interconnected memory dies (eg, Figure 2 ) is a bus training process performed on the memory dies 220-1 and 220-2 described in . For example, although test data can be received separately at each memory die of the interconnected memory dies, feedback data can be output (e.g., sent) from one of the interconnected memory dies in a combined manner. For example, if each of the interconnected memory dies (e.g., including two memory dies) receives the same 7-bit test data, then the 7-bit feedback data generated at each of the two interconnected memory dies can be combined so that the feedback data sent back to the controller 104 includes only 7 bits instead of 14 bits. As used herein, the term "output" may be used interchangeably with other terms such as "transmit," "transmit," and "send." The bus training circuit 109 can combine feedback data from the interconnected memory dies in a random manner. Further details on randomly combining feedback data from the interconnected memory dies are described in . Figure 2 5. In addition, further details of the structural components of the bus training circuit are illustrated in FIG. 3.

[0036] Figure 2 A block diagram illustrating a link architecture between interconnected memory dies 220-1 and 220-2 (collectively referred to as memory dies 220) according to several embodiments of the present disclosure. More specifically, Figure 2 The bus training circuit 109 within each memory die 220-1, 220-2 is described in further detail.

[0037] Figure 2 Two memory dies 220-1 and 220-2 are illustrated; however, embodiments are not limited to memory dies that may be similar to Figure 2 A specific number of memory dies interconnected (eg, coupled) together in the manner described. Each memory die 220 is not Figure 2 is fully described in and may further include Figure 2 For example, each memory die 220 may include a memory cell array, data received from the outside may be written to the memory cell array, or data may be read from the memory cell array. Although the embodiment is not limited thereto, the memory dies 220-1 and 220-2 may correspond to a rank. Figure 2 As illustrated, the memory dies 220-1 and 220-2 that are interconnected together may also be "stacked" (eg, stacked in a vertical manner).

[0038] Memory die 220-1 may be a main memory die externally connected to a substrate, while memory die 220-2 may be an auxiliary memory die that is not coupled to a substrate but is internally coupled to a main memory die (e.g., memory die 220-1) to transfer data via the main memory die. Figure 2 As shown, the secondary memory die 220-2 is internally coupled to the primary memory die 220-1 via a CQ bus 232 (or "wire link"), which may be formed via wire bonding.

[0039] like Figure 2 As shown, memory dies 220-1, 220-2 include CA pads 216-1, 216-2, respectively, which can receive clock and / or CA signals, such as a clock signal sent via CLK bus 214 (eg, Figure 2 The “CLK” shown) and the CA signal sent via the CA bus 212 (such as Figure 2 2. The memory dies 220-1 and 220-2 of the interconnected memory dies may be coupled to the same CA bus 212 to receive the CA signal at substantially the same time. As used herein, the term "substantially" means that the characteristic need not be absolute but close enough to achieve the advantage of the characteristic. For example, substantially at the same time is not limited to operations performed at absolutely the same time and may include timing that is desired to be simultaneous but may not be exactly simultaneous due to manufacturing limitations. The clock signal that may be received via the CLK bus 214 may represent a system clock such as a CA clock, and various components of the corresponding memory die 220 may operate based on the clock signal.

[0040] During a CBT operation (which may be initiated by setting one or more specific mode register bits (e.g., MR16 OP[5:4]), one or more CA signals received at the memory dies 220-1 and 220-2 may indicate a command sequence (e.g., a mode register set (MRS) command, a mode register write (MRW) command, etc.), test data for one or more CBT operations, etc. The CA signals received at the memory dies 220-1 and 220-2 may be buffered at respective buffers 218-1 and 218-2. Each selector 222-1 and 222-2 (e.g., Figure 2 The "BMCBT_a" shown) can selectively send bits (eg, a set of test data) buffered at the corresponding buffer 218 to the selectors 224-1, 224-2 (eg, Figure 2 For example, selector 222 may select a set of test data received at buffer 218 prior to another set of test data and send the selected test data to selector 224.

[0041] like Figure 2 As illustrated, each selector 224 may receive inputs from a corresponding selector 222 and a corresponding CQ pad 230, as well as a control signal from a pseudo-random combination pointer 226. In a specific example such as CBT operation, the selector 224-2 of the link memory die 220-2 provides feedback data (corresponding to test data received at the memory die 220-2) to the CQ pad 230-2 to further send the feedback data to the interface memory die 220-1 (e.g., to the CQ pad 230-1 of the interface memory die 220-1) via the CQ bus 232. The feedback data received at the memory die 220-1 may be input to the selector 224-1 of the memory die 220-1. Continuing with the CBT operation example, the selector 224-1 also receives the feedback data (corresponding to the test data received at the memory die 220-1) as input.

[0042] Selector 224-1 may combine two inputs (e.g., first feedback data from memory die 220-1 and second feedback data from memory die 220-2) to generate combined feedback data. For example, if each of the first feedback data and the second feedback data includes 7 bits (e.g., 7 bits of feedback data from memory die 220-1 and 7 bits of feedback data from memory die 220-2), the combined feedback data may also include 7 bits, 3 bits from one (e.g., first or second) feedback data and 4 bits from the other (e.g., first or second) feedback data, but embodiments are not limited to a specific number of bits of the first or second feedback data that may be included in the combined feedback data.

[0043] like Figure 2 As illustrated, memory dies 220-1 and 220-2 include pseudo-random combination pointers 226-1 and 226-2, respectively.Each pseudo-random pointer 226 can indicate to a respective selector 224 how to combine inputs received at the respective selector 224 to produce a combined output.

[0044] At least when performing bus training operations such as CBT operations, the pseudo-random combination pointer 226-2 of the link memory die may be disabled, while the pseudo-random combination pointer 226-1 of the interface memory die is enabled and used for bus training operations. During bus training operations, the pseudo-random combination pointer 226-1 may provide a "random pointer" bit whose number is equal to the number of each input received at the selector 224-1.

[0045] Selector 224-1 may combine input bits (e.g., test data received from both memory die 220-1 and 220-2) as indicated by the "random pointer" bits. For example, assuming that a binary value of "0" represents memory die 220-1 and a binary value of "1" represents memory die 220-2 and the "random pointer" bits received at selector 224-1 are "0100111", selector 224-1 generates a combined output bit by including feedback data from memory die 220-1 on those bit positions corresponding to "random pointer" bits having "0" (e.g., the first, third, and fourth bits) and including feedback data from memory die 220-2 on those bit positions corresponding to "random pointer" bits having "1" (e.g., the second, fifth, sixth, and seventh bits).

[0046] The test data may be sent (e.g., transferred) from the memory die 220-1 via the external data bus 228-1 (e.g., a data input / output bus, also referred to in the art as "DQ") and further returned to the controller (e.g., Figure 1 As described herein, the memory die 220-2, as a link die, may not be coupled to the external data bus 228-1 (e.g., Figure 2 The external data bus 228-2 shown in dashed lines in FIG. 2 is not coupled to the substrate). Although the embodiment is not limited thereto, the external data bus 228-1 may be a 7-bit wide data bus. Figure 2 The 4-bit SPI registers are labeled “DQ<6:0>” in the figure.

[0047] In some embodiments, the controller 104 may force the pseudo-random combination pointer 226 to operate independently of (e.g., regardless of) a bus training operation (which may be initiated by setting a particular mode register bit, such as MR16 OP[4]), for example, to test and / or determine an operational trend of the pseudo-random combination pointer 226.

[0048] For example, the controller 104 may force one memory die (e.g., memory die 220-1) to send a "low" signal (e.g., corresponding to a binary value of "0") and force the other memory die (e.g., memory die 220-1) to send a "high" signal (e.g., corresponding to a binary value of "1") from selectors 222-1 and 222-2 to selectors 224-1 and 224-2, respectively. The "low" signal is further sent to memory die 220-1. Continuing with this example, selector 224-1 receives input bits (e.g., 7 bits) from memory die 220-2, where each bit is a "1", and receives input bits (e.g., 7 bits) from memory die 220-1, where each bit is a "0". As indicated by pseudo-random combination pointer 226 and as described herein, the inputs received at selector 224-1 may be combined to be included in the output bits. Since whether the output bits are from memory die 220-1 or 220-2 is determinable based on the corresponding binary values ​​of the bits, the output bits may indeed indicate the random pointer bits generated at the pseudo-random combination pointer 226. For example, the output bits "0100111" received from memory die 220-1 (e.g., at the controller 104) further indicate that the random pointer bits "0100111" are used to combine the input bits from memory die 220-1 and 220-2. Although the embodiments are not limited in this regard, the controller 104 may force the memory die 220 to continuously send multiple groups of output bits in the manner described above. In combination Figures 5A to 5C Further details of this test of the pseudo-random combination pointer 226 are described.

[0049] Figures 3A to 3B A block diagram illustrating a portion of one of the interconnected memory dies (eg, bus training circuit 309 ) including a pseudo-random combination pointer 326 in accordance with several embodiments of the present disclosure is shown. Figures 3A to 3B The bus training circuit 309 described in FIG. 3 may be similar to the corresponding memory die (eg, Figure 2 220 - 1 ) of the bus training circuit 109 of the interface die 220 - 1 illustrated in FIG.

[0050] like Figure 3A As shown, bus training circuit 309 includes logic gate 340 (eg, an XOR gate) that can receive inputs such as a bus training command ( ) indicating initiation and execution of a bus training operation. Figure 3AThe "CBT Start" signal shown in the figure and the bus training initialization command ( Figure 3A Although embodiments are not limited in this regard, bus training operations performed on interconnected memory dies (including bus training circuit 309) may be CBT operations. In response to receiving a command, logic gate 340 may generate an output signal and send it to pulse generation component 342.

[0051] In response to receiving a signal from logic gate 340, pulse generation component 342 may generate a signal ( Figure 3A ) and sends it to logic gate 344 (e.g., an XOR gate) and sequential logic circuit 347 (e.g., a flip-flop). The "CBT_CS_P" pulse may further cause and / or allow logic gate 344 to generate one or more signals ( Figure 3A and in the form of a pulse) and sends it to the pseudo-random combination pointer 326 (similar to Figure 2 The pseudo-random combination pointer 226-1 and / or 226-2) and the delay component 353 described in the figure.

[0052] like Figures 3A to 3B As shown, the pseudo-random combination pointer 326 includes a shift register, such as a linear feedback shift register (LFSR) 348. The LFSR 348 can generate a number of random bits ( Figure 3B ) where the number of bits is equal to the number of bits from Figure 1 348. The number of "test data" received by the controller 104 shown in FIG. 340 is shown in FIG. 341. For example, if the "test data" received at each memory die of the interconnected memory dies (e.g., memory dies 220-1 and 220-2) respectively has 7 bits, then the random bits generated at the LFSR 348 may further have 7 bits. Although the random bits generated at the LFSR 348 are illustrated as 7 bits, embodiments are not limited to a specific number of random bits that may be generated at the LFSR 348.

[0053] The counting component 350 may receive the random bits from the LFSR 348 and count the number of "1"s within the random bits. The number of "1"s determined to be within the random bits may be indicated via a binary code. For example, Figure 3BAs shown, a random bit without a "1" may be indicated via a binary code of "000"; a random bit with one "1" may be indicated via a binary code of "001"; a random bit with two "1"s may be indicated via a binary code of "010"; a random bit with three "1"s may be indicated via a binary code of "011"; a random bit with four "1"s may be indicated via a binary code of "100"; a random bit with five "1"s may be indicated via a binary code of "101"; a random bit with six "1"s may be indicated via a binary code of "110"; and a random bit with seven "1"s may be indicated via a binary code of "111". A binary code (e.g., one of the seven binary codes) may be provided to a selector 352, which may be set for a test mode register (in Figure 3B TMRS).

[0054] The selector 352 may output one or more signals ( Figure 3B and shown in pulse form). Although Figures 3A to 3B This illustrates a circuit / component designed to determine whether a 7-bit random bit has three or four "1's", but embodiments are not limited to a specific number of bits that the random bit contains or a specific number (e.g., three or four) of "1's" that the random bit is being checked for. For example, the selector 352 may provide a signal when the received binary code indicates that the random bit has two, three, four, or five "1's".

[0055] Delay component 353 can "mirror" the input pulse received from logic gate 344 ( Figure 3A ) to generate and send one or more pulses ( Figure 3B The delay component 353 is shown as "lat34" in FIG. Figure 3A The “LFSR_P” shown in Figure 3B 354) to synchronize the timing of receiving the "DET34F" and "lat34" signals at the sequential logic circuit 354 (e.g., a flip-flop). The sequential logic circuit 354 may generate and provide a signal ( Figure 3B The "HIT34F" shown in the video).

[0056] The bus training circuit 309 further includes a sequential logic circuit 357 (eg, a flip-flop) that can receive a signal indicating a bus training initialization command ( Figure 3A) and a signal from delay element 353 and similar to the "lat34" signal provided to sequential logic circuit 354. Sequential logic circuit 357 may generate signal ( Figure 3B ) and sends it to logic gate 356 (e.g., an XOR gate), which may further generate an output signal and send it to logic gate 358.

[0057] The delay component 355 may further mirror the input signal received from the delay component 353 to generate one or more signals (e.g., in the form of pulses) and send them to the logic gate 358 (e.g., an AND gate). The delay component 353 introduces a time delay between the input signal received from the delay component 353 and the output signal of the delay component 355 to synchronize the timing of receiving the signals from the logic gate 356 and the delay component 355 at the logic gate 358.

[0058] The signal may be delayed in various forms (e.g., "LFSR_P", "LFSR_CLK2", etc.) via delay components 353, 355, logic gate 358, and pulse re-adjustment component 343, as long as the random bits generated at LFSR 348 are indicated as not having three or four "1's" (e.g., as long as "HIT34F" is driven high, as Figure 4 For example, the signal ( Figure 3A ) may be input to the pulse re-adjustment component 343, which may be further input to the pseudo-random combination pointer 326 (eg, the LFSR 348 of the pseudo-random combination pointer 326).

[0059] The pulse re-adjustment component 343 can re-adjust the pulse width of the "LFSR_CLK2" pulse, which is circulated through the circuit system (e.g., Figure 3A355, logic gate 358, and pulse realignment component 343 as illustrated in FIG. 35A and FIG. 35B , may experience undesirable distortion due to PVT variations when the “LFSR_CLK2” pulse is connected to the logic gate 344. For example, the pulse width (of the “LFSR_CLK2” pulse) may have increased while cycling through the circuits (e.g., inverters) of the delay components 353, 355. The pulse realignment component 343 may generate (e.g., create) a pulse (which will be input to the logic gate 344) by generating two pulses with the same increased width: a first pulse starting at a rising edge and a second pulse starting at a falling edge. The time between the rising edge (of the first pulse) and the falling edge (of the second pulse) may correspond to the desired pulse width of the “LFSR_P” pulse. In addition to the increased pulse width of the “LFSR_CLK2” pulse as received at the pulse realignment component 343, the increase introduced by the pulse realignment component 343 may correspond to the gate delay (e.g., of the two inverters). Each time a "LFSR_CLK2" pulse is received at the pulse readjustment component 343, the pulse width of the pulse may be readjusted.

[0060] Once the random bit is indicated as having three or four "1's", the LFSR 348 may send (e.g., latch) the random bit (having three or four "1's") to the sequential logic circuit 347. In response to receiving the random bit, the sequential logic circuit 347 (e.g., a flip-flop) may generate and send a "random pointer" bit to the selector 324 to cause and / or allow the selector 324 to select and combine input bits (e.g., "test data" received from memory dies (e.g., memory dies 220-1 and 220-2) respectively) based on the "random pointer" bit. For example, if each input ("CBT data from LK die" and "CBT data from IF die") has seven bits, then the selector 324 may combine the inputs from the two memory dies to generate and output seven bits having three bits and four bits from the two memory dies, respectively. As shown herein, the random bits may be transmitted on the DQ bus (e.g., Figure 2 2 and 3. The CBT operation is performed by sending (eg, transmitting) output on the DQ bus 228-1 as feedback data and a response to a CBT operation.

[0061] Figure 4 A method for interconnecting memory dies (e.g., Figure 2 460 illustrates a timing diagram of a memory die 220-1, 220-2 (illustrated in FIG. 46) performing a bus training operation (eg, a CBT operation). The timing diagram 460 illustrates a signal "Init_done" 462 (similar to Figure 3A "CBT INIT" shown in the ), "CBT_CS" 464 (similar to Figure 3A"CBT Start" shown in ), "LFSR_P" 466 (similar to Figure 3A 468 (similar to the "LFSR_P" shown in Figure 3B "PR_CA<6:0>" shown in the figure), "DET34F" 470 (similar to Figure 3B "DET34F" shown in ), "lat34" 472 (similar to Figure 3B "lat34"), "HIT34F" 474 (similar to Figure 3B "HIT34F" shown in the ), "init" 476 (similar to Figure 3B "initF" shown in Figure 3A LFSR_CLK2 shown in the figure).

[0062] The initialization phase (similar to the bus training initialization operation) can be performed at signal 462 such as Figure 4 is driven high (e.g., in response to Figure 3A In response to the bus training initialization command, the "init" signal 476 may be further driven high, such as Figure 4 As described.

[0063] When signal 462 is driven high, signal 464 may be periodically switched to generate pulses on “LFSR_P” signal 466. As used herein, the term “toggling” or the like (e.g., toggled) refers to a change in the state of a signal, such as from a low state (referred to as “low”) to a high state (referred to as “high”) or from high to low. For example, each pulse on “LFSR_P” signal 466 involves switching “LFSR_P” signal 466 twice to generate a rising edge and a falling edge of each pulse, respectively.

[0064] like Figure 4As shown, each "LFSR_P" pulse may further cause a corresponding "lat34" pulse to be generated on "lat34" signal 472; each "lat34" pulse may further cause a corresponding "LFSR_CLK2" pulse to be generated on "LFSR_CLK2" signal 478; and each "LFSR_CLK2" pulse may again cause a corresponding "LFSR_P" pulse to be generated on "LFSR_P" signal 466. During the initialization phase, the "LFSR_P", "lat34" and "LFSR_CLK2" pulses may be continuously generated until both the "init" signal 476 and the "LFSR_CLK2" signal 478 are driven low.

[0065] Each "LFSR_P" pulse may cause the LFSR 348 to further generate each number of random bits "PR_CA<6:0>", such as 468-1, ..., 468-12. A "P" on the signal 468 indicates that the number of random bits (e.g., 7 bits) includes the expected number (e.g., three or four) of "1s", while an "F" on the signal 468 indicates the opposite (e.g., the number of random bits does not include the expected number of "1s"). For example, in Figure 4 In the example shown and during the initialization phase, four groups (e.g., numbers) of random bits 468-1, 468-2, 468-4, and 468-6 are labeled "P" (e.g., indicated as having an expected number of "1's"), and two groups 468-3 and 468-5 are labeled "F" (e.g., indicated as not having an expected number of "1's").

[0066] The "DET34F" signal 470 is driven low in response to the corresponding set of random bits 468-1, 468-2, 468-4, and 468-6 being labeled "P," and is driven high in response to the corresponding set of random bits being labeled "F." Similarly, the "HIT34F" signal 474 is driven low in response to the corresponding set of random bits 468-3 and 468-5 being labeled "P," and is driven high in response to the corresponding set of random bits being labeled "F."

[0067] The training phase may be initiated in response to each pulse on the “CBT_CS” signal 464, which may be generated in response to a corresponding bus training command (similar to the bus training operation). Each bus training command may toggle the “CBT_CS” signal 464 to generate a corresponding pulse (e.g., “CBT1”, “CBT2”, and “CBT3” pulses 464-1, 464-2, and 464-3). Each CBT pulse on the signal 464 may cause continuous and periodic pulses to be generated on the “LFSR_P” signal 466, such as Figure 4 As shown. Figure 4As further shown in , each pulse on the “LFSR_P” signal 466 may further cause a corresponding pulse on the “lat34” signal 472, which may further cause a corresponding pulse on the “LFSR_CLK2” signal 478. A pulse on the “LFSR_CLK2” signal 478 may again cause a corresponding pulse on the “LFSR_P” signal 466.

[0068] The pulses on the signals 466, 472, and 478 may be continuously and periodically generated unless the set of random bits generated in response to each pulse on the "LFSR_P" signal 466 is indicated as having a desired number (e.g., three or four) of "1's." Once the "DET34F" and "HIT34" signals 470 and 474 are driven low due to a set of random bits (e.g., random bit groups 468-9, 468-10, and 468-12) being determined to have a desired number of "1's," no more pulses are generated on the "LFSR_CLK2" signal 478, which causes a corresponding set of random bits to be latched into the sequential logic circuit 347 and further latched into the selector 324.

[0069] like Figure 4 As shown, for example, the first two groups of random bits 468-7 and 468-8 generated in response to the “CBT1” pulse on the “CBT_CS” signal 464 are determined to not have the expected number of “1”s and may be labeled “F”, respectively. Once the third group of random bits 468-9 (labeled “P2”) are determined to have the expected number of “1”s, the pulses that have been periodically generated on the “LFSR_CLK2” signal 478 are no longer generated. In addition, the first group of random bits 468-10 (labeled “P3”) generated in response to the “CBT2” pulse on the “CBT_CS” signal 464 is determined to have the expected number of “1”s, which causes the pulses on the “LFSR_CLK2” signal 478 to no longer be generated. In addition, the first group of random bits 468-11 generated in response to the “CBT3” pulse on the “CBT_CS” signal 464 is determined to not have the expected number of “1”s and may be labeled “F”, respectively. Once it is determined that the second set of random bits 468-12 (labeled "P4") has the expected number of "1's", the pulses that have been periodically generated on the "LFSR_CLK2" signal 478 are no longer generated.

[0070] Figures 5A to 5C The following describes several embodiments of the present disclosure from pseudo-random combination pointers (for example, respectively in Figure 2 3 and the pseudo-random combination pointer 226 and / or 326) generated by the example output bit sequence. More specifically, Figures 5A to 5C The example output bit sequence illustrated in can be generated as a result of testing of the pseudo-random combination pointers 226 and / or 326.

[0071] Columns 580-1, ..., 580-7 respectively illustrate the DQ bus (e.g., Figure 2 For example, column 580-1 illustrates the bit value (or binary value) of the "DQ6" bit; column 580-2 illustrates the bit value of the "DQ5" bit; column 580-3 illustrates the bit value of the "DQ4" bit; column 580-4 illustrates the bit value of the "DQ3" bit; column 580-5 illustrates the bit value of the "DQ2" bit; column 580-6 illustrates the bit value of the "DQ1" bit; and column 580-7 illustrates the bit value of the "DQ0" bit.

[0072] Column 582 shows two hexadecimal ( Figures 5A to 5C , where the left hexadecimal value represents the three-digit hexadecimal value of the binary value 580-1, ..., 580-3, and the right hexadecimal value represents the four-digit hexadecimal value of the binary value 580-4, ..., 580-7. Column 584 illustrates the number of "1"s in each row corresponding to the 7 bits of DQ0, ..., DQ7, respectively. For example, example row 585 is illustrated as having bits "0101011" including four "1"s, with a hexadecimal value of "2" on the left three bits "010" of the bits, and a hexadecimal value of "B" on the right four bits "1011" of the bits.

[0073] Figures 5A to 5C The sequence of the 7-bit groups described in the example above can be as follows: Figure 2 Example output bits that may be output from memory die 220-1 (e.g., selector 224-1 of memory die 220-1) as a result of the test of the pseudo-random combination pointer 226 described. For example, a sequence of groups of output bits (corresponding to rows, respectively) may be output from memory die 220-1 independently of input test data that would otherwise be sent to memory die 220 as part of the CBT operation (e.g., in the absence of the input test data). Thus, a sequence of groups of output bits may be continuously provided from memory die 220-1 independent of (e.g., regardless of) whether the number of "1's" in each group of output bits has three "1's" or four "1's".

[0074] The group of output bits output as a result of the testing of the pseudo-random combination pointer 226 may be used in various configurations associated with bus training operations (eg, CBT operations). Figure 5A The group of output bits indicated by 586 in FIG. 1 indicates that at most six clock cycles are required to arrive at another group of output bits having three or four "1s". More specifically, as Figure 5AAs indicated by 586 in , once it hits three "1s" at a set of output bits "111000" with hexadecimal values ​​of "7" and "0", it takes six cycles to reach "000111" with three "1s" and hexadecimal values ​​of "0" and "E". Therefore, these "six" clock cycles can be used as the worst-case scenario for the circuit design and / or configuration tCACD (of the bus training circuit 109), which refers to the time that can be spent between two CBT operations. In some embodiments, tCACD can be configured to be 20 nanoseconds (ns).

[0075] Although specific embodiments have been illustrated and described herein, it will be appreciated by those skilled in the art that arrangements calculated to achieve the same results may replace the specific embodiments shown. The present disclosure is intended to cover adaptations or variations of one or more embodiments of the present disclosure. It will be appreciated that the above description has been made in an illustrative and non-restrictive manner. Combinations of the above embodiments and other embodiments not explicitly described herein will be apparent to those skilled in the art after reviewing the above description. The scope of one or more embodiments of the present disclosure includes other applications in which the above structures and processes are used. Therefore, the scope of one or more embodiments of the present disclosure should be determined with reference to the appended claims and the full range of equivalents to which such claims are entitled.

[0076] In the foregoing detailed description, some features are grouped together in a single embodiment for the purpose of simplifying the disclosure. This method of disclosure should not be interpreted as reflecting an intention that the disclosed embodiments of the disclosure must use more features than those explicitly recited in each claim. Rather, as the appended claims reflect, the subject matter of the invention lies in less than all the features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.

Claims

1. A method for bus training of interconnected memory dies, comprising: In response to receiving a bus training command and test data associated with the bus training command and having a first number of bits, generating a first number of random pointer bits having the first number of bits; In response to determining that the first number of random pointer bits has a second number of bits with a first binary value, generating combined feedback data based on the first number of random pointer bits by randomly combining first feedback data corresponding to the first test data received at a first memory die (220-1) and second feedback data corresponding to the first test data received at a second memory die (220-2) to generate combined feedback data, the combined feedback data comprising: a portion of the first feedback data having the second number of bits; and a portion of the second feedback data having a third number of bits; and In response to the bus training command, the feedback data is sent on an external data bus (228-1) coupled to the first memory die or the second memory die.

2. The method of claim 1 , further comprising, in response to determining that the first number of random pointer bits has the third number of bits with the first binary value, generating the combined feedback data based on the first number of random pointer bits by randomly combining the first feedback data and the second feedback data to generate the combined feedback data, the combined feedback data comprising: a portion of the first feedback data having the third number of bits; and The portion of the second feedback data has the second number of bits.

3. The method according to claim 1, wherein: The first memory die corresponds to a main memory die (220-1) coupled to the external data bus; The second memory die corresponds to an auxiliary memory die (220-2) internally coupled to the primary memory die; and The method further comprises: receiving the first test data at the second memory die; and In response to receiving the first test data, the second feedback data is sent to the first memory die to allow the second feedback data to be randomly combined with the first feedback data.

4. The method according to any one of claims 1 to 3, further comprising: responsive to determining that the first number of random pointer bits has a fourth number of bits with the first binary value, generating a second number of random pointer bits; and In response to determining that the second number of random pointer bits has the first or second number of bits with the first binary value, generating the combined feedback data based on the second number of random pointer bits by randomly combining the first feedback data and the second feedback data to generate the combined feedback data, the combined feedback data comprising: a portion of the first feedback data having the third number of bits; and The portion of the second feedback data having the second number of bits.

5. The method of any one of claims 1 to 3, further comprising generating the sequence of random pointer bits in response to receiving a bus training initialization command and regardless of whether each number of random pointer bits of the sequence of random pointer bits has the second number of bits with the first binary value.

6. An apparatus for bus training of interconnected memory dies, comprising: a first memory die (220-1) coupled to the substrate via an external data bus (228-1) and a command / address CA bus (212); and a second memory die (220-2) coupled to the CA bus and internally coupled to the first memory die; The first memory die is configured to: In response to receiving a first bus training command including first test data having a first number of bits, generating a first number of random pointer bits having the first number of bits; In response to the first number of random pointer bits being determined to have a second number of bits with a first binary value, generating first combined feedback data based on the first number of random pointer bits, the first combined feedback data comprising a portion of the first feedback data having the second number of bits and a portion of the second feedback data having a third number of bits, wherein: The first feedback data corresponds to the first test data received at the first memory die; and the second feedback data corresponds to the first test data received at the first memory die; and The first combined feedback data is sent on the external data bus.

7. The apparatus of claim 6, wherein the first memory die is configured to: in response to the first number of random pointer bits being determined to have a fourth number of bits with the first binary value, generating a second number of random pointer bits having the first number of bits; in response to the second number of random pointer bits being determined to have the second number of bits with the first binary value, generating second combined feedback data based on the second number of random pointer bits, the second combined feedback data comprising a portion of the first feedback data having the second number of bits and a portion of the second feedback data having the third number of bits; and The second combined feedback data is sent on the external data bus.

8. The apparatus of claim 6, wherein the first combined feedback data comprises: the portion of the first feedback data at bit positions of the first combined feedback data, the bit positions respectively corresponding to the bit positions of the first number of random pointer bits having the first binary value; and The portions of the second feedback data at respective bit positions of the first combined feedback data, the respective bit positions respectively corresponding to bit positions of the first number of random pointer bits having a second binary value.

9. The apparatus according to any one of claims 6 to 8, wherein each bit position of the first combined feedback data further corresponds to a corresponding pin of the external data bus.

10. The apparatus of any one of claims 6 to 8, wherein the second memory die is not coupled to the substrate.

11. The apparatus of any one of claims 6 to 8, wherein the first memory die is configured to generate a sequence of random pointer bits in response to a bus training initialization command received prior to the bus training command, regardless of whether a corresponding one of the random pointer bits is determined to have the second number of bits with the first binary value.

12. An apparatus for bus training of interconnected memory dies, comprising: a first memory die (220-1) coupled to a substrate via a first external data bus (228-1) and a command / address CA bus (212); the first memory die configured to send first feedback data in response to receiving test data having a first number of bits via the CA bus; and a second memory die (220-2) coupled to the CA bus and internally coupled to the first memory die, the second memory die configured to send second feedback data in response to receiving the test data via the CA bus; The first memory die includes bus training logic (109; 309) configured to: In response to receiving a bus training command including the test data via the CA bus, continuously generating a sequence of random pointer bits until it is determined that a number of random pointer bits of the sequence have a second or third number of bits with a first binary value; Generates combined feedback data including: a portion of the first feedback data at bit positions of the combined feedback data, the bit positions respectively corresponding to bit positions of the one number of random pointer bits having the first binary value; and a portion of the second feedback data at corresponding bit positions of the combined feedback data, the corresponding bit positions respectively corresponding to the bit positions of the one number of random pointer bits having a second binary value; and The combined feedback data is sent on the external data bus.

13. The apparatus of claim 12, wherein: The second memory die is internally coupled to the first memory die via a wire link (232); and The second memory die is configured to send the second feedback data to the first memory die via the wire link to allow the first memory die to combine the first and second feedback data.

14. The apparatus of claim 12, wherein a sum of the second number and the third number is equal to the first number.

15. The apparatus of claim 14, wherein: The first memory further includes a shifter register (348) configured to generate the sequence of the number of random pointer bits; and The shifter register is further configured to continuously generate a sequence of random bits in response to a bus training initialization command received prior to the bus training command and regardless of whether a corresponding number of random bits of the sequence of random bits are determined to have the second number or a third number of bits having a first binary value, the random bits each having the first number.

16. The apparatus of claim 15, wherein: the shifter register being configured to generate each number of random bits of the sequence in response to a respective one of a number of input pulses received at the shifter register, wherein each input pulse of the number of input pulses has a first pulse width; and Wherein the apparatus further comprises a pulse width re-adjuster coupled to the shifter register, the pulse width re-adjuster configured to re-adjust an increased second pulse width of a corresponding input pulse of the number of input pulses to the first pulse width.

17. The apparatus of claim 12, further comprising a controller (104) coupled to the first memory die and the second memory die, wherein the controller is configured to: causing the second memory die to output a first number of bits having the first binary value and sending the first number of bits to the first memory die; and causing the first memory die to output a second number of bits having the second binary value, and randomly combining the first number of bits and the second number of bits to produce a third number of bits, the third number of bits comprising: a portion of the first number of bits having the second number and having the first binary value; and A portion of the second number of bits has the third quantity and has the second binary value.

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