Semiconductor structure preparation method and semiconductor structure

Abstract

The present disclosure relates to a semiconductor structure preparation method and a semiconductor structure, and relates to the field of integrated circuit technology, including: providing a substrate; based on a target mask, forming a first through hole that sequentially penetrates a support stack along a first direction; forming a target stack on the inner side wall of the first through hole, the target stack defines a second through hole, and the target stack includes a target carbon layer and an isolation layer that are alternately stacked from outside to inside; forming a dielectric stack that fills the second through hole; based on a target mask, forming a third through hole that penetrates the dielectric stack and exposes the target stack; after etching and removing the remaining dielectric stack in the second through hole through the third through hole, over-etching the first dielectric layer to obtain a groove that exposes a portion of the conductive layer; removing the target carbon layer, forming a metal barrier layer that covers the inner side wall of the third through hole and the inner surface of the groove, and including an air gap between adjacent remaining isolation layers. At least the number of masks used can be reduced, and the complexity and cost of the preparation process can be reduced.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuit manufacturing, and in particular to a semiconductor structure preparation method and a semiconductor structure. Background Art

[0002] With the rapid development of semiconductor technology, the market has increasingly higher requirements for the integration, performance and reliability of integrated circuits, resulting in an increase in the number of stacked film layers and structural complexity within the chip.

[0003] Metal wires are generally used inside the chip to achieve communication connections between transistors, capacitors, resistors, etc. The increasing number of stacked film layers and structural complexity inside the chip place increasingly higher requirements on the process of preparing high aspect ratio metal interconnect structures.

[0004] However, the traditional process for preparing high aspect ratio metal interconnect structures requires redefining additional masks for etching the interconnect structures, and places high requirements on the etching performance of the etching machine, resulting in high complexity and cost of the preparation process. Summary of the invention

[0005] Based on this, it is necessary to provide a semiconductor structure preparation method and a semiconductor structure to address the problems in the above-mentioned background technology, which can at least reduce the number of masks used and reduce the complexity and cost of the preparation process while improving the performance and reliability of preparing high aspect ratio metal interconnect structures.

[0006] According to various embodiments of the present disclosure, a first aspect of the present disclosure provides a method for preparing a semiconductor structure, comprising:

[0007] Providing a substrate, the substrate comprising a conductive layer, a first dielectric layer and a support stack stacked in sequence along a first direction vertical to a top surface of the substrate;

[0008] Based on the target mask, forming first through holes sequentially penetrating the support stack along a first direction;

[0009] Forming a target stack on the inner side wall of the first through hole, wherein the target stack defines a second through hole, wherein the second through hole exposes a portion of the first dielectric layer, and the target stack includes a target carbon layer and an isolation layer alternately stacked from outside to inside;

[0010] forming a dielectric stack covering the support stack, the target stack, and filling the second through hole;

[0011] Based on the target mask, forming a third through hole penetrating the dielectric stack along the first direction and exposing the target stack;

[0012] After simultaneously etching and removing the remaining dielectric stack and the isolation layer of a preset thickness in the second through hole through the third through hole, the first dielectric layer is overetched to obtain a groove exposing a portion of the conductive layer;

[0013] removing the target carbon layer to obtain the remaining isolation layers arranged at intervals;

[0014] A metal barrier layer is formed to cover the inner sidewall of the third through hole, the top surface of the remaining isolation layer, and the inner surface of the groove, wherein air gaps are included between adjacent remaining isolation layers.

[0015] The method for preparing the semiconductor structure in the above embodiment is to provide a conductive layer, a first dielectric layer and a support stack stacked in sequence along a first direction perpendicular to the top surface of the substrate on the substrate, and to form a first through hole that penetrates the support stack in sequence along the first direction based on a target mask; to form a target stack on the inner side wall of the first through hole, the target stack defines a second through hole, the second through hole exposes part of the first dielectric layer, the target stack includes a target carbon layer and an isolation layer alternately stacked from the outside to the inside, and the second through hole exposes the first dielectric layer; then, a dielectric stack covering the support stack and the target stack and filling the second through hole is formed, so that the depth-to-width ratio of the subsequent interconnect structure can be set by setting the number of film layers and the thickness of the film layers of the dielectric stack; then, based on the aforementioned target mask, a third through hole that penetrates the dielectric stack in the first direction and exposes the target stack is formed, and the shape, position and size of the third through hole are consistent with the shape, position and size of the first through hole, so that the preparation process requirements of the interconnect structure in various application scenarios can be met without increasing the additional mask development and design costs; Furthermore, after the remaining dielectric stack and the isolation layer of preset thickness in the second through hole are simultaneously etched and removed through the third through hole, the first dielectric layer is overetched to obtain a groove exposing a portion of the conductive layer, and then the target carbon layer is removed to obtain the remaining isolation layers arranged at intervals, so that after a metal barrier layer covering the inner side wall of the third through hole, the top surface of the remaining isolation layer, and the inner surface of the groove is formed, an air gap located between adjacent remaining isolation layers is obtained, so that the bottom of the metal interconnection structure subsequently formed in the third through hole is isolated from the surrounding dielectric side walls through the air gap, effectively improving the isolation effect; since the opening size of the second through hole is smaller than the opening size of the third through hole, a T-shaped metal interconnection structure is formed, avoiding the formation of voids or gaps at the bottom due to the decrease in kinetic energy of deposited metal ions during the process of depositing metal to form the metal interconnection structure, thereby improving the performance of the prepared metal interconnection structure; the metal barrier layer can prevent metal ions from entering the dielectric side walls during the subsequent deposition of metal to form the metal interconnection structure, and can effectively avoid the generation of current leakage channels, further improving the performance and reliability of the prepared metal interconnection structure.

[0016] In some embodiments, the support stack includes a third dielectric layer and a second dielectric layer located between the first dielectric layer and the third dielectric layer; under the same etching conditions, when the isolation layer of the target thickness is removed, the remaining dielectric stack in the second through hole is removed synchronously; the thickness of the third dielectric layer is related to the target thickness, so that after the remaining dielectric stack in the second through hole is removed, the isolation layer of the target thickness is removed during the process of over-etching the third dielectric layer through the second through hole.

[0017] In some embodiments, the innermost isolation layer of the target stack away from the supporting stack defines a second through hole, and the outermost target carbon layer of the target stack is adjacent to the second dielectric layer, so that after the target carbon layer is removed, the remaining isolation layer is adjacent to the second dielectric layer via an air gap, and the metal interconnect structure prepared subsequently is prevented from forming steps on the first dielectric layer, thereby reducing the impedance of the prepared metal interconnect structure.

[0018] In some embodiments, the dielectric stack includes at least two dielectric layers stacked in sequence along a first direction; wherein, the bottom dielectric layer of the at least two dielectric layers covers the third dielectric layer and the target stack, and is partially filled in the second through hole, so as to facilitate setting the number of film layers and the thickness of the film layers of the dielectric stack according to the aspect ratio of the metal interconnect structure prepared in different application scenarios, so as to meet the actual process requirements of different application scenarios; by setting the bottom dielectric layer of at least two dielectric layers to cover the third dielectric layer and the target stack, and to partially fill in the second through hole, the formation of different film layer interfaces in the second through hole is avoided, and arcing (Arcing) induced by the existence of the film layer interface is avoided, thereby improving the yield and reliability of the metal interconnect structure.

[0019] In some embodiments, forming the third through hole includes: obtaining a patterned photoresist layer located on the top surface of the dielectric stack based on the target photomask; etching the dielectric stack based on the patterned photoresist layer and using the third dielectric layer as an etch stop layer to obtain the third through hole. The shape, position and size of the third through hole are consistent with the shape, position and size of the first through hole. Therefore, without increasing the cost of additional mask development and design, by reusing the target photomask, the complexity and cost of the preparation process are reduced while improving the performance and reliability of the high aspect ratio metal interconnect structure.

[0020] In some embodiments, under the same etching conditions, the etching rates of the first dielectric layer and the isolation layer are the same, so that under the same etching conditions, the first dielectric layer and the isolation layer of the same thickness are removed simultaneously; while forming the groove, a remaining isolation layer having a top surface flush with the top surface of the second dielectric layer is obtained, so that after removing the target carbon layer, the remaining isolation layer arranged at intervals is obtained, so that after forming a metal barrier layer covering the inner side wall of the third through hole, the top surface of the remaining isolation layer, and the inner surface of the groove, an air gap is obtained between adjacent remaining isolation layers, so that the bottom of the metal interconnection structure subsequently formed in the third through hole is isolated from the surrounding dielectric side walls via the air gap.

[0021] In some embodiments, removing the target carbon layer includes: treating and removing the target carbon layer with a target gas containing ozone, wherein the target carbon layer is oxidized into carbon dioxide and water by the target gas containing ozone and then removed, thereby obtaining an isolation layer separated by an air gap.

[0022] In some embodiments, the target carbon layer includes α-carbon and / or fluorinated amorphous carbon.

[0023] In some embodiments, the isolation layer includes silicon nitride, silicon oxynitride, silicon carbide nitride, or a combination thereof.

[0024] In some embodiments, the first dielectric layer includes silicon, nitrogen, and carbon.

[0025] In some embodiments, the second aspect of the present disclosure provides a semiconductor structure, including a substrate and a metal barrier layer, the substrate including a conductive layer, a first dielectric layer and a support stack stacked in sequence along a first direction perpendicular to the top surface of the substrate; the support stack includes a first through hole extending along the first direction to the first dielectric layer; the first through hole includes isolation layers arranged in sequence and spaced apart along a second direction parallel to the top surface of the substrate, wherein the innermost isolation layer away from the support stack defines a groove exposing a portion of the conductive layer; the metal barrier layer at least covers a portion of the side wall of the first through hole, the top surface of the isolation layer, and the inner surface of the groove.

[0026] In some embodiments, the innermost isolation layer away from the support stack defines a second through hole exposing the groove; and the metal barrier layer further covers an inner sidewall of the second through hole.

[0027] In some embodiments, the semiconductor structure further includes a dielectric stack located on a top surface of the support stack; the first through hole also penetrates the dielectric stack along a first direction; and the metal barrier layer also extends into the dielectric stack along the first direction.

[0028] In some embodiments, the support stack includes a third dielectric layer, and a second dielectric layer located between the first dielectric layer and the third dielectric layer; and a top surface of the isolation layer is flush with a top surface of the second dielectric layer.

[0029] The unexpected technical effects that can be produced by the embodiments of the present disclosure include:

[0030] The bottom of the metal interconnect structure is isolated from the surrounding dielectric side walls by an air gap, which effectively improves the isolation effect; the T-shaped metal interconnect structure can avoid the appearance of voids or gaps at the bottom due to the decrease in kinetic energy of deposited metal ions during the process of depositing metal to form the metal interconnect structure, thereby improving the performance of the prepared metal interconnect structure; the metal barrier layer can prevent metal ions from entering the dielectric side walls during the subsequent process of depositing metal to form the metal interconnect structure, which can effectively avoid the generation of current leakage channels, further improving the performance and reliability of the prepared metal interconnect structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0032] Figure 1 Shown is a schematic flow chart of a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0033] Figure 2 It is a schematic diagram of a longitudinal cross-sectional structure of a semiconductor structure obtained after forming a first through hole in step S20 in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0034] Figure 3 It is a schematic diagram of a longitudinal cross-sectional structure of a semiconductor structure obtained after a target stack is formed in step S30 in a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0035] Figure 4 It is a schematic diagram of a longitudinal cross-sectional structure of a semiconductor structure obtained after a dielectric stack is formed in step S40 in a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0036] Figure 5 It is a schematic diagram of a longitudinal cross-sectional structure of a semiconductor structure obtained after forming a third through hole in step S50 in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0037] Figure 6 It is a schematic diagram of a longitudinal cross-sectional structure of a semiconductor structure obtained after removing the remaining dielectric stack in the second through hole in step S60 in a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0038] Figure 7It is a schematic diagram of a longitudinal cross-sectional structure of a semiconductor structure obtained after a groove is formed in step S60 in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0039] Figure 8 It is a schematic diagram of the longitudinal cross-sectional structure of a semiconductor structure obtained after removing the target carbon layer in step S70 in a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0040] Fig. 9 It is a schematic diagram of a longitudinal cross-sectional structure of a semiconductor structure obtained after a metal barrier layer is formed in step S80 in a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0041] Fig.10 It is a schematic diagram of a longitudinal cross-sectional structure of a semiconductor structure obtained after forming a first via hole and a second via hole in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0042] Fig.11 It is a schematic diagram of a longitudinal cross-sectional structure of a semiconductor structure obtained after forming a first dielectric layer in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0043] Fig.12 It is a schematic diagram of a longitudinal cross-sectional structure of a semiconductor structure obtained after forming a patterned photoresist layer in a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0044] Fig.13 It is a schematic diagram of a longitudinal cross-sectional structure of a semiconductor structure obtained after forming a second via hole in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0045] Fig.14 It is a schematic diagram of a longitudinal cross-sectional structure of a semiconductor structure obtained after the first dielectric layer is overetched through a second via hole in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0046] Fig.15 It is a schematic diagram of the longitudinal cross-sectional structure of a semiconductor structure obtained after removing a target carbon layer in a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0047] Fig.16 Shown is a schematic diagram of the longitudinal cross-sectional structure of a semiconductor structure obtained after a metal barrier layer is formed in a semiconductor structure preparation method provided in one embodiment of the present disclosure.

[0048] Description of reference numerals:

[0049] 100, substrate; 1, conductive layer; 2, first dielectric layer; 3, second dielectric layer; 4, third dielectric layer; PR, patterned photoresist layer; H1, first through hole; 20, target stack; 21, target carbon layer; 22, isolation layer; 51, first dielectric layer; 52, second dielectric layer; 53, third dielectric layer; 50, dielectric stack; H2, second through hole; H3, third through hole; H4, groove; 7, air gap; V1, first via hole; V2, second via hole; 9, metal barrier layer. DETAILED DESCRIPTION

[0050] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0051] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0052] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0053] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0054] When used herein, the singular forms "a", "an" and " / the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or components may be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0055] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic representations of ideal embodiments (and intermediate structures) of the present disclosure, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the present disclosure should not be limited to the particular shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the present disclosure.

[0056] It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present disclosure in a schematic manner. Although the illustrations only show components related to the present disclosure and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout type may also be more complicated.

[0057] The “stacked layer” or “stacked structure” in the embodiments of the present disclosure may include one layer or one layer.

[0058] See also Figure 1 In some embodiments, a method for preparing a semiconductor structure is provided, comprising: steps S10 to S80, wherein:

[0059] Step S10: providing a substrate, the substrate comprising a conductive layer, a first dielectric layer and a support stack stacked in sequence along a first direction vertical to a top surface of the substrate;

[0060] Step S20: Based on the target mask, forming first through holes that sequentially penetrate the support stack along a first direction;

[0061] Step S30: forming a target stack on the inner side wall of the first through hole, wherein the target stack defines a second through hole, the second through hole exposes a portion of the first dielectric layer, and the target stack includes a target carbon layer and an isolation layer alternately stacked from outside to inside;

[0062] Step S40: forming a dielectric stack covering the support stack, the target stack, and filling the second through hole;

[0063] Step S50: Based on the target mask, forming a third through hole penetrating the dielectric stack along the first direction and exposing the target stack;

[0064] Step S60: after simultaneously etching through the third through hole and removing the remaining dielectric stack and the isolation layer of a preset thickness in the second through hole, over-etching the first dielectric layer to obtain a groove exposing a portion of the conductive layer;

[0065] Step S70: removing the target carbon layer to obtain the remaining isolation layers arranged at intervals;

[0066] Step S80: forming a metal barrier layer covering the inner sidewall of the third through hole, the top surface of the remaining isolation layer, and the inner surface of the groove, wherein air gaps are included between adjacent remaining isolation layers.

[0067] Please continue reading Figure 1, by arranging a conductive layer, a first dielectric layer and a support stack in sequence along a first direction perpendicular to the top surface of the substrate on the substrate, after forming a first through hole that penetrates the support stack in sequence along the first direction based on a target mask; forming a target stack that defines a second through hole on the inner side wall of the first through hole, the target stack includes a target carbon layer and an isolation layer that are alternately stacked from the outside to the inside, and the second through hole exposes the first dielectric layer; then forming a dielectric stack that covers the support stack, the target stack, and fills the second through hole, so that the depth-to-width ratio of the subsequent interconnect structure can be set by setting the number of film layers and the thickness of the film layer of the dielectric stack; then, based on the aforementioned target mask, a third through hole that penetrates the dielectric stack in the first direction and exposes the target stack can be formed, and the shape, position and size of the third through hole are consistent with the shape, position and size of the first through hole, so that without increasing the additional mask research and development and design costs, it can meet the preparation process requirements of the interconnect structure in various different application scenarios; further, synchronously etching and removing through the third through hole After the remaining dielectric stack and the isolation layer of preset thickness are formed in the second through hole, the first dielectric layer is overetched to obtain a groove exposing a portion of the conductive layer, and then the target carbon layer is removed to obtain the remaining isolation layers arranged at intervals, so that after forming a metal barrier layer covering the inner side wall of the third through hole, the top surface of the remaining isolation layer, and the inner surface of the groove, an air gap located between adjacent remaining isolation layers is obtained, so that the bottom of the metal interconnection structure subsequently formed in the third through hole is isolated from the surrounding dielectric side walls via the air gap, effectively improving the isolation effect; since the opening size of the second through hole is smaller than the opening size of the third through hole, a T-shaped metal interconnection structure is formed, avoiding the formation of voids or gaps at the bottom due to the decrease in the kinetic energy of the deposited metal ions during the process of depositing metal to form the metal interconnection structure, thereby improving the performance of the prepared metal interconnection structure; the metal barrier layer can prevent metal ions from entering the dielectric side walls during the subsequent deposition of metal to form the metal interconnection structure, and can effectively avoid the generation of current leakage channels, further improving the performance and reliability of the prepared metal interconnection structure.

[0068] See also Figure 2 In some embodiments, the material of the substrate 100 provided in step S10 may include but is not limited to semiconductor materials, insulating materials, conductor materials, or any combination thereof. The substrate 100 is a semiconductor structure that provides mechanical support and electrical properties for manufacturing a semiconductor structure. The substrate 100 may be a single-layer structure or a multi-layer structure. For example, the substrate 100 may be a III / V semiconductor substrate or a II / VI semiconductor substrate. Those skilled in the art may select the type of substrate 100 according to the type of transistor formed on the substrate 100, so the type of substrate 100 should not limit the scope of protection of the present disclosure.

[0069] As an example, see Figure 2, on the substrate 100, along a direction away from the substrate 100, for example, in the OY direction, a conductive layer 1, a first dielectric layer 2, a second dielectric layer 3 and a third dielectric layer 4 are stacked in sequence, and the second dielectric layer 3 and the third dielectric layer 4 are used to jointly constitute a support stack (not shown); the conductive layer 1, the first dielectric layer 2, the second dielectric layer 3 and the third dielectric layer 4 can be formed in sequence by chemical vapor deposition or physical vapor deposition (PVD) and other processes, and the chemical vapor deposition process method can include but is not limited to atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PVD). One or more of the above methods may be used. For example, low-pressure chemical vapor deposition has good step coverage. The use of low-pressure chemical vapor deposition can increase the deposition rate and output and reduce the process cost. Low-pressure chemical vapor deposition does not require a carrier gas and can reduce particle contamination.

[0070] As an example, see Figure 2 In step S20, a photoresist material layer (not shown) may be coated on the top surface of the third dielectric layer 4, and then the photoresist material layer may be patterned based on the target mask to obtain a patterned photoresist layer PR including an opening pattern for defining parameters such as the shape, size and position of the first through hole, and then the third dielectric layer 4 and the second dielectric layer 3 may be etched based on the patterned photoresist layer PR to obtain a first through hole H1 that sequentially penetrates the third dielectric layer 4 and the second dielectric layer 3 along a first direction, such as the OY direction, and the first through hole H1 exposes a portion of the first dielectric layer 2. The material of the first dielectric layer 2 may include, but is not limited to, a doped silicon carbide (NDC) film, and the NDC film contains silicon, nitrogen and carbon. The material of the second dielectric layer 3 may include, but is not limited to, silicon oxide, tetraethyl orthosilicate (TEOS), etc., or a combination thereof. The material of the third dielectric layer 4 may include, but is not limited to, silicon nitride, silicon oxynitride, silicon carbide nitride, etc., or a combination thereof. The material of the conductive layer 1 may include, but is not limited to, titanium, tungsten, nickel, cobalt, silver, cobalt silicide, aluminum, palladium, copper, etc. or a combination thereof.

[0071] As an example, see Figure 2-Figure 3The thickness of the first dielectric layer 2 may be 400 angstroms to 1200 angstroms, for example, the thickness of the first dielectric layer 2 may be 400 angstroms, 600 angstroms, 800 angstroms, 1000 angstroms or 1200 angstroms, etc. The thickness of the second dielectric layer 3 may be 5000 angstroms to 7000 angstroms, for example, the thickness of the second dielectric layer 3 may be 5000 angstroms, 6000 angstroms or 7000 angstroms, etc. The thickness of the third dielectric layer 4 may be 1500 angstroms to 2500 angstroms, for example, the thickness of the third dielectric layer 4 may be 1500 angstroms, 2000 angstroms or 2500 angstroms, etc.

[0072] As an example, see Figure 2-Figure 3 In step S30, after removing the patterned photoresist layer PR, a target stack 20 can be formed on the inner side wall of the first through hole H1, and the target stack 20 defines a second through hole H2, and the second through hole H2 exposes a portion of the first dielectric layer 2. The target stack 20 includes a target carbon layer 21 and an isolation layer 22 alternately stacked from the outside to the inside.

[0073] As an example, see Figure 3 , the opening size of the first through hole H1 may be 1.6 μm-1.8 μm, for example, the opening size of the first through hole H1 may be 1.6 μm, 1.7 μm or 1.8 μm, etc. The opening size of the second through hole H2 may be 300 nm-500 nm, for example, the opening size of the second through hole H2 may be 300 nm, 400 nm or 500 nm, etc. The opening size may refer to the length along the OX direction.

[0074] As an example, see Figure 3 , the thickness of the target carbon layer 21 is less than half of the thickness of the isolation layer 22, and the thickness in the embodiment of the present disclosure is the length along the OX direction. The thickness of the target carbon layer 21 can be 10nm-20nm, for example, the thickness of the target carbon layer 21 can be 10nm, 13nm, 15nm, 18nm or 20nm, etc. The thickness of the isolation layer 22 can be determined according to the opening size of the second through hole H2 and the thickness and number of the target carbon layer 21. For example, the opening size of the first through hole H1 is 1.7μm, the opening size of the second through hole H2 is 324 nm, the thickness of the target carbon layer 21 is 10nm, and the number of stacked layers of the target carbon layer 21 is 2, then the thickness of the isolation layer 22 can be 3500nm-4500nm, for example, the thickness of the isolation layer 22 can be 3500nm, 3800nm, 4000nm, 4200nm, 4300nm or 4500nm, etc.

[0075] As an example, see Figure 2-Figure 3In step S30, the target carbon layer 21 and the isolation layer 22 can be alternately deposited in sequence to form an alternately stacked target carbon layer 21 and an isolation layer 22. The alternately stacked target carbon layer 21 and the isolation layer 22 are used to jointly constitute the target stack 20. The innermost isolation layer 22 of the target stack 20 away from the support stack defines the second through hole H2. The outermost target carbon layer 21 of the target stack 20 is adjacent to the second dielectric layer 3, so that after the target carbon layer 21 is removed, the remaining isolation layer 22 is adjacent to the second dielectric layer 3 through the air gap 7, and the metal interconnection structure prepared later is prevented from forming a step on the first dielectric layer 2, thereby reducing the impedance of the prepared metal interconnection structure. Then, the target carbon layer 21 and the isolation layer 22 located on the top surface of the third dielectric layer 4 are removed, and the target carbon layer 21 and the isolation layer 22 exposed by the second through hole H2 are removed until the second through hole H2 exposes part of the top surface of the first dielectric layer 2. The patterned photoresist layer PR can protect and prevent the third dielectric layer 4 from being damaged during the etching of the target carbon layer 21 and the isolation layer 22. Furthermore, the patterned photoresist layer PR can be removed simultaneously during the process of removing the target carbon layer 21 and the isolation layer 22 on the top surface of the third dielectric layer 4, thereby avoiding the step of separately removing the patterned photoresist layer PR on the top surface of the third dielectric layer 4, thereby reducing the complexity and cost of the preparation process.

[0076] As an example, see Figure 2-Figure 3 The material of the target carbon layer 21 may include but is not limited to α-carbon, fluorinated amorphous carbon, etc. or a combination thereof. The isolation layer 22 includes silicon nitride, silicon oxynitride, silicon carbonitride, etc. or a combination thereof.

[0077] As an example, see Figure 3-Figure 4 In step S40, a deposition process or a spin-on glass coating (SOG) process can be used to form a dielectric stack 50 covering the third dielectric layer 4, the target stack 20, and filling the second through hole H2. The dielectric stack 50 includes at least two dielectric layers stacked in sequence along the first direction; wherein the bottom dielectric layer of the at least two dielectric layers covers the third dielectric layer 4 and the target stack 20, and partially fills the second through hole H2, so as to facilitate setting the number of film layers and the thickness of the film layers of the dielectric stack 50 according to the aspect ratio of the metal interconnect structure prepared in different application scenarios, so as to meet the actual process requirements of different application scenarios; by setting the bottom dielectric layer of at least two dielectric layers to cover the third dielectric layer 4 and the target stack 20, and partially fill the second through hole H2, the formation of different film layer interfaces in the second through hole H2 is avoided, and arcing is avoided due to the existence of the film layer interface, so as to improve the yield and reliability of the prepared metal interconnect structure.

[0078] As an example, see Figure 4, at least two dielectric layers may include a first dielectric layer 51, a second dielectric layer 52, and a third dielectric layer 53 stacked in sequence along the OY direction, wherein the first dielectric layer 51 covers the third dielectric layer 4, the target stack 20, and fills the second through hole H2, and the first dielectric layer 51 may be TEOS. For example, the first dielectric layer 51 may be formed by a SOG process, and then the top surface of the first dielectric layer 51 is planarized, and then the second dielectric layer 52 is formed on the top surface of the first dielectric layer 51, and the second dielectric layer 52 may be silicon oxide or TEOS; after the top surface of the second dielectric layer 52 is planarized, the third dielectric layer 53 is formed on the top surface of the second dielectric layer 52, and the third dielectric layer 53 may be silicon oxide or TEOS.

[0079] As an example, see Figure 4 The thickness of the first dielectric layer 51 and the second dielectric layer 52 can be the same, for example, both are the maximum thickness that can be deposited by a single process of the deposition machine. Since the thickness of the first dielectric layer 51 and the second dielectric layer 52 still cannot meet the extension height requirement of the subsequent preparation of the metal interconnection structure, the third dielectric layer 53 is further formed, so that the dielectric stack 50 composed of the first dielectric layer 51, the second dielectric layer 52, and the third dielectric layer 53 can meet the extension height requirement of the metal interconnection structure.

[0080] As an example, see Figure 4-Figure 5 In step S50, after the top surface of the third dielectric layer 53 is planarized, a photoresist material layer (not shown) is coated on the top surface of the third dielectric layer 53, and then the photoresist material layer is patterned based on the target mask to obtain a patterned photoresist layer PR including an opening pattern for defining parameters such as the shape, size and position of the third through hole H3. Then, based on the patterned photoresist layer PR, the third dielectric layer 53, the second dielectric layer 52 and the first dielectric layer 51 are etched with the top surface of the third dielectric layer 4 as the etching end point to obtain the target stack 20 and the remaining dielectric stack 50 whose top surfaces are flush with the top surface of the third dielectric layer 4, and form the third through hole H3 that penetrates the third dielectric layer 53, the second dielectric layer 52 and the first dielectric layer 51 along the OY direction and exposes the top surface of the target stack 20.

[0081] As an example, see Figure 5-Figure 6, it can be set that under the same etching conditions, the etching rate of the remaining dielectric stack 50 is significantly greater than the etching rate of the isolation layer 22, and the etching rate of the target carbon layer 21 is much lower than the etching rate of the remaining dielectric stack 50 and the etching rate of the isolation layer 22. For example, the remaining dielectric stack 50 is TEOS, the isolation layer 22 is silicon nitride, and the target carbon layer 21 is α-carbon or fluorinated amorphous carbon. Under the same etching conditions, the etching rate of silicon nitride is significantly lower than the etching rate of TEOS, and α-carbon or fluorinated amorphous carbon will basically not be etched. If the height of the remaining isolation layer 22 after the remaining dielectric stack 50 in the second through hole H2 is removed is d2, and the initial thickness of the isolation layer 22 flush with the top surface of the third dielectric layer 4 is d1, then during the removal of the remaining dielectric stack 50 in the second through hole H2, the thickness of the isolation layer 22 removed synchronously is d1-d2. Therefore, the height of the isolation layer 22 and the height of the remaining dielectric stack 50 in the second through hole H2 can be set according to the etching selectivity ratio between the isolation layer 22 and the remaining dielectric stack 50 in the second through hole H2 .

[0082] As an example, see Figure 6-Figure 7 In step S60, when the isolation layer 22 of the target thickness is removed under the same etching conditions, the remaining dielectric stack 50 in the second through hole H2 is removed simultaneously; the thickness of the third dielectric layer 4 is related to the target thickness, so that after the remaining dielectric stack 50 in the second through hole H2 is removed, the isolation layer 22 of the target thickness is removed during the process of over-etching the third dielectric layer 4 through the second through hole H2.

[0083] As an example, see Figure 6-Figure 7 , in step S60, the etching rate of the isolation layer 22 can be set to be substantially the same as the etching rate of the first dielectric layer 2 under the same etching conditions. If the first dielectric layer 2 exposed by the second through hole H2 is removed, a groove H4 exposing a portion of the conductive layer 1 and a remaining isolation layer 22 whose top surface is flush with the top surface of the second dielectric layer 3 are obtained. At this time, the height of the remaining isolation layer 22 is d3. In the process of removing the first dielectric layer 2 exposed by the second through hole H2, the thickness of the isolation layer 22 removed is d2-d3. Therefore, the thickness of the first dielectric layer 2 can be set to d2-d3. In the process of removing the first dielectric layer 2 exposed by the second through hole H2, a remaining isolation layer 22 whose top surface is flush with the top surface of the second dielectric layer 3 is obtained simultaneously.

[0084] As an example, see Figure 8In step S70, a target gas containing ozone may be used to treat and remove the target carbon layer 21. Ozone (O3), as a strong oxidant, has a very strong oxidizing ability and can react with amorphous carbon to oxidize it into smaller molecules, such as carbon dioxide and water. This reaction is usually carried out under low temperature conditions, and the oxidative decomposition of amorphous carbon is achieved through direct contact between ozone and amorphous carbon. In this way, the target carbon layer 21 is removed, and an air gap 7 is obtained between the adjacent remaining isolation layers 22, and oxidation of the exposed surface of the conductive layer 1 by high temperature can be avoided.

[0085] As an example, see Fig. 9 Since the size of the air gap 7 is smaller than half of the size of the remaining isolation layer 22, which size refers to the length along the OX direction, in the process of depositing and forming the metal barrier layer 9 in step S80, since the opening size of the air gap 7 is small, it is generally sealed in advance. After the metal barrier layer covering the inner side wall of the third through hole H3, the top surface of the remaining isolation layer 22, and the inner surface of the groove H4 is formed, the air gap 7 is included between adjacent remaining isolation layers 22 to reduce the dielectric constant between the metal interconnection structure and the dielectric side wall formed in the third through hole H3 and the groove H4, and avoid the generation of a current leakage channel between the metal interconnection structure and the dielectric side wall. Since the opening size of the second through hole H2 is smaller than the opening size of the third through hole H3, it is convenient to form a T-shaped metal interconnection structure subsequently, and the performance of the prepared metal interconnection structure can be improved by avoiding the formation of voids or gaps at the bottom due to the decrease in the kinetic energy of the deposited metal ions during the process of depositing metal to form the metal interconnection structure; the metal barrier layer 9 can prevent metal ions from entering the dielectric side wall during the subsequent process of depositing metal to form the metal interconnection structure, and can effectively avoid the generation of current leakage channels, thereby further improving the performance and reliability of the prepared metal interconnection structure.

[0086] In some embodiments, a semiconductor structure is provided, which can be manufactured using any semiconductor structure manufacturing method in any of the embodiments of the present disclosure.

[0087] Please continue reading Fig. 9 In some embodiments, the semiconductor structure includes a substrate 100 and a metal barrier layer 9, the substrate 100 includes a conductive layer 1, a first dielectric layer 2 and a support stack (not shown) stacked in sequence along a first direction perpendicular to the top surface of the substrate 100; the support stack includes a first through hole H1 extending along the first direction to the top surface of the first dielectric layer 2; the first through hole H1 includes isolation layers 22 arranged in sequence along a second direction parallel to the top surface of the substrate 100, wherein the innermost isolation layer 22 away from the support stack defines a groove H4 exposing a portion of the conductive layer 1; the metal barrier layer 9 at least covers a portion of the sidewall of the first through hole H1, the top surface of the isolation layer 22, and the inner surface of the groove H4.

[0088] As an example, see Figure 8-Figure 9 The innermost isolation layer 22 away from the support stack defines a second through hole H2 exposing the groove H4; the metal barrier layer 9 also covers the inner sidewall of the second through hole H2.

[0089] As an example, see Figure 8-Figure 9 The semiconductor structure further includes a dielectric stack 50, which is located on the top surface of the support stack; the first through hole H1 also penetrates the dielectric stack 50 along the first direction; and the metal barrier layer 9 also extends into the dielectric stack 50 along the first direction.

[0090] As an example, see Figure 8-Figure 9 The supporting stack includes a third dielectric layer 4 and a second dielectric layer 3 located between the first dielectric layer 2 and the third dielectric layer 4 ; the top surface of the isolation layer 22 is flush with the top surface of the second dielectric layer 3 .

[0091] As an example, see Fig.10 ,and Figure 3 The differences include: Figure 3 The top surface of the second dielectric layer 3 includes a third dielectric layer 4, Fig.10 The first via hole V1 in the second dielectric layer 3 passes through the second dielectric layer 3 along the OY direction, exposing a portion of the top surface of the first dielectric layer 2 . Figure 3 In the embodiment, the inner surface of the first via hole V1 includes a target carbon layer 21 and an isolation layer 22 alternately stacked from the outside to the inside. The preparation process of the target carbon layer 21 and the isolation layer 22 can be referred to. Figure 3 The preparation process of the target carbon layer 21 and the isolation layer 22 will not be described in detail here.

[0092] As an example, see Fig.10 , the thickness of the target carbon layer 21 is less than half of the thickness of the isolation layer 22, and the thickness in the embodiment of the present disclosure is the length along the OX direction. The thickness of the target carbon layer 21 can be 10nm-20nm, for example, the thickness of the target carbon layer 21 can be 10nm, 13nm, 15nm, 18nm or 20nm, etc. The thickness of the isolation layer 22 can be determined according to the opening size of the second via V2 and the thickness and number of the target carbon layer 21. For example, the opening size of the first via V1 is 1.7μm, the opening size of the second via V2 is 324 nm, the thickness of the target carbon layer 21 is 10nm, and the number of stacked layers of the target carbon layer 21 is 2, then the thickness of the isolation layer 22 can be 3500nm-4500nm, for example, the thickness of the isolation layer 22 can be 3500nm, 3800nm, 4000nm, 4200nm, 4300nm or 4500nm, etc. The material of the target carbon layer 21 may include, but is not limited to, α-carbon, fluorinated amorphous carbon, etc. or a combination thereof. The isolation layer 22 may include silicon nitride, silicon oxynitride, silicon carbonitride, etc. or a combination thereof.

[0093] As an example, see Fig.11 , a first dielectric layer 51 is formed by chemical vapor deposition (CVD) to cover the top surface of the target carbon layer 21, the top surface of the isolation layer 22, and the top surface of the second dielectric layer 3. The first dielectric layer 51 may be TEOS. Since CVD has good step coverage, it is easy to form a bubble V2a connected to the second via hole V2 above the second via hole V2.

[0094] As an example, see Fig.12 After the top surface of the first dielectric layer 51 is planarized, a second dielectric layer 52 is formed on the top surface of the first dielectric layer 51. The second dielectric layer 52 may be silicon oxide or TEOS. After the top surface of the second dielectric layer 52 is planarized, a third dielectric layer 53 is formed on the top surface of the second dielectric layer 52. The third dielectric layer 53 may be silicon oxide or TEOS.

[0095] As an example, see Figure 12-13 After the top surface of the third dielectric layer 53 is planarized, a photoresist material layer (not shown) is coated on the top surface of the third dielectric layer 53, and then the photoresist material layer is patterned based on the target mask to obtain a patterned photoresist layer PR including an opening pattern for defining parameters such as the shape, size and position of the first via hole V1, and then based on the patterned photoresist layer PR, the third dielectric layer 53, the second dielectric layer 52 and the first dielectric layer 51 are etched with the top surface of the second dielectric layer 3 as the etching end point to obtain a target carbon layer 21 and an isolation layer 22 whose top surfaces are flush with the top surface of the second dielectric layer 3.

[0096] As an example, see Fig.14 , the first dielectric layer 2 is overetched through the second via hole V2, so that the second via hole V2 exposes a portion of the top surface of the conductive layer 1.

[0097] As an example, see Fig.15 The target carbon layer 21 is treated and removed by a target gas containing ozone to obtain an air gap 7 between adjacent remaining isolation layers 22, and oxidation of the exposed surface of the conductive layer 1 by high temperature can be avoided.

[0098] As an example, see Fig.16Since the size of the air gap 7 is smaller than half of the size of the remaining isolation layer 22, which refers to the length along the OX direction, during the process of depositing and forming the metal barrier layer 9, the opening size of the air gap 7 is small, so it is generally sealed in advance. After the metal barrier layer 9 covering the inner side wall of the second via hole V2 and the top surface of the remaining isolation layer 22 is formed, the air gap 7 is included between adjacent remaining isolation layers 22 to reduce the dielectric constant between the metal interconnection structure and the dielectric side wall formed in the second via hole V2, and avoid the generation of a current leakage channel between the metal interconnection structure and the dielectric side wall. Since the opening size of the second via hole V2 is smaller than the opening size of the first via hole V1, it is convenient to form a T-shaped metal interconnection structure in the subsequent process, and avoid the formation of voids or gaps at the bottom due to the decrease in the kinetic energy of the deposited metal ions during the process of depositing metal to form the metal interconnection structure, thereby improving the performance of the prepared metal interconnection structure; the metal barrier layer 9 can prevent metal ions from entering the dielectric side wall during the subsequent process of depositing metal to form the metal interconnection structure, and can effectively avoid the generation of current leakage channels, further improving the performance and reliability of the prepared metal interconnection structure.

[0099] In some embodiments, see Fig. 9 or Fig.16 , provides a semiconductor structure, including: a semiconductor structure prepared by using any semiconductor structure preparation method in any embodiment of the present disclosure.

[0100] The unexpected technical effects that can be produced by the embodiments of the present disclosure include:

[0101] The bottom of the metal interconnect structure is isolated from the surrounding dielectric side walls by an air gap, which effectively improves the isolation effect; the T-shaped metal interconnect structure can avoid the appearance of voids or gaps at the bottom due to the decrease in kinetic energy of deposited metal ions during the process of depositing metal to form the metal interconnect structure, thereby improving the performance of the prepared metal interconnect structure; the metal barrier layer can prevent metal ions from entering the dielectric side walls during the subsequent deposition of metal to form the metal interconnect structure, which can effectively avoid the generation of current leakage channels, thereby further improving the performance and reliability of the prepared metal interconnect structure.

[0102] In some embodiments, an electronic device is provided, comprising the semiconductor structure in any one of the embodiments of the present disclosure.

[0103] The aforementioned electronic devices include, but are not limited to, suitable types of electronic products such as consumer electronic products, home electronic products, vehicle-mounted electronic products, and financial terminal products. Among them, consumer electronic products include mobile phones, tablet computers, laptop computers, desktop monitors, all-in-one computers, etc. Home electronic products include smart door locks, televisions, refrigerators, wearable devices, etc. Vehicle-mounted electronic products include vehicle-mounted navigation systems and vehicle-mounted DVDs, etc. Financial terminal products include ATM machines and self-service terminals, etc.

[0104] Please note that for the sake of simplicity of the specification, in the structural schematic diagrams given in the embodiments below, unless the corresponding cross-sectional structural schematic diagrams are given separately, other structural schematic diagrams of different perspectives of structures related to the inventive points of the embodiments of the present disclosure can refer to each other.

[0105] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0106] The above-described embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure shall be subject to the attached claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a conductive layer, a first dielectric layer and a support stack stacked in sequence along a first direction perpendicular to the top surface of the substrate; Based on the target mask, forming first through holes sequentially penetrating the support stack along the first direction; forming a target stack on the inner sidewall of the first through hole, wherein the target stack defines a second through hole exposing a portion of the first dielectric layer, and the target stack includes a target carbon layer and an isolation layer alternately stacked from outside to inside; forming a dielectric stack covering the support stack, the target stack, and filling the second through hole; Based on the target mask, forming a third through hole penetrating the dielectric stack along the first direction and exposing the target stack; After simultaneously etching and removing the remaining dielectric stack and the isolation layer of a preset thickness in the second through hole through the third through hole, the first dielectric layer is overetched to obtain a groove exposing a portion of the conductive layer; removing the target carbon layer to obtain the remaining isolation layers arranged at intervals; forming a metal barrier layer covering the inner sidewall of the third through hole, the top surface of the remaining isolation layer, and the inner surface of the groove, wherein air gaps are included between adjacent remaining isolation layers; The support stack includes a third dielectric layer, and a second dielectric layer located between the first dielectric layer and the third dielectric layer; Under the same etching conditions, when removing the isolation layer of target thickness, the remaining dielectric stack in the second through hole is removed synchronously; The thickness of the third dielectric layer is related to the target thickness.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The second through hole is defined by the innermost isolation layer of the target stack away from the support stack.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that: The dielectric stack comprises at least two dielectric layers sequentially stacked along the first direction; Wherein, the bottom dielectric layer of the at least two dielectric layers covers the third dielectric layer and the target stack, and partially fills the second through hole.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that: Forming the third through hole comprises: obtaining a patterned photoresist layer located on a top surface of the dielectric stack based on the target photomask; Based on the patterned photoresist layer and using the third dielectric layer as an etching stop layer, the dielectric stack is etched to obtain the third through hole.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that: Under the same etching conditions, the etching rates of the first dielectric layer and the isolation layer are the same; While forming the groove, a remaining isolation layer is obtained whose top surface is flush with the top surface of the second dielectric layer.

6. The method for preparing a semiconductor structure according to any one of claims 1 to 3, characterized in that: Removing the target carbon layer comprises: The target carbon layer is treated and removed using a target gas containing ozone.

7. The method for preparing a semiconductor structure according to any one of claims 1 to 3, characterized in that: Includes at least one of the following features: The target carbon layer includes α-carbon and / or fluorinated amorphous carbon; The isolation layer comprises silicon nitride, silicon oxynitride, silicon carbide nitride or a combination thereof; The first dielectric layer includes silicon, nitrogen and carbon.

8. A semiconductor structure, characterized in that: The semiconductor structure is prepared by the semiconductor structure preparation method according to any one of claims 1 to 7, wherein the semiconductor structure comprises: A substrate, the substrate comprising a conductive layer, a first dielectric layer and a support stack stacked in sequence along a first direction perpendicular to the top surface of the substrate; the support stack comprises a first through hole extending along the first direction to the first dielectric layer; the first through hole comprises isolation layers arranged in sequence along a second direction parallel to the top surface of the substrate, wherein the innermost isolation layer away from the support stack defines a groove exposing a portion of the conductive layer; The metal barrier layer at least covers a portion of the sidewall of the first through hole, the top surface of the isolation layer, and the inner surface of the groove.

9. The semiconductor structure according to claim 8, characterized in that: An innermost isolation layer away from the support stack defines a second through hole exposing the groove; The metal barrier layer also covers the inner sidewall of the second through hole.

10. The semiconductor structure according to claim 8, characterized in that Also includes: a dielectric stack located on a top surface of the support stack; The first through hole also penetrates the dielectric stack along the first direction; The metal barrier layer also extends into the dielectric stack along the first direction.

11. The semiconductor structure according to claim 8, characterized in that: The support stack includes a third dielectric layer, and a second dielectric layer located between the first dielectric layer and the third dielectric layer; The top surface of the isolation layer is flush with the top surface of the second dielectric layer.

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