Semiconductor device

Abstract

The embodiment of the invention relates to a semiconductor device. A semiconductor device includes a semiconductor substrate, a first coil, a second coil, a third coil, and a fourth coil, an insulating layer, and a first shield. The semiconductor substrate has a device region and a peripheral region. In a plan view, the peripheral region is present around the device region. The first coil and the second coil are arranged on the device region and in a first direction in a plan view. The third coil and the fourth coil are respectively opposite to the first coil and the second coil through the insulating layer. The first shield is disposed between the semiconductor substrate and the first coil and the second coil and overlaps the first coil and the second coil in a plan view. A width of the first shield in a second direction orthogonal to the first direction is greater than a width of the first coil in the second direction and a width of the second coil in the second direction. The first shield is electrically connected to a reference potential.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2023-113612 filed on Jul. 11, 2023 (including specification, drawings and abstract) is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a semiconductor device. Background Art

[0004] The disclosed technologies are listed below.

[0005] [Patent Document 1] International Publication No. 2014 / 097425

[0006] Patent document 1 discloses a semiconductor device. The semiconductor device disclosed in patent document 1 has a plurality of transformers. Each transformer is composed of coils facing each other via an insulating layer. Each of the plurality of transformers forms a channel for transmitting and receiving signals. Summary of the invention

[0007] In the semiconductor device described in Patent Document 1, crosstalk may occur between channels. Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

[0008] The semiconductor device of the present disclosure includes a semiconductor substrate, a first coil, a second coil, a third coil and a fourth coil, an insulating layer and a first shield. The semiconductor substrate has a device area and a peripheral area. In a plan view, the peripheral area exists around the device area. The first coil and the second coil are arranged on the device area and are arranged in a first direction in the plan view. The third coil and the fourth coil are respectively opposite to the first coil and the second coil via the insulating layer. The first shield is arranged between the semiconductor substrate and the first coil and the second coil and overlaps with the first coil and the second coil in a plan view. The width of the first shield in a second direction orthogonal to the first direction is greater than the width of the first coil in the second direction and the width of the second coil in the second direction. The first shield is electrically connected to a reference potential.

[0009] According to the semiconductor device of the present disclosure, crosstalk between channels can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a block diagram of a semiconductor device DEV1.

[0011] Figure 2 is an explanatory diagram showing an example of signal transmission from the control circuit CC to the drive circuit DR.

[0012] Figure 3 is a first plan view of the semiconductor chip CHP3.

[0013] Figure 4 is a second plan view of the semiconductor chip CHP3.

[0014] Figure 5 is a third plan view of the semiconductor chip CHP3.

[0015] Fig. 6A It is along Figure 5 A cross-sectional view taken along line VIA-VIA in FIG.

[0016] Figure 6B It is along Figure 5 A cross-sectional view taken along line VIB-VIB in FIG.

[0017] Figure 7 This is a diagram of the manufacturing process of the semiconductor chip CHP3.

[0018] Figure 8 is a cross-sectional view for describing the ion implantation step S2.

[0019] Fig. 9 is a cross-sectional view for describing the first insulating film forming step S3.

[0020] Fig.10 is a cross-sectional view for describing the first via plug forming step S4.

[0021] Fig.11 is a cross-sectional view for describing the shield forming step S5.

[0022] Fig.12 is a cross-sectional view for describing the second insulating film forming step S6.

[0023] Fig.13 is a cross-sectional view for describing the second via plug forming step S7.

[0024] Fig.14 is a cross-sectional view for describing the first coil forming step S8.

[0025] Fig.15 is a cross-sectional view for describing the third insulating film forming step S9.

[0026] Fig.16 is a cross-sectional view for describing the third via plug forming step S10 .

[0027] Fig.17 is a cross-sectional view for describing the wiring forming step S11.

[0028] Fig.18is a cross-sectional view for describing the second coil forming step S12.

[0029] Fig.19 is a plan view of the semiconductor chip CHP3 in the semiconductor device DEV2.

[0030] Fig. 20 is a plan view of the semiconductor chip CHP3 in the semiconductor device DEV3.

[0031] Fig.21 is a plan view of the semiconductor chip CHP3 in the semiconductor device DEV4.

[0032] Fig. 22 is a plan view of the semiconductor chip CHP3 in the semiconductor device DEV5.

[0033] Fig.23 It is along Fig. 22 A cross-sectional view taken along line XXIII-XXIII in FIG.

[0034] Fig.24 is a plan view of the semiconductor chip CHP3 in the semiconductor device DEV6.

[0035] Fig.25 It is along Fig.24 A cross-sectional view taken along line XXV-XXV in FIG.

[0036] Fig.26 is a cross-sectional view of a semiconductor chip CHP3 according to a modification of the semiconductor device DEV6. DETAILED DESCRIPTION

[0037] Embodiments of the present disclosure will be described with reference to the accompanying drawings. In the following drawings, the same or equivalent components are represented by the same reference numerals, and the repeated description will not be repeated.

[0038] (First embodiment)

[0039] A semiconductor device according to a first embodiment will be described. The semiconductor device according to the first embodiment is referred to as a semiconductor device DEV1.

[0040] (Configuration of semiconductor device DEV1)

[0041] The configuration of the semiconductor device DEV1 will be described below.

[0042] <General Configuration of Semiconductor Device DEV1>

[0043] The general configuration of the semiconductor device DEV1 will be described below.

[0044] Figure 1 is a block diagram of a semiconductor device DEV1. Figure 1 As shown in , the semiconductor device DEV1 includes semiconductor chips CHP1 , CHP2 , and CHP3 .

[0045] The semiconductor chip CHP1 includes a control circuit CC, a transmission circuit TX1, and a reception circuit RX2. The semiconductor chip CHP2 includes a drive circuit DR, a reception circuit RX1, and a transmission circuit TX2. The transmission circuit TX1 and the reception circuit RX2 are electrically connected to the control circuit CC. The reception circuit RX1 and the transmission circuit TX2 are electrically connected to the drive circuit DR.

[0046] The semiconductor chip CHP3 includes transformers TR1 and TR2 and leads PL1 and PL2.

[0047] The transformer TR1 includes a transmitting coil CL1 and a receiving coil CL2. The transmitting coil CL1 includes a coil CL11 and a coil CL12, and the receiving coil CL2 includes a coil CL21 and a coil CL22. The transmitting coil CL1 and the receiving coil CL2 are electrically connected to a transmitting circuit TX1 and a receiving circuit RX1, respectively.

[0048] More specifically, one end of the coil CL11 is electrically connected to the transmission circuit TX1, the other end of the coil CL11 is electrically connected to one end of the coil CL12, and the other end of the coil CL12 is electrically connected to the transmission circuit TX1. In addition, one end of the coil CL21 is electrically connected to the receiving circuit RX1, the other end of the coil CL21 is electrically connected to one end of the coil CL22 through the lead PL1, and the other end of the coil CL22 is electrically connected to the receiving circuit RX1. The lead PL1 is connected to a reference potential. It should be noted that the reference potential is, for example, a ground potential.

[0049] The transformer TR2 includes a transmitting coil CL3 and a receiving coil CL4. The transmitting coil CL3 includes a coil CL31 and a coil CL32, and the receiving coil CL4 includes a coil CL41 and a coil CL42. The transmitting coil CL3 and the receiving coil CL4 are electrically connected to the transmitting circuit TX2 and the receiving circuit RX2, respectively.

[0050] More specifically, one end of the coil CL31 is electrically connected to the transmission circuit TX2, the other end of the coil CL31 is electrically connected to one end of the coil CL32, and the other end of the coil CL32 is electrically connected to the transmission circuit TX2. In addition, one end of the coil CL41 is electrically connected to the receiving circuit RX2, the other end of the coil CL41 is electrically connected to one end of the coil CL42 through the lead PL2, and the other end of the coil CL42 is electrically connected to the receiving circuit RX2. The lead PL2 is connected to a reference potential.

[0051] In the semiconductor device DEV1, a signal is transmitted from the control circuit CC to the drive circuit DR via the transmission circuit TX1, transformer TR1 and reception circuit RX1. Also, in the semiconductor device DEV1, a signal is transmitted from the drive circuit DR to the control circuit CC via the transmission circuit TX2, transformer TR2 and reception circuit RX2.

[0052] Figure 2 1 is an explanatory diagram showing an example of signal transmission from the control circuit CC to the drive circuit DR. Figure 2 As shown in , the control circuit CC inputs a signal SG1 to the transmitting circuit TX1. The signal SG1 is a square wave. The transmitting circuit TX1 modulates the signal SG1 into a signal SG2 and transmits the signal SG2 to the transmitting coil CL1. When the signal SG2 flows into the transmitting coil CL1, the signal SG3 corresponding to the signal SG2 flows into the receiving coil CL2 through the induced electromotive force. The receiving circuit RX1 amplifies the signal SG3 and demodulates it into a signal SG4 (square wave) and then outputs it to the drive circuit DR. In this way, the signal is sent from the control circuit CC to the drive circuit DR. It should be noted that the signal transmission from the drive circuit DR to the control circuit CC is also performed in the same manner. Therefore, in the semiconductor device DEV1, the signal transmission between the transmitting circuit TX1 and the receiving circuit RX1 and the signal transmission between the transmitting circuit TX2 and the receiving circuit RX2 are performed by a pulse communication method.

[0053] <Detailed Configuration of Semiconductor Chip CHP3>

[0054] The detailed configuration of the semiconductor chip CHP3 will be described below.

[0055] Figure 3 is a first plan view of the semiconductor chip CHP3. Figure 4 is a second plan view of the semiconductor chip CHP3. Figure 5 is a third plan view of the semiconductor chip CHP3. Fig. 6A It is along Figure 5 A cross-sectional view taken along line VIA-VIA in FIG. Figure 6B It is along Figure 5 A cross-sectional view taken along the VIB-VIB line in FIG. Figures 3 to 6B As shown in, the semiconductor chip CHP3 includes a semiconductor substrate SUB, an insulating film IF1, a shielding member SH1, wiring WL1, wiring WL2, wiring WL3 and wiring WL4, an insulating film IF2, via plug VP1, via plug VP2, via plug VP3, via plug VP4, via plug VP5, via plug VP6, via plug VP7 and via plug VP8, a transmitting coil CL1, a receiving coil CL4, wiring WL5, wiring WL6, wiring WL7, wiring WL8 and a lead PL2.

[0056] The semiconductor chip CHP3 further includes a plurality of insulating films IF3, a receiving coil CL2, a lead PL1, a transmitting coil CL3, pads PD1, PD2, PD3, PD4, and PD5, and a guard ring GR1. The semiconductor chip CHP3 further includes a guard ring GR2, a seal ring SR, wiring WL9, and a passivation film PF.

[0057] The semiconductor substrate SUB has a first surface FS and a second surface SS. The first surface FS and the second surface SS are end surfaces in the thickness direction of the semiconductor substrate SUB. The second surface SS is an opposite surface of the first surface FS. The constituent material of the semiconductor substrate SUB is, for example, single crystal silicon. The semiconductor substrate SUB has an impurity implantation region IR. The impurity implantation region IR is formed in the first surface FS. The impurity implantation region IR may be formed in the entire first surface FS, or may be partially formed in the first surface FS. The conductivity type of the semiconductor substrate SUB is, for example, p-type. The dopant concentration in the impurity implantation region IR is higher than the dopant concentration outside the impurity implantation region IR.

[0058] In a plan view, the semiconductor substrate SUB has a device region SUB1, a peripheral region SUB2, and a peripheral region SUB3. The peripheral region SUB2 exists around the device region SUB1 and surrounds the device region SUB1. The peripheral region SUB3 exists in the outer edge of the semiconductor substrate SUB and surrounds the peripheral region SUB2.

[0059] The insulating film IF1 is arranged on the semiconductor substrate SUB. The constituent material of the insulating film IF1 is, for example, silicon oxide.

[0060] The shielding member SH1 is arranged on the insulating film IF1. The shielding member SH1 is arranged on the device area SUB1. In a plan view, the outer shape of the shielding member SH1 is generally rectangular. The constituent material of the shielding member SH1 is, for example, aluminum, aluminum alloy, copper, copper alloy, etc. That is, the constituent material of the shielding member SH1 is, for example, a conductive material containing aluminum as a main component or a conductive material containing copper as a main component. The term "main component" refers to a constituent element that accounts for 50% by mass or more in the constituent material.

[0061] The shield SH1 has an opening OP1, an opening OP2, and an opening OP3. The openings OP1, OP2, and OP3 penetrate the shield SH1 in the thickness direction.

[0062] Wirings WL1, WL2, WL3, and WL4 are arranged on the insulating film IF1. In a plan view, the wiring WL1 is arranged inside the opening OP1. In a plan view, the wirings WL2 and WL3 are arranged inside the opening OP2. The wiring WL4 is arranged inside the opening OP3. The constituent material of the wirings WL1, WL2, WL3, and WL4 is, for example, a conductive material containing aluminum as a main component. The constituent material of the wirings WL1, WL2, WL3, and WL4 may be a conductive material containing copper as a main component.

[0063] The insulating film IF2 is arranged on the insulating film IF1 so as to cover the shield SH1 and the wirings WL1 , WL2 , WL3 , and WL4 . The constituent material of the insulating film IF2 is, for example, silicon oxide.

[0064] The via plugs VP1, VP2, VP3, VP4, VP5, VP6, VP7, and VP8 are embedded in the insulating film IF2. The constituent material of the via plugs VP1, VP2, VP3, VP4, VP5, VP6, VP7, and VP8 is, for example, a conductive material containing tungsten as a main component.

[0065] The transmitting coil CL1 (coils CL11, CL12), the receiving coil CL4 (coils CL41, CL42) and the lead PL2 are arranged on the insulating film IF2. In other words, the coils CL11, CL12, CL41 and CL42 and the lead PL2 are formed in the same layer on the semiconductor substrate SUB. The constituent material of the coils CL11, CL12, CL41 and CL42 and the lead PL2 is, for example, a conductive material containing aluminum as a main component. The constituent material of the coils CL11, CL12, CL41 and CL42 and the lead PL2 can be a conductive material containing copper as a main component.

[0066] In a plan view, coils CL11, CL12, CL41, and CL42 are arranged in a first direction DR1. Coils CL12 and CL41 are adjacent to each other. Coil CL11 is adjacent to coil CL12 from the opposite side of coil CL41. Coil CL42 is adjacent to coil CL41 from the opposite side of coil CL12. Coils CL11, CL12, CL41, and CL42 are arranged on a device region SUB1.

[0067] In a plan view, the coils CL11 and CL12 are wound in a spiral shape. The coils CL11 and CL12 are electrically connected in series. More specifically, the outermost end of the coil CL11 and the outermost end of the coil CL12 are electrically connected to each other.

[0068] In a plan view, coil CL11 is wound counterclockwise from the innermost circumference to the outermost circumference. In a plan view, coil CL12 is wound clockwise from the outermost circumference to the innermost circumference. That is, the winding direction of coil CL11 can be opposite to the winding direction of coil CL12. In other words, coils CL11 and CL12 are in a series auxiliary configuration.

[0069] In a plan view, coils CL41 and CL42 are wound into a spiral shape. In a plan view, coils CL41 and CL42 are adjacent to each other. Coils CL41 and CL42 are electrically connected in series. More specifically, the outermost end of coil CL41 and the outermost end of coil CL42 are electrically connected to each other. Lead PL2 is formed between coil CL41 and coil CL42.

[0070] In a plan view, coil CL41 is wound counterclockwise from the innermost circumference to the outermost circumference. In a plan view, coil CL42 is wound clockwise from the outermost circumference to the innermost circumference. That is, the winding direction of coil CL41 can be opposite to the winding direction of coil CL42. In other words, coils CL41 and CL42 are in a series auxiliary configuration.

[0071] In a plan view, the coils CL11, CL12, CL41 and CL42 overlap with the shield SH1. That is, the shield SH1 is arranged between the coils CL11, CL12, CL41 and CL42 and the semiconductor substrate SUB. In a plan view, the shield SH1 is continuously formed to span between the coils CL12 and CL41.

[0072] The second direction DR2 is a direction orthogonal to the first direction DR1. The width of the shield SH1 in the second direction DR2 is greater than the width of the coil CL11 in the second direction DR2, the width of the coil CL12 in the second direction DR2, the width of the coil CL41 in the second direction DR2, and the width of the coil CL42 in the second direction DR2.

[0073] The wirings WL5, WL6, WL7 and WL8 are arranged on the insulating film IF2. The constituent material of the wirings WL5, WL6, WL7 and WL8 is, for example, a conductive material containing aluminum as a main component. The constituent material of the wirings WL5, WL6, WL7 and WL8 may be a conductive material containing copper as a main component.

[0074] The wiring WL5 is electrically connected to the wiring WL1 by a via plug VP5, the wiring WL6 is electrically connected to the wiring WL2 by a via plug VP6, the wiring WL7 is electrically connected to the wiring WL3 by a via plug VP7, and the wiring WL8 is electrically connected to the wiring WL4 by a via plug VP8.

[0075] A plurality of insulating films IF3 are stacked on the insulating film IF2. The insulating film IF3 in the bottommost layer covers the coils CL11, CL12, CL41, and CL42, the lead PL2, and the wirings WL5, WL6, WL7, and WL8. The constituent material of the insulating film IF3 is, for example, silicon oxide.

[0076] The coils CL21, CL22, CL31 and CL32 are arranged on the topmost insulating film IF3. The constituent material of the coils CL21, CL22, CL31 and CL32 is, for example, a conductive material containing aluminum as a main component. The constituent material of the coils CL21, CL22, CL31 and CL32 may be a conductive material containing copper as a main component.

[0077] The coils CL21 and CL22 are respectively opposite to the coils CL11 and CL12 via a plurality of insulating films IF3. In other words, the coils CL21 and CL22 overlap with the coils CL11 and CL12 in a plan view. From another angle, the coils CL21 and CL22 are magnetically coupled to the coils CL11 and CL12, respectively.

[0078] The coils CL21 and CL22 are wound into a spiral shape in a plan view. The coils CL21 and CL22 are adjacent to each other in a plan view. The coils CL21 and CL22 are electrically connected in series. More specifically, the end at the outermost periphery of the coil CL21 and the end at the outermost periphery of the coil CL22 are electrically connected to each other. A lead PL1 is formed between the coil CL21 and the coil CL22.

[0079] In a plan view, coil CL21 is wound counterclockwise from the innermost circumference to the outermost circumference. In a plan view, coil CL22 is wound clockwise from the outermost circumference to the innermost circumference. That is, the winding direction of coil CL21 can be opposite to the winding direction of coil CL22. In other words, coils CL21 and CL22 are in a series auxiliary configuration.

[0080] The coils CL31 and CL32 are respectively opposite to the coils CL41 and CL42 via a plurality of insulating films IF3. In other words, the coils CL31 and CL32 overlap with the coils CL41 and CL42 in a plan view. From another perspective, the coils CL31 and CL32 are magnetically coupled to the coils CL41 and CL42, respectively.

[0081] The coils CL31 and CL32 are wound into a spiral shape in a plan view. The coils CL31 and CL32 are adjacent to each other in a plan view. The coils CL31 and CL32 are electrically connected in series. More specifically, the outermost end of the coil CL31 and the outermost end of the coil CL32 are electrically connected to each other.

[0082] In a plan view, coil CL31 is wound counterclockwise from the innermost circumference to the outermost circumference. In a plan view, coil CL32 is wound clockwise from the outermost circumference to the innermost circumference. That is, the winding direction of coil CL31 can be opposite to the winding direction of coil CL32. In other words, coils CL31 and CL32 are in a series auxiliary configuration.

[0083] The distance between coil CL11 and coil CL21 or between coil CL12 and coil CL22 may be, for example, greater than 6 μm and less than 14 μm. The distance between coil CL41 and coil CL31 or between coil CL42 and coil CL32 may be, for example, greater than 6 μm and less than 14 μm.

[0084] Pads PD1, PD2, PD3, PD4 and PD5 are arranged on the topmost insulating film IF3. Pad PD1 is connected to the end of the innermost circumference of coil CL21 and pad PD2 is connected to the end of the innermost circumference of coil CL22. Pad PD3 is connected to the end of the innermost circumference of coil CL31 and pad PD4 is connected to the end of the innermost circumference of coil CL32. Pad PD5 is connected to the end of lead PL1 on the opposite sides of coils CL21 and CL22. The constituent material of pads PD1, PD2, PD3, PD4 and PD5 is, for example, a conductive material containing aluminum as a main component. The constituent material of pads PD1, PD2, PD3, PD4 and PD5 can be a conductive material containing copper as a main component.

[0085] The guard ring GR1 is arranged on the insulating film IF3 in the topmost layer. The guard ring GR1 has a first portion GR1a and a second portion GR1b. The first portion GR1a surrounds the receiving coil CL2 in a plan view, and the second portion GR1b surrounds the transmitting coil CL3 in a plan view. The pad PD5 is in contact with the guard ring GR1 (first portion GR1a). Therefore, the guard ring GR1 is connected to the reference potential in the same manner as the lead PL1. The constituent material of the guard ring GR1 is, for example, a conductive material containing aluminum as a main component. The constituent material of the guard ring GR1 may be a conductive material containing copper as a main component.

[0086] The guard ring GR2 has a plurality of wirings WL10 and a plurality of via plugs VP9. The wirings WL10 are arranged on each of the insulating film IF1, the insulating film IF2, and the plurality of insulating films IF3. In other words, the shield SH1 is formed in the same layer as the wirings WL10 in the bottom layer. The via plugs VP9 are embedded in the insulating film IF2 and each of the plurality of insulating films IF3. The wirings WL10 and the via plugs VP9 are alternately stacked on the peripheral area SUB2. The guard ring GR2 (more specifically, the wirings WL10 in the top layer) is connected to a reference potential.

[0087] The constituent material of the wiring WL10 is, for example, a conductive material containing aluminum as a main component. The constituent material of the wiring WL10 may be a conductive material containing copper as a main component. The constituent material of the via plug VP9 is, for example, a conductive material containing tungsten as a main component.

[0088] The wiring WL9 is arranged on the insulating film IF1. The wiring WL9 is connected to the shield SH1 at one end and to the wiring WL10 of the bottom layer at the other end. Therefore, the shield SH1 is connected to the reference potential. The constituent material of the wiring WL9 is, for example, a conductive material containing aluminum as a main component. The constituent material of the wiring WL9 may be a conductive material containing copper as a main component.

[0089] The sealing ring SR has a plurality of wirings WL11 and a plurality of via plugs VP10. The wirings WL11 are arranged on each of the insulating film IF1, the insulating film IF2, and the plurality of insulating films IF3. The via plugs VP10 are embedded in each of the insulating film IF1, the insulating film IF2, and the plurality of insulating films IF3. The wirings WL11 and the via plugs VP10 are alternately stacked on the peripheral region SUB3. Since the via plugs VP10 are also embedded in the insulating film IF1, the sealing ring SR is electrically connected to the semiconductor substrate SUB (more specifically, the impurity injection region IR). The reference potential is connected to the sealing ring SR (more specifically, the wirings WL11 in the topmost layer). Therefore, the semiconductor substrate SUB is also connected to the reference potential.

[0090] The constituent material of the wiring WL11 is, for example, a conductive material containing aluminum as a main component. The constituent material of the wiring WL11 may be a conductive material containing copper as a main component. The constituent material of the via plug VP10 is, for example, a conductive material containing tungsten as a main component.

[0091] The passivation film PF is arranged on the topmost insulating film IF3 so as to cover the receiving coil CL2 (coils CL21, CL22), the transmitting coil CL3 (coils CL31, CL32), the lead PL1, the pads PD1, PD2, PD3, PD4 and PD5, the guard ring GR1, the topmost wiring WL10 and the topmost wiring WL11. It should be noted that the pads PD1, PD2, PD3, PD4 and PD5 are exposed from the opening of the passivation film PF. The constituent material of the passivation film PF is, for example, silicon nitride.

[0092] <Method for Manufacturing Semiconductor Chip CHP3>

[0093] Next, a method of manufacturing the semiconductor chip CHP3 will be described.

[0094] Figure 7 FIG. 1 is a diagram of the manufacturing process of the semiconductor chip CHP3. Figure 7As shown in, the manufacturing method of the semiconductor chip CHP3 includes a preparation step S1, an ion implantation step S2, a first insulating film forming step S3, a first via plug forming step S4, a shielding member forming step S5, a second insulating film forming step S6, a second via plug forming step S7, a first coil forming step S8, a third insulating film forming step S9, a third via plug forming step S10, a wiring forming step S11, a second coil forming step S12 and a passivation film forming step S13.

[0095] In the preparation step S1, a semiconductor substrate SUB is prepared. After the preparation step S1, an ion implantation step S2 is performed. Figure 8 is a cross-sectional view for describing the ion implantation step S2. Figure 8 As shown in FIG. 1 , in the ion implantation step S2 , the impurity implantation region IR is formed by ion implantation. After the ion implantation step S2 , the first insulating film forming step S3 is performed.

[0096] Fig. 9 1 is a cross-sectional view for describing the first insulating film forming step S3. In the first insulating film forming step S3, the insulating film IF1 is formed on the semiconductor substrate SUB by, for example, a CVD (chemical vapor deposition) method. After the first insulating film forming step S3, the first via plug forming step S4 is performed.

[0097] Fig.10 2 is a cross-sectional view for describing the first via plug forming step S4. Fig.10 As shown in, in the first via plug forming step S4, the via plug VP10 is embedded in the insulating film IF1. In the first via plug forming step S4, first, a via is formed in the insulating film IF1 by dry etching using a resist pattern formed by photolithography as a mask. Second, the constituent material of the via plug VP10 is embedded in the via by, for example, a CVD method. Third, the constituent material of the via plug VP10 protruding from the via is removed by, for example, a CMP (chemical mechanical polishing) method. After the first via plug forming step S4, a shield forming step S5 is performed.

[0098] Fig.11 2 is a cross-sectional view for describing the shielding member forming step S5. Fig.11As shown in, in the shield forming step S5, a shield SH1 is formed on the insulating film IF1. In the shield forming step S5, first, the constituent material of the shield SH1 is deposited by, for example, a sputtering method. Second, the deposited constituent material of the shield SH1 is patterned by, for example, dry etching using a resist pattern formed by photolithography as a mask. In the shield forming step S5, wirings WL1, WL2, WL3, and WL4 are also formed in the same manner. Although not shown, in the shield forming step S5, wirings WL9, WL10, and WL11 are also formed in the same manner. After the shield forming step S5, a second insulating film forming step S6 is performed.

[0099] Fig.12 2 is a cross-sectional view for describing the second insulating film forming step S6. Fig.12 As shown in FIG. 1 , in the second insulating film forming step S6, an insulating film IF2 is formed on the insulating film IF1 so as to cover the shield SH1 and the wirings WL1, WL2, WL3, WL4, WL9 ( Fig.12 Not shown), WL10( Fig.12 Not shown) and WL11 ( Fig.12 In the second insulating film forming step S6, first, the constituent material of the insulating film IF2 is deposited by, for example, a CVD method. Second, the constituent material of the deposited insulating film IF2 is planarized by, for example, a CMP method. After the second insulating film forming step S6, a second via plug forming step S7 is performed.

[0100] Fig.13 2 is a cross-sectional view for describing the second via plug forming step S7. Fig.13 As shown in the figure, in the second via plug forming step S7, via plugs VP1, VP2, VP3, VP4, VP5, VP6, VP7 and VP8 are embedded in the insulating film IF2 by the same method as the first via plug forming step S4. Although not shown, in the second via plug forming step S7, via plugs VP9 and VP10 are also formed in the same manner. After the second via plug forming step S7, the first coil forming step S8 is performed.

[0101] Fig.14 is a cross-sectional view for describing the first coil forming step S8. Fig.14As shown in, in the first coil forming step S8, the transmitting coil CL1 and the receiving coil CL4 are formed on the insulating film IF2. In the first coil forming step S8, first, the constituent materials of the transmitting coil CL1 and the receiving coil CL4 are deposited by, for example, a sputtering method. Second, for example, by dry etching, using a resist pattern formed by photolithography as a mask, the deposited constituent materials of the transmitting coil CL1 and the receiving coil CL4 are patterned by, for example, dry etching using a resist pattern formed by photolithography as a mask. In the first coil forming step S8, the wirings WL5, WL6, WL7 and WL8 and the lead PL2 are also formed in the same manner. Although not shown, the wirings WL10 and WL11 are also formed in the same manner in the first coil forming step S8. After the first coil forming step S8, the third insulating film forming step S9 is performed.

[0102] Fig.15 2 is a cross-sectional view for describing the third insulating film forming step S9. Fig.15 As shown in FIG. 1 , in the third insulating film forming step S9, an insulating film IF3 is formed on the insulating film IF2 by the same method as the second insulating film forming step S6 so as to cover the transmitting coil CL1, the receiving coil CL4, the lead PL2, and the wirings WL5, WL6, WL7, and WL8 ( Fig.15 After the third insulating film forming step S9, a third via plug forming step S10 is performed.

[0103] Fig.16 2 is a cross-sectional view for describing the third via plug forming step S10. Fig.16 As shown in FIG. 1 , in the third via plug forming step S10 , via plugs VP9 and VP10 are embedded in the insulating film IF3 by the same method as the second via plug forming step S7 . After the third via plug forming step S10 , a wiring forming step S11 is performed. Fig.17 2 is a cross-sectional view for describing the wiring forming step S11. Fig.17 As shown in , in the wiring forming step S11, wirings WL10 and WL11 are formed by the same method as the first coil forming step S8. The third insulating film forming step S9, the third via plug forming step S10, and the wiring forming step S11 are repeated until the insulating film IF3 in the topmost layer is formed. After the insulating film IF3 in the topmost layer is formed, the second coil forming step S12 is performed.

[0104] Fig.18 2 is a cross-sectional view for describing the second coil forming step S12. Fig.18As shown in FIG. 1 , in the second coil forming step S12, a receiving coil CL2, a transmitting coil CL3, a lead PL1, pads PD1 to PD5, a guard ring GR1, and a wiring WL10 are formed on the topmost insulating film IF3 by the same method as the first coil forming step S8 ( Fig.18 Not shown) and WL11 ( Fig.18 (not shown in the figure). After the second coil forming step S12, a passivation film forming step S13 is performed.

[0105] In the passivation film forming step S13, the passivation film PF is formed on the topmost insulating film IF3 so as to cover the receiving coil CL2, the transmitting coil CL3, the lead PL1, the pads PD1 to PD5, the guard ring GR1, and the wirings WL10 and WL11. In the passivation film forming step S13, first, the constituent material of the passivation film PF is deposited by, for example, a CVD method. Second, the constituent material of the passivation film PF is patterned by, for example, dry etching using a resist pattern formed by photolithography as a mask.

[0106] After the above steps, cutting or the like is performed, thereby forming a Figures 3 to 6B The structure shown in FIG. 1 is a single piece of the semiconductor chip CHP3.

[0107] <Effect of semiconductor device DEV1>

[0108] Next, the effects of the semiconductor device DEV1 will be described.

[0109] In the semiconductor device DEV1, the transformers TR1 and TR2 are incorporated in the semiconductor chip CHP3. Since semiconductor elements such as transistors are not formed in the semiconductor chip CHP3, the manufacturing process of the semiconductor chip CHP3 can be optimized according to the transformers TR1 and TR2.

[0110] When the shielding member SH1 is not arranged, the insulating films IF1 and IF2 between the transmitting coil CL1 (coils CL11, CL12) and the semiconductor substrate SUB constitute a capacitor. Similarly, the insulating films IF1 and IF2 between the receiving coil CL4 (coils CL41, CL42) and the semiconductor substrate SUB constitute a capacitor. Since the above-mentioned capacitor has a small impedance for high-frequency signals, the current flowing through one of the transmitting coil CL1 and the receiving coil CL4 flows through the capacitor and the semiconductor substrate SUB to reach the other coil of the transmitting coil CL1 and the receiving coil CL4, thereby causing crosstalk between channels.

[0111] It should be noted that if the impurity implantation region is formed on the entire first surface FS, since it is not necessary to form a mask in the ion implantation step S2, the process of forming the semiconductor chip CHP3 is simplified. However, if the impurity implantation region is formed on the entire first surface FS, since the resistance of the semiconductor substrate SUB is reduced, the current flowing through one of the transmitting coil CL1 and the receiving coil CL4 can flow through the capacitor and the semiconductor substrate SUB to reach the other of the transmitting coil CL1 and the receiving coil CL4.

[0112] In the semiconductor device DEV1, since the shield SH1 coupled to the reference potential is arranged between the transmission coil CL1 and the reception coil CL4, the capacitive coupling described above is less likely to occur. Therefore, according to the semiconductor device DEV1, crosstalk between channels can be suppressed.

[0113] (Second embodiment)

[0114] A semiconductor device according to a second embodiment will be described. The semiconductor device according to the second embodiment is referred to as a semiconductor device DEV2. Here, points different from the semiconductor device DEV1 will be mainly described and the repeated description will not be repeated.

[0115] <Configuration of semiconductor device DEV2>

[0116] The configuration of the semiconductor device DEV2 will be described below.

[0117] The semiconductor device DEV2 includes a semiconductor chip CHP1, a semiconductor chip CHP2, and a semiconductor chip CHP3. In this respect, the configuration of the semiconductor device DEV2 is common to the configuration of the semiconductor device DEV1.

[0118] Fig.19 FIG. 1 is a plan view of the semiconductor chip CHP3 in the semiconductor device DEV2. Fig.19 As shown in, in the semiconductor device DEV2, a plurality of openings OP4 are formed in the shielding member SH1. The openings OP4 penetrate the shielding member SH1 in the thickness direction. In a plan view, the plurality of openings OP4 are arranged in, for example, a grid pattern. The plurality of openings OP4 may be arranged in a checkerboard pattern. In a plan view, the length of the openings OP4 in the longitudinal direction is, for example, less than 50 μm. In these aspects, the configuration of the semiconductor device DEV2 is different from the configuration of the semiconductor device DEV1.

[0119] <Effect of semiconductor device DEV2>

[0120] Next, the effects of the semiconductor device DEV2 will be described.

[0121] Due to the magnetic flux generated by the current flowing through the transmitting coil CL1 (coils CL11, CL12) and the receiving coil CL4 (coils CL41, CL42), eddy current can flow in the shielding member SH1. However, since the opening OP4 is formed in the shielding member SH1 in the semiconductor device DEV2, the range of the eddy current flow is limited by the opening OP4. Therefore, it is possible to suppress the semiconductor device DEV2 from generating eddy current in the shielding member SH1. In addition, even if the opening OP4 is formed, if the length of the opening OP4 in the longitudinal direction in the plan view is less than 50 μm, the shielding member SH1 can also sufficiently suppress the crosstalk between the channels.

[0122] (Third Embodiment)

[0123] A semiconductor device according to a third embodiment will be described. The semiconductor device according to the third embodiment is referred to as a semiconductor device DEV3. Here, points different from the semiconductor device DEV1 will be mainly described and will not be repeated.

[0124] <Configuration of semiconductor device DEV3>

[0125] The configuration of the semiconductor device DEV3 will be described below.

[0126] The semiconductor device DEV3 includes a semiconductor chip CHP1, a semiconductor chip CHP2, and a semiconductor chip CHP3. In this respect, the configuration of the semiconductor device DEV3 is common to that of the semiconductor device DEV1.

[0127] Fig. 20 FIG. 1 is a plan view of a semiconductor chip CHP3 in a semiconductor device DEV3. Fig. 20 As shown in FIG. 1 , in the semiconductor device DEV3, a plurality of slit openings OP5 are formed in the shield SH1. The slit openings OP5 penetrate the shield SH1 in the thickness direction. For example, the plurality of slit openings OP5 are radially arranged in a plan view. In these respects, the configuration of the semiconductor device DEV3 is different from that of the semiconductor device DEV1.

[0128] <Effect of semiconductor device DEV3>

[0129] Next, the effects of the semiconductor device DEV3 will be described.

[0130] Due to the magnetic flux generated by the current flowing through the transmitting coil CL1 (coils CL11, CL12) and the receiving coil CL4 (coils CL41, CL42), an eddy current may flow in the shield SH1. However, since the slit opening OP5 is formed in the shield SH1 in the semiconductor device DEV3, the range in which the eddy current flows is limited by the slit opening OP5. Therefore, it is possible to suppress the semiconductor device DEV3 from generating an eddy current in the shield SH1.

[0131] (Fourth embodiment)

[0132] A semiconductor device according to a fourth embodiment will be described. The semiconductor device according to the fourth embodiment is referred to as a semiconductor device DEV4. Here, points different from the semiconductor device DEV1 will be mainly described and the repeated description will not be repeated.

[0133] <Configuration of semiconductor device DEV4>

[0134] The configuration of the semiconductor device DEV4 will be described below.

[0135] The semiconductor device DEV4 includes a semiconductor chip CHP1, a semiconductor chip CHP2, and a semiconductor chip CHP3. In this respect, the configuration of the semiconductor device DEV4 is common to the configuration of the semiconductor device DEV1.

[0136] Fig.21 FIG. 4 is a plan view of the semiconductor chip CHP3 in the semiconductor device DEV4. Fig.21 As shown in FIG. 1 , in the semiconductor device DEV4, in a plan view, the shielding member SH1 is formed separately between the coil CL12 and the coil CL41. That is, in the semiconductor device DEV4, the shielding member SH1 has a first portion SH1a overlapping with the transmitting coil CL1 in a plan view and a second portion SH1b overlapping with the receiving coil CL4 in a plan view.

[0137] In the semiconductor device DEV4, the semiconductor chip CHP3 has a wiring WL9a and a wiring WL9b instead of the wiring WL9. The wiring WL9a is connected to the first part SH1a at one end and to the wiring WL10 at the other end. Therefore, the first part SH1a is connected to the reference potential. The wiring WL9b is connected to the second part SH1b at one end and to the wiring WL10 at the other end. Therefore, the second part SH1b is connected to the reference potential. In these respects, the configuration of the semiconductor device DEV4 is different from the configuration of the semiconductor device DEV1.

[0138] <Effect of semiconductor device DEV4>

[0139] Next, the effects of the semiconductor device DEV4 will be described.

[0140] The insulating film IF2 between the transmitting coil CL1 (coils CL11, CL12) and the shielding member SH1 constitutes a capacitor. Similarly, the insulating film IF2 between the receiving coil CL4 (coils CL41, CL42) and the shielding member SH1 also constitutes a capacitor. Therefore, the high-frequency current flowing in one of the transmitting coil CL1 and the receiving coil CL4 flows to the other of the transmitting coil CL1 and the receiving coil CL4 through the above-mentioned capacitor and the shielding member SH1, thereby causing crosstalk between channels in some cases.

[0141] Since in the semiconductor device DEV4, in a plan view, the shielding member SH1 is formed separately between the transmitting coil CL1 and the receiving coil CL4 (between the coil CL12 and the coil CL41), the above-mentioned current cannot flow from one of the transmitting coil CL1 and the receiving coil CL4 to the other of the transmitting coil CL1 and the receiving coil CL4. Therefore, according to the semiconductor device DEV4, crosstalk between channels can be further suppressed.

[0142] (Fifth Embodiment)

[0143] A semiconductor device according to a fifth embodiment will be described. The semiconductor device according to the fifth embodiment is referred to as a semiconductor device DEV5. Here, points different from the semiconductor device DEV1 will be mainly described and the repeated description will not be repeated.

[0144] <Configuration of semiconductor device DEV5>

[0145] The configuration of the semiconductor device DEV5 will be described below.

[0146] The semiconductor device DEV5 includes a semiconductor chip CHP1, a semiconductor chip CHP2, and a semiconductor chip CHP3. In this respect, the configuration of the semiconductor device DEV5 is common to the configuration of the semiconductor device DEV1.

[0147] Fig. 22 is a plan view of the semiconductor chip CHP3 in the semiconductor device DEV5. Fig.23 It is along Fig. 22 A cross-sectional view taken along line XXIII-XXIII in FIG. Fig. 22 and Fig.23 As shown in FIG. 8 , the semiconductor device DEV5 includes a shield SH2 and a plurality of via plugs VP11 .

[0148] In a plan view, the shield SH2 is arranged between the transmission coil CL1 and the reception coil CL4. More specifically, in a plan view, the shield SH2 is arranged between the coil CL12 and the coil CL41. The shield SH2 is composed of, for example, a wiring WL12 and a via plug VP11.

[0149] The wiring WL12 is arranged on the insulating film IF2. That is, the wiring WL12 is formed in the same layer as the transmitting coil CL1 (coils CL11, CL12) and the receiving coil CL4 (coils CL41, CL42). In the plan view, the wiring WL12 extends in the second direction DR2. The constituent material of the wiring WL12 is a conductive material containing aluminum as a main component. The constituent material of the wiring WL12 may be a conductive material containing copper as a main component. The via plug VP11 is embedded in the insulating film IF2. In the plan view, a plurality of via plugs VP11 are arranged at intervals in the second direction DR2. The constituent material of the via plug VP11 is a conductive material containing tungsten as a main component.

[0150] The width of the wiring WL12 in the second direction DR2 is greater than the width of the coil CL12 in the second direction DR2 and the width of the coil CL41 in the second direction DR2. For example, the wiring WL12 is connected to the wiring WL10 arranged on the insulating film IF2. In addition, the via plug VP11 electrically connects the wiring WL12 and the shielding member SH1. Therefore, the shielding member SH2 is electrically connected to the reference potential.

[0151] The shortest distance between the lower coil (transmitting coil CL1, receiving coil CL4) and the upper coil (receiving coil CL2, transmitting coil CL3) is defined as the first distance. The shortest distance between the upper coil and the shield SH2 (wiring WL12) is defined as the second distance. In order to ensure the withstand voltage between the lower coil and the upper coil, the second distance is greater than the first distance. In these aspects, the configuration of the semiconductor device DEV5 is the same as the configuration of the semiconductor device DEV1.

[0152] It should be noted that the via plug VP11 is formed in the second via plug forming step S7 and the wiring WL12 is formed in the first coil forming step S8 .

[0153] <Effect of semiconductor device DEV5>

[0154] Next, the effects of the semiconductor device DEV5 will be described.

[0155] Since the transmitting coil CL1 and the receiving coil CL4 are adjacent to each other, the electromagnetic wave generated by the current flowing through one of the transmitting coil CL1 and the receiving coil CL4 interferes with the other of the transmitting coil CL1 and the receiving coil CL4, thereby causing crosstalk between channels in some cases. In the semiconductor device DEV5, in a plan view, a shield SH2 electrically connected to a reference potential is arranged between the transmitting coil CL1 and the receiving coil CL4. Therefore, according to the semiconductor device DEV5, the shield SH2 serves as a Faraday shield and can suppress the occurrence of the above-mentioned crosstalk between channels.

[0156] In the semiconductor device DEV5, since the constituent material of the shield SH2 (constituent material of the wiring WL12, constituent material of the via plug VP11) is a metal material having low resistance and electrons induced by electromagnetic waves are quickly discharged from the shield SH2, the shield SH2 effectively functions as a Faraday shield.

[0157] (Sixth Embodiment)

[0158] A semiconductor device according to a sixth embodiment will be described. The semiconductor device according to the sixth embodiment is referred to as a semiconductor device DEV6. Here, points different from the semiconductor device DEV5 will be mainly described and the repeated description will not be repeated.

[0159] <Configuration of semiconductor device DEV6>

[0160] The configuration of the semiconductor device DEV6 will be described below.

[0161] The semiconductor device DEV6 includes a semiconductor chip CHP1, a semiconductor chip CHP2, and a semiconductor chip CHP3. In this respect, the configuration of the semiconductor device DEV6 is common to the configuration of the semiconductor device DEV5.

[0162] Fig.24 is a plan view of the semiconductor chip CHP3 in the semiconductor device DEV6. Fig.25 It is along Fig.24 A cross-sectional view taken along line XXV-XXV in FIG. Fig.24 and Fig.25 As shown in FIG. 8 , the semiconductor device DEV6 does not have a shield SH1 .

[0163] In the semiconductor device DEV6, the shielding member SH2 is composed of a wiring WL12, a wiring WL13 and a via plug VP11. That is, the shielding member SH2 is composed of a wiring formed in the same layer as the wiring WL10 located on the insulating film IF1, a wiring formed in the same layer as the wiring WL10 located on the insulating film IF2, and a via plug between these wirings. In a plan view, the wiring WL13 extends in the second direction DR2. The wiring WL13 is arranged on the insulating film IF1. In a plan view, the wiring WL13 overlaps with the wiring WL12. The constituent material of the wiring WL13 is, for example, a conductive material containing aluminum as a main component. The constituent material of the wiring WL13 is a conductive material containing copper as a main component. In the semiconductor device DEV6, in the shielding formation step S5, the wiring WL13 is formed instead of the shielding member SH1.

[0164] The wiring WL12 and the wiring WL13 are electrically connected through a plurality of via plugs VP11. In addition, the wiring WL13 is connected to the wiring WL10 on the insulating film IF1. That is, the wiring WL12 and the wiring WL13 are stacked via a plurality of via plugs VP11. Therefore, the shield SH2 is connected to the reference potential. Since the plurality of via plugs VP11 are arranged at intervals, the wiring WL12 and the wiring WL13 are connected in a point via structure. The interval between two adjacent via plugs VP11 is defined as an interval SP. The interval SP is, for example, greater than 0.3 μm and less than 2 μm. In these respects, the configuration of the semiconductor device DEV6 is different from the configuration of the semiconductor device DEV5.

[0165] <Edit>

[0166] Fig.26 is a cross-sectional view of a semiconductor chip CHP3 according to a modification of the semiconductor device DEV6. Fig.26 It is shown that the Fig.24 The cross section at the position of the IIV-IIV line in FIG. Fig.26 As shown in , the number of via plugs VP11 may be one. In this case, the via plugs VP11 are continuously formed in the direction in which the wirings WL12 and WL13 extend in a plan view. In other words, the wirings WL12 and WL13 may be connected in a slit via structure.

[0167] <Effects of semiconductor device DEV6>

[0168] Next, the effects of the semiconductor device DEV6 will be described.

[0169] Also in the semiconductor device DEV6, since the shield SH2 electrically connected to the reference potential is arranged between the transmitting coil CL1 and the receiving coil CL4 in a plan view, the shield SH2 serves as a Faraday shield and can suppress the occurrence of crosstalk between channels. If the interval SP is 2 μm or less, the interval SP is smaller than the wavelength of the electromagnetic wave generated by the transmitting coil CL1 and the receiving coil CL4, and thus the occurrence of crosstalk between channels can be sufficiently suppressed. When the via plug VP11 is continuously formed in the direction in which the wiring WL12 and the wiring WL13 extend, there is no gap between adjacent via plugs VP11, and thus the occurrence of crosstalk between channels can be further suppressed.

[0170] (Additional statement)

[0171] The above-described embodiment includes the following configurations.

[0172] <Additional Statement 1>

[0173] A semiconductor device, comprising:

[0174] a first semiconductor chip;

[0175] a second semiconductor chip; and

[0176] The third semiconductor chip,

[0177] The first semiconductor chip has a first transmitting circuit and a first receiving circuit.

[0178] The second semiconductor chip has a second transmitting circuit and a second receiving circuit.

[0179] The third semiconductor chip comprises a semiconductor substrate, a first coil, a second coil, a third coil, a fourth coil, an insulating layer and a first shielding member,

[0180] The semiconductor substrate has a device region and a peripheral region,

[0181] Wherein the peripheral region exists around the device region in the plan view,

[0182] wherein the first coil and the second coil are arranged on the device region and arranged in a first direction in a plan view,

[0183] The third coil and the fourth coil are respectively opposite to the first coil and the second coil via the insulating layer,

[0184] wherein the first shield is arranged between the semiconductor substrate and the first coil and the second coil, and overlaps the first coil and the second coil in a plan view,

[0185] wherein the width of the first shielding member in a second direction orthogonal to the first direction is greater than the width of the first coil in the second direction and the width of the second coil in the second direction,

[0186] wherein the first shield is electrically connected to a reference potential,

[0187] wherein a signal transmitted from the first transmitting circuit is transmitted to the second receiving circuit via the first coil and the third coil, and

[0188] The signal transmitted from the second transmitting circuit is transmitted to the first receiving circuit via the fourth coil and the second coil.

[0189] <Additional Statement 2>

[0190] A semiconductor device according to additional statement 1,

[0191] The signal transmission method from the first transmitting circuit to the second receiving circuit and the signal transmission method from the second transmitting circuit to the first receiving circuit are pulse communication methods.

[0192] <Additional statement 3>

[0193] A semiconductor device according to additional statement 1,

[0194] The first shielding member is continuously formed so as to span between the first coil and the second coil in a plan view.

[0195] <Additional Statement 4>

[0196] A semiconductor device according to additional statement 1,

[0197] The first shielding member has a plurality of openings, and

[0198] The plurality of openings are arranged in a grid pattern or a checkerboard pattern in plan view.

[0199] <Additional Statement 5>

[0200] A semiconductor device according to additional statement 4,

[0201] The length of the opening in the longitudinal direction in a plan view is 50 μm or less.

[0202] <Additional Statement 6>

[0203] A semiconductor device according to additional statement 1,

[0204] wherein the first shielding member has a plurality of slit openings, and

[0205] Therein, a plurality of slit openings are arranged radially in a plan view.

[0206] <Additional Statement 7>

[0207] A semiconductor device according to additional statement 1,

[0208] Wherein in a plan view, the first shield is formed solely between the first coil and the second coil.

[0209] <Additional Statement 8>

[0210] The semiconductor device according to additional statement 1, further comprising a second shield arranged between the first coil and the second coil in a plan view,

[0211] wherein the width of the second shielding member in the second direction is greater than the width of the first coil in the second direction and the width of the second coil in the second direction, and

[0212] The second shield is electrically connected to the reference potential.

[0213] <Additional Statement 9>

[0214] A semiconductor device according to additional statement 8,

[0215] Therein, the first shield is electrically connected to the second shield and via the second shield is electrically connected to a reference potential.

[0216] <Additional statement 10>

[0217] A semiconductor device according to additional statement 8,

[0218] wherein the second shield is spaced apart from the first coil and the second coil in plan view, and

[0219] In a plan view, a distance between the first coil and the second shielding member and a distance between the second coil and the second shielding member are greater than or equal to 12 μm and less than or equal to 100 μm.

[0220] <Additional Statement 11>

[0221] A semiconductor device according to additional statement 8,

[0222] The second shielding member has a plurality of first via plugs and a first wiring and a second wiring stacked through the plurality of first via plugs, and

[0223] The interval between two adjacent first via plugs in the plurality of first via plugs is greater than or equal to 0.3 μm and less than or equal to 2 μm.

[0224] <Additional Statement 12>

[0225] A semiconductor device according to additional statement 8,

[0226] wherein the second shielding member has a first via plug and a first wiring and a second wiring stacked via the first via plug, and

[0227] The first via plug is continuously formed along a direction in which the first wiring and the second wiring extend.

[0228] <Additional Statement 13>

[0229] A semiconductor device according to additional statement 8,

[0230] wherein the second shielding member has at least one first via plug and a first wiring and a second wiring stacked via the at least one first via plug,

[0231] The first via plug is made of a conductive material containing tungsten as a main component, and

[0232] The constituent material of the first wiring and the constituent material of the second wiring are conductive materials containing aluminum or copper as a main component.

[0233] <Additional Statement 14>

[0234] A semiconductor device according to additional statement 1,

[0235] The first shielding member is made of a conductive material containing aluminum or copper as a main component.

[0236] <Additional Statement 15>

[0237] The semiconductor device according to additional statement 1, further comprising a lead formed in the same layer as the first shield and connected to the first shield.

[0238] <Additional Statement 16>

[0239] The semiconductor device according to additional statement 8, further comprising a guard ring arranged on the peripheral area,

[0240] The guard ring has a plurality of wirings and a plurality of second via plugs,

[0241] wherein the wiring and the second via plug are alternately stacked,

[0242] wherein the plurality of wirings include a third wiring in a bottommost layer and a fourth wiring in an upper layer of the third wiring,

[0243] wherein the first shield is formed in the same layer as the third wiring, and

[0244] The second shield is formed in the same layer as the third wiring, the fourth wiring, and the second via plug located between the third wiring and the fourth wiring.

[0245] <Additional Statement 17>

[0246] A semiconductor device according to additional statement 1,

[0247] The distance between the first coil and the third coil or the distance between the second coil and the fourth coil is greater than 6 μm and less than 14 μm.

[0248] <Additional Statement 18>

[0249] A semiconductor device according to additional statement 1,

[0250] wherein the first coil and the third coil are magnetically coupled to each other, and wherein the first coil and the third coil are magnetically coupled to each other, and

[0251] The second coil and the fourth coil are magnetically coupled to each other.

[0252] In the above, the invention made by the inventors of the present application has been specifically described based on the embodiments. However, it goes without saying that the present invention is not limited to the aforementioned embodiments and can be variously modified within the scope not departing from the gist thereof.

Claims

1. A semiconductor device, comprising: Semiconductor substrate; a first coil, a second coil, a third coil, and a fourth coil; Insulation layer; as well as A first shielding member, The semiconductor substrate has a device region and a peripheral region. wherein the peripheral region exists around the device region in a plan view, wherein the first coil and the second coil are arranged on the device region and arranged in a first direction in a plan view, wherein the third coil and the fourth coil are respectively opposite to the first coil and the second coil via the insulating layer, wherein the first shield is arranged between the semiconductor substrate and the first and second coils and overlaps the first and second coils in a plan view, wherein a width of the first shielding member in a second direction orthogonal to the first direction is greater than a width of the first coil in the second direction and a width of the second coil in the second direction, and Wherein the first shield is electrically connected to a reference potential.

2. The semiconductor device according to claim 1, The first shielding member is continuously formed so as to span between the first coil and the second coil in a plan view.

3. The semiconductor device according to claim 1, wherein the first shielding member has a plurality of openings, and The plurality of openings are arranged in a grid pattern or a checkerboard pattern in a plan view.

4. The semiconductor device according to claim 3, The length of the opening in the longitudinal direction in a plan view is 50 μm or less.

5. The semiconductor device according to claim 1, wherein the first shielding member has a plurality of slit openings, and Wherein the plurality of slit openings are radially arranged in a plan view.

6. The semiconductor device according to claim 1, In a plan view, the first shielding member is formed solely between the first coil and the second coil.

7. The semiconductor device according to claim 1, further comprising a second shielding member arranged between the first coil and the second coil in a plan view, wherein the width of the second shielding member in the second direction is greater than the width of the first coil in the second direction and the width of the second coil in the second direction, and Wherein the second shield is electrically connected to the reference potential.

8. The semiconductor device according to claim 7, The first shield is electrically connected to the second shield and is electrically connected to the reference potential via the second shield.

9. The semiconductor device according to claim 7, wherein the second shield is spaced apart from the first coil and the second coil in plan view, and In a plan view, a distance between the first coil and the second shield and a distance between the second coil and the second shield are greater than or equal to 12 μm and less than or equal to 100 μm.

10. The semiconductor device according to claim 7, wherein the second shielding member has a plurality of first via plugs and a first wiring and a second wiring stacked via the plurality of first via plugs, and The interval between two adjacent first via plugs among the plurality of first via plugs is greater than or equal to 0.3 μm and less than or equal to 2 μm.

11. The semiconductor device according to claim 7, wherein the second shielding member has a first via plug and a first wiring and a second wiring stacked via the first via plug, and The first via plug is formed continuously along a direction in which the first wiring and the second wiring extend.

12. The semiconductor device according to claim 7, wherein the second shielding member has at least one first via plug and a first wiring and a second wiring stacked via the at least one first via plug, wherein the first via plug is made of a conductive material containing tungsten as a main component, and The constituent material of the first wiring and the constituent material of the second wiring are conductive materials containing aluminum or copper as a main component.

13. The semiconductor device according to claim 1, The first shielding member is made of a conductive material containing aluminum or copper as a main component. 14 . The semiconductor device according to claim 1 , further comprising a lead formed in the same layer as the first shield and connected to the first shield.

15. The semiconductor device according to claim 7, further comprising a guard ring arranged on the peripheral area, wherein the guard ring has a plurality of wirings and a plurality of second via plugs, wherein the wirings and the second via plugs are alternately stacked, wherein the plurality of wirings include a third wiring in a bottommost layer and a fourth wiring in an upper layer of the third wiring, wherein the first shield is formed in the same layer as the third wiring, and The second shield is formed in the same layer as the third wiring, the fourth wiring, and the second via plug located between the third wiring and the fourth wiring.

16. The semiconductor device according to claim 1, In a plan view, a distance between the first coil and the third coil or a distance between the second coil and the fourth coil is greater than or equal to 6 μm and less than or equal to 14 μm.

17. The semiconductor device according to claim 1, wherein the first coil and the third coil are magnetically coupled to each other, and Wherein the second coil and the fourth coil are magnetically coupled to each other.

18. A semiconductor device comprising: Semiconductor substrate; a first coil, a second coil, a third coil, a fourth coil, a fifth coil, a sixth coil, a seventh coil and an eighth coil; Insulation layer; as well as A first shielding member, The semiconductor substrate has a device region and a peripheral region. wherein the peripheral region exists around the device region in a plan view, wherein the first coil, the second coil, the fifth coil and the sixth coil are arranged on the device region and in a first direction in a plan view, wherein the first coil and the second coil are adjacent to each other, wherein the fifth coil is adjacent to the first coil from the opposite side of the second coil and is electrically connected in series with the first coil, wherein the sixth coil is adjacent to the second coil from the opposite side of the first coil and is electrically connected in series with the second coil, wherein the third coil, the fourth coil, the seventh coil and the eighth coil are respectively opposite to the first coil, the second coil, the fifth coil and the sixth coil via the insulating layer, wherein the seventh coil is electrically connected in series to the third coil, wherein the eighth coil is electrically connected in series to the fourth coil, wherein the first shield is arranged between the semiconductor substrate and the first coil, the second coil, the fifth coil and the sixth coil, and overlaps with the first coil, the second coil, the fifth coil and the sixth coil in a plan view, wherein a width of the first shield in a second direction orthogonal to the first direction is greater than a width of the first coil in the second direction, a width of the second coil in the second direction, a width of the fifth coil in the second direction, and a width of the sixth coil in the second direction, and Wherein the first shield is electrically connected to a reference potential.

19. The semiconductor device according to claim 18, further comprising a second shielding member arranged between the first coil and the second coil in a plan view, wherein the width of the second shielding member in the second direction is greater than the width of the first coil in the second direction, the width of the second coil in the second direction, the width of the fifth coil in the second direction, and the width of the sixth coil in the second direction, and Wherein the second shield is electrically connected to the reference potential.

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