Circuit device and power conversion circuit

Abstract

The present invention suppresses the number of terminals in a power conversion circuit. Provided is a circuit device provided with a power conversion circuit and a control circuit for controlling the power conversion circuit, the power conversion circuit having: a control terminal to which a control signal from the control circuit is input; an output terminal that outputs an output signal to the control circuit; and a data recognition unit that recognizes an input data signal input to the output terminal. The data recognition unit receives a first superimposed signal obtained by superimposing the output signal and the input data signal, and recognizes the input data signal on the basis of the first superimposed signal and the output signal.

Description

Technical Field

[0001] The invention relates to a circuit device and a power conversion circuit. Background Art

[0002] Conventionally, there are known electric circuits such as power conversion circuits and control circuits for controlling the circuits (see, for example, Patent Documents 1 to 4).

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2014-93903

[0006] Patent Document 2: Japanese Patent Application Publication No. 2009-258016

[0007] Patent Document 3: Japanese Patent Application Publication No. 2011-172336

[0008] Patent Document 4: Japanese Patent Application Publication No. 2020-96436 Summary of the invention

[0009] Technical issues

[0010] In a circuit such as a power conversion circuit, it is preferable to have a small number of terminals.

[0011] Technical Solution

[0012] In order to solve the above problems, in one embodiment of the present invention, a circuit device is provided, which includes a power conversion circuit and a control circuit that controls the power conversion circuit. In the above circuit device, the power conversion circuit may have a control terminal to which a control signal from the control circuit is input. In any of the above circuit devices, the power conversion circuit may have an output terminal that outputs an output signal to the control circuit. In any of the above circuit devices, the power conversion circuit may have a data recognition unit that recognizes an input data signal input to the output terminal.

[0013] In any of the above circuit devices, the data identification unit may be input with a first superimposed signal obtained by superimposing the output signal and the input data signal. In any of the above circuit devices, the data identification unit may identify the input data signal based on the first superimposed signal and the output signal.

[0014] In any of the above-mentioned circuit devices, the data identification unit may generate the input data signal by extracting pulses other than pulses of the output signal from pulses included in the first superimposed signal.

[0015] In any of the above-mentioned circuit devices, the output signal may include an alarm signal indicating whether the power conversion circuit is in a predetermined state.

[0016] In any of the above circuit devices, the output signal may include an output data signal output by the power conversion circuit.

[0017] Any of the above circuit devices may include a first transmission unit, which is provided between the output terminal and the control circuit and outputs the signal from the output terminal to the control circuit. Any of the above circuit devices may include a second transmission unit that superimposes the input data signal from the control circuit on the signal at the output terminal. In any of the above circuit devices, the data recognition unit may receive the signal at the output terminal.

[0018] In any of the above circuit devices, the control circuit may receive the first superimposed signal and identify the output signal according to the first superimposed signal and the input data signal.

[0019] In any of the above circuit devices, the first transmission unit can transmit a signal with a current value greater than a reference current value among the signals at the output terminal to the control circuit. In any of the above circuit devices, the second transmission unit can convert the input data signal into a signal with a current smaller than the reference current value and superimpose it on the signal at the output terminal.

[0020] In any of the above-mentioned circuit devices, the power conversion circuit may include a clock identification unit that separates a clock signal input to the control terminal from the control signal.

[0021] In any of the above circuit devices, the control terminal may be input with a second superimposed signal obtained by superimposing the control signal and the clock signal having an amplitude different from that of the control signal. In any of the above circuit devices, the clock identification unit may separate the control signal from the clock signal based on the amplitude of each pulse included in the second superimposed signal.

[0022] Any of the above circuit devices may include a third transmission unit, which is provided between the control circuit and the control terminal and transmits the control signal to the control terminal. Any of the above circuit devices may include a fourth transmission unit, which is provided between the control circuit and the control terminal and transmits the clock signal to the control terminal to generate the second superimposed signal. In any of the above circuit devices, at least one of the third transmission unit and the fourth transmission unit may include an amplitude conversion unit that converts the amplitude of a signal.

[0023] In any of the above circuit devices, the control circuit may arrange the pulse of the control signal and the pulse of the clock signal in different periods.

[0024] In any of the above-mentioned circuit devices, the control circuit may be capable of arranging a pulse of the control signal and a pulse of the clock signal in the same period.

[0025] Any of the above-mentioned circuit devices may have an amplitude control unit, which is arranged between the control circuit and the control terminal, and generates a pulse having an amplitude different from the amplitude of either the pulse of the control signal or the pulse of the clock signal during the period when the pulse of the control signal overlaps with the pulse of the clock signal.

[0026] In any of the above circuit devices, the amplitude control section may have a power supply wiring. In any of the above circuit devices, the amplitude control section may have a signal wiring to which the control signal is applied. In any of the above circuit devices, the amplitude control section may have a first resistor, a second resistor, and a third resistor connected in series between the power supply wiring and the signal wiring. In any of the above circuit devices, the clock signal is applied to a connection point between the first resistor and the second resistor. In any of the above circuit devices, the connection point between the second resistor and the third resistor may be connected to the control terminal.

[0027] In a second aspect of the present invention, there is provided a power conversion circuit controlled by a control circuit. The power conversion circuit may include a control terminal to which a control signal from the control circuit is input. Any of the power conversion circuits may include an output terminal to output an output signal to the control circuit. Any of the power conversion circuits may include a data recognition unit to recognize an input data signal input to the output terminal.

[0028] In any of the above power conversion circuits, the data identification unit may be input with a first superimposed signal obtained by superimposing the output signal and the input data signal. In any of the above power conversion circuits, the data identification unit may identify the input data signal based on the first superimposed signal and the output signal.

[0029] In any of the above-mentioned power conversion circuits, the data identification unit may generate the input data signal by extracting pulses other than pulses of the output signal from among pulses included in the first superimposed signal.

[0030] In any of the above-mentioned power conversion circuits, the output signal may include an alarm signal indicating whether the power conversion circuit is in a preset state.

[0031] In any of the above-mentioned power conversion circuits, the output signal may include an output data signal output by the power conversion circuit.

[0032] Any of the above-mentioned power conversion circuits may include a clock identification unit that separates a clock signal input to the control terminal from the control signal.

[0033] In any of the above power conversion circuits, the control terminal may be input with a second superimposed signal obtained by superimposing the control signal and the clock signal having an amplitude different from that of the control signal. In any of the above power conversion circuits, the clock identification unit may separate the control signal from the clock signal based on the amplitude of each pulse included in the second superimposed signal.

[0034] The above-mentioned invention content does not list all the features of the present invention. In addition, sub-combinations of these feature groups can also constitute inventions. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 This is a diagram showing an example of a circuit device 10 according to an embodiment of the present invention.

[0036] Figure 2 1 is a diagram showing a specific circuit example of the circuit device 10 .

[0037] Figure 3 It is a timing diagram for explaining the operation related to the input data signal SDAIu and the output signal OS.

[0038] Figure 4 This is a timing diagram that explains the operation related to the control signal and the clock signal.

[0039] Figure 5 2 is a diagram showing another configuration example of the third transmission unit 330 and the power conversion circuit 200 .

[0040] Figure 6 1 is a timing chart for explaining the operations of the control circuit 100 , the transmission device 300 , and the signal recognition unit 250 .

[0041] Explanation of symbols

[0042] 10: Circuit device, 100: Control circuit, 102: Control output terminal, 104: Clock output terminal, 106: Input terminal, 108: Data output terminal, 200: Power conversion circuit, 202: Control terminal, 204: Output terminal, 210: Signal output unit, 211: Resistor, 212: Buffer circuit, 213: NOR circuit, 220: Data identification unit, 221: Reference voltage generation unit, 222: Comparator, 223: Logic circuit, 230: Control identification unit, 231: Reference voltage generation unit, 232: Comparator, 240: Clock identification unit, 241: Reference voltage generation unit, 242: Comparator, 243: Logic circuit, 250: Signal identification unit, 251, 252, 253: Reference voltage generation unit, 261, 262, 263: Comparator, 270: Logic circuit, 300: Transmission device, 310: first transmission unit, 311: resistor, 313: photocoupler, 314: light emitting element, 315: light receiving element, 316: resistor, 320: second transmission unit, 321: buffer circuit, 322: resistor, 323: photocoupler, 324: light emitting element, 325: light receiving element, 326: Zener diode, 330: third transmission unit, 331: buffer circuit, 332: resistor, 333: photocoupler, 334: light emitting element, 335: light receiving element, 336: resistor, 340: fourth transmission unit, 341: buffer circuit, 342: resistor, 343: photocoupler, 344: light emitting element, 345: light receiving element, 346: Zener diode, 350: amplitude control unit, 351: first resistor, 352: second resistor, 353: third resistor, 354: power supply wiring, 355: signal wiring. DETAILED DESCRIPTION

[0043] The present invention is described below by the embodiments of the invention, but the following embodiments do not limit the invention involved in the claims. In addition, all combinations of the features described in the embodiments are not necessarily necessary for the solution of the invention. It should be noted that in this specification and the drawings, for elements having substantially the same function and structure, repeated descriptions are omitted by marking the same figure numerals, and for elements that are not directly related to the present invention, illustrations are omitted. In addition, in one drawing, for elements having the same function and structure, the figure numerals are representatively marked, and for others, the figure numerals are sometimes omitted.

[0044] In this specification, when it is said that they are "same" or "equal", it may include the case where there is an error due to manufacturing variation, etc. The error is within 10%, for example.

[0045] Figure 11 is a diagram showing an example of a circuit device 10 according to an embodiment of the present invention. The circuit device 10 includes one or more power conversion circuits 200 and a control circuit 100. The power conversion circuit 200 can output power to other circuits of an object device provided with the circuit device 10. As an example, the control circuit 100 is a computer provided in the object device. The control circuit 100 can control circuits of the object device other than the power conversion circuit 200. As an example, the object device is a vehicle or an industrial robot, etc., but is not limited thereto. The circuit device 10 may further include a transmission device 300 that transmits a signal between the power conversion circuit 200 and the control circuit 100. The transmission device 300 may be provided for each power conversion circuit 200.

[0046] The power conversion circuit 200 converts input power into a predetermined output power. As an example, the power conversion circuit 200 is an ACDC converter that converts DC power into AC power, but the form of the power conversion circuit 200 is not limited to this. The power conversion circuit 200 may include power semiconductors such as IGBTs. The power conversion circuit 200 may include an inverter. The power conversion circuit 200 may supply power to an electric motor such as a motor.

[0047] The control circuit 100 controls the power conversion circuit 200. The control circuit 100 can control the on and off of the operation of the power conversion circuit 200, and can also control the amplitude or frequency of the power output by the power conversion circuit 200. The control circuit 100 of this example sends a control signal to each power conversion circuit 200. The control signal can control the switching of the transistor inside the power conversion circuit 200.

[0048] The power conversion circuit 200 has a control terminal 202 and an output terminal 204. A control signal from the control circuit 100 is input to the control terminal 202 via the transmission device 300. The output terminal 204 outputs an output signal to the control circuit 100. The output signal is transmitted by the transmission device 300.

[0049] The output signal is, for example, a signal indicating the state of the power conversion circuit 200. The output signal may include an alarm signal indicating whether the power conversion circuit 200 has become a predetermined state. The state may be an abnormal state such as an overcurrent state in which a current exceeding a predetermined value flows through a predetermined portion of the power conversion circuit 200, an overvoltage state in which a voltage exceeding a predetermined value is applied to a predetermined portion of the power conversion circuit 200, or an overheat state in which the temperature of a predetermined portion of the power conversion circuit 200 becomes above a predetermined value. The power conversion circuit 200 may change the pulse width of the alarm signal according to the type of abnormal state. Thus, the control circuit 100 can detect the type of abnormality generated in the power conversion circuit 200.

[0050] The output signal may also include an output data signal generated by the power conversion circuit 200. The output signal may include one or both of the alarm signal and the output data signal. The output data signal may be a signal that numerically represents the internal state of the power conversion circuit 200. The output data signal may represent the numerical value of a parameter such as temperature, voltage, current, etc. of a predetermined part of the power conversion circuit 200. The output data signal may also be data generated in response to a request from the control circuit 100. Each signal in this specification may be a signal that represents one or more bits of information by a configuration pattern of pulses on a time axis.

[0051] The control circuit 100 of this example has a control output terminal 102, a clock output terminal 104, an input terminal 106, and a data output terminal 108. The control output terminal 102 outputs a control signal. The clock output terminal 104 outputs a clock signal. The input terminal 106 inputs an output signal from the power conversion circuit 200. The data output terminal 108 outputs an input data signal.

[0052] The input data signal is a signal including data input to the power conversion circuit 200. The input data signal may include arbitrary data. The input data signal may include data specifying the destination of the output signal of the power conversion circuit 200, data recorded in the memory inside the power conversion circuit 200, or data for controlling the operation of the power conversion circuit 200.

[0053] The clock signal is used for communication between the control circuit 100 and the power conversion circuit 200. For example, the power conversion circuit 200 can sample the data value of the input data signal according to the period of the clock signal. The clock signal can also be used as an operation clock for the internal circuit of the power conversion circuit 200.

[0054] The period of the clock signal may be less than the pulse width of the alarm signal. The period of the clock signal may be less than half of the pulse width of the alarm signal. The power conversion circuit 200 may generate an alarm signal having a pulse width that is an integer multiple of the period of the clock signal. The power conversion circuit 200 may generate an output data signal having the same period as the clock signal. The control circuit 100 may determine that an alarm signal is output when the pulse width of the output signal becomes greater than a certain value. The power conversion circuit 200 may output one of the alarm signals and the output data signal at the same time, preferably one of them. The power conversion circuit 200 may output the alarm signal preferentially.

[0055] The transmission device 300 of this example inputs the input data signal from the control circuit 100 to the output terminal 204 of the power conversion circuit 200. The power conversion circuit 200 has a data recognition unit that recognizes the input data signal input to the output terminal 204. The output terminal 204 functions as a terminal for outputting an output signal and functions as a terminal for inputting an input data signal, so that the number of terminals of the power conversion circuit 200 can be reduced.

[0056] The transmission device 300 can input both the control signal and the clock signal to the control terminal 202. The power conversion circuit 200 can have a clock identification unit that separates the clock signal input to the control terminal 202 from the control signal. The control terminal 202 functions as a terminal for inputting the control signal and as a terminal for inputting the clock signal, so that the number of terminals of the power conversion circuit 200 can be further reduced.

[0057] When a plurality of power conversion circuits 200 are connected to a common terminal of the control circuit 100, an identification code may be assigned to each power conversion circuit 200. The identification code may be included in at least one of the input data signal and the output data signal. When the control circuit 100 starts communicating with any power conversion circuit 200, it may send an input data signal including the identification code of the power conversion circuit 200. When each power conversion circuit 200 receives an input data signal including an identification code corresponding to itself, it may act according to the input data signal. The control circuit 100 may determine which power conversion circuit 200 the output data signal is from based on the identification information included in the output data signal.

[0058] The control circuit 100 may notify the power conversion circuit 200 of the start of communication by sending a clock signal. In other examples, the control circuit 100 may notify the start of communication in the same way as I2C communication. The control circuit 100 may also notify the start of communication using an input data signal.

[0059] Figure 2 1 is a diagram showing a specific circuit example of the circuit device 10. First, the structure related to the output signal and the input data signal transmitted between the output terminal 204, the input terminal 106, and the data output terminal 108 is described. Next, the structure related to the control signal and the clock signal transmitted between the control terminal 202, the control output terminal 102, and the clock output terminal 104 is described.

[0060] (Structure related to output signal and input data signal)

[0061] The power conversion circuit 200 of this example includes a signal output unit 210 and a data recognition unit 220 connected to the output terminal 204. The signal output unit 210 outputs an output signal OS transmitted from the power conversion circuit 200 to the control circuit 100. The output signal OS may include at least one of the alarm signal ALMOm and the output data signal SDAOm. The output signal OS of this example is a logical OR signal of the alarm signal ALMOm and the output data signal SDAOm.

[0062] The signal output unit 210 of this example has a NOR circuit 213, a buffer circuit 212, and a resistor 211. The NOR circuit 213 outputs an output signal OS representing the NOR of the alarm signal ALMOm and the output data signal SDAOm. For example, the alarm signal ALMOm and the output data signal SDAOm may be signals representing one or more bits of information according to the configuration pattern of pulses on the time axis. Each signal in this specification may be a signal in which an H-level voltage represents a logic value of 1 and an L-level voltage represents a logic value of 0. The NOR circuit 213 of this example may output an L-level voltage when at least one of the alarm signal ALMOm and the output data signal SDAOm shows an H-level voltage, and may output an H-level voltage when both the alarm signal ALMOm and the output data signal SDAOm show an L-level voltage.

[0063] The buffer circuit 212 outputs a signal corresponding to the output signal OS. The output terminal of the buffer circuit 212 is connected to the output terminal 204 via the resistor 211. The input data signal SDAIu from the control circuit 100 is applied to the output terminal 204 of this example. Therefore, the first superimposed signal WAS1 obtained by superimposing the output signal OS and the input data signal SDAIu is applied to the output terminal 204. In this example, the first superimposed signal WAS1 contains a mixture of pulses of the output signal OS and pulses of the input data signal SDAIu.

[0064] The data identification unit 220 extracts the input data signal SDAIm from the first superimposed signal WAS1. In this specification, the symbol u or m is sometimes added to the end of the symbol of each signal transmitted between the control circuit 100 and the power conversion circuit 200. The signal marked with the symbol u is a signal sent by the control circuit 100 or received by the control circuit 100. The signal marked with the symbol m is a signal sent by the power conversion circuit 200 or received by the power conversion circuit 200.

[0065] The data identification unit 220 of this example identifies the input data signal SDAIm based on the first superimposed signal WAS1 and the output signal OS. For example, the input data signal SDAIm can be identified by extracting a pulse train that is not a pulse of the output signal OS from the pulses included in the first superimposed signal WAS1. The data identification unit 220 of this example includes a reference voltage generation unit 221, a comparator 222, and a logic circuit 223.

[0066] The reference voltage generating section 221 generates a first reference voltage for extracting each pulse of the first superimposition signal WAS1. The first reference voltage in this example is higher than the L-level voltage of all pulses included in the first superimposition signal WAS1, and lower than the H-level voltage.

[0067] The comparator 222 outputs a signal showing an L-level voltage when the voltage of the first superimposed signal WAS1 is lower than the first reference voltage, and showing an H-level voltage when the voltage of the first superimposed signal WAS1 is higher than the first reference voltage. This signal includes all pulses of the first superimposed signal WAS1 (waveform showing an L-level voltage).

[0068] The logic circuit 223 extracts pulses other than the pulses of the output signal OS from the pulses included in the first superimposed signal WAS1 to generate the input data signal SDAIm. The logic circuit 223 of this example outputs the input data signal SDAIm which becomes L level when the output signal OS shows an H level voltage and the output of the comparator 222 shows an L level voltage, and becomes H level in other periods. That is, during the period when the output signal OS does not have a pulse and the first superimposed signal WAS1 has a pulse, the input data signal SDAIm has a pulse. The logic circuit 223 can output a signal obtained by logically inverting the inverted signal of the output of the comparator 222 and the output signal OS. The logic circuit 223 can have other structures. For example, the logic circuit 223 can also include a circuit that outputs a logical exclusive OR of the output signal OS and the first superimposed signal WAS1.

[0069] According to such a configuration, the input data signal SDAIm input to the output terminal 204 can be extracted from the first superimposed signal WAS1. Since a terminal for receiving the input data signal SDAIm does not need to be newly provided, the number of terminals of the power conversion circuit 200 can be reduced.

[0070] The transmission device 300 of this example has a first transmission section 310 and a second transmission section 320 provided between the output terminal 204 and the control circuit 100. The first transmission section 310 outputs the signal at the output terminal 204 to the input terminal 106 of the control circuit 100. The second transmission section 320 superimposes the input data signal SDAIu from the data output terminal 108 of the control circuit 100 on the signal at the output terminal 204. Thus, the first superimposed signal WAS1 is applied to the output terminal 204.

[0071] The first transmission unit 310 of this example includes a resistor 311, a photocoupler 313, and a resistor 316. The photocoupler 313 includes a light emitting element 314 such as a light emitting diode and a light receiving element 315 such as a phototransistor. By using the photocoupler 313, a signal can be transmitted while electrically isolating the transmission side and the reception side of the signal.

[0072] The light emitting element 314 emits light in response to the pulse of the first superimposed signal WAS1. A predetermined high voltage (e.g., 15V) is applied to the anode of the light emitting element 314 in this example, and a predetermined high voltage (e.g., 15V) is also applied to the cathode of the light emitting element 314 via the resistor 316. In addition, the cathode of the light emitting element 314 is connected to the output terminal 204. Thus, when the first superimposed signal WAS1 becomes an L-level voltage, the light emitting element 314 emits light.

[0073] The light receiving element 315 converts the light from the light emitting element 314 into an electrical signal. The light receiving element 315 can generate an electrical signal with an amplitude different from that of the first superimposed signal WAS1, or can generate an electrical signal with the same amplitude as that of the first superimposed signal WAS1. A predetermined high voltage VDD is applied to the collector of the light receiving element 315 of this example via the resistor 311, and a predetermined reference potential GND1 is applied to the emitter. In addition, the collector of the light receiving element 315 is connected to the input terminal 106. Thus, an input signal ALMu_SDAu having the same pulse pattern as the first superimposed signal WAS1 and having an amplitude corresponding to the high voltage VDD is applied to the input terminal 106. The high voltage VDD may be different from the high voltage (e.g., 15V) applied to the resistor 316. The high voltage VDD in this example is 5V. The reference potential GND1 is, for example, 0V.

[0074] The pulse pattern of the input signal ALMu_SDAu is the same as the pulse pattern of the first superimposed signal WAS1. Therefore, the input signal ALMu_SDAu includes pulses of both the output signal OS and the input data signal SDAIu. The control circuit 100 can extract the pulse pattern of the output signal OS from the input signal ALMu_SDAu based on the pulse pattern of the input data signal SDAIu generated by itself. The control circuit 100 can extract the pulses in the period in which the input data signal SDAIu does not have a pulse from the pulses of the input signal ALMu_SDAu as the pulse pattern of the output signal OS. This processing can be performed by a computer-based logical operation processing, or it can be performed by a circuit similar to the data identification unit 220.

[0075] The second transmission unit 320 of this example includes a buffer circuit 321, a resistor 322, a photocoupler 323, and a Zener diode 326. The photocoupler 323 includes a light emitting element 324 such as a light emitting diode and a light receiving element 325 such as a phototransistor.

[0076] The light emitting element 324 emits light in response to the pulse of the input data signal SDAIu. The anode of the light emitting element 324 in this example is applied with a high voltage VDD. The cathode of the light emitting element 324 is connected to the output of the buffer circuit 321 via the resistor 322. The input of the buffer circuit 321 is connected to the data output terminal 108. The buffer circuit 321 applies a voltage corresponding to the input data signal SDAIu to the cathode of the light emitting element 324. Thus, the light emitting element 324 emits light in response to the pulse (L level voltage) in the input data signal SDAIu.

[0077] The light receiving element 325 converts the light from the light emitting element 324 into an electrical signal. A predetermined high voltage (for example, 15V) is applied to the collector of the light receiving element 325 of this example via the Zener diode 326 and the resistor 316, and a predetermined reference potential GND2 is applied to the emitter. The reference potential GND2 is, for example, 0V.

[0078] The anode of the Zener diode 326 is connected to the collector of the light receiving element 325, and a high voltage (e.g., 15V) is applied to the cathode of the Zener diode 326 via the resistor 316. In addition, the cathode of the Zener diode 326 is connected to the output terminal 204. The amplitude of the input data signal SDAIu superimposed on the output terminal 204 is determined according to the breakdown voltage of the Zener diode 326. In this example, the L-level voltage of the input data signal SDAIu superimposed on the output terminal 204 is equal to the breakdown voltage of the Zener diode 326. The breakdown voltage of the Zener diode 326 can be less than the high voltage (e.g., 15V) applied to the resistor 316. As an example, the breakdown voltage of the Zener diode 326 is 5V.

[0079] As described above, a signal having the same pulse pattern as the first superimposed signal WAS1 can be input to the input terminal 106 of the control circuit 100. The control circuit 100 can identify the output signal OS based on the received first superimposed signal WAS1 and the input data signal SDAIu. The control circuit 100 can determine the pulses of the first superimposed signal WAS1 that are inconsistent with the pulses of the input data signal SDAIu as the pulses of the output signal OS. The control circuit 100 can also stop the output of the input data signal SDAIu when it is determined that there are pulses of the output signal OS in the first superimposed signal WAS1. As a result, in the first superimposed signal WAS1, the pulses of the input data signal SDAIu do not overlap with the pulses of the output signal OS, and the pulses of the output signal OS can be communicated preferentially. When the pulses of the output signal OS are not received within the set period, the control circuit 100 can restart the output of the input data signal SDAIu.

[0080] In other examples, a signal having the same pulse pattern as the output signal OS may be input to the input terminal 106 of the control circuit 100. In this case, the control circuit 100 can process the pulse pattern of the signal input to the input terminal 106 as the pulse pattern of the output signal OS. The first transmission unit 310 transmits a signal (in this example, a pulse) in which a current exceeding the reference current value flows in the first superimposed signal WAS1 at the output terminal 204 to the control circuit 100. The reference current value is the lower limit current value at which the light emitting element 314 can emit light.

[0081] The buffer circuit 212 and the resistor 211 of this example cause a current greater than the reference current value to flow through the light-emitting element 314 in response to the pulse of the output signal OS. On the other hand, the second transmission unit 320 converts the input data signal SDAIu into a signal having a current smaller than the reference current value, and superimposes it on the signal at the output terminal 204. By adjusting the breakdown current of the Zener diode 326, the current flowing in response to the pulse of the input data signal SDAIu can be adjusted. The second transmission unit 320 may also have an element such as a resistor that adjusts the breakdown current of the Zener diode 326 in series with the Zener diode 326. Thus, the light-emitting element 314 can emit light in response to the pulse of the output signal OS, rather than the light-emitting element 314 emitting light in response to the pulse of the input data signal SDAIu. Therefore, a signal with the same pulse pattern as the output signal OS can be input to the input terminal 106 of the control circuit 100.

[0082] (Structure related to control signals and clock signals)

[0083] The power conversion circuit 200 of this example includes a control identification unit 230 and a clock identification unit 240 connected to a control terminal 202. A second superimposed signal WAS2 obtained by superimposing a control signal BRu and a clock signal SCLu is input to the control terminal 202. The control identification unit 230 identifies the control signal BRu included in the second superimposed signal WAS2. The clock identification unit 240 identifies the clock signal SCLu included in the second superimposed signal WAS2.

[0084] The second superimposed signal WAS2 includes pulses of the control signal BRu and pulses of the clock signal SCLu. The pulses of the control signal BRu and the pulses of the clock signal SCLu included in the second superimposed signal WAS2 are pulses that can be distinguished from each other. The amplitude of the pulse of the control signal BRu in this example is different from the amplitude of the pulse of the clock signal SCLu.

[0085] The control identification unit 230 separates the control signal BRu and the clock signal SCLu included in the second superimposed signal WAS2 and identifies them. The control identification unit 230 of this example identifies the pulses of the control signal BRu based on the amplitude of each pulse included in the second superimposed signal WAS2. The control identification unit 230 of this example includes a reference voltage generation unit 231 and a comparator 232.

[0086] The reference voltage generating unit 231 generates a second reference voltage corresponding to the amplitude of the pulses of the control signal Bru and the clock signal SCLu. For example, when the voltage of the pulse of the control signal BRu (in this example, the voltage of the L level) is lower than the voltage of the pulse of the clock signal SCLu, the second reference voltage is a voltage between the voltage of the pulse of the control signal BRu and the voltage of the pulse of the clock signal SCLu.

[0087] The comparator 232 outputs a control signal BRm that shows an L-level voltage when the voltage of the second superimposed signal WAS2 is lower than the second reference voltage, and shows an H-level voltage when the voltage of the second superimposed signal WAS2 is higher than the second reference voltage. In this example, the voltage of the pulse of the control signal BRu is lower than the second reference voltage, and the voltage of the pulse of the clock signal SCLu is higher than the second reference voltage. Therefore, by comparing the voltage of the second superimposed signal WAS2 with the second reference voltage, it is possible to generate a control signal BRm obtained by extracting the pulse of the control signal BRu included in the second superimposed signal WAS2.

[0088] The clock identification unit 240 separates the clock signal SCLu and the control signal BRu included in the second superimposed signal WAS2 and identifies them. The clock identification unit 240 of this example identifies the pulses of the clock signal SCLu based on the amplitude of each pulse included in the second superimposed signal WAS2. The clock identification unit 240 of this example includes a reference voltage generation unit 241, a comparator 242, and a logic circuit 243.

[0089] The reference voltage generator 241 generates a third reference voltage corresponding to the amplitude of the pulses of the control signal Bru and the clock signal SCLu. The third reference voltage in this example is higher than the voltage (L level voltage) of the pulses of either the control signal BRu or the clock signal SCLu, and lower than the H level voltage.

[0090] The comparator 242 outputs a signal showing an L-level voltage when the voltage of the second superimposed signal WAS2 is lower than the third reference voltage, and showing an H-level voltage when the voltage of the second superimposed signal WAS2 is higher than the third reference voltage. In this example, the voltage of each pulse of the control signal BRu and the clock signal SCLu is lower than the third reference voltage. Therefore, the signal output by the comparator 242 includes all the pulses of the second superimposed signal WAS2.

[0091] The logic circuit 243 extracts pulses other than the pulses of the control signal BRm from the pulses included in the second superimposed signal WAS2, and generates the clock signal SCLm. The logic circuit 243 of this example outputs the clock signal SCLm which becomes L level during the period when the control signal BRm shows an H level voltage and the comparator 242 outputs an L level voltage, and becomes H level during other periods. The logic circuit 243 can output a signal obtained by inverting the logical AND of the inverted signal outputted from the comparator 242 and the control signal BRm. The logic circuit 243 can have other structures as described in the logic circuit 223.

[0092] With such a configuration, the control signal BRu and the clock signal SCLu input to the control terminal 202 can be separated and identified from each other. Since a new terminal for inputting the clock signal SCLu need not be provided, the number of terminals of the power conversion circuit 200 can be reduced.

[0093] In this example, the case where the voltage of the pulse of the control signal BRu is lower than the voltage of the pulse of the clock signal SCLu is described. In other examples, the voltage of the pulse of the control signal BRu may be higher than the voltage of the pulse of the clock signal SCLu. When the second superimposed signal WAS2 including such a pulse is input to Figure 2 In the case of the control terminal 202 shown, the output of the control recognition unit 230 corresponds to the clock signal SCLm, and the output of the clock recognition unit 240 corresponds to the control signal BRm.

[0094] The transmission device 300 of this example includes a third transmission section 330 and a fourth transmission section 340 provided between the control terminal 202 and the control circuit 100. The third transmission section 330 outputs the control signal BRu from the control output terminal 102 to the control terminal 202. The fourth transmission section 340 superimposes the clock signal SCLu from the clock output terminal 104 on the signal at the control terminal 202. Thus, the second superimposed signal WAS2 is applied to the control terminal 202.

[0095] The third transmission unit 330 of this example includes a buffer circuit 331, a resistor 332, a photocoupler 333, and a resistor 336. The photocoupler 333 includes a light emitting element 334 such as a light emitting diode and a light receiving element 335 such as a phototransistor.

[0096] The light emitting element 334 emits light in response to the pulse of the control signal BRu. The anode of the light emitting element 334 in this example is applied with a high voltage VDD. The cathode of the light emitting element 334 is connected to the output of the buffer circuit 331 via the resistor 332. The input of the buffer circuit 331 is connected to the control output terminal 102. The buffer circuit 331 applies a voltage corresponding to the control signal BRu to the cathode of the light emitting element 334. Thus, the light emitting element 334 emits light in response to the pulse (L level voltage) in the control signal BRu.

[0097] The light receiving element 335 converts the light from the light emitting element 334 into an electrical signal. A predetermined high voltage (e.g., 15V) is applied to the collector of the light receiving element 335 of this example via the resistor 336, and a predetermined reference potential GND2 is applied to the emitter of the light receiving element 335. As a result, a control signal BRu having an amplitude corresponding to the high voltage (e.g., 15V) is applied to the control terminal 202.

[0098] The fourth transmission unit 340 of this example includes a buffer circuit 341, a resistor 342, a photocoupler 343, and a Zener diode 346. The photocoupler 343 includes a light emitting element 344 such as a light emitting diode and a light receiving element 345 such as a phototransistor.

[0099] The light emitting element 344 emits light in response to the pulse of the clock signal SCLu. The anode of the light emitting element 344 in this example is applied with a high voltage VDD. The cathode of the light emitting element 344 is connected to the output of the buffer circuit 341 via the resistor 342. The input of the buffer circuit 341 is connected to the clock output terminal 104. The buffer circuit 341 applies a voltage corresponding to the clock signal SCLu to the cathode of the light emitting element 344. Thus, the light emitting element 344 emits light in response to the pulse (L level voltage) in the clock signal SCLu.

[0100] The light receiving element 345 converts light from the light emitting element 344 into an electric signal. A predetermined high voltage (eg, 15V) is applied to the collector of the light receiving element 345 of this example via the Zener diode 346 and the resistor 336, and a predetermined reference potential GND2 is applied to the emitter of the light receiving element 345.

[0101] The anode of the Zener diode 346 is connected to the collector of the light receiving element 345, and a high voltage (e.g., 15V) is applied to the cathode of the Zener diode 346 via the resistor 336. In addition, the cathode of the Zener diode 346 is connected to the control terminal 202. The amplitude of the clock signal SCLm superimposed on the control terminal 202 is determined according to the breakdown voltage of the Zener diode 346. The breakdown voltage of the Zener diode 346 can be smaller than the high voltage applied to the resistor 336. As an example, the breakdown voltage of the Zener diode 346 is 5V.

[0102] As described above, the amplitude of the pulse of the control signal BRu included in the second superimposed signal WAS2 in this example is different from the amplitude of the pulse of the clock signal SCLu. At least one of the third transmission section 330 and the fourth transmission section 340 may include an amplitude conversion section that converts the amplitude of a signal. Figure 2 In the example of , the Zener diode 346 of the fourth transmission unit 340 functions as an amplitude conversion unit. According to such a configuration, the pulse of the control signal BRu and the pulse of the clock signal SCLu included in the second superimposed signal WAS2 can be separated.

[0103] Figure 3 1 is a timing diagram illustrating the operation related to the input data signal SDAIu and the output signal OS. Figure 2 As described in , the control circuit 100 outputs the input data signal SDAIu. The power conversion circuit 200 outputs the output signal OS.

[0104] like Figure 3 As shown, the first superimposed signal WAS1 at the output terminal 204 includes pulses of the input data signal SDAIu and the output signal OS. The amplitude of the pulse of the input data signal SDAIu included in the first superimposed signal WAS1 may be different from the amplitude of the pulse of the output signal OS. In this example, the pulse corresponding to the input data signal SDAIu has an amplitude (15V to 5V) corresponding to the breakdown voltage (e.g., 5V) of the Zener diode 326. In addition, the pulse corresponding to the output signal OS has an amplitude (15V to 0V) corresponding to the reference potential GND2 (0V). In other examples, the pulse of the input data signal SDAIu included in the first superimposed signal WAS1 and the pulse of the output signal OS may also have the same amplitude.

[0105] The first transmission unit 310 transmits the first superimposed signal WAS1 to the input terminal 106. The first transmission unit 310 of this example transmits the first superimposed signal WAS1 with the same amplitude of each pulse through the photocoupler 313. The control circuit 100 of this example receives the input signal ALMu_SDAu having the same pulse pattern as the first superimposed signal WAS1. As described above, the control circuit 100 can identify the output signal OS of the power conversion circuit 200 based on the input signal ALMu_SDAu and the input data signal SDAIu generated by itself.

[0106] The reference voltage generating unit 221 of the data identification unit 220 generates a first reference voltage capable of extracting all pulses included in the first superimposed signal WAS1. The reference voltage generating unit 221 of this example generates a voltage higher than 5V and lower than 15V. The comparator 222 compares the first reference voltage with the voltage of the first superimposed signal WAS1. The pulse pattern of the signal output by the comparator 222 is the same as the pulse pattern of the first superimposed signal WAS1. In this example, the pulse pattern of the signal output by the comparator 222 is the same as the pulse pattern of the signal ALMu_SDAu, so it is omitted.

[0107] The logic circuit 223 generates the input data signal SDAIm based on the signal output from the comparator 222 and the output signal OS. As described above, the logic circuit 223 extracts pulses that do not overlap with the pulses of the output signal OS from the pulses included in the signal output from the comparator 222. Thus, the input data signal SDAIm can be generated.

[0108] Figure 4 is a timing diagram that illustrates the actions related to the control signal and the clock signal. Figure 2 As described in , the control circuit 100 outputs the control signal Bru and the clock signal SCLu. The control signal Bru and the clock signal SCLu output by the control circuit 100 are signals that become the high voltage VDD during a period without a pulse and become the reference potential GND1 (0V) during a period with a pulse.

[0109] like Figure 4 As shown, the second superimposed signal WAS2 at the control terminal 202 includes pulses of the control signal BRu and the clock signal SCLu. The amplitude of the pulse of the control signal BRu included in the second superimposed signal WAS2 of this example is different from the amplitude of the pulse of the clock signal SCLu. In this example, the pulse corresponding to the clock signal SCLu has an amplitude (15V to 5V) corresponding to the breakdown voltage (e.g., 5V) of the Zener diode 346. In addition, the pulse corresponding to the control signal BRu has an amplitude (15V to 0V) corresponding to the reference potential GND2 (0V).

[0110] The reference voltage generation unit 231 of the control identification unit 230 generates a second reference voltage capable of extracting only the pulse corresponding to the control signal BRu from the pulses included in the second superimposition signal WAS2. The second reference voltage in this example is greater than 0V and less than 5V.

[0111] The comparator 232 of the control identification section 230 compares the voltage of the second superimposed signal WAS2 with the second reference voltage. The pulse pattern of the control signal BRm output by the comparator 232 is the same as the pulse pattern of the control signal of the control signal BRu.

[0112] The reference voltage generating section 241 of the clock identification section 240 generates a third reference voltage capable of extracting all pulses included in the second superimposed signal WAS2. The third reference voltage in this example is higher than 5 V and lower than 15 V. The comparator 242 compares the third reference voltage with the voltage of the second superimposed signal WAS2. The pulse pattern of the signal output by the comparator 242 is the same as the pulse pattern of the second superimposed signal WAS2.

[0113] The logic circuit 243 generates the clock signal SCLm based on the signal output from the comparator 242 and the control signal BRm. As described above, the logic circuit 243 extracts pulses that do not overlap with the pulses of the control signal BRm from the pulses included in the signal output from the comparator 242. Thus, the clock signal SCLm can be generated.

[0114] The control circuit 100 of this example arranges the pulses of the control signal BRu and the pulses of the clock signal SCLu in different periods. Figure 4 In the example, the pulse of the control signal BRu is arranged in the period A, and the pulse of the clock signal SCLu is arranged in the period B. With such an arrangement, the pulse of the control signal BRu and the pulse of the clock signal SCLu can be distinguished with high accuracy.

[0115] Figure 5is a diagram showing another structural example of the third transmission unit 330 and the power conversion circuit 200. The control circuit 100 of this example can configure the pulse of the control signal BRu and the pulse of the clock signal SCLu in the same period. The transmission device 300 of this example generates a pulse of an amplitude different from either the pulse of the control signal BRu or the pulse of the clock signal SCLu when the pulse of the control signal BRu overlaps with the pulse of the clock signal SCLu. Thus, a single pulse of the control signal BRu, a single pulse of the clock signal SCLu, and a pulse where the control signal BRu overlaps with the clock signal SCLu can be identified respectively. The second superimposed signal includes these pulses. The power conversion circuit 200 determines whether each pulse is a single pulse of the control signal BRu, a single pulse of the clock signal SCLu, or a pulse where the control signal BRu overlaps with the clock signal SCLu based on the amplitude of each pulse of the second superimposed signal.

[0116] The third transmission unit 330 of this example has an amplitude control unit 350 instead of the resistor 336. Figure 2 The amplitude control unit 350 is provided between the control circuit 100 and the control terminal 202, and generates a pulse having an amplitude different from the amplitude of either the pulse of the control signal BRu or the pulse of the clock signal SCLu during the period when the pulse of the control signal BRu overlaps with the pulse of the clock signal SCLu.

[0117] The amplitude control unit 350 of this example includes a power supply wiring 354, a signal wiring 355, a first resistor 351, a second resistor 352, and a third resistor 353. The power supply wiring 354 is a wiring to which a predetermined high voltage (e.g., 15 V) is applied. The signal wiring 355 is a wiring to which a control signal BRu is applied. The signal wiring 355 of this example is connected to the collector of the light receiving element 335.

[0118] The first resistor 351, the second resistor 352, and the third resistor 353 are connected in series between the power supply wiring 354 and the signal wiring 355. The first resistor 351 is connected to the power supply wiring 354, and the third resistor 353 is connected to the signal wiring 355. The second resistor 352 is connected between the first resistor 351 and the third resistor 353.

[0119] The clock signal SCLu is applied to the connection point between the first resistor 351 and the second resistor 352. In this example, the cathode of the Zener diode 346 is connected to the connection point. In addition, the connection point between the second resistor 352 and the third resistor 353 is connected to the control terminal 202. The resistance values ​​of the first resistor 351, the second resistor 352, and the third resistor 353 may be the same or different.

[0120] During the period when the pulses of the control signal BRu and the clock signal SCLu overlap, the light receiving element 335 and the light receiving element 345 are turned on. The voltage at the connection point between the first resistor 351 and the second resistor 352 is clamped to the breakdown voltage (5V) of the Zener diode 346. In addition, the reference potential GND2 (0V) is applied to the signal wiring 355. Therefore, the voltage of the second superimposed signal WAS2 becomes a voltage obtained by dividing 5V by the resistance ratio of the second resistor 352 and the third resistor 353. As an example, when the resistance values ​​of the second resistor 352 and the third resistor 353 are equal, the voltage of the second superimposed signal WAS2 is 2.5V.

[0121] The voltage of the second superimposed signal WAS2 in the case where the pulse of the control signal BRu exists alone and in the case where the pulse of the clock signal SCLu exists alone can be different from Figure 4 The voltage of each signal is determined in accordance with the resistance value of each resistor, etc. The voltage of the second superimposed signal WAS2 in the case where the pulse of the control signal BRu exists alone and the pulse of the clock signal SCLu exists alone can also be the same as Figure 4 In this example, the voltage of the second superimposed signal WAS2 when the pulse of the control signal BRu exists alone is lower than the voltage of the second superimposed signal WAS2 during the period when the pulses of the control signal BRu and the clock signal SCLu overlap (for example, 0V). In addition, the voltage of the second superimposed signal WAS2 when the pulse of the clock signal SCLu exists alone is higher than the voltage of the second superimposed signal WAS2 during the period when the pulses of the control signal BRu and the clock signal SCLu overlap (for example, 5V).

[0122] During the period when the pulse of the control signal BRu exists alone, the light receiving element 335 is turned on and the light receiving element 345 is turned off. The voltage at the connection point between the first resistor 351 and the second resistor 352 is not clamped by the Zener diode 346. In addition, the reference potential GND2 (0V) is applied to the signal wiring 355. Therefore, the voltage of the second superimposed signal WAS2 becomes a voltage obtained by dividing 15V by the resistance ratio of the first resistor 351, the second resistor 352, and the third resistor 353. As an example, when the sum of the resistance values ​​of the first resistor 351 and the second resistor 352 is much larger than the resistance value of the third resistor 353, the voltage of the second superimposed signal WAS2 is approximately 0V. The resistance value of the first resistor 351 can be greater than the sum of the resistance values ​​of the second resistor 352 and the third resistor 353.

[0123] During the period when the pulse of the clock signal SCLu exists alone, the light receiving element 335 is turned off and the light receiving element 345 is turned on. The voltage at the connection point between the first resistor 351 and the second resistor 352 is clamped to 5V by the Zener diode 346. In addition, the signal wiring 355 is disconnected from the reference potential GND2 (0V). Therefore, the voltage of the second superimposed signal WAS2 is 5V.

[0124] The power conversion circuit 200 of this example includes a signal recognition unit 250 that functions as a control recognition unit 230 and a clock recognition unit 240. Figures 1 to 4 The example described in is the same.

[0125] The signal identification unit 250 separates the control signal BRu and the clock signal SCLu from the second superimposed signal WAS2. As described above, in the second superimposed signal WAS2, there are pulses with different amplitudes in the case where the pulse of the control signal BRu exists alone, the case where the pulse of the clock signal SCLu exists alone, and the case where the pulses of the control signal BRu and the clock signal SCLu overlap. The signal identification unit 250 determines whether each pulse is a single pulse of the control signal BRu and the clock signal SCLu or a pulse obtained by overlapping the control signal BRu and the clock signal SCLu based on the amplitude of each pulse of the second superimposed signal WAS2. The signal identification unit 250 generates the control signal BRm and the clock signal SCLm based on the determination result.

[0126] The signal recognition unit 250 of this example includes a reference voltage generation unit 251, a comparator 261, a reference voltage generation unit 252, a comparator 262, a reference voltage generation unit 253, a comparator 263, and a logic circuit 270. The operation of the signal recognition unit 250 will be described using a timing chart.

[0127] Figure 6 1 is a timing diagram for explaining the operation of the control circuit 100, the transmission device 300, and the signal recognition unit 250. The control circuit 100 of this example outputs both the pulse of the control signal BRu and the pulse of the clock signal SCLu during period C. The operation during periods A and B is similar to Figure 4 Same as the example.

[0128] When the pulse of the control signal BRu exists alone, the voltage of the second superimposed signal WAS2 becomes the first voltage (0 V in this example). When the pulse of the control signal BRu overlaps with the pulse of the clock signal SCLu, the voltage of the second superimposed signal WAS2 becomes the second voltage (2.5 V in this example). When the pulse of the clock signal exists alone, the voltage of the second superimposed signal WAS2 becomes the third voltage (5 V in this example).

[0129] The reference voltage generating unit 251 generates a fourth reference voltage that is higher than the first voltage (0 V) and lower than the second voltage (2.5 V). The comparator 261 outputs an L-level voltage when the voltage of the second superimposed signal WAS2 is lower than the fourth reference voltage, and outputs an H-level voltage when the voltage of the second superimposed signal WAS2 is higher than the fourth reference voltage. Thus, the comparator 261 outputs a signal that is L-level during a period when the pulse of the control signal BRu exists alone and is H-level during other periods.

[0130] The reference voltage generating unit 252 generates a fifth reference voltage that is higher than the second voltage (2.5V) and lower than the third voltage (5V). The comparator 262 outputs an L-level voltage when the voltage of the second superimposed signal WAS2 is lower than the fifth reference voltage, and outputs an H-level voltage when the voltage of the second superimposed signal WAS2 is higher than the fifth reference voltage. Thus, the comparator 262 outputs a signal that is L-level during the period when the pulse of the control signal BRu is present and H-level during other periods, regardless of the presence or absence of the pulse of the clock signal SCLu. The signal recognition unit 250 of this example sets the signal output by the comparator 262 as the control signal BRm.

[0131] The reference voltage generating unit 253 generates a sixth reference voltage that is higher than the third voltage (5V) and lower than a predetermined high voltage (15V). The comparator 263 outputs an L-level voltage when the voltage of the second superimposed signal WAS2 is lower than the sixth reference voltage, and outputs an H-level voltage when the voltage of the second superimposed signal WAS2 is higher than the sixth reference voltage. Thus, the comparator 263 outputs a signal that is L-level during a period when there is a pulse of at least one of the control signal Bru and the clock signal SCLu, and is H-level during other periods.

[0132] The logic circuit 270 generates a clock signal SCLm based on the signal output by the comparator 261 and the signal output by the comparator 263. The logic circuit 270 of this example outputs a voltage of an L level during a period when the signal output by the comparator 261 shows an H level and the signal output by the comparator 263 shows an L level. During other periods, the logic circuit 270 outputs a voltage of an H level. The signal recognition unit 250 of this example sets the signal output by the logic circuit 270 as the clock signal SCLm. The logic circuit 270 can invert the inverted signal of the output of the comparator 263 and the logical AND of the output of the comparator 261 and output them.

[0133] According to this example, the control signal BRu and the clock signal SCLu can be transmitted simultaneously using one control terminal 202. Therefore, the number of terminals of the power conversion circuit 200 can be reduced and the degree of freedom of the signal patterns of the control signal BRu and the clock signal SCLu can be increased.

[0134] The present invention has been described above using the embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various changes or improvements can be made to the above embodiments. According to the description of the claims, the method to which such changes or improvements are made can also be included in the technical scope of the present invention.

Claims

1. A circuit device, characterized in that: A power conversion circuit and a control circuit for controlling the power conversion circuit are provided. The power conversion circuit has: a control terminal to which a control signal from the control circuit is input; an output terminal, which outputs an output signal to the control circuit; as well as The data recognition unit recognizes an input data signal input to the output terminal.

2. The circuit arrangement according to claim 1, characterized in that The data identification unit receives a first superimposed signal obtained by superimposing the output signal and the input data signal. The data identification section identifies the input data signal based on the first superimposed signal and the output signal.

3. The circuit arrangement according to claim 2, characterized in that The data identification unit extracts pulses other than pulses of the output signal from among pulses included in the first superimposed signal to generate the input data signal.

4. The circuit arrangement according to claim 1, characterized in that The output signal includes an alarm signal indicating whether the power conversion circuit is in a preset state.

5. The circuit arrangement according to claim 1, characterized in that The output signal includes an output data signal output by the power conversion circuit.

6. The circuit arrangement according to claim 2, characterized in that The circuit device further comprises: a first transmission unit, which is provided between the output terminal and the control circuit and outputs a signal from the output terminal to the control circuit; as well as a second transmission section that superimposes the input data signal from the control circuit on the signal at the output terminal, The data recognition section receives a signal at the output terminal.

7. The circuit arrangement according to claim 2, characterized in that The control circuit receives the first superimposed signal and identifies the output signal according to the first superimposed signal and the input data signal.

8. The circuit arrangement according to claim 6, characterized in that The first transmission unit transmits a signal having a value greater than or equal to a reference current among the signals at the output terminal to the control circuit. The second transfer section converts the input data signal into a signal having a current smaller than the reference current value, and superimposes the converted signal on the signal at the output terminal.

9. The circuit arrangement according to any one of claims 1 to 8, characterized in that The power conversion circuit further includes a clock identification unit that separates a clock signal input to the control terminal from the control signal.

10. The circuit arrangement according to claim 9, characterized in that The control terminal receives an input of a second superimposed signal obtained by superimposing the control signal and the clock signal having an amplitude different from that of the control signal. The clock identification unit separates the control signal from the clock signal based on the amplitude of each pulse included in the second superimposed signal.

11. The circuit arrangement according to claim 10, characterized in that The circuit device further comprises: a third transmission unit, which is disposed between the control circuit and the control terminal and transmits the control signal to the control terminal; as well as a fourth transmission unit, which is provided between the control circuit and the control terminal, and transmits the clock signal to the control terminal to generate the second superimposed signal, At least one of the third transmission section and the fourth transmission section includes an amplitude conversion section that converts the amplitude of a signal.

12. The circuit arrangement according to claim 10, characterized in that The control circuit arranges the pulse of the control signal and the pulse of the clock signal in different periods.

13. The circuit arrangement according to claim 10, characterized in that The control circuit can arrange the pulse of the control signal and the pulse of the clock signal in the same period.

14. The circuit arrangement according to claim 13, characterized in that The circuit device also includes an amplitude control unit, which is arranged between the control circuit and the control terminal, and generates a pulse having an amplitude different from the amplitude of either the pulse of the control signal or the pulse of the clock signal during the period when the pulse of the control signal overlaps with the pulse of the clock signal.

15. The circuit arrangement according to claim 14, characterized in that The amplitude control unit comprises: Power wiring; a signal wiring to which the control signal is applied; as well as A first resistor, a second resistor, and a third resistor are connected in series between the power supply wiring and the signal wiring, The clock signal is applied to a connection point between the first resistor and the second resistor. A connection point between the second resistor and the third resistor is connected to the control terminal.

16. A power conversion circuit, characterized in that: Controlled by a control circuit, with: a control terminal to which a control signal from the control circuit is input; an output terminal that outputs an output signal to the control circuit; and The data recognition unit recognizes an input data signal input to the output terminal.

17. The power conversion circuit according to claim 16, characterized in that: The data identification unit receives a first superimposed signal obtained by superimposing the output signal and the input data signal. The data identification section identifies the input data signal based on the first superimposed signal and the output signal.

18. The power conversion circuit according to claim 17, characterized in that: The data identification unit extracts pulses other than pulses of the output signal from among pulses included in the first superimposed signal to generate the input data signal.

19. The power conversion circuit according to claim 16, characterized in that: The output signal includes an alarm signal indicating whether the power conversion circuit is in a preset state.

20. The power conversion circuit according to claim 16, characterized in that: The output signal includes an output data signal output by the power conversion circuit.

21. The power conversion circuit according to any one of claims 16 to 20, characterized in that: The power conversion circuit further includes a clock identification unit that separates a clock signal input to the control terminal from the control signal.

22. The power conversion circuit according to claim 21, characterized in that: The control terminal receives an input of a second superimposed signal obtained by superimposing the control signal and the clock signal having an amplitude different from that of the control signal. The clock identification unit separates the control signal from the clock signal based on the amplitude of each pulse included in the second superimposed signal.

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