Time synchronization methods and time synchronization devices

Abstract

This application discloses a time synchronization method and a time synchronization device, belonging to the field of communication technology. The time synchronization method includes: receiving the i-th pulse signal transmitted by a second chip within a transmission cycle, wherein the second chip transmits n pulse signals within the transmission cycle, the i-th pulse signal is a pulse signal among the n pulse signals, the pulse widths of any two pulse signals within the transmission cycle are different, and the pulse width of the pulse signal is used to characterize the transmission sequence number of the pulse signal within the transmission cycle, the time interval between any two adjacent pulse signals within the transmission cycle is a first time interval, i is an integer greater than 0, n is an integer greater than 1, and i is less than or equal to n; updating the time of the first chip according to the pulse width of the i-th pulse signal to synchronize the time of the first chip with the time of the second chip.

Description

Technical Field

[0001] This application relates to the field of communication technology, specifically to a time synchronization method and a time synchronization device. Background Technology

[0002] In related technologies, when multiple chips work collaboratively in an electronic device, it is usually necessary to keep them on the same time base. To achieve this, the master chip typically sends a pulse to the other slave chips every time period, along with a master chip timestamp matching the current pulse, to the other slave chips that need to synchronize their time.

[0003] However, with this time synchronization method, if any pulse signal or timestamp signal is lost or abnormal due to hardware interference or untimely processing by the receiving chip, the time synchronization of the slave chip will be incorrect. It is evident that the existing time synchronization method is prone to causing time synchronization errors in the slave chip. Summary of the Invention

[0004] The purpose of this application is to provide a time synchronization method and a time synchronization device that can solve the problem that existing time synchronization methods are prone to errors in the time synchronization process.

[0005] In a first aspect, embodiments of this application provide a time synchronization method, executed by a first chip, the method comprising:

[0006] The receiver receives the i-th pulse signal transmitted by the second chip within a transmission cycle, wherein the second chip transmits n pulse signals within the transmission cycle, the i-th pulse signal is a pulse signal among the n pulse signals, any two pulse signals within the transmission cycle have different pulse widths, and the pulse width of the pulse signal is used to characterize the transmission sequence number of the pulse signal within the transmission cycle, the time interval between any two adjacent pulse signals within the transmission cycle is a first time interval, i is an integer greater than 0, n is an integer greater than 1, and i is less than or equal to n;

[0007] The time of the first chip is updated according to the pulse width of the i-th pulse signal so that the time of the first chip is synchronized with the time of the second chip.

[0008] Secondly, embodiments of this application provide a time synchronization method, executed by a second chip, the method comprising:

[0009] During the transmission cycle, a pulse signal is sent to the first chip every first time interval. The second chip sends n pulse signals during the transmission cycle. The pulse widths of any two pulse signals during the transmission cycle are different, and the pulse width of the pulse signal is used to characterize the transmission sequence number of the pulse signal during the transmission cycle. The n is an integer greater than 1.

[0010] Thirdly, embodiments of this application provide a time synchronization device applied to a first chip, the device comprising:

[0011] A receiving module is configured to receive the i-th pulse signal transmitted by the second chip within a transmission cycle, wherein the second chip transmits n pulse signals within the transmission cycle, the i-th pulse signal is a pulse signal among the n pulse signals, any two pulse signals within the transmission cycle have different pulse widths, and the pulse width of the pulse signal is used to characterize the transmission sequence number of the pulse signal within the transmission cycle, the time interval between any two adjacent pulse signals within the transmission cycle is a first time interval, i is an integer greater than 0, n is an integer greater than 1, and i is less than or equal to n;

[0012] The update module is used to update the time of the first chip according to the pulse width of the i-th pulse signal, so as to synchronize the time of the first chip with the time of the second chip.

[0013] Fourthly, embodiments of this application provide a time synchronization device applied to a second chip, the device comprising:

[0014] The transmitting module is used to transmit a pulse signal to the first chip at a first time interval during the transmitting cycle. The second chip transmits n pulse signals during the transmitting cycle. The pulse widths of any two pulse signals during the transmitting cycle are different, and the pulse width of the pulse signal is used to characterize the transmission sequence number of the pulse signal during the transmitting cycle. The n is an integer greater than 1.

[0015] Fifthly, embodiments of this application provide an electronic device including a processor and a memory, wherein the memory stores a program or instructions executable on the processor, and the program or instructions, when executed by the processor, implement the steps of the method described in the first or second aspect.

[0016] In a sixth aspect, embodiments of this application provide a readable storage medium on which a program or instructions are stored, which, when executed by a processor, implement the steps of the method described in the first or second aspect.

[0017] In a seventh aspect, embodiments of this application provide a chip, the chip including a processor and a communication interface, the communication interface being coupled to the processor, the processor being used to run programs or instructions to implement the steps of the method described in the first or second aspect.

[0018] Eighthly, embodiments of this application provide a computer program product stored in a storage medium, which is executed by at least one processor to implement the steps of the method described in the first or second aspect.

[0019] In this embodiment, since the pulse width of each received pulse signal can characterize the transmission sequence number of the current pulse signal in the transmission cycle, and the time interval between any two adjacent pulse signals in the transmission cycle is the first time interval, the relative time interval between the i-th pulse signal and the previously received pulse signals can be determined based on the pulse width of the currently received i-th pulse signal and the first time interval. Thus, even if the timestamp corresponding to the i-th pulse signal is not received, the timestamp corresponding to the i-th pulse signal can be determined based on the timestamp corresponding to the previously received pulse signals and the relative time interval between the current i-th pulse signal and the previously received pulse signals. Furthermore, since the relative time interval between the current pulse signal and the previously received pulse signals can be determined based on the pulse width of the currently received pulse signal and the first time interval, meaning the pulse width of each pulse signal can serve as the relative time information inherent in the pulse signal, when a pulse signal is lost during transmission, because the pulse signal itself carries relative time information, the accurate timestamp can still be calculated based on the pulse width of the newly received pulse signal upon re-receiving it. This solves the problem of error-prone time synchronization in existing time synchronization methods. Attached Figure Description

[0020] Figure 1 This is one of the flowcharts illustrating a time synchronization method provided in an embodiment of this application;

[0021] Figure 2 This is a waveform diagram of pulse transmission in an embodiment of this application;

[0022] Figure 3 This is a second schematic flowchart of a time synchronization method provided in an embodiment of this application;

[0023] Figure 4 This is the third flowchart illustrating a time synchronization method provided in this application embodiment;

[0024] Figure 5 This is the fourth flowchart illustrating a time synchronization method provided in the embodiments of this application;

[0025] Figure 6 This is one of the structural schematic diagrams of a time synchronization device provided in the embodiments of this application;

[0026] Figure 7 This is a second schematic diagram of the structure of a time synchronization device provided in an embodiment of this application;

[0027] Figure 8 These are schematic diagrams of the structure of electronic devices provided in some embodiments of this application;

[0028] Figure 9 One of the hardware structure diagrams of an electronic device provided for some embodiments of this application;

[0029] Figure 10 This is a second schematic diagram of the hardware structure of an electronic device provided for some embodiments of this application. Detailed Implementation

[0030] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0031] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0032] The following description, in conjunction with the accompanying drawings, details a time synchronization method and a time synchronization device provided in this application through specific embodiments and application scenarios.

[0033] Please see Figure 1 , Figure 1 This is a flowchart illustrating a time synchronization method provided in an embodiment of this application. The time synchronization method is executed by a first chip and includes the following steps:

[0034] Step 101: Receive the i-th pulse signal transmitted by the second chip within the transmission cycle, wherein the second chip transmits n pulse signals within the transmission cycle, the i-th pulse signal is a pulse signal among the n pulse signals, the pulse widths of any two pulse signals within the transmission cycle are different, and the pulse width of the pulse signal is used to characterize the transmission sequence number of the pulse signal within the transmission cycle, the time interval between any two adjacent pulse signals within the transmission cycle is the first time interval, i is an integer greater than 0, n is an integer greater than 1, and i is less than or equal to n;

[0035] Step 102: Update the time of the first chip according to the pulse width of the i-th pulse signal so that the time of the first chip is synchronized with the time of the second chip.

[0036] In related technologies, to meet various demands for enhanced performance, external chips other than the main processor are added to electronic devices such as mobile phones for dedicated business processing. These include dedicated chips for camera image processing and display processing, and these chips need to maintain the same time reference as the main processor when processing data. Based on this, in some embodiments of this application, the second chip can be the main processor in the electronic device, while the first chip can be various external chips in the electronic device. It is understood that an electronic device can include multiple different first chips, and the second chip can send pulse signals and timestamps to each first chip according to the method provided in the embodiments of this application to achieve time synchronization between the various first chips and the second chip.

[0037] It should be noted that, in the embodiments of this application, the above-mentioned time synchronization method can be applied not only to electronic devices such as mobile phones, but also to time synchronization scenarios involving multiple sensors and multiple processors in the fields of virtual reality (VR) / wearable devices / robotics.

[0038] For example, in some embodiments of this application, the time synchronization method can also be applied to time synchronization between multiple sensors. Since sensors usually include chips, when multiple sensors work together, the chip in one of the sensors can be used as the second chip in the embodiments of this application, while the chips in other sensors can be used as the first chip. Based on the time synchronization method provided in the embodiments of this application, time synchronization between multiple sensors can be achieved.

[0039] For example, in other embodiments of this application, the time synchronization method can also be applied to time synchronization between multiple processors. When multiple processors work together, one of the processors can be used as the second chip in the embodiments of this application, while the other processors can be used as the first chip. Based on the time synchronization method provided in the embodiments of this application, time synchronization between multiple processors can be achieved.

[0040] The aforementioned transmission period can be a manually set period. Specifically, a transmission period can consist of n consecutively transmitted pulse signals. For example, the transmitted pulse signals can be encoded. N pulse signals encoded as 1 to n can be used as the n pulse signals in the first transmission period, n pulse signals encoded as n+1 to 2n can be used as the n pulse signals in the second transmission period, and so on, thus determining the encoding of the pulse signals in each transmission period. The encoding of the pulse signals can also determine the transmission order; the smaller the encoding, the earlier the transmission order. The aforementioned n pulse signals can be transmitted with a first time interval as the pulse period, where the time interval between the rising edges of two adjacent pulse signals is the first time interval.

[0041] Understandably, the first chip and the second chip can pre-select and agree on the pulse widths of different pulse signals transmitted within a transmission cycle. For example, the pulse width of the first pulse signal can be defined as the first pulse width, the pulse width of the second pulse signal as the second pulse width, and so on, with the pulse width of the i-th pulse signal being the i-th pulse width, and so on, with the pulse width of the n-th pulse signal being the n-th pulse width, and so on. Thus, after receiving the i-th pulse signal, the first chip can determine the transmission sequence number of the i-th pulse signal within the transmission cycle based on its pulse characteristics, and can determine the timestamp corresponding to the i-th pulse signal based on this.

[0042] For example, in some embodiments of this application, when the first chip does not receive the timestamp corresponding to the i-th pulse signal, and the transmission sequence number of the i-th pulse signal is determined to be 5 based on the pulse width of the i-th pulse signal, and the first chip has previously received the timestamp corresponding to the pulse signal with transmission sequence number 3, the timestamp corresponding to the pulse signal with transmission sequence number 3 can be increased by twice the first time interval to obtain the timestamp corresponding to the i-th pulse signal. The timestamp of the first chip when it receives the i-th pulse signal can then be updated to the timestamp corresponding to the i-th pulse signal obtained therein, thereby realizing the process of updating the time of the first chip according to the pulse width of the i-th pulse signal.

[0043] For example, in some embodiments of this application, when the first chip does not receive the timestamp corresponding to the i-th pulse signal, and the transmission sequence number of the i-th pulse signal is determined to be 6 based on the pulse width of the i-th pulse signal, and the first chip has previously received the timestamp corresponding to the pulse signal with transmission sequence number 1, the timestamp corresponding to the pulse signal with transmission sequence number 1 can be increased by five times the first time interval to obtain the timestamp corresponding to the i-th pulse signal. The timestamp of the first chip when it receives the i-th pulse signal can then be updated to the timestamp corresponding to the i-th pulse signal obtained therein, thereby realizing the process of updating the time of the first chip according to the pulse width of the i-th pulse signal.

[0044] In this embodiment, since the pulse width of each received pulse signal can characterize the transmission sequence number of the current pulse signal in the transmission cycle, and the time interval between any two adjacent pulse signals in the transmission cycle is the first time interval, the relative time interval between the i-th pulse signal and the previously received pulse signals can be determined based on the pulse width of the currently received i-th pulse signal and the first time interval. Thus, even if the timestamp corresponding to the i-th pulse signal is not received, the timestamp corresponding to the i-th pulse signal can be determined based on the timestamps of the previously received pulse signals and the relative time interval between the current i-th pulse signal and the previously received pulse signals. Furthermore, since the relative time interval between the current pulse signal and the previously received pulse signals can be determined based on the pulse width of the currently received pulse signal and the first time interval, meaning the pulse width of each pulse signal can serve as the relative time information inherent in the pulse signal, when a pulse signal is lost during transmission, because the pulse signal itself carries relative time information, the accurate timestamp can still be calculated based on the pulse width of the newly received pulse signal upon its re-receipt. This solves the problem of error-prone time synchronization in existing time synchronization methods.

[0045] Optionally, the pulse width of the first pulse signal within the transmission period is a first pulse width, and updating the time of the first chip based on the pulse width of the i-th pulse signal includes:

[0046] If the pulse width of the i-th pulse signal is not equal to the first pulse width, the time of the first chip is updated based on the first timestamp and the pulse width of the i-th pulse signal so that the time of the first chip is synchronized with the time of the second chip. The first timestamp is the timestamp sent by the second chip to the first chip, and the first timestamp is the timestamp when the second chip sends the first pulse signal to the first chip within the transmission period.

[0047] The aforementioned first timestamp can be the current timestamp of the second chip when it starts sending the first pulse signal; specifically, it can be the current timestamp of the clock in the second chip. That is, the first timestamp can be the timestamp of the rising edge of the first pulse signal. For example, please refer to [link to relevant documentation]. Figure 2 When P1 is the first pulse signal, Figure 2 In this context, t1 represents the first timestamp. It is understandable that... Figure 2 The horizontal axis in the diagram is the time axis, and the unit of the horizontal axis can be various time units, such as microseconds. Figure 2 Δt in the above context can be the first time interval.

[0048] It is understandable that the first chip will perform a time update each time it receives a pulse signal from the second chip, in order to synchronize the time of the first chip with the time of the second chip. For ease of understanding, the following explanation uses the time update process of the first chip within one transmission cycle as an example to further illustrate the time synchronization method:

[0049] Upon receiving the first pulse signal within the aforementioned transmission cycle, the first chip can simultaneously receive a first timestamp corresponding to the first pulse signal transmitted by the second chip. This first timestamp can be a timestamp transmitted by the second chip via a serial peripheral interface (SPI), an I2C bus, or a Universal Asynchronous Receiver / Transmitter (UART). The first timestamp corresponds to the rising edge of the first pulse signal. After receiving the first timestamp, the first chip can update the timestamp of when it began receiving the first pulse signal to the first timestamp, or it can update the current timestamp based on the timestamp of when it began receiving the first pulse signal.

[0050] Subsequently, after receiving other pulse signals within the aforementioned transmission cycle, the first chip can determine the sequence number of the currently received pulse signal based on the pulse width. For example, when the current pulse signal is determined to be the second pulse signal in the transmission cycle based on the pulse width, since the time difference between the rising edge of the first pulse signal and the rising edge of the second pulse signal is the first time interval, and the timestamp of the first pulse signal is the first timestamp, the timestamp of the rising edge of the second pulse signal can be determined as the sum of the first timestamp and the first time interval. Then, the timestamp at which the first chip begins receiving the second pulse signal can be updated to the determined timestamp of the rising edge of the second pulse signal, or the timestamp of the current time point can be updated based on the determined timestamp of the rising edge of the second pulse signal. Accordingly, when the current pulse signal is determined to be the third pulse signal in the transmission cycle based on the pulse width, since the time difference between the rising edge of the first pulse signal and the rising edge of the third pulse signal is twice the first time interval, and the timestamp of the first pulse signal is the first timestamp, it can be determined that the rising edge timestamp of the third pulse signal is the sum of twice the first time interval and the first timestamp. Based on this, the timestamp of the first chip is updated. Similarly, the rising edge timestamp corresponding to each pulse signal in the above transmission cycle can be determined based on this method, and the timestamp of the first chip can be updated based on the determined rising edge timestamp of the pulse signal to achieve time synchronization between the first chip and the second chip.

[0051] It is understandable that during the collaborative operation of the first chip and the second chip, the transmitted pulse signals may form multiple transmission cycles, and time synchronization can be performed in each transmission cycle according to the time synchronization method described above.

[0052] In this embodiment, since the pulse width of the i-th pulse signal is not equal to the first pulse width, the time of the second chip can be updated based on the first timestamp and the pulse width of the i-th pulse signal. That is, other pulse signals in the same transmission cycle, except for the first pulse signal, can also update the time of the second chip based on the first timestamp. Thus, during time synchronization, only one timestamp signal needs to be sent for n pulse signals in the same transmission cycle. Compared with related technologies, which require sending a timestamp signal for each pulse signal, this helps to reduce the transmission frequency of the timestamp signal, thereby reducing the probability of transmission errors during transmission, and further reducing the probability of time synchronization errors in the first chip during time synchronization.

[0053] Optionally, the pulse width of the first pulse signal within the transmission period is a first pulse width, and after the receiving second chip transmits the i-th pulse signal within the transmission period, the method further includes:

[0054] When the pulse width of the i-th pulse signal is equal to the first pulse width and the first timestamp sent by the second chip is received, the timestamp of the first chip when it receives the i-th pulse signal is updated to the first timestamp so that the time of the first chip is synchronized with the time of the second chip. The first timestamp is the timestamp of the second chip when it sends the first pulse signal to the first chip in the transmission period.

[0055] Wherein, the pulse width of the i-th pulse signal being equal to the first pulse width can mean that the i-th pulse signal is the first pulse signal in the above-mentioned transmission cycle.

[0056] The above-mentioned updating the timestamp of the first chip when it receives the i-th pulse signal to the first timestamp can mean: updating the timestamp of the first chip when it starts receiving the first pulse signal to the first timestamp, or it can mean using the timestamp of the first chip when it starts receiving the first pulse signal as the first timestamp as the reference to update the timestamp of the current time point.

[0057] In this embodiment, when the pulse width of the i-th pulse signal is equal to the first pulse width and the first timestamp sent by the second chip is received, the timestamp of the first chip when receiving the i-th pulse signal is updated to the first timestamp, thereby achieving time synchronization between the first chip and the second chip when the first pulse signal is received.

[0058] Optionally, the pulse width of the first pulse signal within the transmission period is a first pulse width, and after the receiving second chip transmits the i-th pulse signal within the transmission period, the method further includes:

[0059] When the pulse width of the i-th pulse signal is equal to the first pulse width and no first timestamp is received from the second chip, a third timestamp is determined based on the second timestamp, the first time interval, and n. The first timestamp is the timestamp when the second chip sends the first pulse signal to the first chip in the transmission cycle, and the second timestamp is the timestamp corresponding to the first pulse signal in the previous transmission cycle.

[0060] The timestamp of the first chip when it receives the i-th pulse signal is updated to the third timestamp, so that the time of the first chip is synchronized with the time of the second chip.

[0061] The aforementioned failure to receive the first timestamp sent by the second chip can mean that the first chip failed to successfully receive the first timestamp sent by the second chip. For example, this could be due to hardware interference or untimely processing by the receiving chip, causing the first chip to fail to receive the first timestamp sent by the second chip.

[0062] The aforementioned second timestamp can be the rising edge timestamp corresponding to the first pulse signal in the previous transmission cycle of the current transmission cycle. Since the rising edge of the first pulse signal in the current transmission cycle is separated from the rising edge of the first pulse signal in the previous transmission cycle by n first time intervals, and the rising edge timestamp of the first pulse signal in the previous transmission cycle is the second timestamp, it can be determined that the rising edge timestamp of the first pulse signal in the current transmission cycle is the sum of the second timestamp and n times the first time interval. That is, the aforementioned third timestamp is the sum of the second timestamp and n times the first time interval.

[0063] The above-mentioned updating the timestamp of the first chip when it receives the i-th pulse signal to the third timestamp can mean: updating the timestamp of the first chip when it starts receiving the i-th pulse signal to the third timestamp, or it can mean using the timestamp of the first chip when it starts receiving the i-th pulse signal as the third timestamp as a reference to update the timestamp of the current time point.

[0064] The aforementioned transmission cycle can be a non-first transmission cycle during the time synchronization process between the first chip and the second chip, meaning that the transmission cycle has a previous transmission cycle. Furthermore, for the first transmission cycle during the time synchronization process between the first chip and the second chip, if the first timestamp corresponding to the first pulse signal is not received, the first chip can request the second chip to retransmit the timestamp until the timestamp is received.

[0065] In this embodiment, if the first timestamp corresponding to the first pulse signal is not successfully received in a transmission cycle, the time point corresponding to the first pulse signal in the current transmission cycle can still be updated based on the second timestamp in the previous transmission cycle, which is beneficial to further improve the time synchronization effect between the first chip and the second chip.

[0066] Optionally, the pulse widths of the n pulse signals gradually increase according to the transmission order, and the difference between the pulse widths of any two adjacent pulse signals is a first width; or,

[0067] The pulse widths of the n pulse signals decrease gradually according to the transmission order, and the difference between the pulse widths of any two adjacent pulse signals is the first width.

[0068] The pulse widths of the aforementioned n pulse signals gradually increase according to the transmission order, and the difference between the pulse widths of any two adjacent pulse signals is the first width. Specifically, during the process of the second chip sending n pulse signals to the first chip in sequence according to the pulse period as the first time interval, the pulse width of the current pulse signal is increased by the first width compared to the pulse width of the previously sent pulse signal.

[0069] Accordingly, the pulse widths of the aforementioned n pulse signals gradually decrease according to the transmission order, and the difference between the pulse widths of any two adjacent pulse signals is the first width. Specifically, during the process of the second chip sequentially sending n pulse signals to the first chip according to the pulse period as the first time interval, the pulse width of the current pulse signal is reduced by the first width compared to the pulse width of the previously sent pulse signal.

[0070] Please see Figure 3 The following explanation uses the example of the pulse widths of the n pulse signals increasing sequentially according to the transmission order, with the difference between the pulse widths of any two adjacent pulse signals being the first width, to further illustrate the time synchronization method. Here, the first width is denoted as Δw, the first time interval as Δt, the currently received pulse signal as Wi, and the first pulse width as W0. The first chip is a slave processor, and the second chip is a master processor. Please refer to [link to relevant documentation]. Figure 2 , Figure 2 The diagram illustrates the pulse waveforms of the n pulse signals transmitted, where the first timestamp is t1, the pulse width of the first pulse signal P1 is W0, the pulse width of the second pulse signal P2 is W0 + Δw, and the pulse width of the nth pulse signal Pn is W0 + (n-1) * Δw. The first pulse signal in the next transmission cycle is Pn+1, and the pulse width of Pn+1 is W0. The time synchronization method includes the following steps:

[0071] Receive the i-th pulse signal;

[0072] Determine whether the i-th pulse signal Wi is equal to W0;

[0073] If Wi equals W0, then determine whether the first timestamp has been received, where Wi equals W0 indicates that the i-th pulse signal is the first pulse signal in the current transmission cycle, and the first timestamp is the timestamp when the transmitting end sends the i-th pulse signal;

[0074] If the first timestamp is received, the timestamp of the first chip when it receives the i-th pulse signal is updated to the first timestamp;

[0075] If the first timestamp is not received, a third timestamp is determined based on the second timestamp, the first time interval, and n, and the timestamp of the first chip when it receives the i-th pulse signal is updated to the third timestamp.

[0076] If Wi is not equal to W0, then the time of the first chip is updated based on the first timestamp and the pulse width of the i-th pulse signal;

[0077] Determine whether time synchronization has ended. If yes, end the synchronization; otherwise, receive the (i+1)th pulse signal.

[0078] In this embodiment, by gradually increasing or decreasing the pulse width of the n pulse signals according to the transmission order, and the difference between the pulse widths of any two adjacent pulse signals is the first width, it is beneficial to subsequently determine the timestamp corresponding to each pulse signal and update the time of the first chip based on the determined timestamp corresponding to the pulse signal.

[0079] Please see Figure 4 This application also provides a time synchronization method applied to a second chip, the method comprising the following steps:

[0080] Step 401: During the transmission cycle, a pulse signal is sent to the first chip every first time interval. The second chip sends n pulse signals during the transmission cycle. The pulse widths of any two pulse signals during the transmission cycle are different, and the pulse width of the pulse signal is used to characterize the transmission sequence number of the pulse signal during the transmission cycle. The n is an integer greater than 1.

[0081] Optionally, sending a pulse signal to the first chip every first time interval during the transmission period includes:

[0082] Obtain the transmission sequence number of the pulse signal to be transmitted within the transmission period, wherein the pulse signal to be transmitted is any one of the n pulse signals;

[0083] When the transmission sequence number of the pulse signal to be transmitted is an integer multiple of n plus 1, the pulse signal to be transmitted is sent to the first chip, and a first timestamp is sent to the first chip, the first timestamp being the timestamp when the second chip sends the pulse signal to be transmitted;

[0084] If the transmission sequence number of the pulse signal to be transmitted is not an integer multiple of n plus 1, the pulse signal to be transmitted is transmitted to the first chip.

[0085] Optionally, the pulse widths of the n pulse signals gradually increase according to the transmission order, and the difference between the pulse widths of any two adjacent pulse signals is a first width; or,

[0086] The pulse widths of the n pulse signals decrease gradually according to the transmission order, and the difference between the pulse widths of any two adjacent pulse signals is the first width.

[0087] This implementation method is a second chip-side time synchronization method corresponding to the first chip-side time synchronization method provided in the above embodiments. Its specific implementation process corresponds to the above embodiments and has the same beneficial effects. To avoid repetition, it will not be described again here.

[0088] For easier understanding, please refer to Figure 2 and Figure 5 The following specific embodiment will be used to further explain the time synchronization method, which includes the following steps:

[0089] The second chip sends a pulse signal P1 and a timestamp signal t1, where P1 is the first pulse signal in the transmission cycle and t1 is the timestamp when the second chip sends P1 to the first chip.

[0090] Determine whether there is an interval of Δt, that is, whether there is an interval of Δt from the last transmitted pulse signal, where Δt is the first time interval. If not, continue to determine whether there is an interval of Δt.

[0091] If the interval duration has reached Δt, then determine whether the encoding i of the pulse signal Pi to be sent is an integer multiple of n + 1.

[0092] If i is an integer multiple of n + 1, send a pulse signal Pi to the first chip, and then send a timestamp signal ti corresponding to the pulse signal Pi to the first chip. Here, i being an integer multiple of n + 1 indicates that the pulse signal to be sent is the first pulse signal in a transmission cycle.

[0093] End time synchronization and return to the above step "Determine if there is an interval Δt";

[0094] If i is not an integer multiple of n + 1, then send a pulse signal Pi to the first chip. Here, i is not an integer multiple of n + 1, indicating that the pulse signal to be sent is not the first pulse signal in a transmission cycle. Therefore, only the pulse signal Pi needs to be sent, without sending the corresponding timestamp, and the time synchronization ends. Then return to the above step "determine whether there is an interval Δt".

[0095] Please see Figure 6 , Figure 6This is a schematic diagram of a time synchronization device 600 provided in an embodiment of this application. The time synchronization device 600 is applied to a first chip, and the device includes:

[0096] The receiving module 601 is used to receive the i-th pulse signal transmitted by the second chip during the transmission cycle, wherein the second chip transmits n pulse signals during the transmission cycle, the i-th pulse signal is a pulse signal among the n pulse signals, any two pulse signals within the transmission cycle have different pulse widths, and the pulse width of the pulse signal is used to characterize the transmission sequence number of the pulse signal within the transmission cycle, the time interval between any two adjacent pulse signals within the transmission cycle is a first time interval, i is an integer greater than 0, n is an integer greater than 1, and i is less than or equal to n;

[0097] The update module 602 is used to update the time of the first chip according to the pulse width of the i-th pulse signal, so that the time of the first chip is synchronized with the time of the second chip.

[0098] Optionally, the pulse width of the first pulse signal within the transmission cycle is a first pulse width. The update module 602 is specifically used to update the time of the first chip based on a first timestamp and the pulse width of the i-th pulse signal when the pulse width of the i-th pulse signal is not equal to the first pulse width, so as to synchronize the time of the first chip with the time of the second chip. The first timestamp is the timestamp sent by the second chip to the first chip, and the first timestamp is the timestamp when the second chip sends the first pulse signal to the first chip within the transmission cycle.

[0099] Optionally, the pulse width of the first pulse signal in the transmission cycle is the first pulse width. The update module 602 is specifically used to update the timestamp of the first chip when it receives the i-th pulse signal to the first timestamp when the pulse width of the i-th pulse signal is equal to the first pulse width and the first timestamp sent by the second chip is received, so as to synchronize the time of the first chip with the time of the second chip. The first timestamp is the timestamp when the second chip sends the first pulse signal to the first chip in the transmission cycle.

[0100] Optionally, the pulse width of the first pulse signal within the transmission period is a first pulse width, and the device further includes:

[0101] The determining module is configured to determine a third timestamp based on a second timestamp, the first time interval, and n when the pulse width of the i-th pulse signal is equal to the first pulse width and no first timestamp transmitted by the second chip is received, wherein the first timestamp is the timestamp when the second chip transmits the first pulse signal to the first chip within the transmission cycle, and the second timestamp is the timestamp corresponding to the first pulse signal in the previous transmission cycle;

[0102] The update module 602 is further configured to update the timestamp of the first chip when it receives the i-th pulse signal to the third timestamp, so that the time of the first chip is synchronized with the time of the second chip.

[0103] Optionally, the pulse widths of the n pulse signals gradually increase according to the transmission order, and the difference between the pulse widths of any two adjacent pulse signals is a first width; or,

[0104] The pulse widths of the n pulse signals decrease gradually according to the transmission order, and the difference between the pulse widths of any two adjacent pulse signals is the first width.

[0105] In this embodiment, since the pulse width of each received pulse signal can characterize the transmission sequence number of the current pulse signal in the transmission cycle, and the time interval between any two adjacent pulse signals in the transmission cycle is the first time interval, the relative time interval between the i-th pulse signal and the previously received pulse signals can be determined based on the pulse width of the currently received i-th pulse signal and the first time interval. Thus, even if the timestamp corresponding to the i-th pulse signal is not received, the timestamp corresponding to the i-th pulse signal can be determined based on the timestamps of the previously received pulse signals and the relative time interval between the current i-th pulse signal and the previously received pulse signals. Furthermore, since the relative time interval between the current pulse signal and the previously received pulse signals can be determined based on the pulse width of the currently received pulse signal and the first time interval, meaning the pulse width of each pulse signal can serve as the relative time information inherent in the pulse signal, when a pulse signal is lost during transmission, because the pulse signal itself carries relative time information, the accurate timestamp can still be calculated based on the pulse width of the newly received pulse signal upon its re-receipt. This solves the problem of error-prone time synchronization in existing time synchronization methods.

[0106] The time synchronization device 600 in this embodiment can be an electronic device or a component within an electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal or other devices besides a terminal. For example, the electronic device can be a mobile phone, tablet computer, laptop computer, PDA, in-vehicle electronic device, mobile internet device (MID), augmented reality (AR) / virtual reality (VR) device, robot, wearable device, ultra-mobile personal computer (UMPC), netbook, or personal digital assistant (PDA), etc. It can also be a server, network attached storage (NAS), personal computer (PC), television (TV), ATM, or self-service machine, etc. This embodiment does not specifically limit the functionality of the electronic device.

[0107] The time synchronization device 600 in this embodiment can be a device with an operating system. This operating system can be Android, iOS, or other possible operating systems; this embodiment does not specifically limit its use.

[0108] The time synchronization device 600 provided in this application embodiment can achieve... Figure 1 The various processes implemented in the method implementation examples will not be described again here to avoid repetition.

[0109] Please see Figure 7 , Figure 7 This is a schematic diagram of a time synchronization device 700 provided in an embodiment of this application. The time synchronization device 700 is applied to a second chip, and the device includes:

[0110] The transmitting module 701 is used to transmit a pulse signal to the first chip at a first time interval during the transmitting period. The second chip transmits n pulse signals during the transmitting period. The pulse widths of any two pulse signals during the transmitting period are different, and the pulse width of the pulse signal is used to characterize the transmission sequence number of the pulse signal during the transmitting period. The n is an integer greater than 1.

[0111] Optionally, the sending module 701 includes:

[0112] The acquisition submodule is used to acquire the transmission sequence number of the pulse signal to be transmitted within the transmission period, wherein the pulse signal to be transmitted is any one of the n pulse signals;

[0113] The transmitting submodule is configured to transmit the pulse signal to be transmitted to the first chip when the transmission sequence number of the pulse signal to be transmitted is an integer multiple of n plus 1, and to transmit a first timestamp to the first chip, wherein the first timestamp is the timestamp when the second chip transmits the pulse signal to be transmitted.

[0114] The transmitting submodule is further configured to transmit the pulse signal to be transmitted to the first chip when the transmission sequence number of the pulse signal to be transmitted is not an integer multiple of n plus 1.

[0115] Optionally, the pulse widths of the n pulse signals gradually increase according to the transmission order, and the difference between the pulse widths of any two adjacent pulse signals is a first width; or,

[0116] The pulse widths of the n pulse signals decrease gradually according to the transmission order, and the difference between the pulse widths of any two adjacent pulse signals is the first width.

[0117] In this embodiment, since the pulse width of each received pulse signal can characterize the transmission sequence number of the current pulse signal in the transmission cycle, and the time interval between any two adjacent pulse signals in the transmission cycle is the first time interval, the relative time interval between the i-th pulse signal and the previously received pulse signals can be determined based on the pulse width of the currently received i-th pulse signal and the first time interval. Thus, even if the timestamp corresponding to the i-th pulse signal is not received, the timestamp corresponding to the i-th pulse signal can be determined based on the timestamps of the previously received pulse signals and the relative time interval between the current i-th pulse signal and the previously received pulse signals. Furthermore, since the relative time interval between the current pulse signal and the previously received pulse signals can be determined based on the pulse width of the currently received pulse signal and the first time interval, meaning the pulse width of each pulse signal can serve as the relative time information inherent in the pulse signal, when a pulse signal is lost during transmission, because the pulse signal itself carries relative time information, the accurate timestamp can still be calculated based on the pulse width of the newly received pulse signal upon its re-receipt. This solves the problem of error-prone time synchronization in existing time synchronization methods.

[0118] The time synchronization device 700 in this embodiment can be an electronic device or a component within an electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal or other devices besides a terminal. For example, the electronic device can be a mobile phone, tablet computer, laptop computer, PDA, in-vehicle electronic device, mobile internet device (MID), augmented reality (AR) / virtual reality (VR) device, robot, wearable device, ultra-mobile personal computer (UMPC), netbook, or personal digital assistant (PDA), etc. It can also be a server, network attached storage (NAS), personal computer (PC), television (TV), ATM, or self-service machine, etc. This embodiment does not specifically limit the specific type of device.

[0119] The time synchronization device 700 in this embodiment can be a device with an operating system. This operating system can be Android, iOS, or other possible operating systems; this embodiment does not specifically limit its use.

[0120] The time synchronization device 700 provided in this application embodiment can achieve... Figure 4 The various processes implemented in the method implementation examples will not be described again here to avoid repetition.

[0121] Optionally, such as Figure 8 As shown, this application embodiment also provides an electronic device 800, including a processor 801, a memory 802, and a program or instructions stored in the memory 802 and executable on the processor 801. When the program or instructions are executed by the processor 801, they implement the above-mentioned... Figure 1 or Figure 4 The time synchronization method embodiments shown in the examples are all processes that can achieve the same technical effect, and will not be described again here to avoid repetition.

[0122] It should be noted that the electronic devices in the embodiments of this application include the mobile electronic devices and non-mobile electronic devices described above.

[0123] Figure 9 A schematic diagram of the hardware structure of an electronic device according to an embodiment of this application.

[0124] The electronic device 900 includes, but is not limited to, components such as: radio frequency unit 901, network module 902, audio output unit 903, input unit 904, sensor 905, display unit 906, user input unit 907, interface unit 908, memory 909, and processor 910.

[0125] The radio frequency unit 901 is used to receive the i-th pulse signal transmitted by the second chip during the transmission cycle. The second chip transmits n pulse signals during the transmission cycle, and the i-th pulse signal is a pulse signal among the n pulse signals. The pulse widths of any two pulse signals within the transmission cycle are different, and the pulse width of the pulse signal is used to characterize the transmission sequence number of the pulse signal within the transmission cycle. The time interval between any two adjacent pulse signals within the transmission cycle is a first time interval. i is an integer greater than 0, n is an integer greater than 1, and i is less than or equal to n.

[0126] The processor 910 is configured to update the time of the first chip according to the pulse width of the i-th pulse signal, so as to synchronize the time of the first chip with the time of the second chip.

[0127] Optionally, the processor 910 is further configured to update the time of the first chip based on a first timestamp and the pulse width of the i-th pulse signal when the pulse width of the i-th pulse signal is not equal to the first pulse width, so as to synchronize the time of the first chip with the time of the second chip, wherein the first timestamp is the timestamp sent by the second chip to the first chip, and the first timestamp is the timestamp when the second chip sends the first pulse signal to the first chip within the transmission period.

[0128] Optionally, the processor 910 is further configured to update the timestamp of the first chip when it receives the i-th pulse signal to the first timestamp when the pulse width of the i-th pulse signal is equal to the first pulse width and the first timestamp sent by the second chip is received, so as to synchronize the time of the first chip with the time of the second chip, wherein the first timestamp is the timestamp when the second chip sends the first pulse signal to the first chip in the transmission period.

[0129] Optionally, the processor 910 is further configured to determine a third timestamp based on a second timestamp, the first time interval, and n when the pulse width of the i-th pulse signal is equal to the first pulse width and no first timestamp transmitted by the second chip is received, wherein the first timestamp is the timestamp when the second chip transmits the first pulse signal to the first chip within the transmission cycle, and the second timestamp is the timestamp corresponding to the first pulse signal in the previous transmission cycle;

[0130] The processor 910 is further configured to update the timestamp of the first chip when it receives the i-th pulse signal to the third timestamp, so that the time of the first chip is synchronized with the time of the second chip.

[0131] Optionally, the pulse widths of the n pulse signals gradually increase according to the transmission order, and the difference between the pulse widths of any two adjacent pulse signals is a first width; or,

[0132] The pulse widths of the n pulse signals decrease gradually according to the transmission order, and the difference between the pulse widths of any two adjacent pulse signals is the first width.

[0133] Those skilled in the art will understand that the electronic device 900 may also include a power supply (such as a battery) for supplying power to various components. The power supply may be logically connected to the processor 910 through a power management system, thereby enabling functions such as managing charging, discharging, and power consumption through the power management system. Figure 9 The electronic device structure shown does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown, or combine certain components, or have different component arrangements, which will not be elaborated here.

[0134] It should be understood that, in this embodiment, the input unit 904 may include a graphics processing unit (GPU) 9041 and a microphone 9042. The GPU 9041 processes image data of still images or videos obtained by an image capture device (such as a camera) in video capture mode or image capture mode. The display unit 906 may include a display panel 9061, which may be configured in the form of a liquid crystal display, an organic light-emitting diode, or the like. The user input unit 907 includes a touch panel 9071 and other input devices 9072. The touch panel 9071 is also called a touch screen. The touch panel 9071 may include a touch detection device and a touch controller. Other input devices 9072 may include, but are not limited to, physical keyboards, function keys (such as volume control buttons, power buttons, etc.), trackballs, mice, and joysticks, which will not be described in detail here.

[0135] The memory 909 can be used to store software programs and various data. The memory 909 may primarily include a first storage area for storing programs or instructions and a second storage area for storing data. The first storage area may store the operating system, application programs or instructions required for at least one function (such as sound playback, image playback, etc.). Furthermore, the memory 909 may include volatile memory or non-volatile memory, or both. The non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct memory bus RAM (DRRAM). The memory 909 in the embodiments of this application includes, but is not limited to, these and any other suitable types of memory.

[0136] Processor 910 may include one or more processing units; optionally, processor 910 integrates an application processor and a modem processor, wherein the application processor mainly handles operations involving the operating system, user interface, and applications, and the modem processor mainly handles wireless communication signals, such as a baseband processor. It is understood that the aforementioned modem processor may also not be integrated into processor 910.

[0137] Figure 10 A schematic diagram of the hardware structure of an electronic device according to an embodiment of this application.

[0138] The electronic device 1000 includes, but is not limited to, components such as: radio frequency unit 1001, network module 1002, audio output unit 1003, input unit 1004, sensor 1005, display unit 1006, user input unit 1007, interface unit 1008, memory 1009, and processor 1010.

[0139] The radio frequency unit 1001 is used to send a pulse signal to the first chip at a first time interval during the transmission cycle. The second chip sends n pulse signals during the transmission cycle. The pulse widths of any two pulse signals during the transmission cycle are different, and the pulse width of the pulse signal is used to characterize the transmission sequence number of the pulse signal during the transmission cycle. The n is an integer greater than 1.

[0140] Optionally, the processor 1010 is configured to obtain the transmission sequence number of the pulse signal to be transmitted within the transmission period, wherein the pulse signal to be transmitted is any one of the n pulse signals;

[0141] The radio frequency unit 1001 is configured to send the pulse signal to be transmitted to the first chip when the transmission sequence number of the pulse signal to be transmitted is an integer multiple of n plus 1, and to send a first timestamp to the first chip, wherein the first timestamp is the timestamp when the second chip sends the pulse signal to be transmitted.

[0142] The radio frequency unit 1001 is used to send the pulse signal to be sent to the first chip when the transmission sequence number of the pulse signal to be sent is not an integer multiple of n plus 1.

[0143] Optionally, the pulse widths of the n pulse signals gradually increase according to the transmission order, and the difference between the pulse widths of any two adjacent pulse signals is a first width; or,

[0144] The pulse widths of the n pulse signals decrease gradually according to the transmission order, and the difference between the pulse widths of any two adjacent pulse signals is the first width.

[0145] Those skilled in the art will understand that the electronic device 1000 may also include a power supply (such as a battery) for supplying power to various components. The power supply may be logically connected to the processor 1010 through a power management system, thereby enabling functions such as managing charging, discharging, and power consumption through the power management system. Figure 10 The electronic device structure shown does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown, or combine certain components, or have different component arrangements, which will not be elaborated here.

[0146] It should be understood that, in this embodiment, the input unit 1004 may include a graphics processing unit (GPU) 10041 and a microphone 10042. The GPU 10041 processes image data of still images or videos obtained by an image capture device (such as a camera) in video capture mode or image capture mode. The display unit 1006 may include a display panel 10061, which may be configured in the form of a liquid crystal display, an organic light-emitting diode, or the like. The user input unit 1007 includes a touch panel 10071 and other input devices 10072. The touch panel 10071 is also called a touch screen. The touch panel 10071 may include a touch detection device and a touch controller. Other input devices 10072 may include, but are not limited to, physical keyboards, function keys (such as volume control buttons, power buttons, etc.), trackballs, mice, and joysticks, which will not be described in detail here.

[0147] The memory 1009 can be used to store software programs and various data. The memory 1009 may primarily include a first storage area for storing programs or instructions and a second storage area for storing data. The first storage area may store the operating system, application programs or instructions required for at least one function (such as sound playback, image playback, etc.). Furthermore, the memory 1009 may include volatile memory or non-volatile memory, or both. The non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct memory bus RAM (DRRAM). The memory 1009 in this embodiment includes, but is not limited to, these and any other suitable types of memory.

[0148] The processor 1010 may include one or more processing units; optionally, the processor 1010 integrates an application processor and a modem processor, wherein the application processor mainly handles operations involving the operating system, user interface, and applications, and the modem processor mainly handles wireless communication signals, such as a baseband processor. It is understood that the aforementioned modem processor may also not be integrated into the processor 1010.

[0149] This application also provides a readable storage medium storing a program or instructions. When the program or instructions are executed by a processor, they implement the various processes of the above-described time synchronization method embodiments and achieve the same technical effect. To avoid repetition, they will not be described again here.

[0150] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0151] This application embodiment also provides a chip, which includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is used to run programs or instructions to implement the various processes of the above-described time synchronization method embodiments and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0152] It should be understood that the chip mentioned in the embodiments of this application may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0153] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0154] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0155] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A time synchronization method, executed by a first chip, characterized in that, The method includes: The system receives the i-th pulse signal transmitted by the second chip within a transmission cycle. The second chip transmits n pulse signals within the transmission cycle, and the i-th pulse signal is one of the n pulse signals. Any two pulse signals within the transmission cycle have different pulse widths, and the pulse width of the pulse signal is used to characterize the transmission sequence number of the pulse signal within the transmission cycle. The time interval between any two adjacent pulse signals within the transmission cycle is a first time interval. i is an integer greater than 0, and n is an integer greater than 1, and i is less than or equal to n. The pulse width of the first pulse signal within the transmission cycle is the first pulse width. If the pulse width of the i-th pulse signal is not equal to the first pulse width, the time of the first chip is updated based on the first timestamp and the pulse width of the i-th pulse signal so that the time of the first chip is synchronized with the time of the second chip. The first timestamp is the timestamp sent by the second chip to the first chip, and the first timestamp is the timestamp when the second chip sends the first pulse signal to the first chip within the transmission period.

2. The method according to claim 1, characterized in that, After receiving the i-th pulse signal transmitted by the second chip within the transmission period, the method further includes: When the pulse width of the i-th pulse signal is equal to the first pulse width and the first timestamp sent by the second chip is received, the timestamp of the first chip when it receives the i-th pulse signal is updated to the first timestamp so that the time of the first chip is synchronized with the time of the second chip. The first timestamp is the timestamp of the second chip when it sends the first pulse signal to the first chip in the transmission period.

3. The method according to claim 1, characterized in that, After receiving the i-th pulse signal transmitted by the second chip within the transmission period, the method further includes: When the pulse width of the i-th pulse signal is equal to the first pulse width and no first timestamp is received from the second chip, a third timestamp is determined based on the second timestamp, the first time interval, and n. The first timestamp is the timestamp when the second chip sends the first pulse signal to the first chip in the transmission cycle, and the second timestamp is the timestamp corresponding to the first pulse signal in the previous transmission cycle. The timestamp of the first chip when it receives the i-th pulse signal is updated to the third timestamp so that the time of the first chip is synchronized with the time of the second chip.

4. A time synchronization method, executed by a second chip, characterized in that, The method includes: During the transmission cycle, a pulse signal is sent to the first chip every first time interval. The second chip sends n pulse signals during the transmission cycle. The pulse widths of any two pulse signals during the transmission cycle are different, and the pulse width of the pulse signal is used to characterize the transmission sequence number of the pulse signal during the transmission cycle. The n is an integer greater than 1. The step of sending a pulse signal to the first chip every first time interval during the transmission period includes: Obtain the transmission sequence number of the pulse signal to be transmitted within the transmission period, wherein the pulse signal to be transmitted is any one of the n pulse signals; When the transmission sequence number of the pulse signal to be transmitted is an integer multiple of n plus 1, the pulse signal to be transmitted is sent to the first chip, and a first timestamp is sent to the first chip, the first timestamp being the timestamp when the second chip transmits the pulse signal to be transmitted.

5. A time synchronization device applied to a first chip, characterized in that, The device includes: A receiving module is configured to receive the i-th pulse signal transmitted by the second chip within a transmission cycle, wherein the second chip transmits n pulse signals within the transmission cycle, the i-th pulse signal is a pulse signal among the n pulse signals, any two pulse signals within the transmission cycle have different pulse widths, and the pulse width of the pulse signal is used to characterize the transmission sequence number of the pulse signal within the transmission cycle, the time interval between any two adjacent pulse signals within the transmission cycle is a first time interval, i is an integer greater than 0, n is an integer greater than 1, and i is less than or equal to n, and the pulse width of the first pulse signal within the transmission cycle is a first pulse width; The update module is configured to update the time of the first chip based on a first timestamp and the pulse width of the i-th pulse signal when the pulse width of the i-th pulse signal is not equal to the first pulse width, so as to synchronize the time of the first chip with the time of the second chip. The first timestamp is the timestamp sent by the second chip to the first chip, and the first timestamp is the timestamp when the second chip sends the first pulse signal to the first chip within the transmission period.

6. The apparatus according to claim 5, characterized in that, The pulse width of the first pulse signal in the transmission cycle is the first pulse width. The update module is specifically used to update the timestamp of the first chip when it receives the i-th pulse signal to the first timestamp when the pulse width of the i-th pulse signal is equal to the first pulse width and the first timestamp sent by the second chip is received, so as to synchronize the time of the first chip with the time of the second chip. The first timestamp is the timestamp when the second chip sends the first pulse signal to the first chip in the transmission cycle.

7. The apparatus according to claim 5, characterized in that, The pulse width of the first pulse signal within the transmission cycle is the first pulse width, and the device further includes: The determining module is configured to determine a third timestamp based on a second timestamp, the first time interval, and n when the pulse width of the i-th pulse signal is equal to the first pulse width and no first timestamp transmitted by the second chip is received, wherein the first timestamp is the timestamp when the second chip transmits the first pulse signal to the first chip within the transmission cycle, and the second timestamp is the timestamp corresponding to the first pulse signal in the previous transmission cycle; The update module is further configured to update the timestamp of the first chip when it receives the i-th pulse signal to the third timestamp, so that the time of the first chip is synchronized with the time of the second chip.

8. A time synchronization device applied to a second chip, characterized in that, The device includes: The transmitting module is used to transmit a pulse signal to the first chip at a first time interval during the transmitting cycle. The second chip transmits n pulse signals during the transmitting cycle. The pulse widths of any two pulse signals during the transmitting cycle are different, and the pulse width of the pulse signal is used to characterize the transmission sequence number of the pulse signal during the transmitting cycle. The n is an integer greater than 1. The sending module includes: The acquisition submodule is used to acquire the transmission sequence number of the pulse signal to be transmitted within the transmission period, wherein the pulse signal to be transmitted is any one of the n pulse signals; The transmitting submodule is configured to transmit the pulse signal to be transmitted to the first chip when the transmission sequence number of the pulse signal to be transmitted is an integer multiple of n plus 1, and to transmit a first timestamp to the first chip, wherein the first timestamp is the timestamp when the second chip transmits the pulse signal to be transmitted.

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