Wireline transmission time division duplex system and node device therein

Abstract

Provided are a wired transmission time division duplex system and a node device thereof. The node device comprises a receiver configured to receive a data frame; a transmitter configured to send a processed data frame; a frame header detection circuit configured to identify a frame header and a preamble in a non-return-to-zero coding format from the data frame based on a specific code sequence, and obtain frame header information accordingly, and detect a level jump edge in the frame header and the preamble, and output a reference clock signal based on the detection result; and a clock and data recovery circuit configured to map a multi-level digital signal of a data segment after the frame header and the preamble into binary data bits using a corresponding pulse amplitude modulation format based on the frame header information, and recover a local receiving clock based on the reference clock signal. The slave node device effectively overcomes the synchronization difficulty and slow clock recovery in a multi-level pulse amplitude modulation system.

Description

Technical Field

[0001] This invention relates to the field of wired communication technology, and more particularly to a wired time-division duplex system and its slave node device. Background Technology

[0002] As wired communication systems increasingly demand higher data transmission rates, traditional non-return-to-zero (NRZ) code technology is struggling to meet the ever-growing bandwidth requirements. To achieve higher data throughput within limited channel bandwidth, pulse amplitude modulation (PAM), which transmits multiple bits of information per symbol period, significantly improves data transmission capacity per unit time and has become an important direction for upgrading high-speed wired communication systems.

[0003] In a time-division duplex system employing a daisy-chain topology with one master and multiple slaves, reliable detection of the frame header and preamble is fundamental to achieving synchronization between nodes and correct data reception. In existing technologies, when a system is upgraded to use multi-level pulse amplitude modulation (MLPM), the entire data frame, including the frame header and preamble, is typically encoded and transmitted using MLPM.

[0004] While multi-level pulse amplitude modulation (MLPM) can guarantee the transmission rate of data frames and superframes, it still presents the following technical challenges: First, in communication systems without crystal oscillators but requiring a constant frame rate, node devices need to obtain clock information from the frame header to achieve frame synchronization. When the frame header and preamble themselves also use MLPM, their signal amplitude changes are complex, making it very difficult to directly and reliably extract pure phase information as a clock reference, thus affecting the stability and accuracy of system synchronization. Second, in burst mode, the clock data recovery (CDR) circuit needs to lock in a very short time. The effective transition edge density of the MLPM signal is relatively low, which may slow down or even cause the locking process of the clock and data recovery circuits to fail, making it unsuitable for the requirements of rapid burst communication. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this disclosure provides a method for implementing frame headers and preambles in a wired high-speed transmission time-division duplex system, thereby solving the aforementioned problems.

[0006] In a first aspect, embodiments of this disclosure provide a node device in a wired time-division duplex system, wherein the node device is either a slave node device or a master node device, the wired time-division duplex system adopts a daisy-chain topology with one master and multiple slaves, and the node device includes:

[0007] Receiver, used to receive data frames from upstream nodes;

[0008] The transmitter is used to send the processed data frames to downstream nodes;

[0009] The frame header detection circuit is used to identify the frame header and preamble using a non-return-to-zero encoding format from the data frame based on a specific code pattern sequence, and obtain the frame header information accordingly. At the same time, it detects the level transition edges in the frame header and preamble, and outputs a reference clock signal based on the detection results.

[0010] The clock and data recovery circuit is used to map the multi-level digital signal of the frame header and the data segment after the preamble into binary data bits according to the frame header information using a multi-level pulse amplitude modulation format, and to recover the local receiving clock based on the reference clock signal.

[0011] The data processing unit is used to perform application-level processing on the data segments of binary data bits output by the clock and data recovery circuit.

[0012] In some embodiments, the frame header detection circuit further includes: determining the protocol type followed by the data segment based on the frame header and preamble;

[0013] The clock and data recovery circuit includes: mapping the multi-level digital signal into binary data bits using the corresponding multi-level pulse amplitude modulation format according to the protocol type.

[0014] In some embodiments, determining the protocol type followed by the data segment based on the frame header and preamble includes:

[0015] The protocol type followed by the data segment is determined based on the different code sequences of the frame header and preamble or the identifiers embedded in the frame header and preamble.

[0016] In some embodiments, it further includes: a data and clock recovery auxiliary locking module, used to adjust the parameters of the clock and data recovery circuit or directly provide a phase calibration signal during the detection of the frame header and preamble.

[0017] In some embodiments, the multilevel pulse amplitude modulation format is PAM3, PAM4, PAM8, or PAM16.

[0018] In some embodiments, the frame header, preamble, and / or data segment are encoded using Hamming codes or synchronization codes at the application layer.

[0019] Secondly, embodiments of this disclosure provide a wired time-division duplex system, including a master node and multiple slave nodes connected in series via wired communication links to form a daisy-chain topology, wherein the slave nodes are the aforementioned node devices.

[0020] Thirdly, embodiments of this disclosure provide a data processing method in a wired time-division duplex system, wherein the wired time-division duplex system adopts a daisy-chain topology including one master node and multiple slave nodes, and the data processing method includes:

[0021] The master node or the slave node uses a non-return-to-zero encoding format to encode the frame header and preamble in the data frame, and uses a multi-level pulse amplitude modulation format to encode the data segment after the frame header and preamble.

[0022] The slave node or the master node identifies the frame header and preamble based on a specific code sequence, and obtains the frame header information accordingly. It also obtains the reference clock signal by detecting the level transition edges in the frame header and preamble.

[0023] The slave node or the master node further maps the multi-level digital signal of the data segment into binary data bits using a multi-level pulse amplitude modulation format based on the frame header information, and recovers the local receiving clock based on the reference clock signal.

[0024] In some embodiments, the slave node or the master node further includes: determining the protocol type followed by the data segment based on the frame header and preamble, and mapping the multilevel digital signal into binary data bits using the corresponding multilevel pulse amplitude modulation format according to the protocol type.

[0025] In some embodiments, the slave node or the master node determines the protocol type followed by the data segment based on the different code sequences of the frame header and preamble or the identifier embedded in the frame header and preamble.

[0026] In summary, the embodiments of the present invention, by employing non-return-to-zero (NRZ) encoding for the frame header and preamble signals in a multi-level pulse amplitude modulation system and utilizing the transition edges of the NRZ encoded signals to recover the clock, effectively overcome the difficulties in synchronization and slow clock recovery caused by uniformly adopting this modulation method while fully utilizing multi-level pulse amplitude modulation to improve the data rate. Attached Figure Description

[0027] The above and other objects, features and advantages of the present disclosure will become clearer from the following description of embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0028] Figure 1 This is a network diagram of a wired time-division duplex system;

[0029] Figure 2 It shows in Figure 1 The system shown is a superframe timing flowchart of data being transmitted sequentially between nodes.

[0030] Figure 3 This diagram illustrates the structure of a data frame in the prior art, where the frame header, preamble, and subsequent data segments all employ non-return-to-zero (NRZ) coding modulation.

[0031] Figure 4 An example diagram showing the specific code structure of a frame header and preamble is provided.

[0032] Figure 5 A schematic diagram of a frame header and preamble using a non-return-to-zero encoding format is shown in a multi-level pulse amplitude modulation system according to an embodiment of the present disclosure.

[0033] Figure 6 A schematic diagram of the structure of a node device using the above-described data frame design, as proposed in an embodiment of this disclosure, is provided. Detailed Implementation

[0034] The invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown.

[0035] Terminology Explanation

[0036] The frame header and preamble are specific code sequences used to identify the start of a data frame and to achieve node synchronization and clock recovery.

[0037] Non-Return to Zero (NRZ) code transmits data signals by directly transmitting electrical pulses through the physical medium (cable). For example, in unipolar NRZ code, the digital signals "1" and "0" are transmitted through positive and zero levels (or negative and zero levels), respectively; in bipolar NRZ code, the digital signals "1" and "0" are transmitted through positive and negative levels, respectively.

[0038] Pulse amplitude modulation (PAM) is a technique that modulates signals by changing the amplitude of a pulse carrier. Based on the amplitude variation mechanism, it can be divided into two types: natural sampling and flat-top sampling. It includes formats such as PAM2 (NRZ), PAM4, PAM8, and PAM16, where each symbol transmits 1 to 4 bits. Multilevel pulse amplitude modulation is a specific subset of PAM, specifically referring to formats that use two or more amplitude levels for modulation.

[0039] Edge correspondence refers to the fact that the edge of a pulse signal or clock signal is roughly aligned with the edge of another signal, allowing for a fixed phase deviation between the two signal edges. For example, due to factors such as device delay or line delay, the two signals can still be considered to be "edge-corresponding".

[0040] Time-division duplex transmission refers to bidirectional (i.e., uplink and downlink) data transmission achieved by dividing the same physical communication channel into different time segments.

[0041] This invention can be presented in various forms, some of which will be described below.

[0042] Figure 1 This is a network diagram of a wired time-division duplex system 100, including a host 101, a master node 102, and slave nodes 1 to N connected in series via wired communication links, where N is greater than or equal to 2. The master node 102 and slave nodes 1 to N form a daisy-chain topology with one master and many slaves. The host 101 is the data source and ultimate controller of the system, responsible for generating valid service data or commands to be transmitted and submitting them to the master node 102. At the same time, it receives and processes response or status data aggregated from the master node. The master node 102 is the scheduler of the communication network, responsible for organizing downlink and uplink frames according to a fixed transmission period and strictly dividing the time slots of downlink and uplink frames to achieve time-division duplex. Slave nodes 1 to N are the service execution units of the communication network. Within their allocated time slots or data segments, they receive data sent by upstream nodes directly or process it before sending it to downstream nodes. The wired time-division duplex system 100 can be, for example, an audio playback system deployed in a recording studio or live performance, to synchronously and with low latency transmit the main audio signal from the mixing console to multiple digital amplifiers, audio processors, or stage monitoring equipment. The wired time-division duplex system 100 can also be a vehicle-mounted playback system, synchronously and with low latency transmitting high-quality audio (such as multi-channel surround sound) or video data from a host device (such as a video playback system on an external terminal) to multiple speakers or displays distributed throughout the vehicle.

[0043] Figure 2 It shows in Figure 1The system is illustrated in the superframe timing flowchart, showing the sequential data transmission between nodes. The process operates on a fixed transmission cycle, with only one complete superframe transmitted within each cycle. A superframe consists of two sequential parts: a downlink frame and an uplink frame, collectively completing a bidirectional communication between the master node and all slave nodes. At the start of a superframe, the master node first sends a downlink frame downstream from its sending port B. This downlink frame is received by slave node 1's receiving port A. Slave node 1 processes the received downlink frame internally and then sends the processed downlink frame back to slave node 2's receiving port A via its own sending port B. Slave node 2 processes the received downlink frame internally and then sends the processed downlink frame back to slave node 3's receiving port A via its own sending port B. This process continues, with the downlink frame sequentially passing through each intermediate slave node along the communication link until it is finally received by the receiving port A of the final slave node N. After receiving the downlink frame, slave node N waits for a pre-set fixed delay before initiating uplink frame transmission upstream from its sending port B. The transmission path of uplink frames is the opposite of that of downlink frames. Once the master node successfully receives an uplink frame, it marks the end of a superframe, and the system prepares to enter the next transmission cycle. This time-division duplex timing design ensures that data in a daisy-chain topology can complete a round of interaction between the master node and all slave nodes in an orderly and efficient manner.

[0044] Figure 3 This diagram illustrates the structure of a data frame in the prior art, where the frame header, preamble, and subsequent data segments all employ non-return-to-zero (NRZ) coded modulation. Figure 3 As shown, a data frame consists of two sequential parts: a frame header and preamble at the beginning, and the data segment that follows. The frame header and preamble are composed of a specific code sequence with a fixed number of bits. The main function of the frame header and preamble is to identify the start of the data frame, informing downstream nodes that data has arrived and they need to prepare to receive it. The subsequent data segment carries the actual information to be transmitted, using a non-return-to-zero (NRZ) coding modulation format with variable bit lengths, which vary according to specific communication requirements. Figure 4 An example diagram of the specific code pattern structure of a frame header and preamble is shown. As shown in the figure, the frame header and preamble are composed of a specific 24-bit code pattern sequence, specifically: "010101001101100100110101", with no amplitude variation in the specific code pattern sequence.

[0045] Based on the above data frame design, during data transmission, the slave or master node monitors the received downlink or uplink data frames. When a sequence that perfectly matches the preset frame header and preamble pattern is detected, it is determined to be a valid frame header. After detecting the last bit of the frame header and preamble sequence, the slave node knows that the following signal is the required data segment, thus initiating the data segment reception and recovery process. This structural design, which clearly separates the fixed, known frame header and preamble from the variable data segment, provides a foundation for achieving reliable frame start detection and data boundary delineation.

[0046] Figure 5 This diagram illustrates a frame header and preamble using a non-return-to-zero (NRZ) coding format in a multi-level pulse amplitude modulation (MPM) system according to an embodiment of this disclosure. The core of this method lies in encoding and transmitting the frame header and preamble using different coding formats than the subsequent data segments. Specifically, as shown in the diagram, the frame header and preamble use a NRZ coding format, while the subsequent data segments use a multi-level pulse amplitude modulation (MPM) format. The specific code type and bit count of the frame header and preamble are not limited; they can be 24-bit Hamming code, 24-bit comma code, 40-bit Hamming code, or 40-bit comma code, etc. The multi-level pulse amplitude modulation (MPM) format can be PAM3, PAM4, or PAM8, etc.

[0047] based on Figure 5 The given data frame design allows slave or master nodes to directly and reliably extract pure phase information from the dense and regular level transition edges provided by the frame header and preamble during data transmission. This phase information is then used as the reference clock signal for the local clock and data recovery circuit, avoiding the inability to quickly obtain the reference clock source for the local clock and data recovery circuit due to the complex processing of the multi-level pulse amplitude modulation format. At the same time, it also enables high-efficiency data transmission in the multi-level pulse amplitude modulation format.

[0048] Figure 6 A schematic diagram of the structure of a node device using the above-described data frame design, as proposed in an embodiment of this disclosure, is provided. The node device may be... Figure 1 In this context, a slave node device can also be a master node device. For ease of description, Figure 6 Only the relevant modules are shown.

[0049] As shown in the figure, the analog front end 11 of the receiver is a key module that is linked to the digital processing core. It is mainly responsible for receiving analog signals, amplifying, filtering, and performing analog-to-digital conversion (ADC) on the analog signals to obtain the converted digital signals.

[0050] The frame header detection circuit 12 is used to identify specific code patterns (such as 24-bit Hamming code) in a non-return-to-zero (NRZ) encoding format. It matches known, fixed NRZ encoding pattern sequences in the signal output from the analog front-end. Once the code pattern sequence is detected, it can be determined that the code pattern is the frame header and preamble. The following signal is the data segment encoded using multi-level pulse amplitude modulation (MLPM). The frame header information is then output to the clock and data recovery circuit 14. The frame header detection circuit 12 is also used to detect the high and low level transition edges of the frame header and preamble, and obtain a reference clock signal based on these transition edges. The reference clock signal is then output to the clock and data recovery circuit 14.

[0051] In some embodiments, the frame header detection circuit 12 is also used for protocol identification. For example, the frame header detection circuit 12 determines whether subsequent data segments follow a new protocol (e.g., PAM3, PAM4, and PAM8) or an old protocol (full NRZ encoding) based on the detected different code pattern sequences of the non-return-to-zero encoding format (e.g., a new protocol uses one specific code pattern sequence, while an old NRZ protocol uses another). As another example, the frame header detection circuit 12 determines whether subsequent data segments follow a new protocol (e.g., PAM3, PAM4, PAM8, or PAM16) or an old protocol (full NRZ encoding) based on the identification information (e.g., a fixed number of bits at a fixed position) embedded in the detected non-return-to-zero encoding format code pattern sequence.

[0052] The clock and data recovery circuit 14 is mainly responsible for clock synchronization and data recovery. Specifically, based on the frame header information output by the frame header detection circuit 12, a predetermined level pulse amplitude modulation technique is used to map the multi-level digital signals of the data segment after the frame header and preamble into binary data bits. At the same time, based on the reference clock signal output by the frame header detection circuit 12, the local receiving clock is recovered through a phase-locked loop (PLL) 13 or similar technique, so that the local receiving clock is synchronized with the frame rate and bit rate of the transmitting end, ensuring that the local processing timing is aligned with the superframe, downlink frame / uplink frame period of the entire system.

[0053] In some embodiments, when the frame header detection circuit 12 is used for protocol identification, the clock and data recovery circuit 14 uses the corresponding level pulse amplitude modulation format to map the multi-level digital signal after the frame header and preamble into binary data bits according to the protocol type output by the frame header detection circuit 12. For example, the PAM4 signal of the received data segment is recovered into binary data bits.

[0054] The data processing unit 15 performs application-level processing on the data segment of binary data bits (e.g., updating, modifying, or replacing the data bits) and sends the processed data bits to the transmitter 16. Alternatively, the digital signal processor 15 may not perform any processing on the binary data bits of the data segment and directly forward the data to the transmitter 16.

[0055] Transmitter 16 uses non-return-to-zero encoding format to encode the frame header and preamble, and multi-level pulse amplitude modulation format to encode the data segment to debug the data, and converts the digital signal into an analog signal for transmission.

[0056] In some embodiments, Figure 6 The node device 600 is also equipped with a CDR AidLocking module, which may adjust the parameters of the clock data recovery circuit 14 (such as increasing the loop bandwidth) or directly provide a forced phase calibration signal during the detection of the NRZ preamble. In the burst communication mode of the time-division duplex system, the clock data recovery circuit 14 may lose lock or be in an open-loop state after the silence period. The dense transitions of the NRZ preamble to the CDR provide the optimal lock training sequence. This module utilizes this characteristic to ensure that the CDR can quickly enter a stable locked state within the short frame header time to correctly sample subsequent data segments.

[0057] Compared with the prior art, the embodiments disclosed herein have the following advantages:

[0058] By transmitting the frame header and preamble using different encoding formats than the subsequent data segments—specifically, the frame header and preamble employ Non-Return-to-Zero (NRZ) encoding, while the data segments use Multi-Level Pulse Amplitude Modulation (MLPM)—a synergistic optimization is achieved. Specifically, firstly, because the NRZ-encoded frame header and preamble signals have simple waveforms and no amplitude variations, downstream slave nodes can directly and reliably extract pure phase information from them. This provides a stable and readily available reference clock source for slave nodes lacking high-precision local crystal oscillators, effectively ensuring the frame synchronization accuracy and stability of the system under high-speed transmission. Secondly, the NRZ-encoded signal has a higher effective transition edge density, which significantly improves the locking speed and reliability of the clock data recovery circuit in burst communication mode. This effectively alleviates the locking difficulties and even loss of lock caused by the sparse transition edges of the multi-level modulated signal, ensuring the rapid establishment of the communication link. Finally, by embedding identification information to distinguish different protocols in the specific code patterns of the frame header and preamble, the node can quickly identify the protocol followed by the current transmission after completing the frame header detection, and adjust the recovery method of subsequent data segments accordingly. Thus, without adding extra complex hardware or control channels, efficient and smooth compatibility with old protocols using non-return-to-zero coding and new protocols using multi-level modulation is achieved.

[0059] The embodiments of this disclosure are as described above. These embodiments do not exhaustively describe all details, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the embodiments of this disclosure, thereby enabling those skilled in the art to make good use of the embodiments of this disclosure and modifications based on them. The embodiments of this disclosure are limited only by the claims and their full scope and equivalents.

Claims

1. A node device in a wired time-division duplex system, wherein the wired time-division duplex system adopts a daisy-chain topology with one master and multiple slaves, and the node device is either a slave node device or a master node device therein, the node device comprising: Receiver, used to receive data frames; The transmitter is used to send processed data frames; The frame header detection circuit is used to identify the frame header and preamble using a non-return-to-zero encoding format from the data frame based on a specific code pattern sequence, and obtain the frame header information accordingly. At the same time, it detects the level transition edges in the frame header and preamble, and outputs a reference clock signal accordingly. The clock and data recovery circuit is used to map the multi-level digital signal of the frame header and the data segment after the preamble into binary data bits according to the frame header information using a multi-level pulse amplitude modulation format, and to recover the local receiving clock based on the reference clock signal. The data processing unit is used to perform application-level processing on the data segments of binary data bits output by the clock and data recovery circuit.

2. The node device according to claim 1, wherein, The frame header detection circuit further includes: determining the protocol type followed by the data segment based on the frame header and preamble; The clock and data recovery circuit includes: mapping the multi-level digital signal into binary data bits according to a multi-level pulse amplitude modulation format corresponding to the protocol type.

3. The node device according to claim 1, wherein, The step of determining the protocol type followed by the data segment based on the frame header and preamble includes: The protocol type followed by the data segment is determined based on the different code sequences of the frame header and preamble or the identifiers embedded in the frame header and preamble.

4. The node device according to claim 1, further comprising: The data and clock recovery auxiliary locking module is used to adjust the parameters of the clock and data recovery circuit or directly provide a phase calibration signal during the detection of the frame header and preamble.

5. The node device according to claim 1, wherein, The multilevel pulse amplitude modulation grid is PAM3, PAM4, PAM8 or PAM16.

6. The node device according to claim 1, wherein, The frame header and preamble and / or the data segment are encoded using Hamming code or synchronization code at the application level.

7. A wired time-division duplex system, comprising a master node and a plurality of slave nodes connected in series via a wired communication link to form a daisy-chain topology, wherein the slave node or the master node is a node device as described in any one of claims 1 to 6.

8. A data processing method in a wired time-division duplex system, wherein the wired time-division duplex system adopts a daisy-chain topology containing one master node and multiple slave nodes, the data processing method comprising: The master node or the slave node uses a non-return-to-zero encoding format to encode the frame header and preamble in the data frame, and uses a multi-level pulse amplitude modulation format to encode the data segment after the frame header and preamble. The slave node or the master node identifies the frame header and preamble based on a specific code sequence, and obtains the frame header information accordingly. It also obtains the reference clock signal by detecting the level transition edges in the frame header and preamble. The slave node or the master node further maps the multi-level digital signal of the data segment into binary data bits using the corresponding multi-level pulse amplitude modulation format according to the frame header information, and recovers the local receiving clock based on the reference clock signal.

9. The data processing method according to claim 8, wherein, The slave node or the master node further includes: determining the protocol type followed by the data segment based on the frame header and preamble, and mapping the multi-level digital signal into binary data bits using the corresponding level pulse amplitude modulation format according to the protocol type.

10. The data processing method according to claim 8, wherein, The slave node or the master node determines the protocol type followed by the data segment based on the different code sequences of the frame header and preamble or the identifier embedded in the frame header and preamble.

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