Semiconductor device

Abstract

Disclosed is a semiconductor device including: an active pattern on a substrate and surrounded by a device isolation pattern; a word line extending in a first direction parallel to a bottom surface of the substrate and located on the active pattern and the device isolation pattern; a bit line extending in a second direction on the active pattern, where the second direction intersects the first direction; a storage node contact on the active pattern; landing pads including a lower landing pad and an upper landing pad sequentially disposed on the storage node contact with an interface therebetween; and a fence pattern on the word line and on a side surface of the landing pad. A height of a top surface of the fence pattern is higher than a height of a top surface of the lower landing pad.

Description

Technical Field

[0001] The present inventive concept relates to semiconductors, and more particularly, to semiconductor devices. Background Art

[0002] Semiconductor devices play an important role in the electronics industry due to their small size, multi-functions and / or low manufacturing cost. Semiconductor devices can be classified into any of semiconductor memory devices that store logic data, semiconductor logic devices that process operations of logic data, and hybrid semiconductor devices having both memory and logic elements.

[0003] Recently, the high speed and low power consumption of electronic products require that semiconductor devices embedded in electronic products should have high operating speed and / or low operating voltage. In order to meet the above requirements, semiconductor devices have become more highly integrated. The high integration of semiconductor devices may lead to reduced reliability of semiconductor devices. Therefore, various studies have been conducted to enhance the reliability of semiconductor devices. Summary of the invention

[0004] Some embodiments of the inventive concept provide a semiconductor device having improved productivity.

[0005] The objects of the inventive concept are not limited to the above-mentioned, and other objects not mentioned above will be clearly understood by those skilled in the art from the following description.

[0006] According to some embodiments of the present invention, a semiconductor device may include: an active pattern located on a substrate and surrounded by a device isolation pattern in a top view; a word line extending in a first direction and located on the active pattern and the device isolation pattern, wherein the first direction is parallel to the bottom surface of the substrate; a bit line extending in a second direction on the active pattern, wherein the second direction intersects the first direction; a storage node contact located on the active pattern; a landing pad including a lower landing pad and an upper landing pad stacked on the storage node contact, wherein the lower landing pad and the upper landing pad have an interface therebetween; and a fence pattern located on the word line and on a side surface of the landing pad. With respect to the substrate, a top surface of the fence pattern is higher than a top surface of the lower landing pad adjacent to the interface between the lower landing pad and the upper landing pad.

[0007] According to some embodiments of the present invention, a semiconductor device may include: an active pattern located on a substrate and surrounded by a device isolation pattern in a top view; a word line extending in a first direction and located on the active pattern and the device isolation pattern, wherein the first direction is parallel to the bottom surface of the substrate; a bit line extending in a second direction on the active pattern, wherein the second direction intersects the first direction; a storage node contact located on the active pattern; a landing pad located on the storage node contact; and a fence pattern located on the word line and on a side surface of the landing pad. The fence pattern may include: a lower fence pattern located on a side surface of the bit line; and an upper fence pattern located on the lower fence pattern and protruding beyond the lower fence pattern in the first direction.

[0008] According to some embodiments of the present invention, a semiconductor device may include: an active pattern located on a substrate and surrounded by a device isolation pattern in a top view; a word line extending in a first direction and located on the active pattern and the device isolation pattern, wherein the first direction is parallel to the bottom surface of the substrate; a bit line extending in a second direction on the active pattern, wherein the second direction intersects the first direction; a storage node contact located on the active pattern; a landing pad located on the storage node contact; a fence pattern located on the word line and on a side surface of the landing pad; and a filling pattern located on the bit line and extending in the second direction. A top surface of the fence pattern may be at substantially the same height as a top surface of the filling pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 A top view of a semiconductor device according to some embodiments of the inventive concept is shown.

[0010] Figure 2A , Figure 2B and Figure 2C Shown along Figure 1 Cross-sectional views taken along lines AA', BB' and CC'.

[0011] Figure 3 Shown along Figure 1 A cross-sectional view taken along line AA'.

[0012] Figure 4A and Figure 4B Shown along Figure 1 A cross-sectional view taken along lines AA' and CC'.

[0013] Figure 5 , Fig. 6A , Figure 6B , Figure 6C , Figure 7 , Fig. 8A , Figure 8B , Figure 8C , Fig. 9 , Fig. 10A , Fig. 10B and Fig. 10C A top view and a cross-sectional view illustrating a method of fabricating a semiconductor device according to some embodiments of the inventive concept.

[0014] Fig.11 and Fig.12 A cross-sectional view illustrating a method of fabricating a semiconductor device according to some embodiments of the inventive concept.

[0015] Fig.13 and Fig.14 A cross-sectional view illustrating a method of fabricating a semiconductor device according to some embodiments of the inventive concept. DETAILED DESCRIPTION

[0016] Semiconductor devices according to some embodiments of the inventive concept will be discussed below with reference to the accompanying drawings.

[0017] Figure 1 A top view of a semiconductor device according to some embodiments of the inventive concept is shown. Figure 2A , Figure 2B and Figure 2C Shown along Figure 1 Cross-sectional views taken along lines AA', BB' and CC'.

[0018] Reference Figures 1 to 2C , a substrate 100 may be provided. The substrate 100 may be a semiconductor substrate, such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate.

[0019] A device isolation pattern STI defining an active pattern ACT may be provided on the substrate 100. The active pattern ACT may be provided in plurality. For example, the active pattern ACT may include a portion of the substrate 100 surrounded by the device isolation pattern STI. For convenience of description, unless otherwise specifically stated in the present disclosure, the substrate 100 may be defined as indicating another portion other than these portions of the substrate 100.

[0020] The active patterns ACT may be parallel to the bottom surface of the substrate 100 and may be spaced apart from each other in the first direction D1 and the second direction D2 intersecting each other. The active patterns ACT may have island shapes separated from each other, and each active pattern ACT may have a strip shape elongated in the third direction D3 parallel to the bottom surface of the substrate 100. The first direction D1, the second direction D2, and the third direction D3 may intersect each other. The active pattern ACT may have a shape protruding in a fourth direction D4 perpendicular to the bottom surface of the substrate 100.

[0021] The device isolation pattern STI may include a dielectric material such as silicon oxide (SiO 2 ) and / or at least one of silicon nitride (SiN). The device isolation pattern STI may be a single layer formed of a single material or a multilayer including two or more materials. In the present disclosure, "A or B", "at least one of A and B", "at least one of A or B", "A, B or C", "at least one of A, B and C", and "at least one of A, B or C" may include one of the elements listed in the corresponding expression above or any possible combination.

[0022] The active pattern ACT may include a first edge portion EA1 and a second edge portion EA2 spaced apart from each other in the third direction D3, and may further include a central portion CA between the first edge portion EA1 and the second edge portion EA2. The first edge portion EA1 and the second edge portion EA2 may be opposite ends of the active pattern ACT in the third direction D3. The central portion CA may be a portion of the active pattern ACT between the first edge portion EA1 and the second edge portion EA2, and may be, for example, a portion of the active pattern ACT between a pair of word lines WL to be discussed below. The first edge portion EA1 and the second edge portion EA2 and the central portion CA may be doped with impurities (e.g., n-type or p-type impurities).

[0023] The word line WL may cross the active pattern ACT and the device isolation pattern STI, extend on the active pattern ACT and the device isolation pattern STI, or be located on the active pattern ACT and the device isolation pattern STI. The word line WL may be provided in a plurality. The word lines WL may be spaced apart from each other in the second direction D2. For example, a pair of word lines WL adjacent to each other in the second direction D2 may cross one active pattern ACT or overlap one active pattern ACT in a direction perpendicular to the substrate 100. The word line WL may be located in a trench region TR provided in the active pattern ACT and the device isolation pattern STI, respectively.

[0024] Each word line WL may include a gate electrode GE, a gate dielectric pattern GI, and a gate capping pattern GC. The gate electrode GE may pass through the active pattern ACT and the device isolation pattern STI in the first direction D1. The gate dielectric pattern GI may be between the gate electrode GE and the active pattern ACT and between the gate electrode GE and the device isolation pattern STI. A gate capping pattern GC covering the top surface of the gate electrode GE or overlapping the top surface of the gate electrode GE may be provided on the gate electrode GE. The gate electrode GE may include a conductive material. For example, the gate electrode GE may be a single layer formed of one material or a multilayer formed of two or more materials. For example, the gate dielectric pattern GI may include silicon oxide (SiO 2 ) and / or at least one of a high-k dielectric material. In the present disclosure, a high-k dielectric material may be defined as a material indicating a dielectric constant greater than a dielectric constant of silicon oxide. For example, the gate capping pattern GC may include silicon nitride (SiN).

[0025] The buffer pattern BP may be disposed on the substrate 100. The buffer pattern BP may cover the active pattern ACT and the device isolation pattern STI or overlap the active pattern ACT and the device isolation pattern STI. The buffer pattern BP may be a single layer or a multi-layer. For example, the buffer pattern BP may include silicon oxide (SiO 2 ), at least one of silicon nitride (SiN) and / or silicon oxynitride (SiON).

[0026] The first recess RS1 may be formed on an upper portion of the active pattern ACT and an upper portion of the device isolation pattern STI adjacent to an upper portion of each of the active patterns ACT.

[0027] The bit line contact DC may be disposed in the first recess RS1. The bit line contact DC may be between the central portion CA of the active pattern ACT and the bit line BL to be discussed below. The bit line contact DC may be provided in plurality. The bit line contacts DC may be spaced apart from each other in the first direction D1 and the second direction D2. The bit line contact DC may electrically connect the corresponding bit line BL to the central portion CA of the corresponding active pattern ACT. For example, the bit line contact DC may include at least one of polysilicon doped with impurities, polysilicon not doped with impurities, and / or a metal material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, or Ir).

[0028] The bit line BL may be disposed on the bit line contact DC. The bit line BL may extend along the second direction D2 on the bit line contact DC. The bit line BL may be provided in a plurality. The bit lines BL may be spaced apart from each other in the first direction D1. For example, the bit line BL may include a metal material such as Ti, Mo, W, Cu, Al, Ta, Ru, or Ir. The bit line BL may include a material having grains formed along the same crystal orientation. For example, the bit line BL may include a material having a single crystal, but the inventive concept is not limited thereto. For example, the bit line BL includes a polycrystalline material having a plurality of grains, and the crystal orientations of the plurality of grains may be similar or substantially the same.

[0029] A first barrier pattern (not shown) may be additionally interposed between the bit line BL and the bit line contact DC and between the bit line BL and the polysilicon pattern PP, which will be discussed below. The first barrier pattern may prevent material diffusion between the bit line BL and the bit line contact DC and between the bit line BL and the polysilicon pattern PP, which will be discussed below. For example, the first barrier pattern may include a metal nitride (e.g., a nitride of Ti, Mo, W, Cu, Al, Ta, Ru, or Ir).

[0030] The polysilicon pattern PP may be disposed between the bit line BL and the buffer pattern BP and between the bit line contacts DC adjacent to each other in the second direction D2. The polysilicon pattern PP may be disposed in plurality. For example, the polysilicon patterns PP may be spaced apart from each other in the first direction D1 and the second direction D2. The top surface of the polysilicon pattern PP and the top surface of the bit line contact DC may be located at substantially the same level or height relative to the top surface of the substrate 100 and may be coplanar with each other. The polysilicon pattern PP may include, for example, polysilicon doped with impurities.

[0031] The bit line cover pattern BCP may be disposed on the bit line BL. The bit line cover pattern BCP may extend in the second direction D2 together with the bit line BL. The bit line cover pattern BCP may be provided in plurality. The bit line cover patterns BCP may be spaced apart from each other in the first direction D1. The bit line cover pattern BCP may overlap vertically with the bit line BL. The bit line cover pattern BCP may be formed of a single layer or multiple layers. The bit line cover pattern BCP may include a first cover pattern, a second cover pattern, and a third cover pattern stacked in sequence. For example, each of the first to third cover patterns may include silicon nitride (SiN). In some embodiments, the bit line cover pattern BCP may include four or more stacked cover patterns.

[0032] The bit line spacer BSP may be disposed on a side surface of the bit line contact DC, a side surface of the bit line BL, and a side surface of the bit line capping pattern BCP. The bit line spacer BSP may extend along the second direction D2 on the side surface of the bit line BL. The bit line spacer BSP may fill the first recess RS1 or be located in the first recess RS1, and may extend along the fourth direction D4 on the side surface of the bit line capping pattern BCP. The bit line spacer BSP may be provided in plurality. The bit line spacer BSP may be spaced apart from each other in the first direction D1. For example, the bit line spacer BSP may include silicon oxide (SiO 2 ), at least one of silicon nitride (SiN), silicon carbonitride (SiOC) and / or silicon oxycarbonitride (SiOCN).

[0033] The bit line spacer BSP may include one spacer or a plurality of spacers. For example, the first to third spacers may be sequentially disposed on the side surfaces of the bit line BL. The second spacer may include an air gap separating the first and third spacers from each other.

[0034] The storage node contact BC may be disposed between the bit lines BL adjacent to each other along the first direction D1. The storage node contact BC may be provided in a plurality. The storage node contact BC may be spaced apart from each other in the first direction D1 and the second direction D2. The storage node contacts BC adjacent to each other in the first direction D1 may be spaced apart from each other across the bit lines BL. The storage node contacts BC adjacent to each other in the second direction D2 may be spaced apart from each other across a fence pattern FN to be discussed below. Each storage node contact BC may fill a second recess RS2 disposed in a corresponding one of the first edge portion EA1 and the second edge portion EA2 of the active pattern ACT, and may be connected to the corresponding edge portion. For example, the storage node contact BC may include at least one of polysilicon doped with impurities, polysilicon not doped with impurities, and / or a metal material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, or Ir).

[0035] The fence pattern FN may be between the bit lines BL adjacent to each other in the first direction D1 on the word line WL. The fence pattern FN may be between the storage node contacts BC adjacent to each other in the second direction D2 on the word line WL. A plurality of fence patterns FN may be provided. The fence patterns FN may be spaced apart from each other in the first direction D1 and the second direction D2. The fence patterns FN adjacent to each other in the first direction D1 may be spaced apart from each other across the bit lines BL. The fence patterns FN adjacent to each other in the second direction D2 may be spaced apart from each other across the storage node contacts BC. The fence pattern FN may include, for example, silicon oxide (SiO 2 ), at least one of silicon nitride (SiN), silicon carbonitride (SiOC) and / or silicon oxycarbonitride (SiOCN).

[0036] The fence pattern FN may include a lower fence pattern FNx and an upper fence pattern FNy that are distinguished from each other without an interface. The upper fence pattern FNy may protrude more than the lower fence pattern FNx in the first direction D1. A bottom surface FNxb of the upper fence pattern FNy may contact a top surface BSPa of the bit line spacer BSP.

[0037] The fence pattern FN may have a first side surface FNS1 pointing in the first direction D1, a second side surface FNS2 pointing in the second direction D2 or the opposite direction thereof, and a third side surface FNS3 opposite to the first side surface FNS1. The first side surface FNS1 of the fence pattern FN may include a first side surface FNxS1 of the lower fence pattern FNx and a first side surface FNyS1 of the upper fence pattern FNy. The second side surface FNS2 of the fence pattern FN may include a second side surface FNxS2 of the lower fence pattern FNx and a second side surface FNyS2 of the upper fence pattern FNy. The third side surface FNS3 of the fence pattern FN may include a third side surface FNxS3 of the lower fence pattern FNx and a third side surface FNyS3 of the upper fence pattern FNy. The first side surface FNyS1 of the upper fence pattern FNy may protrude more in the first direction D1 than the first side surface FNxS1 of the lower fence pattern FNx.

[0038] The second barrier pattern (not shown) may conformally cover the bit line spacer BSP and the storage node contact BC or overlap the bit line spacer BSP and the storage node contact BC. For example, the second barrier pattern may include a metal nitride (e.g., a nitride of Ti, Mo, W, Cu, Al, Ta, Ru, or Ir). The ohmic pattern (not shown) may also be between the second barrier pattern and the storage node contact BC. For example, the ohmic pattern may include a metal silicide (e.g., a silicide of Ti, Mo, W, Cu, Al, Ta, Ru, or Ir).

[0039] A landing pad LP may be disposed on the storage node contact BC. The landing pad LP may be electrically connected to a corresponding one of the first and second edge portions EA1 and EA2 of the active pattern ACT through the corresponding storage node contact BC.

[0040] The landing pad LP may include a lower landing pad LPx and an upper landing pad LPy sequentially disposed on the storage node contact BC. The lower landing pad LPx and the upper landing pad LPy may be distinguished from each other by an interface and may contact each other.

[0041] The lower landing pad LPx may be disposed on the second side surface FNxS2 of the lower fence pattern FNx. The lower landing pad LPx may be between the bit line cover patterns BCP adjacent to each other in the first direction D1. The lower landing pad LPx may be between the lower fence patterns FNx adjacent to each other in the second direction D2. The lower landing pad LPx may be provided in plurality. The lower landing pad LPx may be spaced apart from each other in the first direction D1 and the second direction D2. The lower landing pads LPx adjacent to each other in the first direction D1 may be spaced apart from each other across the bit line cover pattern BCP. The lower landing pads LPx adjacent to each other in the second direction D2 may be spaced apart from each other across the lower fence pattern FNx. The top surface LPxa of the lower landing pad LPx may be located at a level lower than the level of the top surface FNya of the upper fence pattern FNy and substantially the same as the level of the bottom surface FNyb of the upper fence pattern FNy. In other words, the top surface LPxa of the lower landing pad LPx may be at a height lower than the top surface FNya of the upper fence pattern FNy and at substantially the same height as the bottom surface FNyb of the upper fence pattern FNy relative to the top surface of the substrate 100. The lower landing pad LPx may have a uniform width in the second direction D2. For example, the width of the lower landing pad LPx along the second direction D2 may be substantially constant or may decrease in a downward direction.

[0042] The upper landing pad LPy may be disposed on the second side surface FNyS2 of the upper fence pattern FNy. The upper landing pad LPy and the upper fence pattern FNy may be adjacent to each other in the second direction D2. The upper landing pad LPy may be located at a level higher than that of the bit line cover pattern BCP. The upper landing pad LPy may be between the fill patterns FIL adjacent to each other in the first direction D1 described later. The upper landing pad LPy may be between the upper fence patterns FNy adjacent to each other in the second direction D2. The upper landing pad LPy may be provided in plurality. The upper landing pads LPy may be spaced apart from each other in the first direction D1 and the second direction D2. The upper landing pads LPy adjacent to each other in the first direction D1 may be spaced apart from each other across the fill pattern FIL or have the fill pattern FIL placed therebetween. The upper landing pads LPy adjacent to each other in the second direction D2 may be spaced apart from each other across the upper fence pattern FNy. When viewed in a plan view, the upper landing pad LPy may be linearly disposed along the first direction D1 between the word lines WL adjacent to each other in the second direction D2. The upper landing pad LPy may be linearly disposed along the second direction D2 between the fill patterns FIL adjacent to each other in the first direction D1.

[0043] The top surface LPya of the upper landing pad LPy may be located at substantially the same level or height as the top surface FNya of the upper fence pattern FNy relative to the top surface of the substrate.The upper landing pad LPy may protrude more than the lower landing pad LPx in the first direction D1.

[0044] For example, both the lower landing pad LPx and the upper landing pad LPy may be recessed along the second direction D2 relative to the fill pattern FIL to be discussed below. When viewed along the second direction D2, the bottom surface of the upper landing pad LPy may have a width substantially the same as the width of the top surface LPxa of the lower landing pad LPx. When viewed along the second direction D2, the upper landing pad LPy may vertically overlap and completely cover the top surface LPxa of the lower landing pad LPx or completely overlap with the top surface LPxa of the lower landing pad LPx. Therefore, a large contact area may be provided between the top surface LPxa of the lower landing pad LPx and the bottom surface of the upper landing pad LPy. As a result, easy electrical connection may be achieved between the upper landing pad LPy and its corresponding lower landing pad LPx, and the electrical performance of the semiconductor device may be improved.

[0045] The landing pad LP may have a first side surface LPS1 pointing in the first direction D1, a second side surface LPS2 pointing in the second direction D2 or the opposite direction thereof, and a third side surface LPS3 opposite to the first side surface LPS1. The first side surface LPS1 of the landing pad LP may include a first side surface LPxS1 of the lower landing pad LPx and a first side surface LPyS1 of the upper landing pad LPy. The second side surface LPS2 of the landing pad LP may include a second side surface LPxS2 of the lower landing pad LPx and a second side surface LPyS2 of the upper landing pad LPy. The third side surface LPS3 of the landing pad LP may include a third side surface LPxS3 of the lower landing pad LPx and a third side surface LPyS3 of the upper landing pad LPy.

[0046] The second side surface LPxS2 of the lower landing pad LPx may contact the second side surface FNxS2 of the lower fence pattern FNx. The second side surface LPxS2 of the lower landing pad LPx may be continuously connected to the second side surface LPyS2 of the upper landing pad LPy. The second side surface LPxS2 of the lower landing pad LPx may be flat. For example, the second side surface LPxS2 of the lower landing pad LPx may not be concave.

[0047] The first side surface LPyS1 and the third side surface LPyS3 of the upper landing pad LPy may both be in contact with the second side surface LPyS2 of the upper landing pad LPy. For example, the first side surface LPyS1 and the third side surface LPyS3 of the upper landing pad LPy may both be in contact with the second side surface LPyS2 of the upper landing pad LPy, and at the same time, an angle may be formed between the second side surface LPyS2 and each of the first side surface LPyS1 and the third side surface LPyS3. The angle may be angular or may have a curvature.

[0048] The filling pattern FIL may be interposed between upper landing pads LPy adjacent to each other in the first direction D1. The filling pattern FIL may extend in the second direction D2 on the bit line BL. A top surface FILa of the filling pattern FIL may be located at substantially the same level as a top surface LPya of the upper landing pad LPy and a top surface FNya of the fence pattern FN. The filling pattern FIL may be adjacent to the landing pad LP and the fence pattern FN in the first direction D1.

[0049] The filling pattern FIL may be provided in plurality. The plurality of filling patterns FIL may be spaced apart from each other in the first direction D1. The filling patterns FIL adjacent to each other in the first direction D1 may be spaced apart from each other across the upper landing pad LPy or the upper fence pattern FNy. One of a pair of filling patterns FIL adjacent to each other in the first direction D1 may be in contact with the first side surface LPyS1 of the upper landing pad LPy and the first side surface FNyS1 of the upper fence pattern FNy. The other of the pair of filling patterns FIL adjacent to each other in the first direction D1 may be in contact with the third side surface LPyS3 of the upper landing pad LPy and the third side surface FNyS3 of the upper fence pattern FNy. For example, the filling pattern FIL may include silicon nitride (SiN), silicon oxide (SiO 2 ) and / or at least one of silicon oxynitride (SiON).

[0050] The data storage pattern DSP may be disposed on the landing pad LP. The data storage pattern DSP may be disposed in plurality, and the plurality of data storage pattern DSPs may be spaced apart from each other in the first direction D1 and the second direction D2. Each data storage pattern DSP may vertically overlap at least a portion of the corresponding landing pad LP. For example, each data storage pattern DSP may vertically overlap the entire corresponding landing pad LP in a direction perpendicular to the top surface of the substrate 100. In some embodiments, each data storage pattern DSP may be offset beyond the landing pad LP in the first direction D1 or in the opposite direction thereof, and may vertically overlap with a portion of the landing pad LP. The data storage pattern DSP may be electrically connected to one of the first edge portion EA1 and the second edge portion EA2 of the corresponding active pattern ACT through the corresponding landing pad LP and the corresponding storage node contact BC.

[0051] The data storage pattern DSP may be, for example, a capacitor including a bottom electrode, a dielectric layer, and a top electrode. In this case, the semiconductor device according to the present invention may be a dynamic random access memory (DRAM). For another example, the data storage pattern DSP may include a magnetic tunnel junction pattern. In this case, the semiconductor device according to the present invention may be a magnetic random access memory (MRAM). For another example, the data storage pattern DSP may include a phase change material or a variable resistance material. In this case, the semiconductor device according to the present invention may be a phase change random access memory (PRAM) or a resistive random access memory (ReRAM). However, this is merely an example, and the present invention is not limited thereto. The data storage pattern DSP may include various structures and / or materials capable of storing data.

[0052] Reference Figures 3 to 4B , semiconductor devices according to some embodiments of the inventive concept will be described below. For the sake of brevity of description, explanations of components that overlap with those discussed above will be omitted, and differences thereof will be discussed in detail.

[0053] Figure 3 Shown along Figure 1 A cross-sectional view taken along line AA'.

[0054] Reference Figure 3, the first seed pattern SD1 may be between the bit line contact DC and the active pattern ACT. In this case, the bit line contact DC may include a metal material such as Ti, Mo, W, Cu, Al, Ta, Ru, or Ir. When manufacturing the semiconductor device, the bit line contact DC may be grown from the first seed pattern SD1 used as a seed. The first seed pattern SD1 may improve the contact resistance between the bit line contact DC and the active pattern ACT. For example, the first seed pattern SD1 may include a metal silicide (e.g., a silicide of Ti, Mo, W, Cu, Al, Ta, Ru, or Ir). For example, unlike what is shown, the polysilicon pattern PP may not be provided.

[0055] Figure 4A and Figure 4B Shown along Figure 1 A cross-sectional view taken along lines AA' and CC'.

[0056] Reference Figure 4A and Figure 4B , the second seed pattern SD2 may be between the bit line BL and the bit line contact DC. In this case, the bit line contact DC may include doped silicon or undoped silicon. The second seed pattern SD2 may also be between the bit line BL and the polysilicon pattern PP. When manufacturing the semiconductor device, the bit line BL may be grown from the second seed pattern SD2 used as a seed. The second seed pattern SD2 may improve the contact resistance between the bit line BL and the bit line contact DC. For example, the second seed pattern SD2 may include a metal silicide (e.g., a silicide of Ti, Mo, W, Cu, Al, Ta, Ru, or Ir).

[0057] Reference Figures 5 to 14 , a method of manufacturing a semiconductor device according to some embodiments of the inventive concept will be described below. For the sake of brevity of description, explanations of components that overlap with those discussed above will be omitted, and differences will be discussed in detail.

[0058] Figures 5 to 10C A top view and a cross-sectional view illustrating a method of fabricating a semiconductor device according to some embodiments of the inventive concept. Figure 5 , Figure 7 and Fig. 9 A top view illustrating a method of fabricating a semiconductor device according to some embodiments of the inventive concept. Fig. 6A , Fig. 8A and Fig. 10A Shown along Figure 5 , Figure 7 and Fig. 9 A cross-sectional view taken along line AA'. Figure 6B , Figure 8B and Fig. 10B Shown along Figure 5 , Figure 7and Fig. 9 A cross-sectional view taken along line BB'. Figure 6C , Figure 8C and Fig. 10C Shown along Figure 5 , Figure 7 and Fig. 9 A cross-sectional view taken along line CC'.

[0059] Reference Figure 5 and FIG. 6A to FIG. 6C , a substrate 100 may be provided. A device isolation pattern STI may be formed and buried in an upper portion of the substrate 100. The formation of the device isolation pattern STI may include performing a patterning process to partially remove an upper portion of the substrate 100 and filling the removed region with the device isolation pattern STI. The active pattern ACT may be defined as indicating a region of the substrate 100 surrounded by the device isolation pattern STI (e.g., an unremoved upper portion of the substrate 100). An impurity region may be formed in the active pattern ACT. The formation of the impurity region may include performing an ion implantation process to implant impurities into the active pattern ACT.

[0060] The word line WL may be formed in a trench formed on an upper portion of the substrate 100. The formation of the word line WL may include forming a mask pattern (not shown) on the active pattern ACT and the device isolation pattern STI, performing an anisotropic etching process using the mask pattern to form a trench, and partially or completely filling the trench with the word line WL.

[0061] Filling the trench with a word line WL may, for example, include: conformally depositing a gate dielectric pattern GI on an inner surface of the trench, filling the trench with a conductive layer, subjecting the conductive layer to an etch-back process and / or a polishing process to form a gate electrode GE, and forming a gate cover pattern GC on the gate electrode GE that fills the unoccupied portion of the trench.

[0062] The buffer pattern BP and the polysilicon pattern PP may be sequentially formed on the substrate 100. The buffer pattern BP and the polysilicon pattern PP may be formed to cover or overlap the active pattern ACT and the device isolation pattern STI.

[0063] The first recess RS1 may be formed on the active pattern ACT and the device isolation pattern STI. When forming the first recess RS1, the buffer pattern BP and the polysilicon pattern PP may be partially removed. The bit line contact layer DCL may be formed to fill the first recess RS1.

[0064] The first bit line mask layer BMP1L may be formed on the front surface of the substrate 100. The first bit line mask layer BMP1L may include a dielectric material having an etch selectivity relative to surrounding components (e.g., a bit line spacer BSP and a storage node contact BC to be discussed below). For example, the first bit line mask layer BMP1L may include silicon oxide (SiO 2 ) and / or at least one of silicon oxycarbide (SiOC). A first barrier layer (not shown) may also be formed between the first bit line mask layer BMP1L and the bit line contact layer DCL.

[0065] The second bit line mask pattern BMP2 may be formed on the first bit line mask layer BMP1L. The second bit line mask pattern BMP2 may extend in the second direction D2. The second bit line mask pattern BMP2 may be provided in plurality, and the plurality of second bit line mask patterns BMP2 may be spaced apart from each other in the first direction D1.

[0066] Reference Figure 7 and FIG. 8A to FIG. 8C , a portion of the bit line contact layer DCL and a portion of the first bit line mask layer BMP1L may be removed by using the second bit line mask pattern BMP2 as an etching mask to form a bit line contact DC and a first bit line mask pattern BMP1. The unremoved portion of the bit line contact layer DCL may constitute the bit line contact DC or be the bit line contact DC. The unremoved portion of the first bit line mask layer BMP1L may constitute the first bit line mask pattern BMP1 or may be the first bit line mask pattern BMP1. The first bit line mask pattern BMP1 may be formed on the bit line contact DC. The first bit line mask pattern BMP1 may extend in the second direction D2 on the active pattern ACT. The first bit line mask patterns BMP1 may be spaced apart from each other in the first direction D1.

[0067] The bit line spacer BSP may be formed to fill the unoccupied portion of the first recess RS1 and cover or overlap the side surface of the bit line contact DC and the side surface of the first bit line mask pattern BMP1. The formation of the bit line spacer BSP may include forming a plurality of spacers. For example, the first to third spacers may be sequentially formed on the side surface of the first bit line mask pattern BMP1.

[0068] The storage node contact BC may be formed between the first bit line mask patterns BMP1 adjacent to each other in the first direction D1. The formation of the storage node contact BC may include: performing a removal process on a portion of the bit line spacer BSP, forming a second recess RS2 by removing a portion of the buffer pattern BP, a portion of each of the first edge portion EA1 and the second edge portion EA2 of the active pattern ACT, and a portion of the device isolation pattern STI, forming a storage node contact layer (not shown) to fill the space between the second recess RS2 and the first bit line mask pattern BMP1 and cover or overlap the top surface of the first bit line mask pattern BMP1, and removing the storage node contact layer on the top surface of the first bit line mask pattern BMP1 to separate the storage node contacts BC adjacent to each other in the first direction D1 from each other. A chemical mechanical polishing (CMP) process may be performed to remove the storage node contact layer on the top surface of the first bit line mask pattern BMP1.

[0069] Reference Fig. 9 and FIG. 10A to FIG. 10C , the bit line BL may be formed on the bit line contact DC. For example, the formation of the bit line BL may include: removing the first bit line mask pattern BMP1 on the bit line contact DC, and forming the bit line BL in the portion of each region where the first bit line mask pattern BMP1 is removed. The bit line BL may be formed by selective epitaxial growth. Selective epitaxial growth may be a deposition method that grows a specific material only on a specific region.

[0070] According to the inventive concept, the bit line BL can be formed by selective epitaxial growth. Therefore, the bit line BL can be formed to have grains with the same crystal orientation. As a result, the resistance of the bit line BL can be reduced, and the electrical performance of the semiconductor device can be improved.

[0071] The bit line capping pattern BCP may be formed on the bit line BL. For example, the formation of the bit line capping pattern BCP may include: forming a bit line capping layer (not shown) to fill the unoccupied portion of the first bit line mask pattern BMP1 of the region removed and covering or overlapping the top surface of the storage node contact BC, and removing the bit line capping layer on the top surface of the storage node contact BC so that the bit line capping patterns BCP adjacent to each other in the first direction D1 are separated from each other. For example, a chemical mechanical polishing (CMP) process may be performed to remove the bit line capping layer on the top surface of the storage node contact BC.

[0072] According to the inventive concept, the bit line BL and the bit line cover pattern BCP may be sequentially formed in the region where the first bit line mask pattern BMP1 is removed. Therefore, the etching process for forming the bit line BL and the bit line cover pattern BCP may not be performed separately. Instead, the bit line contact DC, the bit line BL, and the bit line cover pattern BCP may be formed by a separate etching process. In this case, the bit line cover pattern BCP may be used as an etching mask and may be formed to have a greater height than when the bit line cover pattern BCP is not used as an etching mask. As a result, the bit line cover pattern BCP may have a high aspect ratio, so when an etching process is performed on each of the bit line contact DC, the bit line BL, and the bit line cover pattern BCP, collapse may occur at each of the bit line contact DC, the bit line BL, and the bit line cover pattern BCP. Therefore, the manufacturing process of forming the bit line BL and the bit line cover pattern BCP using the first bit line mask pattern BMP1 may be easier than the manufacturing process of performing an etching process to form each of the bit line BL and the bit line cover pattern BCP, which may improve the productivity of the semiconductor device.

[0073] The lower landing pad LPx may be formed on the storage node contact BC. For example, the formation of the lower landing pad LPx may include: removing the upper portion of each storage node contact BC, forming a lower landing pad layer to fill the area where the upper portion of each storage node contact BC is removed and cover the top surface of the bit line cover pattern BCP or overlap the top surface of the bit line cover pattern BCP, and removing the lower landing pad layer on the top surface of the bit line cover pattern BCP to form lower landing pads LPx adjacent to each other in the first direction D1. A chemical mechanical polishing (CMP) process may be performed to remove the lower landing pad layer on the top surface of the first bit line cover pattern BCP. The top surface LPxa of the lower landing pad LPx and the top surface of the bit line cover pattern BCP may be located at substantially the same level or height and may be coplanar with each other.

[0074] The fence mask pattern FMP may be formed to extend along the first direction D1 on the lower landing pad LPx. The fence mask pattern FMP may be provided in plurality. The plurality of fence mask patterns FMP may be spaced apart from each other in the second direction D2. The fence mask pattern FMP may include a dielectric material having an etching selectivity relative to surrounding components (e.g., a fence pattern FN to be discussed below). For example, the fence mask pattern FMP may include silicon oxide (SiO 2 ) and / or at least one of silicon oxycarbide (SiOC).

[0075] The fence pattern FN may be formed between the bit lines BL adjacent to each other in the first direction D1 and between the fence mask patterns FMP adjacent to each other in the second direction D2. For example, the formation of the fence pattern FN may include: using the fence mask pattern FMP as an etching mask to remove a portion of the storage node contact BC and a portion of the lower landing pad LPx, and forming the fence pattern FN to fill the area where the portion of the storage node contact BC and the portion of the lower landing pad LPx are removed and also fill the space between the fence mask patterns FMP. The lower fence pattern FNx may be defined as a portion of the fence pattern FN indicating the area filled with the portion of the storage node contact BC and the portion of the lower landing pad LPx removed. The upper fence pattern FNy may be defined as another portion of the fence pattern FN indicating the space between the fence mask patterns FMP. The lower fence pattern FNx and the upper fence pattern FNy may constitute the fence pattern FN or may be the fence pattern FN. The lower fence pattern FNx may be formed to extend along the fourth direction D4 between the bit lines BL adjacent to each other along the first direction D1. The upper fence pattern FNy may be formed to extend along the first direction D1 between the fence mask patterns FMP adjacent to each other along the second direction D2. The top surface FNya of the upper fence pattern FNy may be located at a level or height that is higher than the top surface LPxa of the lower landing pad LPx and substantially the same as the top surface FMPa of the fence mask pattern FMP. The second side surface FNyS2 of the upper fence pattern FNy may contact the fence mask pattern FMP. When the fence pattern FN is formed, the fence pattern FN may divide one storage node contact BC into a plurality of storage node contacts BC spaced apart from each other in the second direction D2, and may divide one lower landing pad LPx into a plurality of lower landing pads LPx spaced apart from each other in the second direction D2.

[0076] Reference Figure 1 and FIG. 2A to FIG. 2C , the upper landing pad LPy may be formed on the lower landing pad LPx. For example, the formation of the upper landing pad LPy may include: removing the fence mask pattern FMP, forming an upper landing pad layer (not shown) to fill the area where the fence mask pattern FMP is removed and cover the top surface FNya of the fence pattern FN or overlap with the top surface FNya of the fence pattern FN, and removing the upper landing pad layer on the top surface FNya of the fence pattern FN to separate the upper landing pads LPy spaced apart from each other in the second direction D2. The upper landing pad LPy, together with the upper fence pattern FNy, may extend along the first direction D1 on the lower landing pad LPx. The top surface LPya of the upper landing pad LPy and the top surface FNya of the fence pattern FN may be located at substantially the same level or height and may be coplanar with each other. The upper landing pads LPy adjacent to each other in the second direction D2 may be spaced apart from each other across the upper fence pattern FNy.

[0077] According to the inventive concept, the upper landing pad LPy can be formed between the regions where the fence mask pattern FMP is removed (for example, between the upper fence patterns FNy adjacent to each other in the second direction D2). Therefore, a separate patterning process for separating the upper landing pads LPy from each other along the second direction D2 can be omitted. In short, the upper landing pad LPy can be easily formed, and the productivity of the semiconductor device can be improved.

[0078] The filling pattern FIL may be formed to cross the upper landing pad LPy and the upper fence pattern FNy or be located on the upper landing pad LPy and the upper fence pattern FNy. The filling pattern FIL may be formed to extend in the second direction D2 on the bit line BL. When the filling pattern FIL is formed, the filling pattern FIL may divide one upper fence pattern FNy into a plurality of upper fence patterns FNy spaced apart from each other in the first direction D1, and may divide one upper landing pad LPy into a plurality of upper landing pads LPy spaced apart from each other in the first direction D1. Thereafter, a data storage pattern DSP may be formed on each upper landing pad LPy.

[0079] Fig.11 and Fig.12 A cross-sectional view illustrating a method of fabricating a semiconductor device according to some embodiments of the inventive concept.

[0080] Reference Fig.11 , in reference FIG. 6A to FIG. 6C After the first recess RS1 discussed is formed, a first seed layer SD1L may be formed in the first recess RS1. The first seed layer SD1L may be formed on the central portion CA of the active pattern ACT. For example, as shown in the figure, the first seed layer SD1L may cover the inner bottom surface of the first recess RS1, overlap with the inner bottom surface of the first recess RS1, or be located on the inner bottom surface of the first recess RS1. For another example, although not shown, the first seed layer SD1L may also cover the inner side surface of the first recess RS1.

[0081] Then, a bit line contact layer DCL may be formed to fill the first recess RS1. The bit line contact layer DCL may be formed through a growth process using the first seed layer SD1L as a seed.

[0082] Reference Fig.12 , the bit line contact DC can be formed by the manufacturing process discussed above. In this process, a portion of the first seed layer SD1L can be removed, and the first seed pattern SD1 can be formed. Then, the reference FET can be manufactured by the manufacturing process discussed above. Figure 3 Discuss semiconductor devices.

[0083] Fig.13 and Fig.14A cross-sectional view illustrating a method of fabricating a semiconductor device according to some embodiments of the inventive concept.

[0084] Reference Fig.13 , you can omit the reference Fig.11 The formation of the first seed layer SD1L is discussed in reference FIG. 6A to FIG. 6C After the bit line contact layer DCL is formed as discussed, a second seed layer SD2L may be formed on the front surface of the substrate 100. The second seed layer SD2L may be formed between the bit line contact layer DCL and the first bit line mask layer BMP1L.

[0085] Reference Fig.14 , the bit line contact DC can be formed by the manufacturing process discussed above. In this process, a portion of the second seed layer SD2L can be removed, and a second seed pattern SD2 can be formed. Then, the reference FET can be manufactured by the manufacturing process discussed above. Figure 4A and Figure 4B Semiconductor devices discussed.

[0086] According to the inventive concept, a bit line can be formed by selective epitaxial growth. Therefore, the bit line can be formed to have grains with the same crystal orientation. As a result, the resistance of the bit line can be reduced, and the electrical performance of the semiconductor device can be improved.

[0087] According to the inventive concept, a bit line and a bit line cover pattern can be sequentially formed in an area where a first bit line mask pattern is removed. Therefore, an etching process for forming a bit line and a bit line cover pattern may not be performed separately. Therefore, a bit line and a bit line cover pattern can be easily formed, and productivity, performance, or yield of a semiconductor device can be improved.

[0088] According to the inventive concept, the upper landing pad can be formed in the area where the fence mask pattern is removed (for example, between the upper fence patterns adjacent to each other in the second direction). Therefore, a separate patterning process for separating the upper landing pads from each other in the second direction can be omitted. In summary, the upper landing pad can be easily formed, and the productivity, performance, or yield of the semiconductor device can be improved.

[0089] The foregoing description provides some embodiments for explaining the inventive concept. Therefore, the inventive concept is not limited to the above embodiments, and those skilled in the art will appreciate that changes in form and detail may be made therein without departing from the spirit and features of the inventive concept.

Claims

1. A semiconductor device, comprising: an active pattern located on the substrate and surrounded by the device isolation pattern in a top view; a word line extending along a first direction and located on the active pattern and the device isolation pattern, wherein the first direction is parallel to a bottom surface of the substrate; a bit line extending along a second direction on the active pattern, wherein the second direction intersects the first direction; a storage node contact, the storage node contact being located on the active pattern; a landing pad, the landing pad comprising a lower landing pad and an upper landing pad stacked on the storage node contact, the lower landing pad and the upper landing pad having an interface therebetween; and a fence pattern located on the word line and on a side surface of the landing pad, Wherein, relative to the substrate, a top surface of the fence pattern is higher than a top surface of the lower landing pad adjacent to the interface between the lower landing pad and the upper landing pad.

2. The semiconductor device according to claim 1, wherein The top surface of the fence pattern is at substantially the same height as a top surface of the upper landing pad relative to the substrate.

3. The semiconductor device according to claim 1, wherein The upper landing pad protrudes beyond the lower landing pad in the first direction.

4. The semiconductor device according to claim 1, further comprising: A bit line cover pattern, the bit line cover pattern is located on the bit line, Wherein, relative to the substrate, the upper landing pad is higher than the bit line covering pattern.

5. The semiconductor device according to claim 4, further comprising: a bit line spacer, the bit line spacer being located on a side surface of the bit line capping pattern, The fence pattern is located on the top surface of the bit line spacer.

6. The semiconductor device according to claim 1, wherein The barrier pattern includes a lower barrier pattern and an upper barrier pattern that are distinguished from each other and have no interface, The upper fence pattern protrudes beyond the lower fence pattern in the first direction.

7. The semiconductor device according to claim 1, wherein The bit line includes a material having grains with crystal orientations in the same direction.

8. The semiconductor device according to claim 1, further comprising: a filling pattern extending along the second direction on the bit line, Wherein, relative to the substrate, a top surface of the filling pattern is at substantially the same height as the top surface of the fence pattern.

9. The semiconductor device according to claim 1, further comprising: a bit line contact, the bit line contact being located between the bit line and the active pattern; as well as A first seed pattern is disposed between the bit line contact and the active pattern.

10. The semiconductor device according to claim 1, further comprising: a bit line contact, the bit line contact being located between the bit line and the active pattern; as well as A second seed pattern is located between the bit line and the bit line contact.

11. A semiconductor device, comprising: an active pattern located on the substrate and surrounded by the device isolation pattern in a top view; a word line extending along a first direction and located on the active pattern and the device isolation pattern, wherein the first direction is parallel to a bottom surface of the substrate; a bit line extending along a second direction on the active pattern, wherein the second direction intersects the first direction; a storage node contact, the storage node contact being located on the active pattern; a landing pad located on the storage node contact; and a fence pattern located on the word line and on a side surface of the landing pad, Wherein, the fence pattern includes: a lower fence pattern located on a side surface of the bit line; and an upper fence pattern located on the lower fence pattern and protruding beyond the lower fence pattern in the first direction.

12. The semiconductor device according to claim 11, further comprising: a bit line spacer, the bit line spacer being located between the lower fence pattern and the bit line, The upper fence pattern is located on the top surface of the bit line spacer.

13. The semiconductor device according to claim 11, wherein The landing pad includes a lower landing pad and an upper landing pad stacked on the storage node contact, Wherein, relative to the substrate, a top surface of the upper landing pad is at substantially the same height as a top surface of the upper fence pattern.

14. The semiconductor device according to claim 13, wherein: The upper landing pad and the lower landing pad contact each other at an interface.

15. The semiconductor device according to claim 11, further comprising: a filling pattern, the filling pattern being located on the bit line and extending along the second direction, Wherein, relative to the substrate, a top surface of the filling pattern is at substantially the same height as a top surface of the upper fence pattern.

16. The semiconductor device according to claim 15, wherein The upper fence pattern includes: a first side surface, the first side surface being located in the first direction; and a second side surface, the second side surface being located in the second direction, wherein the first side surface of the upper fence pattern contacts the filling pattern, and Wherein, the second side surface of the upper fence pattern contacts the landing pad.

17. A semiconductor device, comprising: an active pattern located on the substrate and surrounded by the device isolation pattern in a top view; a word line extending along a first direction and located on the active pattern and the device isolation pattern, wherein the first direction is parallel to a bottom surface of the substrate; a bit line extending along a second direction on the active pattern, wherein the second direction intersects the first direction; a storage node contact, the storage node contact being located on the active pattern; a landing pad, the landing pad being located on the storage node contact; a fence pattern located on the word line and on a side surface of the landing pad; and a filling pattern, the filling pattern being located on the bit line and extending along the second direction, Wherein, relative to the substrate, a top surface of the fence pattern is at substantially the same height as a top surface of the filling pattern.

18. The semiconductor device according to claim 17, in, The filling pattern includes a plurality of filling patterns adjacent to each other in the first direction, and Wherein, the landing pad is located between adjacent filling patterns among the plurality of filling patterns.

19. The semiconductor device according to claim 17, in, The filling pattern includes a plurality of filling patterns adjacent to each other in the first direction, and Wherein, the fence pattern is located between adjacent filling patterns among the plurality of filling patterns.

20. The semiconductor device according to claim 17, wherein The landing pad comprises: a first side surface, the first side surface being located in the first direction; and a second side surface, the second side surface being located in the second direction, wherein the first side surface of the landing pad contacts the filling pattern, and Wherein, the second side surface of the landing pad contacts the fence pattern.

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