Light emitting diode chip and preparation method thereof

Abstract

The present invention provides a light-emitting diode chip and a preparation method thereof, wherein the preparation method of the light-emitting diode chip comprises: providing a substrate required for growth, depositing an N-type semiconductor layer, an active light-emitting layer and a P-type semiconductor layer on the substrate in sequence; preparing an N-type conductive through hole on the P-type semiconductor layer; preparing a current spreading layer on the P-type semiconductor layer and the N-type conductive through hole; preparing a current blocking layer on the current spreading layer, the P-type semiconductor layer not covered by the current spreading layer and the N-type conductive through hole not covered by the current spreading layer; preparing a current blocking layer through hole on the current blocking layer; preparing a first semiconductor layer on the current blocking layer and the current blocking layer through hole; stripping the substrate to completely expose the bottom of the N-type semiconductor layer; preparing a second semiconductor layer at the bottom of the N-type semiconductor layer; and preparing an N-type pad on the first semiconductor layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a light emitting diode chip and a preparation method thereof. Background Art

[0002] In recent years, the light-emitting diode chip technology has developed rapidly under the competition of major manufacturers and has been widely used in various fields such as general lighting, special lighting, direct display screens, backlight display screens, and car lights.

[0003] As LED chips become more and more mature and the speed of technological iteration slows down, how to further improve the luminous efficiency of LED chips, especially when the chips are used under extremely small current density, it is even more difficult to improve the luminous efficiency of chips. How to further improve the luminous efficiency of LED chips is something that every practitioner and researcher thinks about.

[0004] In the prior art, the existing light-emitting diode chips have N-type conductive vias, which will cause an increase in non-radiative recombination of the epitaxial layer around the N-type conductive vias due to the inductively coupled plasma etching process, resulting in a decrease in luminous efficiency at 200um-0um of the N-type conductive vias. When the light-emitting diode chip is used under extremely low current density, the luminous efficiency is highest at 500um-200um around the N-type conductive vias. Summary of the invention

[0005] Based on this, an object of the present invention is to provide a light emitting diode chip and a method for preparing the same, which can effectively solve the deficiencies in the above-mentioned prior art.

[0006] A method for preparing a light emitting diode chip, the method comprising:

[0007] S1, providing a substrate required for growth, and sequentially depositing an N-type semiconductor layer, an active light-emitting layer, and a P-type semiconductor layer on the substrate;

[0008] S2, preparing an N-type conductive through hole on the P-type semiconductor layer;

[0009] S3, preparing a current spreading layer on the P-type semiconductor layer and the N-type conductive through hole;

[0010] S4, preparing a current blocking layer on the current spreading layer, the P-type semiconductor layer not covered by the current spreading layer, and the N-type conductive through hole not covered by the current spreading layer;

[0011] S5, coating a photoresist on the surface of the current blocking layer, then removing part of the photoresist by exposure and development to expose the current blocking layer below the part of the photoresist, and then etching the exposed part of the current blocking layer by BOE etching solution to form a current blocking layer through hole;

[0012] Wherein, the current blocking layer through hole is arranged around the N-type conductive through hole, and the projected area of ​​the current blocking layer through hole increases linearly at a distance of 500um-200um from the edge of the N-type conductive through hole, and decreases linearly at a distance of 200um-0um from the edge of the N-type conductive through hole, and the sum of the areas of all the current blocking layer through holes between 500um-200um from the edge of the N-type conductive through hole is greater than the area of ​​the current blocking layer still retained between 500um-200um from the edge of the N-type conductive through hole, and the sum of the areas of all the current blocking layer through holes between 200um-0um from the edge of the N-type conductive through hole is less than the area of ​​the current blocking layer still retained between 200um-0um from the edge of the N-type conductive through hole;

[0013] S6, preparing a first semiconductor layer on the current blocking layer and the through hole of the current blocking layer;

[0014] S7, peeling off the substrate to completely expose the bottom of the N-type semiconductor layer;

[0015] S8, preparing a second semiconductor layer at the bottom of the N-type semiconductor layer;

[0016] S9, preparing an N-type pad on the first semiconductor layer;

[0017] Furthermore, the specific steps of preparing the N-type conductive via include:

[0018] A photoresist is coated on the surface of the P-type semiconductor layer, and then a part of the photoresist is removed by exposure and development process to expose a part of the P-type semiconductor layer. Then, an inductively coupled plasma etching process is used to remove the exposed P-type semiconductor layer and the active light-emitting layer under this part of the P-type semiconductor layer to form the N-type conductive through hole, and then the excess photoresist is removed.

[0019] Furthermore, the specific steps of preparing the current spreading layer include:

[0020] Indium tin oxide is deposited on the surface of the P-type semiconductor layer and the N-type conductive through hole by using a magnetron sputtering process, and then a photoresist is coated on the surface of the indium tin oxide. Then, part of the photoresist is removed by exposure and development to expose part of the indium tin oxide. Then, the exposed indium tin oxide is removed by an indium tin oxide etching solution, and then excess photoresist is removed to form the current spreading layer.

[0021] Furthermore, the specific steps of preparing the current blocking layer include:

[0022] SiO is deposited on the surface of the current spreading layer, the P-type semiconductor layer not covered by the current spreading layer, and the N-type conductive through hole not covered by the current spreading layer by using a PECVD process.2 as the current blocking layer;

[0023] Wherein, the thickness of the current blocking layer is greater than 5000Å.

[0024] Furthermore, the first semiconductor layer includes a metal reflective layer, a connecting metal layer, a first insulating layer, a first insulating layer through hole, a first bonding layer, a second bonding layer and a conductive silicon substrate which are sequentially arranged on the current blocking layer.

[0025] Furthermore, the step of preparing the first semiconductor layer includes:

[0026] The metal reflective layer is prepared on the surface of the current blocking layer and the current blocking layer through hole, and then the connecting metal layer is prepared on the metal reflective layer and the current blocking layer not covered by the metal reflective layer, and then the first insulating layer is prepared on the connecting metal layer, and then the first insulating layer through hole is prepared on the first insulating layer, and then the first bonding layer is prepared on the first insulating layer and the first insulating layer through hole, and finally the second bonding layer is prepared on the conductive silicon substrate and then the second bonding layer is bonded to the first bonding layer at high temperature.

[0027] Furthermore, the step of preparing the N-type pad includes:

[0028] The side of the conductive silicon substrate away from the second bonding layer is polished, and then Ti metal, Al metal, Ti metal, Ni metal and AuSn metal are sequentially evaporated on the polished side of the conductive silicon substrate using an electron beam evaporation process as the N-type pad.

[0029] Furthermore, the second semiconductor layer includes an isolation trench, a second insulating layer, a second insulating layer through hole and a P-type pad which are sequentially arranged at the bottom of the N-type semiconductor layer.

[0030] Furthermore, the step of preparing the second semiconductor layer includes:

[0031] The isolation trench is prepared on the N-type semiconductor layer, and then a second insulating layer is prepared on the isolation trench. Then, a second insulating layer through hole is prepared on the second insulating layer. Finally, the P-type pad is prepared on the second insulating layer and the second insulating layer through hole.

[0032] The present invention also provides a light emitting diode chip, which is prepared by the light emitting diode chip preparation method as described above.

[0033] Compared with the prior art, the beneficial effects of the present invention are as follows: by setting a current blocking layer and a current blocking layer through hole, by setting the current blocking layer through hole around the N-type conductive through hole, and the projected area of ​​the current blocking layer through hole increases linearly at a distance of 500um-200um from the edge of the N-type conductive through hole, the sum of the areas of the current blocking layer through holes between 500um-200um from the edge of the N-type conductive through hole is greater than the area of ​​the current blocking layer still retained between 500um-200um from the edge of the N-type conductive through hole, so that the projected area of ​​the current blocking layer through hole at a distance of 500um-200um from the edge of the N-type conductive through hole is increased, because the luminous efficiency is the highest at a distance of 500um-200um from the edge of the N-type conductive through hole, increasing the area of ​​the current blocking layer through hole here is equivalent to increasing the area of ​​current injection here, thereby increasing the overall operating voltage of the light-emitting diode chip The reduction is large, and the brightness is slightly reduced. By setting a current blocking layer and a current blocking layer through hole, and by setting the current blocking layer through hole around the N-type conductive through hole and linearly reducing it at 200um-0um from the edge of the N-type conductive through hole, the sum of the areas of all the current blocking layer through holes between 200um-0um from the edge of the N-type conductive through hole is less than the area of ​​the current blocking layer still retained between 200um-0um from the edge of the N-type conductive through hole, because the non-radiative recombination of the epitaxial layer increases at 200um-0um from the edge of the N-type conductive through hole, and the luminous efficiency is low, and the projected area of ​​the current blocking layer through hole is linearly reduced here, which is equivalent to reducing the current injection here, thereby making the overall voltage rise of the light-emitting diode chip smaller and the brightness increase larger, thereby improving the overall brightness of the light-emitting diode chip, reducing the voltage, and thus improving the luminous efficiency of the light-emitting diode chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 is a flow chart of a method for preparing a light emitting diode chip in Example 1 of the present invention;

[0035] Figure 2 is a cross-sectional schematic diagram of a light emitting diode chip in Example 1 of the present invention;

[0036] Figure 3 is a schematic top view of a semi-finished product formed in step S5 in Example 1 of the present invention;

[0037] Figure 4 is a cross-sectional schematic diagram of a semi-finished product formed through step S6 in Example 1 of the present invention;

[0038] Description of main component symbols:

[0039]

[0040] The following specific implementation manner will further illustrate the present invention in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0041] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Several embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0042] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0044] Example 1

[0045] See also Figures 1 to 4 , the method for preparing a light emitting diode chip in an embodiment of the present invention comprises:

[0046] S1, providing a substrate 10 required for growth, and sequentially depositing an N-type semiconductor layer 111, an active light-emitting layer 112, and a P-type semiconductor layer 113 on the substrate 10;

[0047] In this embodiment, the specific process of depositing the N-type semiconductor layer 111, the active light-emitting layer 112 and the P-type semiconductor layer 113 is as follows:

[0048] A substrate 10 is provided, and then the N-type semiconductor layer 111, the active light-emitting layer 112, and the P-type semiconductor layer 113 are sequentially deposited on the substrate 10 by using a MOCVD process, wherein the substrate 10 may be a GaN substrate, an Al 2 O 3 substrate or Si substrate.

[0049] S2, preparing an N-type conductive through hole 114 on the P-type semiconductor layer 113;

[0050] Furthermore, the specific steps of preparing the N-type conductive via 114 include:

[0051] Photoresist is coated on the surface of the P-type semiconductor layer 113, and then a portion of the photoresist is removed by exposure and development processes to expose a portion of the P-type semiconductor layer. Then, an inductively coupled plasma etching process is used to remove the exposed P-type semiconductor layer and the active light-emitting layer under this portion of the P-type semiconductor layer to form the N-type conductive through hole 114, and then excess photoresist is removed.

[0052] S3, preparing a current spreading layer 12 on the P-type semiconductor layer 113 and the N-type conductive via 114;

[0053] Furthermore, the specific steps of preparing the current spreading layer 12 include:

[0054] Indium tin oxide is deposited on the surface of the P-type semiconductor layer 113 and the N-type conductive via 114 by a magnetron sputtering process, and then a photoresist is coated on the surface of the indium tin oxide. Then, part of the photoresist is removed by exposure and development to expose part of the indium tin oxide. Then, the exposed indium tin oxide is removed by an indium tin oxide etching solution, and then the excess photoresist is removed to form the current spreading layer 12.

[0055] S4, preparing a current blocking layer 13 on the current spreading layer 12, the P-type semiconductor layer not covered by the current spreading layer 12, and the N-type conductive through hole not covered by the current spreading layer 12;

[0056] Furthermore, the specific steps of preparing the current blocking layer 13 include:

[0057] SiO is deposited on the surface of the current spreading layer 12, the P-type semiconductor layer not covered by the current spreading layer 12, and the N-type conductive through hole not covered by the current spreading layer 12 by using a PECVD process. 2 As the current blocking layer 13 .

[0058] Wherein, the thickness of the current blocking layer 13 is greater than 5000Å.

[0059] S5, coating the surface of the current blocking layer 13 with photoresist, then removing part of the photoresist by exposure and development to expose the current blocking layer below the photoresist, and then etching the exposed part of the current blocking layer with BOE etching solution to form a current blocking layer through hole 131;

[0060] The current blocking layer through hole 131 is arranged around the N-type conductive through hole 114, and the projected area of ​​the current blocking layer through hole 131 increases linearly at a distance of 500um-200um from the edge of the N-type conductive through hole 114, and decreases linearly at a distance of 200um-0um from the edge of the N-type conductive through hole 114, and the sum of the areas of all the current blocking layer through holes between 500um-200um from the edge of the N-type conductive through hole 114 is greater than the area of ​​the current blocking layer still retained between 500um-200um from the edge of the N-type conductive through hole 114, and the sum of the areas of all the current blocking layer through holes between 200um-0um from the edge of the N-type conductive through hole 114 is less than the area of ​​the current blocking layer still retained between 200um-0um from the edge of the N-type conductive through hole 114;

[0061] Among them, in this embodiment, the sum of the areas of all current blocking layer through holes between 500um-200um from the edge of the N-type conductive through hole 114 is 3 times the area of ​​the current blocking layer still retained between 500um-200um from the edge of the N-type conductive through hole 114, and the sum of the areas of all current blocking layer through holes between 200um-0um from the edge of the N-type conductive through hole 114 is 0.8 times the area of ​​the current blocking layer still retained between 200um-0um from the edge of the N-type conductive through hole 114.

[0062] S6, preparing a first semiconductor layer on the current blocking layer 13 and the current blocking layer through hole 131;

[0063] Furthermore, the first semiconductor layer includes a metal reflective layer 14 , a connecting metal layer 15 , a first insulating layer 16 , a first insulating layer through hole 161 , a first bonding layer 171 , a second bonding layer 172 and a conductive silicon substrate 18 which are sequentially arranged on the current blocking layer 13 .

[0064] Furthermore, the step of preparing the first semiconductor layer includes:

[0065] The metal reflective layer 14 is prepared on the surface of the current blocking layer 13 and the current blocking layer through hole 131, and then the connecting metal layer 15 is prepared on the metal reflective layer 14 and the current blocking layer not covered by the metal reflective layer 14, and then the first insulating layer 16 is prepared on the connecting metal layer 15, and then the first insulating layer through hole 161 is prepared on the first insulating layer 16, and then the first bonding layer 171 is prepared on the first insulating layer 16 and the first insulating layer through hole 161, and finally the second bonding layer 172 is prepared on the conductive silicon substrate 18 and then the second bonding layer 172 is bonded to the first bonding layer 171 at high temperature.

[0066] In this embodiment, the specific steps of preparing the first semiconductor layer include:

[0067] A negative photoresist is coated on the surface of the current blocking layer 13 and the current blocking layer through hole 131, and then a part of the photoresist is removed by exposure and development, and then Ag metal, Ni metal, Ti metal, Ni metal and Ti metal are sequentially evaporated as the metal reflective layer 14 by using an electron beam evaporation process, and then the metal reflective layer located on the photoresist is removed by a lift-off process, and then the photoresist is removed; then a negative photoresist is coated on the metal reflective layer 14 and the current blocking layer not covered by the metal reflective layer 14, and then a part of the photoresist is removed by exposure and development, and then Ni metal, Pt metal, Ni metal, Pt metal, Ni metal and Pt metal layer are sequentially evaporated as the connecting metal layer 15 by using an electron beam evaporation process, and then the connecting metal layer located on the photoresist is removed by a lift-off process, and then the photoresist is removed; then Al is first deposited on the connecting metal layer 15 and the area not covered by the connecting metal layer 15 by an ALD process 2 O 3 film layer, and then in the Al 2 O 3 SiO is deposited on the film layer using PECVD process. 2 as the first insulating layer 16; then, photoresist is coated on the surface of the first insulating layer 16, and then, part of the photoresist is removed by exposure and development to expose the first insulating layer under the part of the photoresist, and then, the exposed first insulating layer is corroded by BOE etching solution to form the first insulating layer through hole 161, and then, the photoresist is removed; then, Cr metal, Al metal, Ti metal, Pt metal, Ti metal, Ni metal and AuSn metal are sequentially evaporated on the first insulating layer 16 and the first insulating layer through hole 161 by electron beam evaporation process as the first bonding layer 171; then, a mixed conductive silicon substrate 18 is provided, and then, Ti metal, Ni metal, Ti metal, Ni metal and AuSn metal are sequentially evaporated on the conductive silicon substrate 18 by electron beam evaporation process as the second bonding layer 172, and then, the first bonding layer 171 and the second bonding layer 172 are bonded by a high-temperature bonding process.

[0068] It should be noted that, in addition to the reflection function, the metal reflection layer 14 also has another function of forming an electrical connection with the current spreading layer 12 through the current blocking layer through hole 131 .

[0069] It should be noted that the thickness of each layer of Ni metal in the connecting metal layer 15 is between 500Å-1000Å, the thickness of each layer of Pt metal is between 200Å-500Å, and the total thickness of all Ni metals in the connecting metal layer 15 is twice the total thickness of all Pt metals, and the connecting metal layer 15 is responsible for electrically connecting the metal reflective layer 14 with the subsequently prepared P-type pad.

[0070] It should be noted that the first insulating layer through hole 161 is located above the N-type conductive through hole 114 and the first insulating layer through hole 161 and the N-type conductive through hole 114 are concentric circles, and the radius of the first insulating layer through hole 161 is smaller than the radius of the N-type conductive through hole 114 .

[0071] It should be noted that, in the first bonding layer 171 , the mass ratio of Au metal to Sn metal in the AuSn alloy is between 77% and 83%, and the thickness of the AuSn alloy is between 3 um and 5 um.

[0072] It should be noted that the bonding temperature during the high temperature bonding process is between 300°C and 350°C.

[0073] S7, peeling off the substrate 10 to completely expose the bottom of the N-type semiconductor layer 111;

[0074] Among them, the specific process of peeling off the substrate in this embodiment is:

[0075] The substrate 10 is removed by laser lift-off technology to completely expose the bottom of the N-type semiconductor layer 111 .

[0076] S8, preparing a second semiconductor layer at the bottom of the N-type semiconductor layer 111;

[0077] Furthermore, the second semiconductor layer includes an isolation trench 115 , a second insulating layer 19 , a second insulating layer through hole 191 and a P-type pad 20 which are sequentially arranged at the bottom of the N-type semiconductor layer 111 .

[0078] Furthermore, the step of preparing the second semiconductor layer includes:

[0079] The isolation trench 115 is prepared on the N-type semiconductor layer 111 , and then a second insulating layer 19 is prepared on the isolation trench 115 . Subsequently, a second insulating layer through hole 191 is prepared on the second insulating layer 19 . Finally, the P-type pad 20 is prepared on the second insulating layer 19 and the second insulating layer through hole 191 .

[0080] In this embodiment, the specific steps of preparing the second semiconductor layer include:

[0081] A photoresist is coated on the bottom of the N-type semiconductor layer 111, and then a portion of the photoresist is removed by exposure and development to expose a portion of the edge of the N-type semiconductor layer. Then, the N-type semiconductor layer with the exposed edge and the active light-emitting layer and the P-type semiconductor layer under the N-type semiconductor layer are removed by an ICP etching process to form the isolation groove 115, and then the photoresist is removed. Then, SiO2 is deposited on the isolation groove 115 and the current blocking layer exposed after etching the isolation groove 115 and the upper surface of the remaining N-type semiconductor layer by a PECVD process. 2 The film is used as the second insulating layer 19; then, photoresist is coated on the surface of the second insulating layer 19, and then, part of the photoresist is removed by exposure and development to expose part of the second insulating layer, and then, BOE is used to etch away the exposed second insulating layer and the current blocking layer under this part of the second insulating layer until the connecting metal layer 15, so as to form a second insulating layer through hole 191; then, an electron beam evaporation process is used to evaporate a layer of Au metal as the P-type pad 20, and then, the Lift-Off process is used to remove the excess metal on the photoresist, and finally, the photoresist is removed.

[0082] S9, preparing an N-type pad 21 on the first semiconductor layer.

[0083] Furthermore, the steps of preparing the N-type pad 21 include:

[0084] The side of the conductive silicon substrate 18 away from the second bonding layer 172 is polished, and then Ti metal, Al metal, Ti metal, Ni metal and AuSn metal are sequentially evaporated on the polished side of the conductive silicon substrate using an electron beam evaporation process as the N-type pad 21.

[0085] It can be understood that by setting the current blocking layer 13 and the current blocking layer through hole 131, by setting the current blocking layer through hole 131 around the N-type conductive through hole 114, and the projected area of ​​the current blocking layer through hole 131 increases linearly at a distance of 500um-200um from the edge of the N-type conductive through hole 114, the sum of the areas of the current blocking layer through holes between 500um-200um from the edge of the N-type conductive through hole 114 is greater than the area of ​​the current blocking layer still retained between 500um-200um from the edge of the N-type conductive through hole 114, so that the projected area of ​​the current blocking layer through hole at a distance of 500um-200um from the edge of the N-type conductive through hole 114 is increased, because the luminous efficiency is the highest at a distance of 500um-200um from the edge of the N-type conductive through hole, and increasing the area of ​​the current blocking layer through hole here is equivalent to increasing the area of ​​current injection here, thereby reducing the overall operating voltage of the light-emitting diode chip. The amplitude of the decrease is large, and the brightness is slightly reduced. By setting the current blocking layer 13 and the current blocking layer through hole 131, by setting the current blocking layer through hole 131 around the N-type conductive through hole 114 and linearly reducing it at a distance of 200um-0um from the edge of the N-type conductive through hole 114, the sum of the areas of all the current blocking layer through holes between 200um-0um from the edge of the N-type conductive through hole 114 is less than the area of ​​the current blocking layer still retained between 200um-0um from the edge of the N-type conductive through hole 114, because the non-radiative recombination of the epitaxial layer increases at a distance of 200um-0um from the edge of the N-type conductive through hole, the luminous efficiency is low, and the projected area of ​​the current blocking layer through hole is linearly reduced here, which is equivalent to reducing the current injection here, thereby making the overall voltage rise of the light-emitting diode chip smaller and the brightness increase larger, thereby improving the overall brightness of the light-emitting diode chip, reducing the voltage, and thus improving the luminous efficiency of the light-emitting diode chip.

[0086] See also Figure 2 , which is a cross-sectional schematic diagram of a light-emitting diode chip prepared by the method for preparing a light-emitting diode chip in an embodiment of the present invention.

[0087] Example 2

[0088] A light emitting diode chip, which is different from the light emitting diode chip prepared in Example 1 in that:

[0089] The sum of the areas of all current blocking layer through holes between 500um-200um from the edge of the N-type conductive through hole is 5 times the area of ​​the current blocking layer still retained between 500um-200um from the edge of the N-type conductive through hole, and the sum of the areas of all current blocking layer through holes between 200um-0um from the edge of the N-type conductive through hole is 0.6 times the area of ​​the current blocking layer still retained between 200um-0um from the edge of the N-type conductive through hole

[0090] Comparative Example 1

[0091] A light emitting diode chip, which is different from the light emitting diode chip prepared in Example 1 in that:

[0092] There is no current blocking layer through hole at a distance of 500um-0um from the edge of the N-type conductive through hole.

[0093] Comparative Example 2

[0094] A light emitting diode chip, which is different from the light emitting diode chip prepared in Example 1 in that:

[0095] The projected area of ​​the current blocking layer through-hole decreases linearly at a distance of 500um-200um from the edge of the N-type conductive through-hole, and increases linearly at a distance of 200um-0um from the edge of the N-type conductive through-hole. The sum of the areas of all the current blocking layer through-holes between 500um-200um from the edge of the N-type conductive through-hole is 0.8 times the area of ​​the current blocking layer still retained between 500um-200um from the edge of the N-type conductive through-hole, and the sum of the areas of all the current blocking layer through-holes between 200um-0um from the edge of the N-type conductive through-hole is 2 times the area of ​​the current blocking layer still retained between 200um-0um from the edge of the N-type conductive through-hole.

[0096] Comparative Example 3

[0097] A light emitting diode chip, which is different from the light emitting diode chip prepared in Example 1 in that:

[0098] The projected area of ​​the current blocking layer through-hole decreases linearly at a distance of 500um-200um from the edge of the N-type conductive through-hole, and increases linearly at a distance of 200um-0um from the edge of the N-type conductive through-hole. The sum of the areas of all the current blocking layer through-holes between 500um-200um from the edge of the N-type conductive through-hole is 2.3 times the area of ​​the current blocking layer still retained between 500um-200um from the edge of the N-type conductive through-hole, and the sum of the areas of all the current blocking layer through-holes between 200um-0um from the edge of the N-type conductive through-hole is 0.8 times the area of ​​the current blocking layer still retained between 200um-0um from the edge of the N-type conductive through-hole.

[0099] Based on the light-emitting diode chips prepared in the above-mentioned embodiments 1 and 2 and the light-emitting diode chips in comparative examples 1 to 3, the light-emitting diode chips prepared in the above-mentioned embodiments 1 and 2 and the light-emitting diode chips in comparative examples 1 to 3 are compared in terms of chip brightness, chip voltage and luminous efficiency, and the corresponding test results are shown in the following table:

[0100]

[0101] It should be noted that in order to ensure the reliability of the verification results, when comparing the chip brightness, chip voltage and luminous efficiency of the light-emitting diode chips prepared in the above-mentioned Examples 1 and 2 of the present invention and the light-emitting diode chips in Comparative Examples 1 to 3, except for the above-mentioned parameters, other processes and parameters should remain consistent.

[0102] In summary, the method for preparing the light-emitting diode chip in the above-mentioned embodiment of the present invention, by setting a current blocking layer and a current blocking layer through hole, by setting the current blocking layer through hole around the N-type conductive through hole, and the projected area of ​​the current blocking layer through hole increases linearly at a distance of 500um-200um from the edge of the N-type conductive through hole, and the sum of the areas of the current blocking layer through holes between 500um-200um from the edge of the N-type conductive through hole is greater than the area of ​​the current blocking layer still retained between 500um-200um from the edge of the N-type conductive through hole, so that the projected area of ​​the current blocking layer through hole at a distance of 500um-200um from the edge of the N-type conductive through hole is increased, because the luminous efficiency is the highest at a distance of 500um-200um from the edge of the N-type conductive through hole, and increasing the area of ​​the current blocking layer through hole here is equivalent to increasing the area of ​​current injection here, thereby making the overall light-emitting diode chip The operating voltage is reduced significantly, and the brightness is slightly reduced. By setting a current blocking layer and a current blocking layer through hole, and by setting the current blocking layer through hole around the N-type conductive through hole and linearly reducing it at 200um-0um from the edge of the N-type conductive through hole, the sum of the areas of all the current blocking layer through holes between 200um-0um from the edge of the N-type conductive through hole is less than the area of ​​the current blocking layer still retained between 200um-0um from the edge of the N-type conductive through hole, because the non-radiative recombination of the epitaxial layer increases at 200um-0um from the edge of the N-type conductive through hole, and the luminous efficiency is low, and the projected area of ​​the current blocking layer through hole is linearly reduced here, which is equivalent to reducing the current injection here, thereby making the overall voltage rise of the light-emitting diode chip smaller and the brightness increase larger, thereby improving the overall brightness of the light-emitting diode chip, reducing the voltage, and thus improving the luminous efficiency of the light-emitting diode chip.

[0103] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0104] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A method for preparing a light emitting diode chip, characterized in that: The preparation method comprises: S1, providing a substrate required for growth, and sequentially depositing an N-type semiconductor layer, an active light-emitting layer, and a P-type semiconductor layer on the substrate; S2, preparing an N-type conductive through hole on the P-type semiconductor layer; The specific steps of preparing the N-type conductive through hole include: Applying photoresist on the surface of the P-type semiconductor layer, then removing part of the photoresist by exposure and development process to expose part of the P-type semiconductor layer, then removing the exposed P-type semiconductor layer and the active light-emitting layer under the P-type semiconductor layer by inductively coupled plasma etching process to form the N-type conductive through hole, and then removing excess photoresist; S3, preparing a current spreading layer on the P-type semiconductor layer and the N-type conductive through hole; S4, preparing a current blocking layer on the current spreading layer, the P-type semiconductor layer not covered by the current spreading layer, and the N-type conductive through hole not covered by the current spreading layer; S5, coating a photoresist on the surface of the current blocking layer, then removing part of the photoresist by exposure and development to expose the current blocking layer below the part of the photoresist, and then etching the exposed part of the current blocking layer by BOE etching solution to form a current blocking layer through hole; Wherein, the current blocking layer through hole is arranged around the N-type conductive through hole, and the projected area of ​​the current blocking layer through hole increases linearly at a distance of 500um-200um from the edge of the N-type conductive through hole, and decreases linearly at a distance of 200um-0um from the edge of the N-type conductive through hole, and the sum of the areas of all the current blocking layer through holes between 500um-200um from the edge of the N-type conductive through hole is greater than the area of ​​the current blocking layer still retained between 500um-200um from the edge of the N-type conductive through hole, and the sum of the areas of all the current blocking layer through holes between 200um-0um from the edge of the N-type conductive through hole is less than the area of ​​the current blocking layer still retained between 200um-0um from the edge of the N-type conductive through hole; S6, preparing a first semiconductor layer on the current blocking layer and the through hole of the current blocking layer; S7, peeling off the substrate to completely expose the bottom of the N-type semiconductor layer; S8, preparing a second semiconductor layer at the bottom of the N-type semiconductor layer; S9, preparing an N-type pad on the first semiconductor layer.

2. The method for preparing a light emitting diode chip according to claim 1, characterized in that: The specific steps of preparing the current spreading layer include: Indium tin oxide is deposited on the surface of the P-type semiconductor layer and the N-type conductive through hole by using a magnetron sputtering process, and then a photoresist is coated on the surface of the indium tin oxide. Then, part of the photoresist is removed by exposure and development to expose part of the indium tin oxide. Then, the exposed indium tin oxide is removed by an indium tin oxide etching solution, and then excess photoresist is removed to form the current spreading layer.

3. The method for preparing a light emitting diode chip according to claim 1, characterized in that: The specific steps of preparing the current blocking layer include: Depositing SiO2 as the current blocking layer on the surface of the current spreading layer, the P-type semiconductor layer not covered by the current spreading layer, and the N-type conductive through hole not covered by the current spreading layer by using a PECVD process; Wherein, the thickness of the current blocking layer is greater than 5000Å.

4. The method for preparing a light emitting diode chip according to claim 1, characterized in that: The first semiconductor layer includes a metal reflective layer, a connecting metal layer, a first insulating layer, a first insulating layer through hole, a first bonding layer, a second bonding layer and a conductive silicon substrate which are sequentially arranged on the current blocking layer.

5. The method for preparing a light emitting diode chip according to claim 4, characterized in that: The steps of preparing the first semiconductor layer include: The metal reflective layer is prepared on the surface of the current blocking layer and the current blocking layer through hole, and then the connecting metal layer is prepared on the metal reflective layer and the current blocking layer not covered by the metal reflective layer, and then the first insulating layer is prepared on the connecting metal layer, and then the first insulating layer through hole is prepared on the first insulating layer, and then the first bonding layer is prepared on the first insulating layer and the first insulating layer through hole, and finally the second bonding layer is prepared on the conductive silicon substrate and then the second bonding layer is bonded to the first bonding layer at high temperature.

6. The method for preparing a light emitting diode chip according to claim 5, characterized in that: The steps of preparing the N-type pad include: The side of the conductive silicon substrate away from the second bonding layer is polished, and then Ti metal, Al metal, Ti metal, Ni metal and AuSn metal are sequentially evaporated on the polished side of the conductive silicon substrate using an electron beam evaporation process as the N-type pad.

7. The method for preparing a light emitting diode chip according to claim 1, characterized in that: The second semiconductor layer includes an isolation groove, a second insulating layer, a second insulating layer through hole and a P-type pad which are sequentially arranged at the bottom of the N-type semiconductor layer.

8. The method for preparing a light emitting diode chip according to claim 7, characterized in that: The step of preparing the second semiconductor layer comprises: The isolation trench is prepared on the N-type semiconductor layer, and then a second insulating layer is prepared on the isolation trench. Then, a second insulating layer through hole is prepared on the second insulating layer. Finally, the P-type pad is prepared on the second insulating layer and the second insulating layer through hole.

9. A light emitting diode chip, characterized in that: The light emitting diode chip is prepared by the preparation method of any one of claims 1 to 8.

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