One time programmable (ROTP) NVM

Abstract

In an embodiment, a method includes receiving a first program bit address associated with a plurality of redundant bit addresses and a first transistor-based memory cell, where the plurality of redundant bit addresses are each associated with a respective transistor-based memory cell; providing a program pulse to a first word line coupled to the first transistor-based memory cell to write the first write value to the first transistor-based memory cell; reading a first bit value from the first transistor-based memory cell; reading redundant bit values from the transistor-based memory cells associated with the plurality of redundant bit addresses; determining a majority bit value based on the first bit value and the redundancy bit value when one of the first bit value and the redundancy bit value does not match the first write value; and asserting the flag signal when the majority bit value does not match the first write value.

Description

[0001] This application claims the benefit of U.S. patent application No. 17 / 937,012, filed on September 30, 2022, which claims the benefit of U.S. Provisional Application No. 63 / 349,227, filed on June 6, 2022, entitled “Fuse Replacement by Real One Time Programing (ROTP) NVM,” which are hereby incorporated by reference into this document. Technical Field

[0002] The present disclosure relates generally to electronic systems and methods and, in particular embodiments, to one-time programmable (OTP) non-volatile memory (NVM). Background Art

[0003] One-time programmable (OTP) memory is often used in integrated circuits (ICs) to store immutable data. OTP memory is a type of memory that can be written to but not erased. OTP memory can be implemented as OTP by decision or as OTP by design.

[0004] The OTP memory implemented as OTP by decision is capable of performing an erase operation by design, but the erase operation is blocked by software. Therefore, the OTP memory implemented as OTP by decision can be programmed and erased during testing, and the erase operation can be disabled during normal operation.

[0005] An OTP memory implemented as an OTP by design (also referred to as a real OTP or ROTP) is an OTP memory that cannot perform an erase operation by design. An example of an ROTP is a fuse array.

[0006] A secure system, such as a secure microcontroller, typically requires an ROTP array for, for example, storing sensitive data. A conventional method of implementing such an ROTP array is to use a fuse array. For example, a secure system may include an OTP array that includes a fuse array, wherein each fuse of the fuse array corresponds to a bit of the OTP array.

[0007] A popular fuse used to implement a fuse array is the so-called polymer fuse (poly fuse). Polymer fuses are usually manufactured to have a conductive trace between two terminals. The programming operation is achieved by injecting a high current into the polymer fuse, which causes the conductive trace to melt and result in a non-conductive state between the two terminals. By checking whether the polymer fuse is conductive or non-conductive, it can be determined whether the bit stored in the polymer fuse is a logical 1 (e.g., a short circuit) or a logical 0 (e.g., an open circuit).

[0008] Once the polymer fuse is non-conductive, the operation cannot be reversed (it is not possible to convert a non-conductive trace to a conductive trace). Therefore, after programming the polymer fuse, an erase operation is not possible. Summary of the invention

[0009] According to an embodiment, a method of operating a memory may include: receiving a first programming bit address, the first programming bit address being associated with a first plurality of redundant bit addresses, wherein the first programming bit address is associated with a first transistor-based memory cell, and wherein the first plurality of redundant bit addresses are each associated with a corresponding transistor-based memory cell; providing a programming pulse to a first word line coupled to the first transistor-based memory cell to write a first write value to the first transistor-based memory cell; reading a first bit value from the first transistor-based memory cell via a first bit line; reading redundant bit values ​​from the transistor-based memory cell associated with the first plurality of redundant bit addresses via corresponding bit lines; determining a majority bit value based on the first bit value and the redundant bit value read from the transistor-based memory cell associated with the first plurality of redundant bit addresses when one of the first bit value and the redundant bit value does not match the first write value; and asserting a flag signal indicating failure to program the first programming bit address to the first write value when the majority bit value does not match the first write value. According to an embodiment, a circuit may include: a plurality of transistor-based memory cells arranged in rows and columns, each transistor-based memory cell including a first bitline terminal and a second bitline terminal coupled to an associated bitline of a plurality of bitlines, and a gate terminal coupled to an associated wordline of a plurality of wordlines, wherein each wordline of the plurality of wordlines is coupled to the gate terminal of the transistor-based memory cell of the associated row; and a controller configured to: provide a programming pulse to a first wordline coupled to a first transistor-based memory cell of the plurality of transistor-based memory cells to write a first write value to the first transistor-based memory cell, causing a first bit value to be read from a first transistor-based memory cell via a first bit line, causing a redundant bit value to be read from a redundant transistor-based memory cell among a plurality of transistor-based memory cells, wherein the redundant transistor-based memory cell is configured to store the same value as the first transistor-based memory cell, determining a majority bit value based on the first bit value and the redundant bit value read from the redundant transistor-based memory cell when one of the first bit value and the redundant bit value does not match a first written value, and causing a flag signal indicating a failure to program the first transistor-based memory cell to the first written value to be asserted when the majority bit value does not match the first written value.

[0010] According to an embodiment, a nonvolatile memory may include: a one-time programmable (OTP) sector including a first plurality of transistor-based memory cells arranged in rows and columns, each of the first plurality of transistor-based memory cells including a first bit line terminal and a second bit line terminal coupled to an associated bit line of a first plurality of bit lines and a gate terminal coupled to an associated word line of a first plurality of word lines; and a non-OTP sector including a second plurality of transistor-based memory cells arranged in rows and columns, each of the second plurality of transistor-based memory cells including a first bit line terminal and a second bit line terminal coupled to an associated word line of a first plurality of word lines. The memory cells of the first and second word lines are configured to receive a first positive voltage during a read mode, a second positive voltage during a write mode, and a first negative voltage during an erase mode; wherein the first and second word lines are configured to receive a third positive voltage during a read mode and a fourth positive voltage during a write mode, wherein the first and second word lines are designed not to receive a negative voltage during any mode; and wherein the transistor-based memory cells of the OTP sector and the transistor-based memory cells of the non-OTP sector are of the same type. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] For a more complete understanding of the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 shows a portion of a transistor-based memory cell array according to an embodiment of the present invention;

[0013] Figure 2 A method for testing an embodiment of the present invention is shown. Figure 1 A flowchart of a method for implementing a memory cell array;

[0014] Figure 3 The embodiment according to the present invention is shown. Figure 1 The voltage associated with the memory cell array and Figure 1 distribution of memory cells in a first state and a second state;

[0015] Figure 4 shows a portion of a transistor-based OTP memory cell array according to an embodiment of the present invention;

[0016] Figure 5 The embodiment according to the present invention is shown. Figure 4 The voltage associated with the memory cell array and Figure 4 distribution of memory cells in a first state and a second state;

[0017] Figure 6 The embodiment of the present invention is shown Figure 4 A simplified top view of the layout of the OTP memory cell array;

[0018] Figure 7 A method for obtaining a Figure 4 A flowchart of a method for implementing an OTP memory cell array read bit;

[0019] Figure 8 A method for programming data to a Figure 4 A flowchart of a method for implementing an OTP memory cell array;

[0020] Fig. 9 A schematic diagram showing a secure integrated circuit (IC) according to an embodiment of the present invention;

[0021] Fig.10 A schematic diagram showing a secure IC according to an embodiment of the present invention; and

[0022] Fig.11 A method for preventing the Figure 4 A flowchart of a method for erasing an OTP memory cell array.

[0023] Corresponding reference numerals in the different figures generally refer to corresponding parts unless otherwise indicated.The figures are drawn to clearly illustrate the relevant aspects of the preferred embodiments and are not necessarily drawn to scale. DETAILED DESCRIPTION

[0024] The manufacture and use of the disclosed embodiments are discussed in detail below. However, it should be understood that the present invention provides many applicable inventive concepts that can be implemented in a variety of specific contexts. The specific embodiments discussed only illustrate specific ways to implement and use the present invention and do not limit the scope of the present invention.

[0025] The following description shows various specific details to provide a deep understanding of several example embodiments according to this specification. Embodiments can be obtained without one or more of these specific details or in the case of other methods, components, materials, etc. In other cases, known structures, materials or operations are not shown or described in detail to avoid blurring the different aspects of the embodiments. References to "embodiments" in this specification indicate that a specific configuration, structure or feature described in the embodiment is included in at least one embodiment. Therefore, phrases such as "in one embodiment" that may appear in different places in this specification do not necessarily refer to the same embodiment completely. In addition, in one or more embodiments, specific configurations, structures or features can be combined in any appropriate manner.

[0026] Embodiments of the invention will be described in a specific context, for example, an OTP array implemented with NOR-based multi-bit memory cells, for example as part of a larger NVM including non-OTP bits, and for example as part of a secure system (such as a secure SoC), such as a secure microcontroller or a secure stand-alone memory (e.g., including an OTP portion and a non-OTP portion). Embodiments of the invention may be implemented with other types of transistor-based memory cells, such as NAND-based memory cells and / or single-bit memory cells. Some embodiments may be implemented as stand-alone OTP memories. Some embodiments may be implemented in non-secure ICs.

[0027] The physical size of a fuse (such as a polymer fuse) is relatively large (eg, about 10 μm). 2 ), and some manufacturing node technologies may not include designs for fuse cells.

[0028] In an embodiment of the present invention, an OTP array is implemented using transistor-based memory cells (such as NOR memory cells). Data invariance is achieved in the OTP array by preventing (e.g., by design) the application of erase pulses (e.g., physically preventing negative voltages from being applied to the gates of the memory cells). Using transistor-based memory cells to implement the OTP array can advantageously result in a smaller OTP implementation (e.g., more than 1000 times smaller than a similarly sized fuse array), and can advantageously enable manufacturing node technologies that lack designs for fuse cells to implement the OTP array.

[0029] Figure 1 FIG. 1 shows a portion of a transistor-based (non-OTP) memory cell array 100 according to an embodiment of the present invention. The memory cell array 100 includes a plurality of nonvolatile memory cells 102 arranged in rows and columns. Figure 1As shown, each memory cell 102 has two conductive terminals, each coupled to a corresponding bit line BL, and a control terminal coupled to a word line WL. In some embodiments, such as embodiments where the memory cell 102 is implemented as a multi-bit memory cell, the two bit lines (e.g., BL) connected to the terminals of the memory cell 102 are connected to the control terminal of the memory cell 102. i and BL i+1 ) can operate as a drain line and a source line, respectively, during a read operation, and as a source line and a drain line, respectively, during a program operation. Thus, in some embodiments, each bit line BL can act as a source line or a drain line, depending on the mode of operation, and depending on which cell 102 and, in some embodiments, which bit within the cell 102 is being read / written (e.g., to the left of the bit line BL or to the right of the bit line BL). In other embodiments, such as in some embodiments where the memory cell 102 is implemented as a single bit memory cell, the two bit lines (e.g., BL ) connected to the terminals of the memory cell 102 may be connected to the terminals of the memory cell 102. i and BL i+1 ) can operate as a source line and a drain line, respectively, regardless of the operating mode (e.g., during reading or writing).

[0030] The following description refers to unit 102 i,j , which is coupled to the word line WL j The control terminal is coupled to the bit line BL i The left terminal is coupled to the bit line BL i+1 right terminal.

[0031] During a read operation, the gate of the memory cell 102 may be biased with a positive voltage (eg, 5V) (eg, using the associated word line WL j ), the bit line BL of the memory cell 102 i+1 The bit line BL can be biased with a small positive voltage (eg, 1.5V) and i The bit line BL may be biased with a low voltage, such as ground. In another embodiment, during a read operation, the bit line BL i and BL i+1 The voltage bias of the memory cell 102 may be reversed. To determine the value stored in the memory cell 102, a sense amplifier (not shown) coupled to the corresponding bit line BL compares the current flowing through the corresponding bit line BL to a current threshold in a known manner; a current below the threshold corresponds to a first state or programmed state (e.g., assigned a logical 0), and a current above the threshold corresponds to a second state or erased state (e.g., assigned a logical 1). In an alternative embodiment, the assigned logical values ​​("0" and "1") may be reversed.

[0032] In some implementations, for example, to mitigate aging caused by multiple programming of the memory cell 102, the current threshold is adaptively changed to track aging changes.

[0033] During a programming (writing) operation, the gate of the memory cell 102 may be biased with a relatively high positive voltage (eg, 9V) (eg, using the associated word line WL j ), bit line BL i The bit line BL can be biased with a relatively high positive voltage (eg, 5V) and i+1 The bit line BL may be at a lower voltage (eg, between 0V and 2V). Under such conditions, the memory cell 102 is programmed to the first state (eg, logic 0). i and BL i+1 The voltage bias of may be reversed to program the memory cell 102 to the first state.

[0034] During an erase operation, the gate of the memory cell 102 may be biased with a negative voltage (eg, −7 V) (eg, using the associated word line WL j ), bit line BL i can be biased with a positive voltage (eg, 5V), and the bit line BL i+1 The bit line BL may be left floating or biased to a weak positive voltage (e.g., less than 5V). Under such conditions, the memory cell 102 is erased to the second state (e.g., logic 1). In another embodiment, the bit line BL i and BL i+1 The voltage bias of may be reversed to erase the memory cell 102 to a second state.

[0035] In some implementations, the voltages applied to the gate, drain, and source of memory cell 102 for reading, programming, and erasing of memory cell 102 may vary depending on the specific manufacturing node and design.

[0036] In some embodiments, each memory cell 102 includes a charge trapping material 104 for storing one or more bits. For example, in some embodiments, the charge trapping material 104 includes a non-conductive material, such as silicon nitride, and is capable of storing 2 bits per memory cell 102. An example of such a multi-bit memory cell is the MirrorBit manufactured by Infineon Technologies. TM Memory Device / Array. In some implementations, each memory cell 102 stores a single bit. Other implementations are possible.

[0037] although Figure 1Only nine memory cells 102 are shown in FIG. 1 , but it should be understood that the memory cell array 100 may include more than nine memory cells 102 , such as hundreds, thousands, or millions (or more) of memory cells 102 .

[0038] Figure 2 A flow chart of an implementation method 200 for testing a memory cell array 100 according to an embodiment of the present invention is shown. The method 200 may be performed for each memory cell 102 of the memory cell array 100.

[0039] During step 202, memory cell 102 is programmed to a first state (eg, logic 0). For example, in some embodiments, a programming pulse (eg, gate voltage of 9V, bit line BL i The voltage at the bit line BL is set to a high positive voltage (eg, 3V to 5V), and the bit line BL i+1 The voltage at V is set to a lower voltage (eg, 0V to 2V). During step 206, the program verification voltage V PV is used as the gate voltage for performing a read operation, where the voltage V PV is higher in magnitude than the operational read voltage V applied to the gate of the memory cell 102 during a read operation. read ,like Figure 3 If the program verification fails, the bit line BL i The voltage at is set to the voltage of the next pulse (eg, an increased voltage or the same voltage) and new programming pulses are provided until the memory cell 102 is verified as successfully programmed (or until a maximum number of attempts is reached and the memory cell 102 is marked as inoperative).

[0040] After performing step 202, the memory cell 102 is erased to a second state (eg, logic 1) during step 212. For example, in some embodiments, an erase pulse (eg, gate voltage of -7V, BL i The voltage at 5V, and floating BL i+1 or bias BL i+1 During step 216, the erase verification voltage V EV is used as the gate voltage for performing a read operation, where the voltage V EV is lower in magnitude than the operating read voltage V read ,like Figure 3 If the erase verification fails, the bit line BL iThe voltage at is set for the next pulse (eg, increases or remains the same) and new erase pulses are provided until the memory cell 102 is verified as successfully erased (or until a maximum number of attempts is reached and the memory cell 102 is marked as inoperative).

[0041] In other embodiments, during the program, erase, verify and read operations in method 200, BL 1 and BL i+1 The voltage bias can be reversed.

[0042] In some embodiments, step 202 may be performed for programming data into memory cells 102 during normal operation. Similarly, in some embodiments, step 212 may be performed for erasing data from memory cells 102 during normal operation.

[0043] Figure 3 shows a voltage V according to an embodiment of the present invention EV 、V read and V PV , and the distribution of memory cells 102 in the first (304) state and the second (302) state.

[0044] In some embodiments, the native distribution of memory cells 102 (as they leave the factory) is represented by curve 302. Even if, for example, a substantial number of memory cells 102 initially fail the first read verify operation (step 216), as can be seen from curve 302 (where a substantial number of memory cells 102 are inherently above voltage V EV ), after several iterations of steps 214 and 216, such a memory cell 102 will also be successfully erased during step 212.

[0045] Also like Figure 3 As shown, during the read operation, the gate voltage V applied to the memory cell 102 is read The erase verification voltage V EV The programming verification voltage V PV between , thereby providing a safety margin to prevent incorrect readings.

[0046] like Figure 1 and Figure 2 As shown, the memory cell array 100 can be erased and is therefore not an OTP memory cell array. Figure 4 1 shows a transistor-based OTP memory cell array 400 according to an embodiment of the present invention. The memory cell array 400 includes a plurality of non-volatile memory cells 102 arranged in rows and columns. Figure 1 and Figure 4As can be seen in FIG. 2 , OTP memory cell array 400 can be implemented in a similar manner to memory cell array 100 and can be operated in a similar manner to memory cell array 100. However, OTP memory cell array 400 cannot receive a negative voltage in word line WL and therefore cannot be erased (step 212 cannot be performed). Therefore, memory cell array 400 is ROTP. As a result, method 200 cannot be applied to OTP memory cell array 400 (because once all memory cells in memory cell 102 of OTP memory cell array 400 are programmed for testing purposes, memory cell 102 of OTP memory cell array 400 cannot be erased and therefore cannot be used to store other data).

[0047] In an embodiment of the present invention, during a read operation of the memory cell 102 of the OTP memory cell array 400, the OTP read voltage V read_OTP is applied to the gate of the memory cell 102, where the OTP read voltage V read_OTP is higher than the read voltage V applied to the gate of the memory cell 102 of the memory cell array 100 during a read operation. read By using a higher read voltage V for the OTP memory cell array 400 than the read voltage for the memory cell array 100 read_OTP , some embodiments successfully use the native distribution of memory cells 102 during normal operation (without erasing memory cells 102 during testing).

[0048] In some embodiments, to program the memory cell 102 of the OTP memory cell array 400, a program verification voltage V ... PV High OTP programming verification voltage V PV_OTP To execute step 202.

[0049] Figure 5 shows a voltage V according to an embodiment of the present invention read_OTP and V PV_OTP , and the distribution of memory cells 102 in the first (304) state and the second (302) state. Figure 5 As shown, the voltage V read_OTP Higher than the voltage V read and can be compared with the voltage V 1_OTP (representing the upper limit of the native distribution 302) and the voltage V PV_OTP equidistant, thereby advantageously providing a safety margin to prevent incorrect readings.

[0050] In some embodiments, a portion of the OTP array is programmed during testing. By sacrificing a (e.g., relatively small) portion of the OTP array, some embodiments advantageously test the programmability of the OTP array and access to the OTP array. For example, in some embodiments, a portion of the OTP memory cell array 400 is programmed (e.g., programmed to a first state) to test access to all word lines and bit lines. By sacrificing a portion of the OTP memory cell array 400, some embodiments advantageously verify that all bit lines and word lines of the OTP memory cell array 400 have proper connectivity and are able to carry the expected current / voltage.

[0051] Figure 6 A simplified top view of the layout of an OTP memory cell array 400 is shown in accordance with an embodiment of the present invention.

[0052] like Figure 6 As shown, the OTP memory cell array 400 has P bit lines BL and Q word lines WL. In some implementations, P can be equal to or less than 1024 and Q can be between 128 and 512. Other values ​​can also be used.

[0053] During testing of the OTP memory cell array 400, a word line (eg, WL 1 ) and a bit line (e.g., BL 1 ) or cache line (e.g., CL 1 ) are programmed (e.g., using step 202, e.g., using V read_OTP and V PV_OTP Instead of V read and V PV ). If all the sacrificed memory cells are successfully programmed, the test of the OTP memory cell array 400 is considered successful because the connection paths to all word lines WL and all bit lines BL are verified.

[0054] In some embodiments, sacrificing a row and a column of the OTP memory cell array 400 advantageously indicates that it is appropriate to trade a small portion of the total capacity of the OTP memory cell array 400 for connection paths to all word lines WL and bit lines BL. For example, in an embodiment where P is equal to 128 and Q is equal to 1024, during testing of the OTP memory cell array 400, 1,151 memory cells of the 131,072 memory cells of the OTP memory cell array 400 are sacrificed.

[0055] In some implementations, during testing of the OTP memory cell array 400, more than one column and / or more than one row of memory cells 102 are sacrificed.

[0056] In some embodiments, the abnormal memory cell 102 of the OTP memory array 400 may have a voltage higher than V associated with the second state. 1_OTP Therefore, some memory cells 102 of the OTP memory array 400 are read using the OTP read voltage V read_OTP When reading, it is possible to read a logic 0 (first state) even though they have never been programmed.

[0057] In some embodiments, abnormal memory cells 102 may be more likely to appear around location 402, which represents the location of a via connecting a metal bit line to a buried bit line. In some embodiments, memory cells 102 that are close to (e.g., directly adjacent to) location 402 (e.g., coupled to a word line WL that is physically closest to location 402) are not used (sacrificed, such as never programmed and / or never read during normal operation), which can advantageously improve the reliability of the OTP memory cell array 400. In some embodiments, multiple locations 402 are found on each bit line BL (i.e., many locations 402 per bit line BL), for example, using physical periodicity.

[0058] In some implementations, read operations on the victim memory cell 102 may be prevented by software, such as by making the victim memory cell 102 non-addressable.

[0059] In an embodiment of the present invention, data is stored in the OTP memory cell array 400 in a redundant manner, and majority voting is used to determine the data stored in the OTP memory cell array 400 when reading the OTP memory cell array 400. By using redundancy and majority voting, some embodiments are advantageously able to reliably use an OTP memory cell array 400 having some defective or abnormal memory cells 102 (e.g., associated with manufacturing process defects) without having to perform method 200 to test the memory cells 102 of the OTP memory cell array 400.

[0060] In some embodiments, triple redundancy is used bit by bit for data stored in the OTP memory cell array 400. For example, in some embodiments, the same bit is stored in three different memory cells 102. In some embodiments, for example, to enhance immunity to cluster defects, the same bit is stored in three physically distant memory cells 102 (e.g., associated with physically distant different word lines WL and different bit lines BL). For example, in some embodiments, each of the bits is stored in a location associated with physically non-adjacent word lines and bit lines. For example, in some embodiments, three redundant bits associated with a single bit of data are stored in memory cells 102 associated with WL=1, BL=1; WL=3, BL=3; and WL=5, BL=5, respectively.

[0061] In some implementations, reading bits from the OTP memory cell array 400 includes using majority voting. Figure 7 A flow chart is shown of an implementation method 700 for reading bits from the OTP memory cell array 400 using majority voting according to an embodiment of the present invention.

[0062] During step 702, an address associated with a bit to be read is received.

[0063] During step 704, values ​​are read from all redundant locations. For example, in an embodiment using triple redundancy, a value is read from each of the three redundant memory cells 102. In some embodiments, reading the value of each bit includes: read_OTP , and comparing the resulting current from the associated bit line BL to a current threshold, wherein a current above the current threshold is interpreted as, for example, a logical 0, and a current below the current threshold is interpreted as, for example, a logical 1.

[0064] In some implementations, because the memory cells 102 of the OTP memory cell array 400 do not undergo multiple programming cycles, the current threshold used during step 704 is fixed and does not change over time (eg, does not track aging).

[0065] During step 706, reporting of the read bits is performed according to majority voting. For example, in some embodiments, reading a bit from the OTP memory cell array 400 includes reading from 3 redundant locations (during step 704) and reporting (during step 706) the state that received the most votes as the read bit. For example, if all of the 3 bits are read as logic 0, the read bit is reported as logic 0. If 2 bits are read as logic 0 and 1 bit is read as logic 1, the read bit is reported as logic 0. If 2 bits are read as logic 1 and 1 bit is read as logic 0, the read bit is reported as logic 1. If all of the 3 bits are read as logic 1, the read bit is reported as logic 1.

[0066] In some embodiments, an error correction code (ECC) is used to detect and correct errors. For example, in some embodiments, the ECC used is capable of correcting one or more errors in the value read (e.g., correcting clusters of read values, such as 128 bits). In some such embodiments, step 706 may be performed before performing the ECC step. In some embodiments, step 706 may be performed after performing the ECC step.

[0067] Figure 8 A flow chart illustrating an implementation method 800 for programming data to an OTP memory cell array 400 according to an embodiment of the present invention is shown. In some embodiments, the method 800 may be performed, for example, in the field.

[0068] During step 802, addresses of bits to be programmed to a first state (e.g., logic 0) are received. In some implementations, only addresses of bits expected to be in the first state (e.g., logic 0) are received during step 802, and addresses of bits expected to be in the second state (e.g., logic 1) are not received (because the associated memory cells 102 are expected to already be in the second state when they come from the factory).

[0069] During step 804, a write buffer is filled with all bits to be programmed to the first state. In some embodiments, the write buffer includes all redundant bit addresses associated with the bits to be programmed. In some embodiments, the write buffer includes additional bit addresses (e.g., bit addresses of other bits to be programmed, along with their corresponding redundant bit addresses).

[0070] As shown in steps 806, 808, 810, 812, 814, 816, and 818, each of the bits stored in the write buffer is attempted to be programmed until all bits are programmed (output "yes" from step 806) or until a bit fails to be programmed (output "no" from step 818). For the purpose of this description, it is assumed that the write buffer includes M bits.

[0071] During step 808, a programming pulse is provided to the OTP memory cell array 400 to attempt to program the kth bit (k is a number between 1 and M) of the write buffer. In some embodiments, step 202 is performed as part of step 808 using the OTP program verification voltage V PV_OTP Instead of V PV .

[0072] In some embodiments, multiple bits (eg, from a write buffer) are programmed simultaneously using the same programming pulse during step 808. For example, in some embodiments, during step 808, all redundant bits associated with the kth bit are programmed during the same programming pulse.

[0073] During step 810, it is determined whether programming of the kth bit is successful. For example, during step 810, the kth bit is read (eg, using a read voltage V read_OTP ). If the read bit matches the bit written to the kth bit during step 808, the output of step 810 is "yes". Otherwise, the output of step 810 is "no".

[0074] If the output of step 810 is "yes", step 806 is performed. Otherwise, if the output of step 810 is "no", and if the number of attempts to program the kth bit is less than the maximum number of attempts (determined during step 812), the drain voltage of the memory cell 102 associated with the kth bit is set for the next programming pulse during step 814. For example, in some embodiments, during step 814, the drain voltage V d The voltage is either raised (eg, by a predetermined amount) (eg, if the maximum drain voltage has not been reached), or left unchanged (eg, if the maximum drain voltage has been reached). After step 814, a new programming pulse is provided during step 808.

[0075] Otherwise, if the maximum number of programming attempts has been reached for the k-th bit (“yes” output from step 812 ), no further attempts are made to program the k-th bit, and step 816 is executed.

[0076] During step 816, a majority read is performed (e.g., using method 700). Once all redundant bits associated with the particular bit address received during step 802 have been attempted to be programmed, step 816 is performed. If the result from the majority read matches the value written (e.g., a logical 0), step 806 is performed. Otherwise (a "no" output from step 818), then programming has failed. In some embodiments, a signal is asserted when programming has failed, for example, to indicate programming failure. In some embodiments, such a signal is provided to, for example, an external controller.

[0077] In some implementations, bit redundancy and majority voting can advantageously improve the reliability of transistor-based OTP and can advantageously enable reliable use of an OTP array having process-defective memory cells 102 .

[0078] In some implementations, method 800 may be used that omits steps 816 and 818 (ie, programming fails when the output of step 812 is "yes") and uses V PV and V read Instead of V PV_OTP and V read_OTP To program the memory cell array 100 (eg, during step 202).

[0079] Fig. 9 A schematic diagram of a security IC 900 according to an embodiment of the present invention is shown. The IC 900 includes a positive voltage generator 902, a negative voltage generator 904, a controller 908, and an internal memory 906. The internal memory 906 includes a plurality of memory sectors. Some of the memory sectors may be implemented using corresponding memory cell arrays 100, and other memory sectors may be implemented using OTP memory cell arrays 400.

[0080] like Fig. 9 As shown, each of the memory sectors implemented using the memory cell array 100 can receive positive and negative voltages from the positive voltage generator 902 and the negative voltage generator 904, respectively, to be provided to the word line WL, for example, during write, erase, and read operations.

[0081] Also like Fig. 9 As shown, none of the memory sectors implemented using the OTP memory cell array 400 can receive a negative voltage from the negative voltage generator 904. As a result, the OTP memory cell array 400 does not receive bipolar power supplies and is physically unable (by design) to perform an erase operation.

[0082] In some embodiments, the read voltage V in the associated word line WL is used. readA read operation is performed on one of the non-OTP sectors implemented using the memory array 100 using a current threshold value (e.g., provided by the positive voltage generator 902) and used to determine the state (e.g., logic 0 or logic 1) of the associated memory cell 102, wherein the current threshold value is adaptive and changes to track the aging of the memory cell; and a read voltage V read_OTP (For example, provided by positive voltage generator 902 and higher than V read ) and a current threshold for determining a state (e.g., logic 0 or logic 1) of an associated memory cell 102 to perform a read operation on one of the OTP sectors implemented using the memory array 400, wherein the current threshold is fixed and does not change over time.

[0083] In some embodiments, the voltage V in the associated word line WL is used PV (eg, provided by positive voltage generator 902) to perform a write operation on one of the non-OTP sectors implemented using memory array 100, while using voltage V PV_OTP (For example, provided by positive voltage generator 902 and higher than V PV ) to perform a write operation on one of the OTP sectors implemented using the memory array 400.

[0084] In some embodiments, voltage generators 902 and 904 can be implemented in any manner known in the art.

[0085] In some embodiments, the internal memory 906 includes one or more OTP sectors (each implemented using the OTP memory cell array 400) and one or more non-OTP NVMs (each implemented using the memory cell array 100). In some embodiments, the internal memory 906 includes one or more OTP sectors but does not include non-OTP NVM sectors.

[0086] In some implementations, each of the memory cells 102 of the OTP sector and the non-OTP sector is implemented as a single bit memory cell.

[0087] In some embodiments, each memory cell in the OTP sector and the non-OTP sector memory cells 102 is implemented as a multi-bit memory cell. For example, in some embodiments, each memory cell in the OTP sector and the non-OTP sector memory cells 102 is implemented as a 2-bit memory cell, such as a MirrorBit TM , where a read operation on either the first or second bit of a 2-bit memory cell is performed by swapping the drain and source of the memory cell 102 in a known manner.

[0088] When using (for example, MirrorBit TM In some implementations of the memory cells 102 of the OTP sector that implement the multi-bit memory cells 102 of the non-OTP sector, all bits of the multi-bit cell are programmed (or not programmed) to have the same value, which can advantageously improve the reliability of the OTP memory cell because the current associated with a logic 0 and the current associated with a logic 1 can be further separated than when mixed values ​​(e.g., one logic 0 and one logic 1) are stored in the same multi-bit memory cell. In some such implementations, the bit of each memory cell in the non-OTP sector memory cells 102 can be treated as an independent bit and can therefore have different values.

[0089] When using (for example, MirrorBit TM In some embodiments of the memory cell 102 of the OTP sector implemented using a multi-bit memory cell of the type, each bit of the multi-bit memory cell is considered as an independent bit and can therefore have a different value from other bits of the same multi-bit memory cell, which can advantageously increase the storage capacity of the OTP sector.

[0090] In some embodiments, the controller 908 is configured to perform or cause performance of program, erase, and read operations for non-OTP memory sectors of the IC 900, and program and read operations for OTP memory sectors of the IC 900. In some embodiments, the controller 908 receives instructions from another controller (not shown), such as another controller external to the IC 900, e.g., via a communication interface, to perform program and / or read operations on OTP memory sectors of the IC 900.

[0091] In some embodiments, the controller 908 is implemented as a general or custom controller or processor, for example, configured to execute instructions from a memory. In some embodiments, the controller 908 includes a finite state machine (FSM). Other implementations are also possible.

[0092] In some implementations, the secure IC 900 is a standalone memory. In some implementations, the secure IC 900 is a secure SoC, such as a secure microcontroller.

[0093] In some implementations, the security IC 900 advantageously provides OTP functionality without the use of a polymer fuse array.

[0094] Fig.101 shows a schematic diagram of a security IC 1000 according to an embodiment of the present invention. IC 1000 operates in a similar manner to IC 900 and includes a positive voltage generator 902, a negative voltage generator 904, and an internal memory 906. However, IC 1000 has a similar or identical layout for all memory sectors in the memory sector (including memory sectors implemented using OTP memory cell array 400 and memory sectors implemented using memory cell array 100). Therefore, and as Fig.10 As shown, a memory sector implemented using the OTP memory cell array 400 is coupled to a negative voltage generator 904 in a manner similar to a memory sector implemented using the memory cell array 100 .

[0095] IC 1000 also includes a controller 1008 instead of controller 908. In some embodiments, controller 1008 is implemented and operates in a similar manner as controller 908. However, when OTP memory cell array 400 is accessed (e.g., for a read or write operation), controller 1008 prevents memory cells 102 located in a memory sector implemented using OTP memory cell array 400 from being erased by forcing the voltage at the output of negative voltage generator 904 to change from a negative voltage to 0V. For example, Fig.11 A flow chart of an implementation method 1100 for preventing erasure of the OTP memory cell array 400 according to an embodiment of the present invention is shown. In some embodiments, the controller 1008 can implement the method 1100 .

[0096] During step 1102, a memory address (e.g., of internal memory 906) to be accessed (e.g., for reading or writing) is received (e.g., by controller 1008). If it is determined during step 1104 that the received memory address is associated with OTP memory cell array 400 ("yes" output from step 1104), then the output of the negative voltage generator (e.g., 904) is set to a non-erased voltage (i.e., a voltage that does not cause memory cell 102 to be erased, such as 0V) (during step 1108). Otherwise, if the received memory address is associated with a non-OTP memory cell (e.g., 100), then the output of the negative voltage generator 904 is set to a target voltage, such as -7V, during step 1106.

[0097] In some implementations, the controller 1008 implements the method 1100 by design (ie, cannot be modified by software) such that the OTP memory cell array 400 is ROTP.

[0098] Example embodiments of the present invention are summarized here. Other embodiments may also be understood based on the entire specification and claims submitted.

[0099] Example implementations of the present disclosure are summarized here. Other implementations are also possible based on the entire specification and claims submitted.

[0100] Example 1. A method comprising: receiving a first programming bit address, the first programming bit address being associated with a first plurality of redundant bit addresses, wherein the first programming bit address is associated with a first transistor-based memory cell, and wherein the first plurality of redundant bit addresses are each associated with a corresponding transistor-based memory cell; providing a programming pulse to a first word line coupled to the first transistor-based memory cell to write a first write value to the first transistor-based memory cell; reading a first bit value from the first transistor-based memory cell via a first bit line; reading redundant bit values ​​from transistor-based memory cells associated with the first plurality of redundant bit addresses via corresponding bit lines; determining a majority bit value based on the first bit value and the redundant bit values ​​read from the transistor-based memory cells associated with the first plurality of redundant bit addresses when one of the first bit value and the redundant bit value does not match the first write value; and asserting a flag signal indicating a failure to program the first programming bit address to the first write value when the majority bit value does not match the first write value.

[0101] Example 2. The method of Example 1, wherein providing a programming pulse to the first word line comprises providing a first positive voltage to the first word line, wherein the first word line is unable to receive a negative voltage.

[0102] Example 3. A method according to Example 1 or 2, wherein each of the transistor-based memory cells associated with the redundant bit address is coupled to a corresponding word line, the method further comprising: when the first bit value and one of the redundant bit values ​​do not match the first write value, providing an additional programming pulse to the word line associated with the first bit value and one of the redundant bit values, and wherein determining the majority bit value includes determining the majority bit value after providing the additional programming pulse.

[0103] Example 4. A method according to Examples 1 to 3, wherein the first transistor-based memory cell and the transistor-based memory cells associated with the first plurality of redundant bit addresses are part of a one-time programmable (OTP) memory array, the method further comprising testing the OTP memory array by programming a first row and a first column of the OTP memory array to a first write value.

[0104] Example 5. The method of Examples 1 and 4, further comprising preventing a read operation on a first row and a first column of the OTP memory array.

[0105] Example 6. A method according to Examples 1 to 5, wherein the first transistor-based memory cell and the transistor-based memory cells associated with the first plurality of redundant bit addresses are part of a one-time programmable (OTP) memory array sector of a memory, the memory also including a non-OTP memory array sector, the method also including reading a second bit value from the transistor-based memory cell of the non-OTP memory array sector by comparing a current from an associated bit line of the non-OTP memory array sector to an adaptive current threshold, wherein reading the first bit value from the first transistor-based memory cell via the first bit line includes comparing the current from the first bit line to a fixed current threshold.

[0106] Example 7. A method according to Examples 1 to 6, wherein the first transistor-based memory cell and the transistor-based memory cells associated with the first plurality of redundant bit addresses are part of a one-time programmable (OTP) memory array sector of a memory, the memory also including a non-OTP memory array sector, the method also including programming a second bit value to a second transistor-based memory cell by providing a first programming voltage to a second word line associated with a second transistor-based memory cell of the non-OTP memory array sector, wherein providing the programming pulse to the first word line includes providing a second programming voltage that is higher than the first programming voltage.

[0107] Example 8. A method according to Examples 1 to 7, wherein the first transistor-based memory cell and the transistor-based memory cells associated with the first plurality of redundant bit addresses are part of a one-time programmable (OTP) memory array sector of a memory, the memory also including a non-OTP memory array sector, the method also including reading a second bit value from a second transistor-based memory cell by providing a first read voltage to a second word line associated with a second transistor-based memory cell of the non-OTP memory array sector, wherein reading the first bit value from the first transistor-based memory cell includes providing a second read voltage to the first transistor-based memory cell that is higher than the first read voltage.

[0108] Example 9. The method of Examples 1-8, wherein each of the transistor-based memory cells associated with the first programming bit address and the first plurality of redundant bit addresses is a multi-bit memory cell.

[0109] Example 10. The method according to Examples 1 to 9 further includes: receiving a plurality of additional programming bit addresses, wherein each of the plurality of additional programming bit addresses is associated with a corresponding multi-bit transistor-based memory cell; and programming each of the multi-bit transistor-based memory cells associated with the plurality of additional programming bit addresses to a first write value, wherein, after programming each of the multi-bit transistor-based memory cells in the multi-bit transistor-based memory cells, each of the bits of each of the multi-bit transistor-based memory cells in the multi-bit transistor-based memory cells is programmed to the first write value.

[0110] Example 11. The method of Examples 1 to 10, wherein the first written value corresponds to a logical zero.

[0111] Example 12. A method according to Examples 1 to 11, wherein the first transistor-based memory cell and the transistor-based memory cells associated with the first plurality of redundant bit addresses are part of a one-time programmable (OTP) memory array sector of a memory, the memory also including a non-OTP memory array sector, the method further comprising: receiving a memory address; setting the output of the negative voltage generator to a target negative voltage when the memory address corresponds to a memory cell of the OTP memory array; and setting the output of the negative voltage generator to a non-erased voltage different from the target negative voltage when the memory address corresponds to a memory cell of the OTP memory array.

[0112] Example 13. The method of Examples 1 to 11, wherein the non-erasing voltage is equal to 0V.

[0113] Example 14. A circuit comprising: a plurality of transistor-based memory cells arranged in rows and columns, each transistor-based memory cell comprising a first bitline terminal and a second bitline terminal coupled to an associated bitline of a plurality of bitlines, and a gate terminal coupled to an associated wordline of a plurality of wordlines, wherein each wordline of the plurality of wordlines is coupled to the gate terminal of the transistor-based memory cell of the associated row; and a controller configured to: provide a programming pulse to a first wordline coupled to a first transistor-based memory cell of the plurality of transistor-based memory cells to write a first write value to the first transistor-based memory cell, such that A first bit value is read from a first transistor-based memory cell via a first bit line, such that a redundant bit value is read from a redundant transistor-based memory cell among a plurality of transistor-based memory cells, wherein the redundant transistor-based memory cell is configured to: store the same value as the first transistor-based memory cell when one of the first bit value and the redundant bit value does not match a first written value, determine a majority bit value based on the first bit value and the redundant bit value read from the redundant transistor-based memory cell, and assert a flag signal indicating a failure to program the first transistor-based memory cell to the first written value when the majority bit value does not match the first written value.

[0114] Example 15. The circuit of Example 14, wherein each transistor-based memory cell of the plurality of transistor-based memory cells comprises a charge-trapping material, the charge-trapping material comprising a non-conductive material.

[0115] Example 16. The circuit of Examples 14-15, wherein the non-conductive material comprises silicon nitride.

[0116] Example 17. The circuit of Examples 14 to 16, wherein each transistor-based memory cell of the plurality of transistor-based memory cells is configured to store a single bit of data.

[0117] Example 18. The circuit of Examples 14 to 17, wherein each transistor-based memory cell of the plurality of transistor-based memory cells is configured to store a plurality of bits of data.

[0118] Example 19. The circuit of Examples 14 and 17-18, wherein each bit of the plurality of bits of the first transistor-based memory cell matches the first written value.

[0119] Example 20. The circuit of Examples 14 to 19, wherein a row of transistor-based memory cells and a column of transistor-based memory cells are programmed to a first written value.

[0120] Example 21. The circuit of Examples 14 to 20, wherein the first transistor-based memory cell and the redundant transistor-based memory cell are each coupled to a different word line and a different bit line.

[0121] Example 22. A nonvolatile memory comprising: a one-time programmable (OTP) sector comprising a first plurality of transistor-based memory cells arranged in rows and columns, each of the first plurality of transistor-based memory cells comprising a first bitline terminal and a second bitline terminal coupled to an associated bitline of a first plurality of bitlines and a gate terminal coupled to an associated wordline of a first plurality of wordlines; and a non-OTP sector comprising a second plurality of transistor-based memory cells arranged in rows and columns, each of the second plurality of transistor-based memory cells comprising a first bitline terminal and a second bitline terminal coupled to an associated wordline of a first plurality of wordlines a first bit line terminal and a second bit line terminal of an associated bit line of the OTP sector and a gate terminal coupled to an associated word line of a second plurality of word lines; wherein the second plurality of word lines are configured to receive a first positive voltage during a read mode, a second positive voltage during a write mode, and a first negative voltage during an erase mode; wherein the first plurality of word lines are configured to receive a third positive voltage during a read mode and a fourth positive voltage during a write mode, wherein the first plurality of word lines are designed not to receive a negative voltage during any mode; and wherein the transistor-based memory cells of the OTP sector and the transistor-based memory cells of the non-OTP sector are of the same type.

[0122] Example 23. The nonvolatile memory of Example 22, wherein the nonvolatile memory does not require a polymer fuse array.

[0123] Example 24. The nonvolatile memory of Examples 22 to 23, wherein the third positive voltage is higher than the first positive voltage, and wherein the fourth positive voltage is higher than the second positive voltage.

[0124] Although the present invention has been described with reference to illustrative embodiments, this description is not intended to be interpreted in a limiting sense. After reference to this specification, various modifications and combinations of the illustrative embodiments and other embodiments of the present invention will be apparent to those skilled in the art. Therefore, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. A method comprising: receiving a first programming bit address, the first programming bit address being associated with a first plurality of redundant bit addresses, wherein the first programming bit address is associated with a first transistor-based memory cell, and wherein the first plurality of redundant bit addresses are each associated with a respective transistor-based memory cell; providing a programming pulse to a first word line coupled to the first transistor-based memory cell to write a first write value to the first transistor-based memory cell; reading a first bit value from the first transistor-based memory cell via a first bit line; reading redundant bit values ​​from transistor-based memory cells associated with the first plurality of redundant bit addresses via corresponding bit lines; determining a majority bit value based on the first bit value and redundant bit values ​​read from transistor-based memory cells associated with the first plurality of redundant bit addresses when one of the first bit value and the redundant bit value does not match the first written value; and When the majority bit value does not match the first write value, a flag signal indicating failure to program the first program bit address to the first write value is asserted.

2. The method according to claim 1, wherein: Providing a programming pulse to the first word line includes providing a first positive voltage to the first word line, wherein the first word line is unable to receive a negative voltage.

3. The method according to claim 1, wherein: Each of the transistor-based memory cells associated with the redundant bit address is coupled to a corresponding word line, the method further comprising: when the first bit value and one of the redundant bit values ​​do not match the first write value, providing an additional programming pulse to the word line associated with the one of the first bit value and the redundant bit value, and wherein determining the majority bit value comprises: determining the majority bit value after providing the additional programming pulse.

4. The method according to claim 1, wherein: The first transistor-based memory cell and the transistor-based memory cells associated with the first plurality of redundant bit addresses are part of a one-time programmable (OTP) memory array, and the method further includes testing the OTP memory array by programming a first row and a first column of the OTP memory array to the first write value. 5 . The method of claim 4 , further comprising preventing a read operation from a first row and a first column of the OTP memory array.

6. The method according to claim 1, wherein: The first transistor-based memory cell and transistor-based memory cells associated with the first plurality of redundant bit addresses are part of a one-time programmable (OTP) memory array sector of a memory, the memory also including a non-OTP memory array sector, the method further comprising: reading a second bit value from the transistor-based memory cell of the non-OTP memory array sector by comparing a current from an associated bit line of the non-OTP memory array sector to an adaptive current threshold, wherein reading the first bit value from the first transistor-based memory cell via the first bit line includes comparing the current from the first bit line to a fixed current threshold.

7. The method according to claim 1, wherein: The first transistor-based memory cell and the transistor-based memory cells associated with the first plurality of redundant bit addresses are part of a one-time programmable (OTP) memory array sector of a memory, the memory also including a non-OTP memory array sector, the method further comprising: programming a second bit value to a second transistor-based memory cell of the non-OTP memory array sector by providing a first programming voltage to a second word line associated with the second transistor-based memory cell, wherein providing a programming pulse to the first word line comprises: providing a second programming voltage that is higher than the first programming voltage.

8. The method according to claim 1, wherein: The first transistor-based memory cell and the transistor-based memory cells associated with the first plurality of redundant bit addresses are part of a one-time programmable (OTP) memory array sector of a memory, the memory also including a non-OTP memory array sector, the method further comprising: reading a second bit value from a second transistor-based memory cell of the non-OTP memory array sector by providing a first read voltage to a second word line associated with the second transistor-based memory cell, wherein reading the first bit value from the first transistor-based memory cell comprises: providing a second read voltage to the first transistor-based memory cell that is higher than the first read voltage.

9. The method according to claim 1, wherein: Each of the transistor-based memory cells associated with the first programming bit address and the first plurality of redundant bit addresses is a multi-bit memory cell.

10. The method according to claim 1, further comprising: receiving a plurality of additional programming bit addresses, wherein each of the plurality of additional programming bit addresses is associated with a corresponding multi-bit transistor-based memory cell; and Programming each of the multi-bit transistor-based memory cells associated with the plurality of additional programming bit addresses to the first write value, wherein, after programming each of the multi-bit transistor-based memory cells, each of the bits of each of the multi-bit transistor-based memory cells is programmed to the first write value.

11. The method according to claim 1, wherein: The first written value corresponds to a logic zero.

12. The method according to claim 1, wherein: The first transistor-based memory cell and transistor-based memory cells associated with the first plurality of redundant bit addresses are part of a one-time programmable (OTP) memory array sector of a memory, the memory also including a non-OTP memory array sector, the method further comprising: receiving a memory address; When the memory address corresponds to a memory cell of the OTP memory array, setting an output of a negative voltage generator to a target negative voltage; and When the memory address corresponds to a memory cell of the OTP memory array, the output of the negative voltage generator is set to a non-erasing voltage different from the target negative voltage.

13. The method according to claim 12, wherein: The non-erasing voltage is equal to 0V.

14. A circuit comprising: a plurality of transistor-based memory cells arranged in rows and columns, each transistor-based memory cell comprising a first bitline terminal and a second bitline terminal coupled to an associated bitline of a plurality of bitlines, and a gate terminal coupled to an associated wordline of a plurality of wordlines, wherein each wordline of the plurality of wordlines is coupled to a gate terminal of a transistor-based memory cell of an associated row; and A controller configured to: causing a programming pulse to be provided to a first word line coupled to a first transistor-based memory cell of the plurality of transistor-based memory cells to write a first write value to the first transistor-based memory cell, causing a first bit value to be read from the first transistor-based memory cell via a first bit line, causing a redundant bit value to be read from a redundant transistor-based memory cell of the plurality of transistor-based memory cells, wherein the redundant transistor-based memory cell is configured to store the same value as the first transistor-based memory cell, determining a majority bit value based on the first bit value and the redundant bit value read from the redundant transistor-based memory cell when one of the first bit value and the redundant bit value does not match the first written value, and When the majority bit value does not match the first written value, a flag signal indicating failure to program the first transistor-based memory cell to the first written value is asserted.

15. The circuit of claim 14, wherein: Each transistor-based memory cell of the plurality of transistor-based memory cells includes a charge-trapping material including a non-conductive material.

16. The circuit of claim 15, wherein: The non-conductive material includes silicon nitride.

17. The circuit of claim 14, wherein: Each transistor-based memory cell of the plurality of transistor-based memory cells is configured to store a single bit of data.

18. The circuit of claim 14, wherein: Each transistor-based memory cell of the plurality of transistor-based memory cells is configured to store a plurality of bits of data.

19. The circuit of claim 18, wherein: Each bit of the plurality of bits of the first transistor-based memory cell matches the first written value.

20. The circuit of claim 14, wherein: A row of transistor-based memory cells and a column of transistor-based memory cells are programmed to the first written value.

21. The circuit of claim 14, wherein: The first transistor-based memory cell and the redundant transistor-based memory cell are each coupled to a different word line and a different bit line.

22. A non-volatile memory comprising: a one-time programmable (OTP) sector comprising a first plurality of transistor-based memory cells arranged in rows and columns, each transistor-based memory cell of the first plurality of transistor-based memory cells comprising a first bitline terminal and a second bitline terminal coupled to an associated bitline of the first plurality of bitlines, and a gate terminal coupled to an associated wordline of the first plurality of wordlines; as well as a non-OTP sector comprising a second plurality of transistor-based memory cells arranged in rows and columns, each transistor-based memory cell of the second plurality of transistor-based memory cells comprising a first bitline terminal and a second bitline terminal coupled to an associated bitline of a second plurality of bitlines and a gate terminal coupled to an associated wordline of a second plurality of wordlines; wherein the second plurality of word lines are configured to receive a first positive voltage during a read mode, a second positive voltage during a write mode, and a first negative voltage during an erase mode; wherein the first plurality of word lines are configured to receive a third positive voltage during a read mode and a fourth positive voltage during a write mode, wherein the first plurality of word lines are designed not to receive a negative voltage during any mode; and Wherein, the transistor-based memory cells of the OTP sector and the transistor-based memory cells of the non-OTP sector are of the same type.

23. The nonvolatile memory according to claim 22, wherein: The non-volatile memory does not require a polymer fuse array.

24. The nonvolatile memory according to claim 22, wherein: The third positive voltage is higher than the first positive voltage, and wherein the fourth positive voltage is higher than the second positive voltage.

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