Control via doped back gate effect

Abstract

Methods and structures are presented for mitigating back-gating effects in radio frequency (RF) silicon-on-insulator (SOI) substrates, RF-SOI. According to an aspect, a first implant or junction is formed in a region of a trap-rich layer (TRL) of the RF-SOI beneath a first circuit / device to be protected. The first implant or junction is entirely contained within the TRL. A planar surface area of the first implant and / or junction entirely contains a projection of a planar surface area of the first circuit and / or device. The first implant or junction is biased via a through-BOX contact (TBC) that penetrates a BOX layer at a shallow trench isolation region formed in the RF-SOI. According to another aspect, a second implant or junction is formed in a region of the TRL beneath a second circuit / device. The first implant or junction and the second implant or junction are not connected and are separated by an undoped region of the TRL.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 336,920, filed April 29, 2022, concerning “BACK-GATE EFFECT CONTROL VIADOPING,” the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to semiconductor technology, and more specifically to methods and structures for back gate mitigation via dopant implantation in a silicon-on-radio frequency (RF) insulator (SOI) substrate. Background Technology

[0004] Figure 1A shows a cross-sectional view of an SOI substrate (100A) comprising a bulk (silicon) substrate (150) on which a thin silicon layer (Si, 110, also referred to as an SOI layer) is formed, covering an insulating BOX layer (120, e.g., SiO2). Circuits comprising devices (e.g., SOI transistors) (also referred to as SOI circuits) can be formed in and over the thin silicon layer (110) using methods and techniques known in the art. For example, Figure 1A shows two circuits (105a, 110a) and (105b, 110b) formed in and over corresponding thin silicon regions (110a) and (110b) of the thin silicon layer (110), such regions being isolated from each other and from other circuits via one or more shallow trench isolation (STI) regions (e.g., 115a, 115b, 115c). In some cases, the circuits (105a, 110a) and / or (105b, 110b) may include RF devices (e.g., transistors), the performance of which may be affected by the parasitic surface conduction (PSC) effect at the interface between the BOX layer (120) and the bulk substrate (150), which is known in the art, due to the capacitor-like configuration created by the SOI stack. As is known to those skilled in the art, PSC may be due to the fixed positive charge within the BOX layer (120) near the interface with the bulk substrate (150) attracting free (charge) carriers, thereby reducing the effective resistivity of the bulk substrate (150) and leading to increased losses and nonlinearity. As shown in the cross-sectional view of the SOI substrate (100B) (also referred to as the RF-SOI substrate) in Figure 1B, a trap-rich layer (130) is provided between the BOX layer and the bulk substrate (150). Due to the presence of the trap-rich layer (130) and the high resistivity (HR-Si) bulk substrate (150), the PSC effect can be reduced, and thus the performance of the RF device can be increased. As is known to those skilled in the art, the presence of a rich trap layer (130) can produce a rich trap effect, which includes trapping free charges (e.g., electrons, charge carriers) under the BOX layer (120), thereby preventing the flow of undesirable coupled currents that could generate signals to / between RF devices formed in the silicon thin layer (110) and between RF devices formed in the silicon thin layer (110).

[0005] In some cases, one or more of the two circuits (105a, 110a) or (105b, 110b) shown in FIG1B can operate at high voltages and / or include switching devices / transistors that can be used to turn on and off relatively high voltages at different time periods (e.g., asynchronously). Such high voltages can induce electric fields in the BOX layer (120) and the trap-rich layer (130) of FIG1B, which can be (e.g., capacitively) coupled to the bulk substrate (150). Therefore, and as is known to those skilled in the art, the bulk substrate (150) can operate as effectively as a parasitic gate electrode (often referred to as a "back gate"), which can affect the overall performance of the devices / transistors in the circuits (105, 110a) and / or (105b, 110b). As is known to those skilled in the art, the effects of such a back gate can include, for example, the effect on the leakage current of transistors formed in the silicon thin layer (110), the shift of the threshold voltage of the transistor, and / or the so-called "back channel" for turning on or off the transistor.

[0006] Methods and structures for mitigating / reducing back-gate effects in circuits and / or devices formed on an RF-SOI substrate (100B) similar to the RF-SOI substrate (100B) of FIG. 1B are described in accordance with the teachings of this disclosure. Summary of the Invention

[0007] According to a first aspect of this disclosure, a silicon-on-insulator (SOI) structure is proposed, comprising: an RF-SOI substrate including: a high resistivity silicon (HR-Si) substrate; a trap-rich layer covering the HR-Si substrate; a buried oxide (BOX) layer covering the trap-rich layer; and a thin silicon layer covering the BOX layer; a first circuit formed in a first silicon region of the thin silicon layer; and a first implantation in a region of the trap-rich layer directly below the first circuit, wherein the first implantation is configured to be biased using a first voltage based on the operating state of the first circuit.

[0008] According to a second aspect, a method for reducing the back-gate effect in a silicon-on-insulator (SOI) circuit is proposed, the method comprising: doping a region of a trap-rich layer located directly beneath the SOI circuit; reducing the resistivity of the region based on the doping, thereby increasing the charge transfer rate of the region; and biasing the region using a voltage based on the operating state of the SOI circuit, thereby reducing the back-gate effect in the SOI circuit, wherein the SOI circuit is formed on an RF-SOI substrate, the RF-SOI substrate comprising: a high-resistivity silicon (HR-Si) substrate; a trap-rich layer covering the HR-Si substrate; a buried oxide (BOX) layer covering the trap-rich layer; and a thin silicon layer covering the BOX layer.

[0009] Other aspects of this disclosure are provided in the specification, drawings and claims of this application. Attached Figure Description

[0010] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate one or more embodiments of this disclosure and, together with the description of exemplary embodiments, serve to illustrate the principles and implementation of this disclosure.

[0011] Figure 1A shows a cross-sectional view of two circuits formed on a prior art silicon-on-insulator (SOI) substrate.

[0012] Figure 1B shows a cross-sectional view of two circuits formed on a prior art radio frequency (RF) SOI (RF-SOI) substrate comprising a high resistivity substrate and a trap-rich layer.

[0013] Figure 2A A cross-sectional view of two circuits formed on an RF-SOI substrate according to an embodiment of the present disclosure is shown. The RF-SOI substrate includes implantation formed in a region of a trap-rich layer.

[0014] Figure 2B A cross-sectional view of two circuits formed on an RF-SOI substrate according to an embodiment of the present disclosure is shown. The RF-SOI substrate includes two implants formed in a partition region of a trap-rich layer.

[0015] Figure 2C It shows Figure 2B Top plan view of the two circuits.

[0016] Figure 3A A cross-sectional view of two circuits formed on an RF-SOI substrate according to an embodiment of the present disclosure is shown. The RF-SOI substrate includes two junctions formed in a partition region of a trap-rich layer.

[0017] Figure 3B It shows Figure 3A The equivalent circuit of the two junction regions.

[0018] Figure 3C A schematic diagram is shown of an embodiment of the present disclosure for biasing a doped region (310b) via a TBC (315b) that can also penetrate the BOX layer (120) at the STI region (115b).

[0019] Figure 4 This is a flowchart illustrating the steps of a method for reducing the back gate effect in silicon-on-insulator (SOI) circuits according to the present disclosure.

[0020] In the various figures, the same reference numerals and names indicate the same elements. Detailed Implementation

[0021] The teachings of this disclosure enable the mitigation of the back gate effect in the substrate (100B) of FIG. 1B by forming implantation regions and / or junction regions in the region of the rich trap layer (130) directly beneath the circuits (105a, 110a) and / or (105b, 110b). In other words, the implantation regions and / or junction regions according to this disclosure can be formed by n-type and / or p-type doping of the region of the rich trap layer (130) directly beneath the circuits (105a, 110a) and / or (105b, 110b).

[0022] The respective implantation regions and / or junction regions according to this disclosure can be completely contained / enclosed within the trap-rich layer (130). The respective implantation regions and / or junction regions according to this disclosure can be separated by undoped regions (laterally) of the trap-rich layer (130). Due to the inherent properties of the trap-rich layer (130) (e.g., via a sufficiently high trap density) to prevent (e.g., significantly reduce) electron / carrier mobility, such undoped regions of the trap-rich layer (130) may contribute to increased electrical isolation between the respective implantation regions and / or junction regions. The respective implantation regions and / or junction regions according to this disclosure can be separated from the HR-Si bulk substrate (150) by the undoped regions of the trap-rich layer (130).

[0023] The junction region according to this disclosure may include an n+ / p- type junction or a p+ / n- type junction. Other implementations and use cases may include any combination of lightly doped and / or heavily doped first-type implantation and opposite-type implantation that can form a junction interface. The type of junction may be based on the type of circuitry and / or device for preventing back-gate effects (e.g., the polarity of the device such as, for example, an N-MOS or P-MOS transistor), and / or on the polarity of the (high) voltage applied to the circuitry and / or device (e.g., positive or negative relative to a reference potential). According to an embodiment of this disclosure, the junction region includes an interface between two implantation regions of opposite polarities (n-type and p-type). According to an embodiment of this disclosure, one of the two implantation regions is formed in a well provided by the other implantation region. In other words, one of the two implantation regions targets a first depth range into the rich trap layer (130) close to the BOX layer (120), and the other implantation region targets a second depth range deeper than the first depth range (and therefore farther away from the BOX layer 120). Thus, the second implantation region surrounds the first implantation region at least within the rich trap layer (130).

[0024] According to embodiments of this disclosure, the injection region and / or junction region can be independently biased to control the potential in the region of the trap-rich layer (130) directly beneath the circuit. The biasing of the injection region and / or junction region according to this disclosure can be provided by one or more through-hole contacts (TBCs) that resistively couple the corresponding bias signal / voltage to the corresponding injection region and / or junction region. Such independent biasing allows for improvements in the performance of the corresponding circuit / device by eliminating / reducing the corresponding back-gate effect. Performance improvements may include, for example, improving the on-state conduction performance of devices in a first circuit while improving / reducing off-state current leakage of devices in a second circuit.

[0025] The teachings of this disclosure can be applied to any RF-SOI substrate including stacked layers (110, 120, 130, 150 of FIG. 1B), wherein the bulk substrate (150) is a high resistivity substrate (HR-Si) having a resistivity greater than / greater than 200 Ohm·cm (e.g., a typical resistivity value of 1000 Ohm·cm). The teachings of this disclosure can also be applied to deposited or implanted trap-rich layers (130). The deposited trap-rich layer (130) may include, for example, a layer of polycrystalline material, such as, for example, polycrystalline silicon, which can provide a sufficiently high trap (area) density. The implanted trap-rich layer (130) can comprise, for example, a layer formed in the bulk substrate (150) or the prefabricated SOI substrate (e.g., 100A in FIG. 1A, where 150 is HR-Si) by implanting a (trap) material (e.g., carbon, germanium, fluorine, xenon, neon) that penetrates the layered (crystalline) structure of the bulk substrate (150) or the prefabricated SOI substrate, which can similarly provide a sufficiently high trap density. The goal of such implantation is to create a sufficiently damaged layer or amorphous layer (e.g., without a crystalline structure) in the silicon directly beneath a BOX layer (e.g., 120 in FIG. 1B) containing a sufficiently high trap density.

[0026] As used herein, a trap-rich layer (e.g., 130) can be characterized by its “trap density” or the areal density of traps, expressed in terms of atoms per square centimeter (at / cm²). 2 Measurements are taken in units of 1 × E⁸ at / cm. According to this disclosure, the trap-rich layer has a value greater than 1 × E⁸ at / cm. 2 (that is, 10) 8 at / cm 2 The (intentionally, specifically, and deliberately induced) trap density. As is known to those skilled in the art, a typical prior art trap-rich layer may have a density as high as approximately 1 × E11 at / cm². 2 The trap density. Therefore, it is greater than 1×E8 at / cm. 2The trap density is high enough that the trap-rich layer (e.g., 130 in Figure 1B) can trap the aforementioned free charges (e.g., electrons, charge carriers), and thus reduce / eliminate the PSC effect under the BOX layer (120). In other words, the traps in the trap-rich layer can prevent the free charge carriers in the substrate from flowing to generate current, just as the free charge carriers would in the absence of traps.

[0027] It should be noted that although single-crystal (e.g., Si) bulk substrates, such as the HR-Si bulk substrate (150) of Figure 1B, may have inherent defects / impurities that can be compared to traps, the areal density of such defects can be higher than 1×E8 at / cm² of trap-rich layers / regions / materials. 2 The specified trap density is several orders of magnitude smaller. To maintain their desired semiconductor properties, the bulk substrate, including HR-Si bulk substrates (e.g., 150 in Figure 1B), must allow for carrier charge flow. Therefore, the (inherent) typical defects / impurities in such substrates can have approximately 1 × E6 at / cm². 2 Or a smaller areal density, or in other words, at least two orders of magnitude smaller than the areal density of the trap-rich layer (e.g., 130 in Figure 1B). Thus, although the HR-Si bulk substrate (150) and the trap-rich layer (130) in Figure 1B can have similar resistivity (e.g., greater than 200 Ohm·cm), they can be clearly distinguished, for example, by their respective trap densities.

[0028] Figure 2A Cross-sectional views of two circuits (105a, 110a) and (105b, 110b) formed on an RF-SOI substrate (100B) according to an embodiment of the present disclosure are shown. The RF-SOI substrate (100B) includes an implantation region (210a) formed in a trap-rich layer (130). Furthermore, as... Figure 2A As shown, the BOX contact (215a, TBC) can be used to provide (e.g., resistively coupled) a bias signal / voltage to the injection region (210a). Those skilled in the art will readily recognize that... Figure 2A The configuration with added implanted regions (210a) and TBCs (215a) described above with reference to FIG1B is shown in accordance with this teaching. Furthermore, those skilled in the art will readily recognize methods and techniques relating to the fabrication / formation of implanted regions (210a) (e.g., doped) and TBCs (215a) (e.g., via stacked metal vias through BOX layers), which are outside the scope of this disclosure.

[0029] Continue to refer to Figure 2AAccording to embodiments of this disclosure, the implantation region (210a) can be n+ type or p+ type. According to some exemplary embodiments of this disclosure, the type of implantation can be based on the voltage of the circuit (105a, 110a) and / or the polarity of the target transistor (to be protected). In some embodiments, biasing the implantation region (210a) via a bias voltage applied through the TBC (215a) can be intended to reduce the difference between the voltage in the silicon region (110a) of the circuit (105a, 110a) and the voltage at the (doped) region of the trap-rich layer (130) directly below the circuit (105a, 110a). In other words, the bias voltage applied through the TBC (215a) may not be static but may vary with the operating state (e.g., voltage) of the circuit (105a, 110a), which is characterized, for example, by the voltage of the circuit. Other implementations may include n-type or p-type or even n-type or p-type dopants for the implantation region (210a).

[0030] Further reference Figure 2A According to embodiments of this disclosure, the doped region of the implantation region (210a) for forming the rich trap layer (130) can be selected to be in a plane (perpendicular to) Figure 2A Extending from the observer's perspective, the plane includes the entire projection of the circuits (105a, 110a) onto the plane. In other words, according to an embodiment of this disclosure, the doped region of the formation implantation region (210a) of the rich trap layer (130) has a surface covering the entire coverage area of ​​the circuits (105a, 110a) above it. Refer to the description below. Figure 2C This will be further described / clarified.

[0031] like Figure 2A As shown, according to an embodiment of this disclosure, the TBC (215a) can penetrate the BOX layer (120) through an STI region (115a) that defines the boundary of the thin silicon region (110a) of the circuit (105a, 110a). As known to those skilled in the art, different circuits on a substrate (e.g., circuits (105a, 110a) and (105b, 110b) formed on an RF-SOI substrate (100B)) can be isolated from each other via STI regions (e.g., 115a, 115b, 115c). For example, as Figure 2A As shown, the STI region (115c) isolates the thin silicon region (110a) of circuits (105a, 110a) from the thin silicon region (110b) of circuits (105b, 110b). Furthermore, the STI regions (115a) and (115b) can respectively isolate the thin silicon regions (110a) and (110b) from the thin silicon regions (not shown) that can be formed on the RF-SOI substrate (100B). Figure 2A Other circuit isolations are shown in the diagram. Therefore, each circuit in (105a, 110a) and (105b, 110b) can be considered as isolated from surrounding circuits via walls of an STI region, which can effectively form an isolation island of the thin silicon region (e.g., 110a, 110b, etc.). Thus, the TBC (215a) can pass through any of the STI regions surrounding the thin silicon region (110a) (including, for example, STI region (115c)) to reach the implantation region (210a) and make (resistive) contact with it. Therefore, as... Figure 2A As shown, the lateral extension of the implanted region (210a) can reach an area of ​​a rich trap layer (130) disposed beneath an STI region (e.g., 115a, 155c), which defines an isolation island of thin silicon regions (110a) of the circuit (105a, 110a). It should be noted that in some embodiments, any one or more of the STI regions (115a, 115b, 115c) can penetrate the BOX layer (120) to contact the rich trap layer (130), or further penetrate the rich trap layer (130). Where the STI region (115c) can penetrate the rich trap layer (130) and the depth of the implanted regions (210a, 210b), increased isolation between subsequent implanted regions can be provided.

[0032] Continue to refer to Figure 2A According to this teaching, doping of a region (e.g., 210a) of the trap-rich layer (130) can alter the local electrical / semiconductor properties of that region. Specifically, doping of region (210a) may not affect the carrier mobility of the region compared to an undoped region of the trap-rich layer (130); instead, doping can increase the carrier density of region (210a) and thus reduce the resistivity of said region (e.g., to less than 200 Ohm·cm). Since the charge transfer performance (e.g., charge transfer rate) of region (e.g., 210a) can be a function of its carrier mobility and its carrier density (and the applied bias), the increased carrier density of the doped region (210a) and the therefore reduced resistivity of the doped region (210a) can increase the charge transfer performance / rate of said region. Therefore, for a bias voltage applied via TBC (215a), the doped region (210a) can be charged to the corresponding bias potential.

[0033] Such charging of the doped region (215a) can be performed at a sufficiently fast rate (e.g., in milliseconds, 10). -3s) This is done to mitigate / reduce the aforementioned back-gate effect. Furthermore, since the doped region (210a) is localized to the rich trap layer (130), as shown in FIG1B, the doped region (210a) is defined by an undoped rich trap region with very poor charge transfer performance (and a high resistivity greater than 200 Ohm·cm), and therefore leakage / circulation of moving charge / current from the doped region (210a) to the region of the rich trap layer (130) below the circuits (105b, 110b) can be controlled (e.g., reduced). Therefore, mitigating the back-gate effect in the circuits (105a, 110a) by applying a bias signal / voltage to the doped region (210a) of the rich trap layer (130) may not affect the operation of the circuits (105b, 110b).

[0034] Figure 2B Cross-sectional views of two circuits (105a, 110a) and (105b, 110b) formed on an RF-SOI substrate (100B) according to an embodiment of the present disclosure are shown. The RF-SOI substrate includes two implantation regions (210a) and (210b) formed in a trap-rich layer (130). Furthermore, as... Figure 2B As shown, BOX contacts (215a) and (215b) can be used to provide (e.g., resistively coupled) corresponding bias signals / voltages to injection regions (210a) and (210b). Those skilled in the art will readily recognize that... Figure 2B The above reference is shown. Figure 2A The description includes an injection region (210b) and a TBC (215b, which penetrates the BOX layer 120 through the STI region 115b) for mitigating / reducing the back-gate effect in the circuits (105b, 110b). Therefore, the above description of the elements (210a, 215a) for mitigating / reducing the back-gate effect in the circuits (105a, 110a) can be equally applied to the elements (210b, 215b) for mitigating / reducing the back-gate effect in the circuits (105b, 110b).

[0035] Continue to refer to Figure 2BBecause the two implanted regions (210a, 210b) are separated by undoped regions of the trap-rich layer (130), they can be charged / discharged independently without affecting each other. In other words, as described above, because the two doped regions (210a, 210b) are not connected, the undoped regions of the trap-rich layer (130) (e.g., in the lateral direction) that inherently have very poor charge transfer performance (and high resistivity greater than 200 Ohm·cm) between the two doped regions (210a, 210b) can prevent leakage of moving charge / current from the doped region (210a) to the doped region (210b) and vice versa. Therefore, mitigating the back-gate effect of either (105a, 110a) or (105b, 110b) may not affect the operation of the other circuit.

[0036] Figure 2C The above reference is shown. Figure 2B The top plan view of the two circuits (105a, 110a) and (105b, 110b) is shown. Figure 2C As shown, the main planar surface / region (shown as dashed lines) of each doped region (210a) or (210b) completely encompasses / covers / encloses the projection of the main planar surface / region of the corresponding circuit (105a, 110a) or (105b, 110b). Furthermore, as... Figure 2C As shown, each TBC in TBC (215a) or (215b) is connected by a corresponding STI region (e.g., Figure 2C The 115a or 115b (not shown) is spaced / isolated from the corresponding circuits (105a, 110a) or (105b, 110b) and (resistively) contacts the corresponding doped region (210a) or (210b). Therefore, as described above, the two doped regions (210a) and (210b) can be charged independently via bias signals / voltages applied to the corresponding TBCs (215a) and (215b). For example, during the on-state of the circuits (105a, 110a) including the high voltage at the circuit, a corresponding high voltage can be applied to the TBC (215a) to charge the doped region (210a) below the circuits (105a, 110a) to a high potential accordingly, protecting the circuits from back-gate effects. Meanwhile, the circuits (105b, 110b) can operate according to the off state including the low voltage at the circuit, and thus a corresponding low voltage can be applied to the TBC (215b) to charge the doped region (210b) below the circuits (105b, 110b) to a low potential accordingly, so as to protect the circuits from the back gate effect independently of the protection of the circuits (105a, 110a).

[0037] Figure 3AA cross-sectional view of two circuits (105a, 110a) and (105b, 110b) formed on an RF-SOI substrate (100B) according to an embodiment of the present disclosure is shown. The RF-SOI substrate includes two junction regions (210a, 310a) and (210b, 310b) formed in a trap-rich layer (130). Those skilled in the art will recognize that... Figure 3A The embodiments shown are based on the above references, for example Figure 2B The described implementation, where instead of using a single dopant (e.g., n+ or p+ type) to dope local regions of the trap-rich layer (130) beneath each of the circuits (105a, 110a) and (105b, 110b), uses two types of dopant to form the respective local junction regions (210a, 310a) and (210b, 310b). For example, referring to junction region (210a, 310a), it may include... Figure 2A or Figure 2B The doped region (210a) is similar to the top doped region (210a) and the bottom and adjacent doped region (310a), wherein both doped regions (210a) and (310a) can be doped regions of the rich trap layer (130) and are therefore completely covered within the rich trap layer (130).

[0038] Specifically, such as Figure 3A As shown, the top doped region (310a) can be formed in the well provided by the bottom doped region (310a), for example, to form the interface region of the junction (210a, 310a). In other words, the lateral extension of the bottom doped region (310a) completely covers the lateral extension of the top doped region (210a). Therefore, as Figure 3A As shown, the top doped region (210a) is laterally defined by the bottom doped region (310a). Therefore, the naming convention used herein (including both top and bottom when applied to doped regions (210a, 310a)) should not be interpreted as excluding such lateral definition / enclosure of the doped region (210a) by the doped region (310a), but rather as including such lateral definition / enclosure. Figure 3A The main lateral extensions / planes are arranged oppositely at the top or bottom. Additionally, as... Figure 3A As shown, the bottom doped region (310a) can be separated from the HR-Si bulk substrate (150) by the undoped region of the trap-rich layer (130). In other words, the junction regions (210a, 310a) are completely contained within the trap-rich layer (130).

[0039] Reference above Figure 3A The same description of the junction regions (210a, 310a) can be applied. Figure 3A The junction region (210b, 310b). Furthermore, as... Figure 3A As shown, the two junction regions (210a, 310a) and (210b, 310b) may not be connected, or in other words, they may be separated by undoped regions of the trap-rich layer (130), which have the same characteristics as those mentioned above. Figure 2B The benefits described by the separation of the doped regions (210a) and (210b) are similar.

[0040] According to an exemplary embodiment of this disclosure, junction regions (210a, 310a) and (210b, 310b) can each be formed by doping adjacent local regions of the trap-rich layer (130) with dopants of opposite polarity / type and / or different doping levels. For example, according to an embodiment of this disclosure, the doped region (210a) or (210b) can be n+ type (heavily doped region), while the doped region (310a) or (310b) can be p- type (lightly doped region). According to another exemplary embodiment of this disclosure, the doped region (210a) or (210b) can be p+ type (heavily doped region), while the doped region (310a) or (310b) can be n- type (lightly doped region). Depending on design goals and performance, other combinations of the types and / or doping levels of the two doped regions forming each junction region (210a, 310a) or (210b, 310b) are possible.

[0041] Figure 3B It shows the formation in Figure 3A The area marked (300A) Figure 3A The equivalent circuit (D) of the two junction regions (210a, 310a) and (210b, 310b) 10a R 130 D 10b Specifically, in Figure 3B The equivalent circuit shown is an exemplary use case where each of the two doped regions (210a) and (210b) is n+ type and each of the two doped regions (310a) and (310b) is p- type. Therefore, as... Figure 3B As shown, corresponding (back-to-back) diodes D are formed at the corresponding interfaces in the corresponding junction regions (210a, 310a) and (210b, 310b). 10a and D 10b diode D 10a and D 10b It is in the opposite direction, and the equivalent resistance R through the undoped region of the trap-rich layer (130) is... 130 Coupled to each other, the undoped region separates the junction regions (210a, 310a) from the junction regions (210b, 310b).

[0042] Figure 3B The equivalent circuit (D) 10a R 130 D 10b The effect of junction regions (210a, 310a) and (210b, 310b) on preventing current leakage between the two heavily doped regions (210a) and (210b) is clearly shown. At the first level, leakage can occur via a (high) resistance R. 130 For example, refer to the above Figure 2A or Figure 2B The method described is similar in that it prevents / reduces current leakage from either of the two doped regions (210a) and / or (210b). At the second level, leakage can be prevented via a (back-to-back) reverse diode D formed by the two junctions (210a, 310a) and (210b, 310b). 10a and D 10b This is to further prevent / reduce current leakage from either of the two doped regions (210a) and / or (210b). Therefore, Figure 3A The implementation method is relative to Figure 2B The advantage of this implementation method can be due to two levels of leakage prevention / reduction, when combined with... Figure 2B Compared to the previous configuration, this configuration can provide higher isolation efficiency between the two regions (210a) and (210b). As a result of this improvement in isolation efficiency, for a given isolation efficiency between the two doped regions (210a) and (210b), Figure 3A The configuration may be able to have a higher performance than Figure 2B The configuration requires low isolation efficiency (e.g., lower resistivity and / or lower trap density and therefore lower grade / cost) for rich trap layer (130) operation.

[0043] The bias of junction regions (210a, 310a) and / or (210b, 310b) can include, for example, according to the reference above. Figure 2A or Figure 2B The described apparatus (e.g., TBC 215a and / or 215b) biases the doped regions (210a) and / or (210b). Further flexibility in controlling the isolation between the two doped regions (210a) and (210b) can be provided by further biasing the two doped regions (310a) and / or (310b). Figure 3CThe present disclosure illustrates a non-limiting exemplary embodiment for biasing a doped region (310b) via a TBC (315b) that can also penetrate the BOX layer (120) at the STI region (115b). It should be noted that the TBC (315b) can penetrate the BOX layer (120) at different STI regions (e.g., at the STI region (115c) or other regions). The biasing of the two doped regions (210b) and (310b) of the junction (210b, 310b) can be achieved by biasing the equivalent diode formed by the junction (e.g.,...). Figure 3B D 10b To achieve better isolation, the two terminals (anode and cathode) are appropriately biased. Figure 3A The doped region (310a) provides an equivalent bias device.

[0044] It should be noted that any of the aforementioned doped regions and / or junction regions used to mitigate / reduce the back-gate effect of (SOI) circuits formed / fabricated on the RF-SOI substrate while providing leakage isolation can coexist on the same RF-SOI substrate. In other words, not all circuits formed / fabricated on the RF-SOI substrate can be protected against back-gate effects according to this teaching, and / or one or more such circuits can be protected by different protection schemes, including via a single doped region (e.g., Figure 2A The protection of 210a) via two doped regions forming the junction region (e.g., Figure 3A The protection of 210a and 310a) (where one of the doped regions is biased), or via two doped regions forming a junction region (e.g., Figure 3C The protection of 210b and 310b (where the two doped regions are biased).

[0045] Figure 4 This is a flowchart (400) illustrating the steps of a method for reducing the back-gate effect in silicon-on-insulator (SOI) circuits according to this disclosure. Figure 4 As shown, such steps include: according to step (410), doping the region of the trap-rich layer located directly below the SOI circuit; according to step (420), reducing the resistivity of the region based on the doping, thereby increasing the charge transfer rate of the region; and according to step (430), biasing the region using a voltage based on the operating state of the SOI circuit, thereby reducing the back-gate effect in the SOI circuit. In such a method, the SOI circuit can be formed on an RF-SOI substrate, which includes: a high-resistivity silicon (HR-Si) substrate; a trap-rich layer covering the HR-Si substrate; a buried oxide (BOX) layer covering the trap-rich layer; and a thin silicon layer covering the BOX layer.

[0046] As used herein, the term "MOSFET" includes any field-effect transistor (FET) having an insulated gate with conductivity that determines its voltage, and includes an insulated gate having a metallic or metalloid, insulator, and / or semiconductor structure. The terms "metal" or "metalloid" include at least one conductive material (e.g., aluminum, copper, or other metals, or highly doped polycrystalline silicon, graphene, or other conductors), "insulator" includes at least one insulating material (e.g., silicon oxide or other dielectric material), and "semiconductor" includes at least one semiconductor material.

[0047] As used in this disclosure, the term "radio frequency" (RF) refers to an oscillation rate in the range of about 3 kHz to about 300 GHz. The term also includes frequencies used in wireless communication systems. RF frequencies can be the frequencies of electromagnetic waves or the frequencies of alternating voltage or current in a circuit.

[0048] Various embodiments of the present invention can be implemented to meet various specifications. Unless otherwise stated above, the selection of appropriate component values ​​is a matter of design choice. Various embodiments of the present invention can be implemented using any suitable integrated circuit (IC) technology (including, but not limited to, MOSFET structures), or in hybrid or discrete circuit form. Integrated circuit embodiments can be fabricated using any suitable substrate and process (including, but not limited to, standard bulk silicon, high resistivity bulk CMOS, and silicon-on-insulator (SOI)). Unless otherwise stated above, embodiments of the present invention can be implemented using other transistor technologies such as bipolar, BiCMOS, LDMOS, BCD, GaAs HBT, GaN HEMT, GaAs pHEMT, and MESFET technologies. However, embodiments of the present invention are particularly useful when fabricated using SOI- or SOS-based processes or when fabricated using processes with similar characteristics. Fabrication in CMOS using SOI processes enables circuits to have low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high-frequency operation (i.e., radio frequency up to and exceeding 300 GHz). Since parasitic capacitance can usually be kept low (or minimized and uniform across all cells, thus allowing for compensation of parasitic capacitance) through careful design, monolithic IC implementations are particularly useful.

[0049] Depending on specific specifications and / or implementation technology (e.g., NMOS, PMOS, or CMOS, and enhancement-mode or depletion-mode transistor devices), voltage levels and / or voltage and / or logic signal polarity can be reversed. The voltage, current, and power handling capabilities of components can be adjusted as needed, for example, by adjusting device size, "stacking" components (especially FETs) in series to withstand greater voltages, and / or using multiple components in parallel to handle greater currents. Additional circuit components can be added to enhance the capabilities of the disclosed circuit and / or provide additional functionality without significantly altering its function.

[0050] The circuits and devices according to the invention can be used alone or in combination with other components, circuits, and devices. Embodiments of the invention can be manufactured as integrated circuits (ICs), which can be encapsulated in IC packages and / or modules to facilitate handling, manufacturing, and / or improve performance. Specifically, IC embodiments of the invention are typically used in modules in which one or more such ICs are combined with other circuit blocks (e.g., filters, amplifiers, passive components, and possibly additional ICs) into a package. The ICs and / or modules are then typically combined with other components typically on a printed circuit board to form part of an end product such as a cellular phone, laptop computer, or tablet computer, or to form a more advanced module that can be used in various products such as vehicles, test equipment, medical devices, etc. Through various configurations of modules and components, such ICs typically support communication modes, typically wireless communication.

[0051] Several embodiments of the present invention have been described. It should be understood that various modifications can be made without departing from the spirit and scope of the invention. For example, some of the steps described above may be order-independent and therefore may be performed in a different order than that described. Furthermore, some of the steps described above may be optional. The various activities described with respect to the methods identified above may be performed in a repetitive, serial, and / or parallel manner.

[0052] It should be understood that the foregoing description is intended to illustrate, not limit, the scope of the invention, which is defined by the scope of the appended claims, and other embodiments are within the scope of the claims. Specifically, the scope of the invention includes any and all possible combinations of one or more of the processes, machines, manufactures, or combinations of substances set forth in the appended claims. (Note that the bracket markings for the claim elements are for ease of reference and do not in themselves indicate a particular desired order or enumeration of the elements; furthermore, such markings may be reused in dependent claims as references to additional elements without being considered as a sequence of markings that initiates conflict.)

Claims

1. A silicon-on-insulator (SOI) structure, comprising: RF-SOI substrate, the RF-SOI substrate comprising: High resistivity silicon HR-Si substrate; A trap-rich layer superimposed on the HR-Si substrate; A buried oxide BOX layer superimposed on the trap-rich layer; and A thin silicon layer superimposed on the BOX layer; A first circuit, the first circuit being formed in a first silicon region of the thin silicon layer; and The first injection is in the region of the trap-rich layer located directly below the first circuit. in, The first injection is configured to be biased using a first voltage based on the operating state of the first circuit. The SOI structure also includes a second injection around the region of the first injection in the rich trap layer, and The interface between the first implantation and the second implantation forms a first junction, which is completely contained in the trap-rich layer and separated from the HR-Si substrate by the undoped region of the trap-rich layer.

2. The silicon-on-insulator (SOI) structure according to claim 1, wherein: The first node is a pn node.

3. The silicon-on-insulator (SOI) structure according to claim 1, wherein: The first injection is formed in the trap of the second injection.

4. The silicon-on-insulator (SOI) structure according to claim 1, wherein: The SOI structure also includes a first TBC (through-box contact). The first TBC penetrates the BOX layer at the first STI (shallow trench isolation) region to contact the first injection; The SOI structure also includes a second TBC (through-box contact), and The second TBC penetrates the BOX layer at the second STI (shallow trench isolation) region to contact the second injection.

5. The silicon-on-insulator (SOI) structure according to claim 4, wherein: The second STI (shallow trench isolation) region is the first STI (shallow trench isolation) region.

6. The silicon-on-insulator (SOI) structure according to claim 4, wherein: The second TBC resistor contacts the second injection to bias the second injection using a second voltage.

7. A silicon-on-insulator (SOI) structure, comprising: RF-SOI substrate, the RF-SOI substrate comprising: High resistivity silicon HR-Si substrate; A trap-rich layer superimposed on the HR-Si substrate; A buried oxide BOX layer superimposed on the trap-rich layer; and A thin silicon layer superimposed on the BOX layer; A first circuit, the first circuit being formed in a first silicon region of the thin silicon layer; and The first injection is in the region of the trap-rich layer located directly below the first circuit. in, The first injection is configured to be biased using a first voltage based on the operating state of the first circuit. The SOI structure also includes: A second circuit is formed in a second silicon region of the thin silicon layer, the second silicon region being isolated from the first silicon region; and The third implantation occurs in the region of the trap-rich layer directly below the second circuit, and is separated from the first implantation by an undoped region of the trap-rich layer. The third injection is configured to be biased using a third voltage based on the operating state of the second circuit. The SOI structure also includes a fourth injection in the region surrounding the third injection of the trap-rich layer, and The interface between the third injection and the fourth injection forms a second junction.

8. The silicon-on-insulator (SOI) structure according to claim 7, wherein: The SOI structure also includes a second injection around the region of the first injection in the rich trap layer, and The interface between the first injection and the second injection forms a first junction. The first node and the second node: The undoped regions of the trap-rich layers are separated from each other, and The trap-rich layer is separated from the HR-Si by the undoped region.

9. The silicon-on-insulator (SOI) structure according to claim 8, wherein: The first junction and the second junction form a back-to-back reverse diode, which is configured to reduce the flow of charge between the first injection and the third injection.

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