Dynamic scheduling method for chip platform resources

Abstract

An embodiment of the present application provides a method for dynamic scheduling of chip platform resources, the method comprising: deploying resource monitoring probes to collect the operating status of the chip platform, building a resource usage indicator database to record CPU utilization and memory bandwidth data, analyzing the timing characteristics and change rules of the operating status to establish a load model, setting resource thresholds based on a system bottleneck identification model, formulating scheduling rules through a policy generator, and creating a resource configuration plan based on resource thresholds and scheduling rules; analyzing the system status through a system bottleneck identification model, selecting a corresponding optimization strategy according to the scheduling rules, building a feedback collection queue, using data analysis technology to evaluate the scheduling effect of executing instructions, inputting the scheduling effect into an evaluation model for verification, and updating the scheduling rules based on the verification results of the evaluation model; the present application can effectively improve the resource management efficiency and performance of the system and achieve more flexible cross-platform support.

Description

Technical Field

[0001] The present application relates to the field of data processing, and in particular to a method for dynamically scheduling chip platform resources. Background Art

[0002] As chip design becomes increasingly complex, the widespread application of multi-core heterogeneous processor architectures has put forward higher requirements for system resource scheduling. The traditional static resource allocation method can no longer adapt to the complex and changeable load characteristics of modern chip platforms, and a more intelligent dynamic scheduling mechanism is needed to improve the overall system performance and resource utilization efficiency.

[0003] The current mainstream resource scheduling solutions mainly use fixed scheduling strategies and threshold control, which lack the ability to perceive and predict the system's operating status in real time. This approach often performs poorly when dealing with dynamic loads and is difficult to respond to sudden performance requirements and resource competition in a timely manner. At the same time, the existing scheduling system does not fully support heterogeneous computing units, and has obvious deficiencies in task allocation and load balancing, resulting in insufficient utilization of system resources.

[0004] In terms of resource monitoring and optimization, existing technologies still have much room for improvement. The scheduling system lacks an effective performance bottleneck identification mechanism and adaptive optimization capabilities, making it difficult to dynamically adjust the scheduling strategy according to actual operating conditions. In addition, cross-platform resource management and virtualization support are relatively weak, affecting the scalability and deployment flexibility of the system. These problems seriously restrict the performance of the chip platform and the efficiency of resource utilization. Summary of the invention

[0005] In response to the problems in the prior art, the present application provides a chip platform resource dynamic scheduling method, which can effectively improve the resource management efficiency and performance of the system and achieve more flexible cross-platform support.

[0006] In order to solve at least one of the above problems, the present application provides the following technical solutions:

[0007] In a first aspect, the present application provides a chip platform resource dynamic scheduling method, comprising:

[0008] Deploy resource monitoring probes to collect the operating status of the chip platform, build a resource usage indicator database to record CPU utilization and memory bandwidth data, analyze the timing characteristics and change rules of the operating status to establish a load model, use the load model to predict the resource usage trend, use the performance evaluator to build a system bottleneck identification model, set resource thresholds based on the system bottleneck identification model, formulate scheduling rules through a policy generator, and create a resource configuration plan based on the resource thresholds and the scheduling rules;

[0009] Construct a dynamic scheduler to convert the resource configuration scheme into execution instructions, design a unified resource allocation interface to support cross-platform scheduling, create a task planner to prioritize the execution instructions, construct a resource optimizer to perform load balancing and resource integration, and construct a task time matrix by calculating the estimated completion time of each execution instruction in each processing unit. Based on the task time matrix, select the processing unit with the minimum completion time to assign tasks. Use a dynamic time slice calculation module to dynamically adjust the size of the polling time slice according to the task priority. Use a task status monitor to track the running status of the execution instruction. Based on the running status, dynamically adjust the migration strategy of the task between processing units. Establish a virtualization manager to handle container creation, create a quota controller to manage the restriction parameters of the resource configuration scheme, and use an execution engine to send the optimized execution instructions to the chip platform.

[0010] Load the monitoring data of the resource monitoring probe at runtime, analyze the system status through the system bottleneck identification model, query the resource usage indicator database to obtain historical data, select the corresponding optimization strategy according to the scheduling rules, build a feedback collection queue, use data analysis technology to evaluate the scheduling effect of the execution instruction, input the scheduling effect into the evaluation model for verification, and update the scheduling rules based on the verification results of the evaluation model.

[0011] Furthermore, the resource monitoring probe is deployed to collect the operating status of the chip platform, a resource usage indicator database is constructed to record CPU utilization and memory bandwidth data, and the timing characteristics and change rules of the operating status are analyzed to establish a load model, including:

[0012] Collect processor operating frequency data through performance counters, obtain processor status information using system call interfaces, deploy memory monitoring modules to record memory usage data, set network monitors to collect bandwidth data, store the operating frequency data, processor status information, memory usage data, and bandwidth data in a time series database, and establish data collection triggers to control the sampling frequency of the time series database;

[0013] The data in the time series database is standardized, the standardized data is segmented using a time window method, a state transfer matrix is ​​constructed to describe the changing pattern of the segmented data, a data analysis method is applied to identify resource usage characteristics from the state transfer matrix, and a prediction model is established to analyze the resource usage characteristics.

[0014] Further, the load model is used to predict resource usage trends, a system bottleneck identification model is constructed using a performance evaluator, resource thresholds are set based on the system bottleneck identification model, scheduling rules are formulated through a policy generator, and a resource configuration plan is created according to the resource thresholds and the scheduling rules, including:

[0015] Input the output data of the load model into the performance evaluator, use a resource dependency graph to describe the relationship between system resources, build a performance scoring matrix based on the resource dependency graph, use a performance indicator weight vector to calculate the performance scores of each system, identify the bottleneck resources in the system according to the performance scores, and generate the system bottleneck identification model;

[0016] Based on the bottleneck resources, an upper threshold and a lower threshold of resource usage are set, a resource scheduling policy library is constructed to store scheduling rule templates, the scheduling rule template is selected according to the upper threshold and the lower threshold, a scheduling rule including resource allocation parameters is generated, and the scheduling rule is applied to a resource configuration generator to create a resource configuration plan.

[0017] Furthermore, the construction of a dynamic scheduler converts the resource configuration scheme into execution instructions, designs a unified resource allocation interface to support cross-platform scheduling, creates a task planner to prioritize the execution instructions, and constructs a resource optimizer to perform load balancing and resource integration, including:

[0018] Parse the resource allocation parameters in the resource configuration scheme, construct an instruction conversion module to map the resource allocation parameters into a target platform instruction format, design a unified scheduling interface specification to define a resource operation instruction set, generate a cross-platform resource allocation instruction according to the instruction set, and encapsulate the resource allocation instruction into an execution instruction sequence;

[0019] Obtain resource requirement information of the execution instruction sequence, calculate the resource occupancy ratio of each execution instruction, set the execution instruction priority based on the resource occupancy ratio, build a priority queue to store the execution instructions, use a load balancing algorithm to adjust the distribution of the execution instructions among processing units, and merge execution instructions with resource affinity to optimize resource utilization.

[0020] Furthermore, the method constructs a task time matrix by calculating the estimated completion time of each execution instruction in each processing unit, selects the processing unit with the minimum completion time to allocate the task based on the task time matrix, and uses a dynamic time slice calculation module to dynamically adjust the polling time slice size according to the task priority, including:

[0021] Extracting the computational complexity parameter of the execution instruction, obtaining the processing capability index of each processing unit, calculating the estimated execution time according to the computational complexity parameter and the processing capability index, establishing a task processing unit mapping table to record the estimated execution time, and generating a task time matrix including the estimated execution time;

[0022] The step of dynamically adjusting the size of the polling time slice includes: reading the execution time estimate in the task time matrix, selecting the processing unit with the smallest execution time estimate as the target processing unit, obtaining the priority value of the execution instruction, calculating the time slice reference value based on the priority value, dynamically adjusting the time slice reference value according to the system load status, and allocating the adjusted time slice to the target processing unit.

[0023] Further, the use of a task status monitor to track the running status of the execution instruction, dynamically adjusting the migration strategy of the task between processing units based on the running status, establishing a virtualization manager to handle container creation, creating a quota controller to manage the restriction parameters of the resource configuration scheme, and using an execution engine to send the optimized execution instruction to the chip platform includes:

[0024] Collecting real-time operating parameters of the execution instruction, recording resource occupancy of the execution instruction on the target processing unit, detecting the load level of the target processing unit, triggering task migration when the load level exceeds a preset threshold, calculating the task migration overhead, selecting a target migration processing unit, and migrating the execution instruction to the target migration processing unit;

[0025] Parse the resource limitation parameters in the resource configuration scheme, create a virtualized container isolation task running environment, set the resource quota limit of the virtualized container, build a resource usage quota control table, write the resource limitation parameters into the quota control table, and send the execution instruction and the quota control table to the target processing unit through the execution engine.

[0026] Furthermore, selecting a corresponding optimization strategy according to the scheduling rule, building a feedback collection queue, using data analysis technology to evaluate the scheduling effect of the execution instruction, inputting the scheduling effect into an evaluation model for verification, and updating the scheduling rule based on the verification result of the evaluation model, includes:

[0027] Read resource usage data from the resource usage quota control table, build a loop feedback queue to store the resource usage data, calculate the resource utilization efficiency of the target processing unit, match the resource utilization efficiency with the optimization target in the scheduling rule, and select the optimization strategy with the highest matching degree from the preset optimization strategy library;

[0028] Extract performance indicators from the resource usage data, calculate the deviation between the actual completion time of the execution instruction and the estimated execution time, count the throughput data of the target processing unit, input the deviation and the throughput data into an evaluation model, judge the scheduling effect according to the output result of the evaluation model, and update the parameters of the scheduling rule based on the scheduling effect.

[0029] In a second aspect, the present application provides a chip platform resource dynamic scheduling device, comprising:

[0030] A resource scheduling module is used to deploy resource monitoring probes to collect the operating status of the chip platform, build a resource usage indicator database to record CPU utilization and memory bandwidth data, analyze the timing characteristics and change rules of the operating status to establish a load model, use the load model to predict the resource usage trend, use a performance evaluator to build a system bottleneck identification model, set resource thresholds based on the system bottleneck identification model, formulate scheduling rules through a policy generator, and create a resource configuration plan based on the resource thresholds and the scheduling rules;

[0031] A resource allocation module is used to build a dynamic scheduler to convert the resource configuration scheme into execution instructions, design a unified resource allocation interface to support cross-platform scheduling, create a task planner to prioritize the execution instructions, build a resource optimizer to perform load balancing and resource integration, build a task time matrix by calculating the estimated completion time of each execution instruction in each processing unit, select the processing unit with the minimum completion time based on the task time matrix to assign tasks, use a dynamic time slice calculation module to dynamically adjust the polling time slice size according to the task priority, use a task status monitor to track the running status of the execution instruction, dynamically adjust the migration strategy of the task between processing units based on the running status, establish a virtualization manager to handle container creation, create a quota controller to manage the restriction parameters of the resource configuration scheme, and use an execution engine to send the optimized execution instructions to the chip platform;

[0032] A dynamic optimization module is used to load the monitoring data of the resource monitoring probe at runtime, analyze the system status through the system bottleneck identification model, query the resource usage indicator database to obtain historical data, select the corresponding optimization strategy according to the scheduling rules, build a feedback collection queue, use data analysis technology to evaluate the scheduling effect of the execution instruction, input the scheduling effect into the evaluation model for verification, and update the scheduling rules based on the verification results of the evaluation model.

[0033] In a third aspect, the present application provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the chip platform resource dynamic scheduling method when executing the program.

[0034] In a fourth aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the chip platform resource dynamic scheduling method.

[0035] In a fifth aspect, the present application provides a computer program product, including a computer program / instruction, which, when executed by a processor, implements the steps of the chip platform resource dynamic scheduling method.

[0036] It can be seen from the above technical solution that the present application provides a method for dynamic scheduling of chip platform resources, which collects the operating status of the chip platform by deploying resource monitoring probes, builds a resource usage indicator database to record CPU utilization and memory bandwidth data, analyzes the timing characteristics and change rules of the operating status to establish a load model, sets resource thresholds based on the system bottleneck identification model, formulates scheduling rules through a policy generator, and creates a resource configuration plan based on resource thresholds and scheduling rules; analyzes the system status through the system bottleneck identification model, selects the corresponding optimization strategy according to the scheduling rules, builds a feedback collection queue, uses data analysis technology to evaluate the scheduling effect of executing instructions, inputs the scheduling effect into the evaluation model for verification, and updates the scheduling rules based on the verification results of the evaluation model, thereby effectively improving the system's resource management efficiency and performance, and achieving more flexible cross-platform support. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0038] Figure 1 This is one of the flow charts of the chip platform resource dynamic scheduling method in the embodiment of the present application;

[0039] Figure 2 This is a second flow chart of the chip platform resource dynamic scheduling method in the embodiment of the present application;

[0040] Figure 3 This is a third flow chart of the chip platform resource dynamic scheduling method in the embodiment of the present application;

[0041] Figure 4 This is a fourth flow chart of the chip platform resource dynamic scheduling method in the embodiment of the present application;

[0042] Figure 5This is a fifth flow chart of the chip platform resource dynamic scheduling method in the embodiment of the present application;

[0043] Figure 6 This is a sixth flow chart of the chip platform resource dynamic scheduling method in the embodiment of the present application;

[0044] Figure 7 FIG7 is a flow chart of a method for dynamically scheduling chip platform resources in an embodiment of the present application;

[0045] Figure 8 A structural diagram of a chip platform resource dynamic scheduling device in an embodiment of the present application;

[0046] Fig. 9 It is a schematic diagram of the structure of an electronic device in an embodiment of the present application.

[0047] Reference numerals:

[0048] Electronic device 9600, central processing unit 9100, memory 9140, communication module 9110, input unit 9120, audio processor 9130, display 9160, power supply 9170, buffer memory 9141, application / function storage unit 9142, data storage unit 9143, driver program storage unit 9144, antenna 9111, speaker 9131, microphone 9132. DETAILED DESCRIPTION

[0049] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0050] The acquisition, storage, use, and processing of data in the technical solution of this application comply with the relevant provisions of national laws and regulations.

[0051] In view of the problems existing in the prior art, the present application provides a method for dynamic scheduling of chip platform resources, which collects the operating status of the chip platform by deploying resource monitoring probes, builds a resource usage indicator database to record CPU utilization and memory bandwidth data, analyzes the timing characteristics and change rules of the operating status to establish a load model, sets resource thresholds based on the system bottleneck identification model, formulates scheduling rules through a policy generator, and creates a resource configuration plan according to the resource thresholds and scheduling rules; analyzes the system status through the system bottleneck identification model, selects the corresponding optimization strategy according to the scheduling rules, builds a feedback collection queue, uses data analysis technology to evaluate the scheduling effect of executing instructions, inputs the scheduling effect into the evaluation model for verification, and updates the scheduling rules based on the verification results of the evaluation model, thereby effectively improving the resource management efficiency and performance of the system and achieving more flexible cross-platform support.

[0052] In order to effectively improve the resource management efficiency and performance of the system and achieve more flexible cross-platform support, the present application provides an embodiment of a chip platform resource dynamic scheduling method, see Figure 1 The chip platform resource dynamic scheduling method specifically includes the following contents:

[0053] Step S101: deploy resource monitoring probes to collect the operating status of the chip platform, build a resource usage indicator database to record CPU utilization and memory bandwidth data, analyze the timing characteristics and change rules of the operating status to establish a load model, use the load model to predict the resource usage trend, use a performance evaluator to build a system bottleneck identification model, set resource thresholds based on the system bottleneck identification model, formulate scheduling rules through a policy generator, and create a resource configuration plan based on the resource thresholds and the scheduling rules;

[0054] Optionally, this embodiment implements real-time collection of the chip platform operating status by deploying resource monitoring probes, which obtain key parameters such as the operating frequency, power consumption, and temperature of the processor core through hardware performance counters and system call interfaces. In a multi-core heterogeneous chip platform, the probes monitor the status data of large and small cores respectively, and transmit the collection results to the resource usage indicator database through a dedicated data channel.

[0055] The resource usage indicator database uses a time series database structure to store performance indicators such as CPU utilization, memory bandwidth, and cache hit rate. The database supports high-frequency writing and time series queries, and optimizes storage efficiency through data compression and sharding storage. For heterogeneous computing platforms, the database records the resource usage of different computing units such as CPU, GPU, and NPU.

[0056] Based on time series data analysis technology, the system performs time domain analysis on storage performance indicators to extract periodic characteristics and burst behavior patterns of resource usage. The data is segmented through a sliding time window to construct a state transition matrix that reflects load characteristics at different time scales. On this basis, a load prediction model is established using a time series prediction algorithm to achieve accurate estimation of future resource demand.

[0057] The performance evaluator analyzes the relationship between various resources in the system based on the resource dependency graph, and identifies the performance bottlenecks in the system by calculating the comprehensive scores of indicators such as resource utilization and response time. In heterogeneous computing scenarios, the evaluator focuses on the data transmission overhead and load balancing between computing units.

[0058] The system sets dynamically adjusted resource usage thresholds based on the identified bottleneck resources, including CPU usage upper limit, memory bandwidth reservation and other parameters. Based on these thresholds and historical experience, the policy generator formulates scheduling rules that adapt to different load conditions, such as task migration strategy and resource isolation strategy.

[0059] Finally, the system integrates the threshold parameters and scheduling rules into a complete resource configuration plan. This plan includes the frequency adjustment strategy of the processor core, the memory bandwidth allocation plan, the scheduling strategy of the computing task, etc. On heterogeneous platforms, the configuration plan also needs to consider the differences in the characteristics of different computing units to ensure the rationality of resource allocation.

[0060] Through this resource monitoring and scheduling mechanism, this embodiment effectively solves the problems of unbalanced resource allocation and inaccurate load prediction on heterogeneous computing platforms. In practical applications, the system can dynamically adjust the resource allocation strategy according to load changes, significantly improving the resource utilization efficiency and performance stability of the platform.

[0061] In scenarios such as high-performance computing and edge computing, the monitoring and prediction mechanism of this embodiment demonstrates excellent adaptability. Through accurate load prediction and timely policy adjustment, the system can optimize energy consumption while ensuring performance, thereby improving the overall performance of the computing platform.

[0062] Step S102: construct a dynamic scheduler to convert the resource configuration scheme into execution instructions, design a unified resource allocation interface to support cross-platform scheduling, create a task planner to prioritize the execution instructions, build a resource optimizer to perform load balancing and resource integration, and construct a task time matrix by calculating the estimated completion time of each execution instruction in each processing unit. Based on the task time matrix, select the processing unit with the minimum completion time to assign tasks, use a dynamic time slice calculation module to dynamically adjust the polling time slice size according to the task priority, use a task status monitor to track the running status of the execution instruction, dynamically adjust the migration strategy of the task between processing units based on the running status, establish a virtualization manager to handle container creation, create a quota controller to manage the restriction parameters of the resource configuration scheme, and use an execution engine to send the optimized execution instruction to the chip platform;

[0063] Optionally, the dynamic scheduler constructed in this embodiment first parses the resource allocation parameters in the resource configuration scheme, including information such as processor core binding relationships, memory allocation strategies, and bandwidth restrictions, and converts these high-level configurations into low-level execution instructions. In view of the characteristics of heterogeneous computing platforms, the scheduler designs a unified resource allocation interface that encapsulates the instruction differences of different hardware platforms and supports unified scheduling operations of heterogeneous computing units such as CPU, GPU, and NPU.

[0064] In the task planning stage, the task planner created in this embodiment assigns execution priority to the instructions by analyzing the resource requirement characteristics of each execution instruction, such as computing density, memory access mode, etc. For computing-intensive tasks, priority is given to their requirements for processor performance; for memory-intensive tasks, the focus is on the usage of memory bandwidth.

[0065] The resource optimizer performs load balancing based on task characteristics and hardware features. By calculating the execution time of tasks on different processing units, a task time matrix is ​​constructed, which reflects the matching degree between tasks and processing units. The optimizer selects the processing unit with the shortest estimated completion time to assign tasks, and dynamically adjusts the polling time slice size according to the task priority to ensure that high-priority tasks get more execution time.

[0066] The task status monitor of this embodiment tracks the running status of the executed instructions in real time, including indicators such as resource utilization, execution progress, and response time. When it is detected that the processing unit load is unbalanced or the task execution efficiency is low, the task migration mechanism is triggered. The migration decision considers the task migration overhead and the load status of the target processing unit and selects the optimal migration solution.

[0067] To achieve resource isolation and precise control, this embodiment establishes a virtualization manager to create an independent task running container. Container technology ensures that resource usage between different tasks does not interfere with each other, and the quota controller strictly manages the resource usage limit of each container. The execution engine sends the optimized execution instructions and resource limit parameters to the corresponding processing unit to ensure that the task is executed according to the predetermined strategy.

[0068] This embodiment effectively solves the problems of unbalanced task scheduling and resource competition conflicts on heterogeneous computing platforms through a unified scheduling framework and a sophisticated resource management mechanism. In practical applications, dynamic time slice adjustment and task migration strategies can flexibly adjust resource allocation according to load changes and improve the resource utilization efficiency of the platform.

[0069] In complex application scenarios such as edge computing, the scheduling mechanism of this embodiment can make full use of heterogeneous computing resources, and through reasonable task allocation and dynamic adjustment, improve the overall computing efficiency while ensuring the performance of key tasks. The introduction of virtualized containers provides reliable isolation guarantee for multi-task parallel processing.

[0070] Step S103: Load the monitoring data of the resource monitoring probe at runtime, analyze the system status through the system bottleneck identification model, query the resource usage indicator database to obtain historical data, select the corresponding optimization strategy according to the scheduling rules, build a feedback collection queue, use data analysis technology to evaluate the scheduling effect of the execution instruction, input the scheduling effect into the evaluation model for verification, and update the scheduling rules based on the verification results of the evaluation model.

[0071] Optionally, this embodiment continuously loads real-time monitoring data collected by resource monitoring probes when the chip platform is running, including key indicators such as the operating frequency, power consumption, temperature, and resource utilization of each processing unit. The probe obtains this data through hardware performance counters and system call interfaces, and transmits it to the data processing module in real time through a dedicated channel.

[0072] Based on the system bottleneck identification model, this embodiment analyzes the current operating status, focusing on abnormal conditions of indicators such as processor utilization, memory bandwidth usage, cache hit rate, etc. By querying historical data in the resource usage indicator database, comparing and analyzing the differences between the current status and historical patterns, potential performance bottlenecks and resource conflicts can be identified.

[0073] This embodiment selects a suitable optimization scheme from the optimization strategy library according to the preset scheduling rules. For example, when a processing unit is detected to be overloaded, the task migration strategy is triggered; when memory bandwidth competition is found, the bandwidth control mechanism is started. In order to track the optimization effect, this embodiment constructs a feedback collection queue to record the execution process and results of each optimization operation.

[0074] Through data analysis technology, this embodiment evaluates the scheduling effect of executing instructions, including multiple dimensions such as task completion time, resource utilization efficiency, and energy consumption level. The evaluation results are input into the evaluation model for verification. The model judges the effectiveness of the optimization strategy by comparing the performance indicators before and after optimization. This embodiment dynamically updates the scheduling rules based on the verification results and continuously optimizes the resource allocation strategy.

[0075] In heterogeneous computing scenarios, the feedback optimization mechanism of this embodiment can timely discover and solve problems such as unbalanced resource allocation and unreasonable task scheduling. For example, in edge computing applications, when it is detected that the GPU load is too high and the CPU is relatively idle, the task allocation strategy is dynamically adjusted to achieve balanced distribution of computing load.

[0076] This embodiment establishes a closed-loop resource management system through continuous monitoring and optimization. In practical applications, this feedback-based optimization mechanism can adaptively adjust resource allocation strategies according to load changes and improve resource utilization efficiency of heterogeneous computing platforms.

[0077] Through real-time monitoring and dynamic optimization, this embodiment effectively solves the problem that traditional fixed scheduling strategies are difficult to cope with complex load changes. In scenarios such as high-performance computing and edge computing, this adaptive optimization mechanism can dynamically adjust resource allocation according to actual operating conditions and improve the overall performance and stability of the computing platform. Especially in scenarios with drastic load fluctuations, the optimization mechanism of this embodiment shows excellent adaptability and ensures efficient use of computing resources.

[0078] From the above description, it can be seen that the chip platform resource dynamic scheduling method provided in the embodiment of the present application can collect the operating status of the chip platform by deploying resource monitoring probes, build a resource usage indicator database to record CPU utilization and memory bandwidth data, analyze the timing characteristics and change rules of the operating status to establish a load model, set resource thresholds based on the system bottleneck identification model, formulate scheduling rules through a policy generator, and create a resource configuration plan based on resource thresholds and scheduling rules; analyze the system status through the system bottleneck identification model, select the corresponding optimization strategy according to the scheduling rules, build a feedback collection queue, use data analysis technology to evaluate the scheduling effect of executing instructions, input the scheduling effect into the evaluation model for verification, and update the scheduling rules based on the verification results of the evaluation model, thereby effectively improving the system's resource management efficiency and performance, and achieving more flexible cross-platform support.

[0079] In one embodiment of the chip platform resource dynamic scheduling method of the present application, see Figure 2 , and can also include the following:

[0080] Step S201: collect processor operating frequency data through performance counters, obtain processor status information using a system call interface, deploy a memory monitoring module to record memory usage data, set a network monitor to collect bandwidth data, store the operating frequency data, the processor status information, the memory usage data and the bandwidth data in a time series database, and establish a data collection trigger to control the sampling frequency of the time series database;

[0081] Step S202: Standardize the data in the time series database, segment the standardized data using a time window method, construct a state transfer matrix to describe the change pattern of the segmented data, apply a data analysis method to identify resource usage characteristics from the state transfer matrix, and establish a prediction model to analyze the resource usage characteristics.

[0082] Optionally, this embodiment first collects the operating frequency data of the processor in real time through the performance counter, including the clock frequency, voltage level and power consumption status of each processor core. At the same time, the operating status information of the processor is obtained through the system call interface, such as core temperature, load level, interrupt processing times and other key parameters. In a heterogeneous computing platform, these data are collected for different types of processing units such as CPU, GPU, NPU, etc.

[0083] In order to comprehensively monitor the usage of system resources, this embodiment deploys a memory monitoring module to record memory usage data, including memory page allocation status, cache hit rate, memory bandwidth usage and other information. The network monitor is responsible for collecting bandwidth usage data of the network interface and recording parameters such as the data packet sending and receiving rate and network delay. These monitoring data are transmitted to the time series database in real time through a dedicated data channel.

[0084] This embodiment uses a time series database to store the collected performance indicator data, and the database supports high-frequency writing and time series query operations. Through data collection triggers, this embodiment can dynamically adjust the sampling frequency according to the load situation, increase the sampling density during critical periods, and appropriately reduce the sampling frequency during idle periods to optimize storage efficiency.

[0085] For the collected data, this embodiment first performs standardization processing to eliminate the dimensional differences between different indicators. Through the time window method, the continuous time series data is divided into multiple time periods, and the length of each time period is dynamically adjusted according to the load characteristics. Based on these segmented data, this embodiment constructs a state transition matrix to describe the conversion rules between resource usage states.

[0086] This embodiment applies a data analysis method to extract resource usage features from the state transition matrix, including periodic patterns, burst behaviors, load trends, etc. In a heterogeneous computing platform, these features reflect the demand patterns of different types of computing tasks for processing resources. Based on the extracted features, this embodiment establishes a prediction model that can accurately predict future resource demand trends.

[0087] Through this data collection and analysis mechanism, this embodiment effectively solves the problem of incomplete resource monitoring and inaccurate prediction of heterogeneous computing platforms. In practical applications, the dynamically adjusted sampling strategy ensures that sufficiently dense monitoring data is obtained at critical moments, while avoiding the waste of storage resources.

[0088] In scenarios such as high-performance computing and edge computing, the data collection and analysis mechanism of this embodiment shows excellent adaptability. Through real-time monitoring and analysis of multi-dimensional performance indicators, potential performance bottlenecks can be discovered in a timely manner, providing reliable data support for subsequent resource scheduling optimization. Especially in application scenarios with complex and changeable load characteristics, the prediction model of this embodiment can accurately grasp the changing trend of resource demand and provide an important basis for the rational allocation of resources.

[0089] In one embodiment of the chip platform resource dynamic scheduling method of the present application, see Figure 3 , and can also include the following:

[0090] Step S301: input the output data of the load model into the performance evaluator, use a resource dependency graph to describe the relationship between system resources, build a performance scoring matrix based on the resource dependency graph, use a performance indicator weight vector to calculate the performance scores of each system, identify the bottleneck resources in the system according to the performance scores, and generate the system bottleneck identification model;

[0091] Step S302: Set the upper and lower thresholds of resource usage based on the bottleneck resources, build a resource scheduling policy library to store scheduling rule templates, select the scheduling rule template according to the upper and lower thresholds, generate scheduling rules containing resource allocation parameters, and apply the scheduling rules to the resource configuration generator to create a resource configuration plan.

[0092] Optionally, this embodiment inputs the output data of the load model into the performance evaluator for analysis, and these data include multi-dimensional load characteristics such as processor usage, memory usage, bandwidth consumption, etc. In order to accurately describe the mutual influence between various resources in the heterogeneous computing platform, this embodiment uses a resource dependency graph to model the relationship between resources, using hardware resources such as processors, memory, and networks as nodes in the graph, and using weighted edges to represent the dependency strength and influence direction between resources.

[0093] Based on the constructed resource dependency graph, this embodiment establishes a performance scoring matrix, which reflects the contribution of different resources to the overall performance. Through the performance indicator weight vector, this embodiment assigns weight coefficients to different types of performance indicators and calculates the comprehensive scores of the system in terms of computing performance, response time, resource utilization, etc. Based on these performance scores, this embodiment can accurately identify the bottleneck resources in the system and generate a system bottleneck identification model based on this.

[0094] This embodiment sets dynamic resource usage thresholds for the identified bottleneck resources. The upper threshold is used to prevent performance degradation caused by excessive resource usage, and the lower threshold is used to avoid waste caused by idle resources. These thresholds are dynamically adjusted according to load characteristics and performance requirements to ensure that resource usage always remains within a reasonable range.

[0095] The resource scheduling policy library constructed in this embodiment stores a variety of scheduling rule templates, which are optimized for different load scenarios and performance targets. According to the set threshold range, this embodiment selects the scheduling rule template that best suits the current scenario, adjusts the template parameters according to specific needs, and generates a scheduling rule containing detailed resource allocation parameters.

[0096] In a heterogeneous computing platform, the bottleneck identification and resource scheduling mechanism of this embodiment can effectively handle complex resource competition problems. For example, when it is detected that the GPU has become a performance bottleneck, the scheduling rules will appropriately reduce the allocation ratio of GPU-intensive tasks and transfer some computing tasks to the CPU or NPU for execution.

[0097] Through the resource configuration generator, this embodiment converts the scheduling rules into specific resource configuration schemes. These configuration schemes include detailed parameters such as processor core binding, memory allocation strategy, bandwidth limitation, etc., to ensure that resource allocation meets the performance optimization goal.

[0098] In practical applications, the bottleneck identification and resource scheduling mechanism of this embodiment shows excellent adaptability. By accurately identifying system bottlenecks and dynamically adjusting resource allocation strategies, the resource utilization efficiency of heterogeneous computing platforms can be effectively improved. Especially in scenarios where load characteristics change dynamically, the scheduling mechanism of this embodiment can quickly respond to changes in performance requirements, adjust resource allocation strategies in a timely manner, and maintain the stability of system performance. In complex application scenarios such as edge computing, this flexible resource scheduling mechanism is of great significance for improving computing efficiency and optimizing energy consumption.

[0099] In one embodiment of the chip platform resource dynamic scheduling method of the present application, see Figure 4 , and can also include the following:

[0100] Step S401: parsing the resource allocation parameters in the resource configuration scheme, constructing an instruction conversion module to map the resource allocation parameters into a target platform instruction format, designing a unified scheduling interface specification to define a resource operation instruction set, generating a cross-platform resource allocation instruction according to the instruction set, and encapsulating the resource allocation instruction into an execution instruction sequence;

[0101] Step S402: Obtain resource requirement information of the execution instruction sequence, calculate the resource occupancy ratio of each execution instruction, set the execution instruction priority based on the resource occupancy ratio, build a priority queue to store the execution instructions, use a load balancing algorithm to adjust the distribution of the execution instructions among processing units, and merge execution instructions with resource affinity to optimize resource utilization.

[0102] Optionally, this embodiment first parses the resource allocation parameters in the resource configuration scheme, which include specific configuration information such as processor core allocation, memory allocation strategy, network bandwidth limit, etc. In order to achieve cross-platform resource scheduling, this embodiment constructs an instruction conversion module, which can accurately map the general resource allocation parameters into specific instruction formats of different target platforms.

[0103] In a heterogeneous computing platform, this embodiment designs a unified scheduling interface specification and defines a complete set of resource operation instruction sets. This instruction set covers basic operations such as processor affinity setting, memory page allocation, and bandwidth control, ensuring that resource scheduling instructions can be uniformly executed between different types of processing units. Based on this instruction set, this embodiment generates cross-platform resource allocation instructions and encapsulates these instructions into a complete execution instruction sequence according to the execution order and dependency relationship.

[0104] This embodiment analyzes the resource demand information of the execution instruction sequence to accurately calculate the proportion of each instruction occupied by processor, memory, bandwidth and other resources. Based on these proportions, this embodiment sets priorities for different execution instructions, and the priority determination takes into account factors such as the urgency of the instruction, resource dependencies and overall execution efficiency.

[0105] In order to efficiently manage execution instructions, this embodiment constructs a priority queue to store these instructions. The instructions in the queue are sorted by priority to ensure that key instructions can be executed first. At the same time, this embodiment uses a load balancing algorithm to dynamically adjust the distribution of instructions among different processing units to avoid local resource overload.

[0106] In the actual execution process, this embodiment will identify and merge execution instructions with resource affinity. For example, for instructions that need to access the same memory area, merged execution can reduce memory access overhead; for computing instructions that use the same GPU core, merged execution can improve GPU resource utilization efficiency.

[0107] The instruction conversion and scheduling mechanism of this embodiment shows significant advantages in complex scenarios such as edge computing. Through a unified scheduling interface and flexible instruction conversion, the problems of inconsistent resource scheduling and low instruction execution efficiency in heterogeneous platforms are effectively solved. Especially in the case of diverse processing unit types and complex load characteristics, the scheduling mechanism of this embodiment can dynamically adjust the instruction execution strategy according to the real-time load conditions.

[0108] Through the priority queue and load balancing algorithm, this embodiment ensures the timely processing of key tasks and the balanced use of system resources. In high-performance computing scenarios, this refined instruction scheduling mechanism can give full play to the computing potential of heterogeneous platforms and improve overall execution efficiency. Combined with the instruction merging optimization of resource affinity, this embodiment further reduces resource scheduling overhead and improves the system's throughput and response speed.

[0109] In one embodiment of the chip platform resource dynamic scheduling method of the present application, see Figure 5 , and can also include the following:

[0110] Step S501: extracting the computational complexity parameter of the execution instruction, obtaining the processing capability index of each processing unit, calculating the estimated execution time according to the computational complexity parameter and the processing capability index, establishing a task processing unit mapping table to record the estimated execution time, and generating a task time matrix including the estimated execution time;

[0111] Step S502: The step of dynamically adjusting the size of the polling time slice includes: reading the execution time estimate in the task time matrix, selecting the processing unit with the smallest execution time estimate as the target processing unit, obtaining the priority value of the execution instruction, calculating the time slice reference value based on the priority value, dynamically adjusting the time slice reference value according to the system load status, and allocating the adjusted time slice to the target processing unit.

[0112] Optionally, this embodiment first extracts computational complexity parameters by analyzing the algorithmic features and data size of the executed instructions, which reflect the amount of computing resources required for the execution of the instructions. At the same time, this embodiment obtains the processing capability indicators of each processing unit in the heterogeneous computing platform, including key parameters such as the instruction execution speed of the CPU, the parallel computing capability of the GPU, and the neural network processing efficiency of the NPU.

[0113] Based on the obtained computational complexity parameters and processing power indicators, this embodiment establishes an accurate execution time estimation model. This model takes into account the characteristics of different types of processing units, such as the CPU is suitable for processing complex control processes, the GPU is good at large-scale parallel computing, and the NPU focuses on neural network computing. Through this model, this embodiment calculates the expected execution time of each execution instruction on different processing units.

[0114] In order to systematically manage these time estimation data, this embodiment constructs a task processing unit mapping table to record in detail the execution time estimation value of each instruction on each processing unit. Based on these records, this embodiment generates a task time matrix, which fully reflects the execution efficiency relationship between instructions and processing units.

[0115] In the time slice allocation process, this embodiment first reads the execution time estimate in the task time matrix, and selects the processing unit with the smallest execution time estimate as the target processing unit through comparison. This selection ensures that the instruction can be executed on the most suitable processing unit, thereby improving the overall processing efficiency.

[0116] This embodiment obtains the priority value of the execution instruction, which comprehensively considers the urgency of the instruction, resource dependencies and the current state of the system. Based on this priority value, this embodiment calculates the time slice reference value, and high priority instructions obtain larger time slices to ensure timely completion.

[0117] In actual operation, this embodiment will dynamically adjust the time slice reference value according to the real-time load status of the system. When the system load is light, the time slice size can be appropriately increased to reduce the context switching overhead; when the load is heavy, the time slice size is reduced to improve the responsiveness of the system. Finally, the adjusted time slice is allocated to the target processing unit for executing specific instructions.

[0118] Through this dynamic time slice adjustment mechanism, this embodiment effectively solves the problem of unbalanced resource allocation and low processing efficiency in heterogeneous computing platforms. In practical applications, this scheduling scheme based on execution time estimation and priority shows excellent adaptability and can flexibly adjust the execution strategy according to the characteristics of different instructions and system status.

[0119] Especially in scenarios with complex and changing load characteristics, the dynamic time slice adjustment mechanism of this embodiment can quickly respond to changes in system requirements, ensure that key tasks are processed in a timely manner, and maintain the overall stability of the system. In application scenarios such as high-performance computing and real-time processing, this precise time management mechanism is of great significance for improving system performance and optimizing resource utilization.

[0120] In one embodiment of the chip platform resource dynamic scheduling method of the present application, see Figure 6 , and can also include the following:

[0121] Step S601: collecting real-time operating parameters of the execution instruction, recording resource occupancy of the execution instruction on the target processing unit, detecting the load level of the target processing unit, triggering task migration when the load level exceeds a preset threshold, calculating the task migration overhead, selecting a target migration processing unit, and migrating the execution instruction to the target migration processing unit;

[0122] Step S602: parse the resource limitation parameters in the resource configuration plan, create a virtualized container isolation task running environment, set the resource quota limit of the virtualized container, build a resource usage quota control table, write the resource limitation parameters into the quota control table, and send the execution instruction and the quota control table to the target processing unit through the execution engine.

[0123] Optionally, this embodiment collects the operating parameters of the execution instructions through a real-time monitoring mechanism, including key indicators such as processor usage, memory usage, cache hit rate, etc. At the same time, the resource usage of the execution instructions on the target processing unit is recorded in detail to establish a resource usage profile. By continuously detecting the load level of the target processing unit, when it is found that the load exceeds a preset threshold, this embodiment triggers the task migration mechanism.

[0124] During the task migration process, this embodiment comprehensively considers the migration overhead, including data transmission cost, state preservation overhead, task restart time and other factors. By establishing a migration cost model, the overall overhead of different migration schemes is calculated, and the optimal target migration processing unit is selected. For example, when the GPU load is too high, some computing tasks may be migrated to an idle CPU or NPU for execution to ensure balanced resource utilization.

[0125] In order to ensure the isolation of task execution and the controllability of resource use, this embodiment analyzes the resource restriction parameters in the resource configuration scheme, which define the resource boundaries required for task execution. Based on these parameters, this embodiment creates a lightweight virtualized container to provide an independent operating environment for each task, effectively avoiding resource contention and mutual interference between different tasks.

[0126] This embodiment sets strict resource quota restrictions for the virtualized container, including the upper limit of CPU time slice usage, memory usage range, network bandwidth limit, etc. These restrictions are uniformly managed through the constructed resource usage quota control table to ensure that task execution does not exceed the predetermined resource boundaries. After the resource limit parameters are written into the quota control table, the execution instruction and the quota control table are sent to the target processing unit through the execution engine.

[0127] In complex scenarios such as edge computing, the task migration and resource isolation mechanism of this embodiment shows significant advantages. When it is detected that a processing unit is overloaded, the task can be migrated to other suitable processing units in a timely manner to avoid performance bottlenecks. For example, in video processing applications, image processing tasks can be flexibly migrated between the GPU and NPU according to the real-time load conditions to maintain processing efficiency.

[0128] Through resource isolation of virtualized containers, this embodiment effectively solves the problems of resource contention and task interference in heterogeneous computing platforms. In the scenario of multi-task parallel execution, each task runs in an independent container environment and is subject to strict resource quota restrictions, ensuring the reasonable allocation of computing resources and improving the efficiency of use.

[0129] This embodiment achieves precise control of resource allocation by executing the engine to uniformly manage task distribution. In practical applications, this fine-grained resource management mechanism can dynamically adjust resource allocation strategies according to task characteristics and system status, improving system resource utilization and processing efficiency. Especially on resource-constrained edge devices, this precise resource control mechanism is of great significance for ensuring system stability and performance optimization.

[0130] In one embodiment of the chip platform resource dynamic scheduling method of the present application, see Figure 7 , and can also include the following:

[0131] Step S701: reading resource usage data from the resource usage quota control table, constructing a loop feedback queue to store the resource usage data, calculating the resource utilization efficiency of the target processing unit, matching the resource utilization efficiency with the optimization target in the scheduling rule, and selecting the optimization strategy with the highest matching degree from the preset optimization strategy library;

[0132] Step S702: extract the performance indicators in the resource usage data, calculate the deviation between the actual completion time of the execution instruction and the estimated execution time, count the throughput data of the target processing unit, input the deviation and the throughput data into the evaluation model, judge the scheduling effect according to the output result of the evaluation model, and update the parameters of the scheduling rule based on the scheduling effect.

[0133] Optionally, this embodiment reads the resource usage data in the resource usage quota control table to grasp the resource consumption of each execution instruction. These data include key indicators such as processor usage, memory occupancy, and bandwidth usage. In order to achieve continuous performance optimization, this embodiment constructs a circular feedback queue to store and analyze the historical change trend of these resource usage data.

[0134] By analyzing resource usage data, this embodiment calculates the resource utilization efficiency of the target processing unit. This efficiency index comprehensively considers multiple dimensions such as processor time utilization, memory access efficiency, and energy efficiency. The calculated resource utilization efficiency is matched and analyzed with the optimization target defined in the scheduling rule. For example, in edge computing scenarios, energy efficiency may be more important, while in high-performance computing scenarios, processor utilization may be more important.

[0135] Based on the matching analysis results, this embodiment selects the optimization strategy with the highest matching degree from the preset optimization strategy library. This strategy library contains optimization solutions for different application scenarios, such as parallel optimization strategies for computationally intensive tasks, data locality optimization strategies for memory-intensive tasks, etc. The selected strategy will directly guide subsequent resource scheduling decisions.

[0136] This embodiment focuses on the evaluation and optimization of execution effects. By extracting performance indicators from resource usage data, the deviation between the actual completion time and the estimated time of executing instructions is calculated. These deviation data reflect the accuracy of the current scheduling strategy. At the same time, the throughput data of the target processing unit is counted to comprehensively evaluate the actual processing capacity of the processing unit.

[0137] The calculated time deviation and throughput data are input into the evaluation model, which can comprehensively analyze multiple performance indicators to generate an overall evaluation result of the current scheduling effect. Based on the evaluation result, this embodiment determines whether the scheduling effect has achieved the expected goal, and dynamically updates the parameters of the scheduling rule accordingly.

[0138] In practical applications, the feedback optimization mechanism of this embodiment shows excellent adaptive capabilities. For example, in video processing applications, when it is detected that the actual processing capacity of some processing units deviates significantly from the expected capacity, the task allocation strategy can be adjusted in time to ensure continuous optimization of processing efficiency.

[0139] Through this closed-loop optimization mechanism, this embodiment effectively solves the problems of inaccurate resource scheduling and insufficient performance optimization in heterogeneous computing platforms. Especially in scenarios where load characteristics change dynamically, this scheduling optimization solution based on real-time feedback can quickly adapt to changes in system status and continuously improve the accuracy of scheduling decisions.

[0140] The dynamic update mechanism of the scheduling rules in this embodiment ensures that the entire scheduling system can be continuously optimized as the operating environment changes. In complex edge computing scenarios, this adaptive scheduling optimization mechanism can continuously improve the processing efficiency of the system, maintain high resource utilization, and ensure the stability and reliability of the system.

[0141] In order to effectively improve the resource management efficiency and performance of the system and achieve more flexible cross-platform support, the present application provides an embodiment of a chip platform resource dynamic scheduling device for implementing all or part of the content of the chip platform resource dynamic scheduling method, see Figure 8 The chip platform resource dynamic scheduling device specifically includes the following contents:

[0142] The resource scheduling module 10 is used to deploy resource monitoring probes to collect the operating status of the chip platform, build a resource usage indicator database to record CPU utilization and memory bandwidth data, analyze the timing characteristics and change rules of the operating status to establish a load model, use the load model to predict the resource usage trend, use a performance evaluator to build a system bottleneck identification model, set resource thresholds based on the system bottleneck identification model, formulate scheduling rules through a policy generator, and create a resource configuration plan based on the resource thresholds and the scheduling rules;

[0143] A resource allocation module 20 is used to construct a dynamic scheduler to convert the resource configuration scheme into execution instructions, design a unified resource allocation interface to support cross-platform scheduling, create a task planner to prioritize the execution instructions, build a resource optimizer to perform load balancing and resource integration, and construct a task time matrix by calculating the estimated completion time of each execution instruction in each processing unit. Based on the task time matrix, the processing unit with the minimum completion time is selected to assign tasks. A dynamic time slice calculation module is used to dynamically adjust the size of the polling time slice according to the task priority. A task status monitor is used to track the running status of the execution instruction. Based on the running status, the migration strategy of the task between the processing units is dynamically adjusted. A virtualization manager is established to handle container creation. A quota controller is created to manage the restriction parameters of the resource configuration scheme. An execution engine is used to send the optimized execution instruction to the chip platform.

[0144] The dynamic optimization module 30 is used to load the monitoring data of the resource monitoring probe at runtime, analyze the system status through the system bottleneck identification model, query the resource usage indicator database to obtain historical data, select the corresponding optimization strategy according to the scheduling rules, build a feedback collection queue, use data analysis technology to evaluate the scheduling effect of the execution instruction, input the scheduling effect into the evaluation model for verification, and update the scheduling rules based on the verification results of the evaluation model.

[0145] From the above description, it can be seen that the chip platform resource dynamic scheduling device provided in the embodiment of the present application can collect the operating status of the chip platform by deploying resource monitoring probes, build a resource usage indicator database to record CPU utilization and memory bandwidth data, analyze the timing characteristics and change rules of the operating status to establish a load model, set resource thresholds based on the system bottleneck identification model, formulate scheduling rules through a policy generator, and create a resource configuration plan based on resource thresholds and scheduling rules; analyze the system status through the system bottleneck identification model, select the corresponding optimization strategy according to the scheduling rules, build a feedback collection queue, use data analysis technology to evaluate the scheduling effect of executing instructions, input the scheduling effect into the evaluation model for verification, and update the scheduling rules based on the verification results of the evaluation model, thereby effectively improving the system's resource management efficiency and performance, and achieving more flexible cross-platform support.

[0146] From the hardware level, in order to effectively improve the resource management efficiency and performance of the system and achieve more flexible cross-platform support, the present application provides an embodiment of an electronic device for implementing all or part of the content of the chip platform resource dynamic scheduling method, and the electronic device specifically includes the following content:

[0147] Processor, memory, communication interface and bus; wherein the processor, memory and communication interface communicate with each other through the bus; the communication interface is used to realize information transmission between the chip platform resource dynamic scheduling device and the core business system, user terminal and related database and other related devices; the logic controller can be a desktop computer, a tablet computer and a mobile terminal, etc., but the present embodiment is not limited thereto. In the present embodiment, the logic controller can be implemented with reference to the embodiment of the chip platform resource dynamic scheduling method and the embodiment of the chip platform resource dynamic scheduling device in the embodiment, and the contents thereof are incorporated herein, and the repeated parts are not repeated.

[0148] It is understandable that the user terminal may include a smart phone, a tablet electronic device, a network set-top box, a portable computer, a desktop computer, a personal digital assistant (PDA), a vehicle-mounted device, a smart wearable device, etc. Among them, the smart wearable device may include smart glasses, a smart watch, a smart bracelet, etc.

[0149] In practical applications, part of the chip platform resource dynamic scheduling method can be executed on the electronic device side as described above, or all operations can be completed in the client device. The specific selection can be based on the processing capability of the client device and the limitations of the user's usage scenario. This application does not limit this. If all operations are completed in the client device, the client device may also include a processor.

[0150] The client device may have a communication module (i.e., a communication unit) that can communicate with a remote server to achieve data transmission with the server. The server may include a server on the task scheduling center side, and other implementation scenarios may also include a server on an intermediate platform, such as a server on a third-party server platform that has a communication link with the task scheduling center server. The server may include a single computer device, or a server cluster consisting of multiple servers, or a server structure of a distributed device.

[0151] Fig. 9 FIG. 9 is a schematic block diagram of the system structure of the electronic device 9600 according to an embodiment of the present application. Fig. 9 As shown, the electronic device 9600 may include a central processor 9100 and a memory 9140; the memory 9140 is coupled to the central processor 9100. It is worth noting that Fig. 9 is exemplary; other types of structures may also be used to supplement or replace this structure to implement telecommunication functions or other functions.

[0152] In one embodiment, the chip platform resource dynamic scheduling method function may be integrated into the central processing unit 9100. The central processing unit 9100 may be configured to perform the following control:

[0153] Step S101: deploy resource monitoring probes to collect the operating status of the chip platform, build a resource usage indicator database to record CPU utilization and memory bandwidth data, analyze the timing characteristics and change rules of the operating status to establish a load model, use the load model to predict the resource usage trend, use a performance evaluator to build a system bottleneck identification model, set resource thresholds based on the system bottleneck identification model, formulate scheduling rules through a policy generator, and create a resource configuration plan based on the resource thresholds and the scheduling rules;

[0154] Step S102: construct a dynamic scheduler to convert the resource configuration scheme into execution instructions, design a unified resource allocation interface to support cross-platform scheduling, create a task planner to prioritize the execution instructions, build a resource optimizer to perform load balancing and resource integration, and construct a task time matrix by calculating the estimated completion time of each execution instruction in each processing unit. Based on the task time matrix, select the processing unit with the minimum completion time to assign tasks, use a dynamic time slice calculation module to dynamically adjust the polling time slice size according to the task priority, use a task status monitor to track the running status of the execution instruction, dynamically adjust the migration strategy of the task between processing units based on the running status, establish a virtualization manager to handle container creation, create a quota controller to manage the restriction parameters of the resource configuration scheme, and use an execution engine to send the optimized execution instruction to the chip platform;

[0155] Step S103: Load the monitoring data of the resource monitoring probe at runtime, analyze the system status through the system bottleneck identification model, query the resource usage indicator database to obtain historical data, select the corresponding optimization strategy according to the scheduling rules, build a feedback collection queue, use data analysis technology to evaluate the scheduling effect of the execution instruction, input the scheduling effect into the evaluation model for verification, and update the scheduling rules based on the verification results of the evaluation model.

[0156] From the above description, it can be seen that the electronic device provided in the embodiment of the present application collects the operating status of the chip platform by deploying resource monitoring probes, builds a resource usage indicator database to record CPU utilization and memory bandwidth data, analyzes the timing characteristics and change rules of the operating status to establish a load model, sets resource thresholds based on the system bottleneck identification model, formulates scheduling rules through a policy generator, and creates a resource configuration plan based on resource thresholds and scheduling rules; analyzes the system status through the system bottleneck identification model, selects the corresponding optimization strategy according to the scheduling rules, builds a feedback collection queue, uses data analysis technology to evaluate the scheduling effect of executing instructions, inputs the scheduling effect into the evaluation model for verification, and updates the scheduling rules based on the verification results of the evaluation model, thereby effectively improving the system's resource management efficiency and performance, and achieving more flexible cross-platform support.

[0157] In another embodiment, the chip platform resource dynamic scheduling device can be configured separately from the central processing unit 9100. For example, the chip platform resource dynamic scheduling device can be configured as a chip connected to the central processing unit 9100, and the chip platform resource dynamic scheduling method function can be implemented through the control of the central processing unit.

[0158] like Fig. 9As shown, the electronic device 9600 may also include: a communication module 9110, an input unit 9120, an audio processor 9130, a display 9160, and a power supply 9170. It is worth noting that the electronic device 9600 does not necessarily have to include Fig. 9 In addition, the electronic device 9600 may also include Fig. 9 For components not shown, reference may be made to the prior art.

[0159] like Fig. 9 As shown, the central processing unit 9100 is sometimes also referred to as a controller or an operation control, and may include a microprocessor or other processor device and / or logic device. The central processing unit 9100 receives input and controls the operation of various components of the electronic device 9600.

[0160] The memory 9140 may be, for example, one or more of a cache, a flash memory, a hard drive, a removable medium, a volatile memory, a non-volatile memory or other suitable devices. The above-mentioned information related to the failure may be stored, and a program for executing the relevant information may also be stored. The CPU 9100 may execute the program stored in the memory 9140 to implement information storage or processing, etc.

[0161] The input unit 9120 provides input to the central processing unit 9100. The input unit 9120 is, for example, a key or a touch input device. The power supply 9170 is used to provide power to the electronic device 9600. The display 9160 is used to display display objects such as images and texts. The display may be, for example, an LCD display, but is not limited thereto.

[0162] The memory 9140 may be a solid-state memory, such as a read-only memory (ROM), a random access memory (RAM), a SIM card, etc. It may also be a memory that saves information even when the power is off, can be selectively erased, and is provided with more data, examples of which are sometimes referred to as EPROMs, etc. The memory 9140 may also be some other type of device. The memory 9140 includes a buffer memory 9141 (sometimes referred to as a buffer). The memory 9140 may include an application / function storage unit 9142, which is used to store application programs and function programs or processes for executing the operation of the electronic device 9600 through the central processor 9100.

[0163] The memory 9140 may also include a data storage unit 9143 for storing data, such as contacts, digital data, pictures, sounds, and / or any other data used by the electronic device. The driver storage unit 9144 of the memory 9140 may include various drivers for communication functions of the electronic device and / or for executing other functions of the electronic device (such as messaging applications, address book applications, etc.).

[0164] The communication module 9110 is a transmitter / receiver that sends and receives signals via the antenna 9111. The communication module 9110 (transmitter / receiver) is coupled to the central processor 9100 to provide input signals and receive output signals, which may be the same as the case of a conventional mobile communication terminal.

[0165] Based on different communication technologies, multiple communication modules 9110 may be provided in the same electronic device, such as a cellular network module, a Bluetooth module and / or a wireless LAN module. The communication module 9110 (transmitter / receiver) is also coupled to a speaker 9131 and a microphone 9132 via an audio processor 9130 to provide an audio output via the speaker 9131 and receive an audio input from the microphone 9132, thereby realizing a common telecommunication function. The audio processor 9130 may include any suitable buffer, decoder, amplifier, etc. In addition, the audio processor 9130 is also coupled to the central processor 9100, so that recording can be performed on the local machine through the microphone 9132, and the sound stored on the local machine can be played through the speaker 9131.

[0166] The embodiments of the present application also provide a computer-readable storage medium capable of implementing all the steps of the chip platform resource dynamic scheduling method in the above-mentioned embodiment, where the execution subject is a server or a client. The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, all the steps of the chip platform resource dynamic scheduling method in the above-mentioned embodiment are implemented. For example, when the processor executes the computer program, the following steps are implemented:

[0167] Step S101: deploy resource monitoring probes to collect the operating status of the chip platform, build a resource usage indicator database to record CPU utilization and memory bandwidth data, analyze the timing characteristics and change rules of the operating status to establish a load model, use the load model to predict the resource usage trend, use a performance evaluator to build a system bottleneck identification model, set resource thresholds based on the system bottleneck identification model, formulate scheduling rules through a policy generator, and create a resource configuration plan based on the resource thresholds and the scheduling rules;

[0168] Step S102: construct a dynamic scheduler to convert the resource configuration scheme into execution instructions, design a unified resource allocation interface to support cross-platform scheduling, create a task planner to prioritize the execution instructions, build a resource optimizer to perform load balancing and resource integration, and construct a task time matrix by calculating the estimated completion time of each execution instruction in each processing unit. Based on the task time matrix, select the processing unit with the minimum completion time to assign tasks, use a dynamic time slice calculation module to dynamically adjust the polling time slice size according to the task priority, use a task status monitor to track the running status of the execution instruction, dynamically adjust the migration strategy of the task between processing units based on the running status, establish a virtualization manager to handle container creation, create a quota controller to manage the restriction parameters of the resource configuration scheme, and use an execution engine to send the optimized execution instruction to the chip platform;

[0169] Step S103: Load the monitoring data of the resource monitoring probe at runtime, analyze the system status through the system bottleneck identification model, query the resource usage indicator database to obtain historical data, select the corresponding optimization strategy according to the scheduling rules, build a feedback collection queue, use data analysis technology to evaluate the scheduling effect of the execution instruction, input the scheduling effect into the evaluation model for verification, and update the scheduling rules based on the verification results of the evaluation model.

[0170] From the above description, it can be seen that the computer-readable storage medium provided in the embodiment of the present application collects the operating status of the chip platform by deploying resource monitoring probes, builds a resource usage indicator database to record CPU utilization and memory bandwidth data, analyzes the timing characteristics and change rules of the operating status to establish a load model, sets resource thresholds based on the system bottleneck identification model, formulates scheduling rules through a policy generator, and creates a resource configuration plan based on resource thresholds and scheduling rules; analyzes the system status through the system bottleneck identification model, selects the corresponding optimization strategy according to the scheduling rules, builds a feedback collection queue, uses data analysis technology to evaluate the scheduling effect of executing instructions, inputs the scheduling effect into the evaluation model for verification, and updates the scheduling rules based on the verification results of the evaluation model, thereby effectively improving the system's resource management efficiency and performance, and achieving more flexible cross-platform support.

[0171] The embodiments of the present application also provide a computer program product capable of implementing all the steps of the chip platform resource dynamic scheduling method in the above embodiments, where the execution subject is a server or a client. When the computer program / instruction is executed by a processor, the steps of the chip platform resource dynamic scheduling method are implemented. For example, the computer program / instruction implements the following steps:

[0172] Step S101: deploy resource monitoring probes to collect the operating status of the chip platform, build a resource usage indicator database to record CPU utilization and memory bandwidth data, analyze the timing characteristics and change rules of the operating status to establish a load model, use the load model to predict the resource usage trend, use a performance evaluator to build a system bottleneck identification model, set resource thresholds based on the system bottleneck identification model, formulate scheduling rules through a policy generator, and create a resource configuration plan based on the resource thresholds and the scheduling rules;

[0173] Step S102: construct a dynamic scheduler to convert the resource configuration scheme into execution instructions, design a unified resource allocation interface to support cross-platform scheduling, create a task planner to prioritize the execution instructions, build a resource optimizer to perform load balancing and resource integration, and construct a task time matrix by calculating the estimated completion time of each execution instruction in each processing unit. Based on the task time matrix, select the processing unit with the minimum completion time to assign tasks, use a dynamic time slice calculation module to dynamically adjust the polling time slice size according to the task priority, use a task status monitor to track the running status of the execution instruction, dynamically adjust the migration strategy of the task between processing units based on the running status, establish a virtualization manager to handle container creation, create a quota controller to manage the restriction parameters of the resource configuration scheme, and use an execution engine to send the optimized execution instruction to the chip platform;

[0174] Step S103: Load the monitoring data of the resource monitoring probe at runtime, analyze the system status through the system bottleneck identification model, query the resource usage indicator database to obtain historical data, select the corresponding optimization strategy according to the scheduling rules, build a feedback collection queue, use data analysis technology to evaluate the scheduling effect of the execution instruction, input the scheduling effect into the evaluation model for verification, and update the scheduling rules based on the verification results of the evaluation model.

[0175] From the above description, it can be seen that the computer program product provided in the embodiment of the present application collects the operating status of the chip platform by deploying resource monitoring probes, builds a resource usage indicator database to record CPU utilization and memory bandwidth data, analyzes the timing characteristics and change rules of the operating status to establish a load model, sets resource thresholds based on the system bottleneck identification model, formulates scheduling rules through a policy generator, and creates a resource configuration plan based on resource thresholds and scheduling rules; analyzes the system status through the system bottleneck identification model, selects the corresponding optimization strategy according to the scheduling rules, builds a feedback collection queue, uses data analysis technology to evaluate the scheduling effect of executing instructions, inputs the scheduling effect into the evaluation model for verification, and updates the scheduling rules based on the verification results of the evaluation model, thereby effectively improving the system's resource management efficiency and performance, and achieving more flexible cross-platform support.

[0176] It should be understood by those skilled in the art that embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0177] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (apparatus), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0178] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0179] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0180] The present invention uses specific embodiments to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A chip platform resource dynamic scheduling method, characterized in that: The method comprises: Deploy resource monitoring probes to collect the operating status of the chip platform, build a resource usage indicator database to record CPU utilization and memory bandwidth data, analyze the timing characteristics and change rules of the operating status to establish a load model, use the load model to predict the resource usage trend, use the performance evaluator to build a system bottleneck identification model, set resource thresholds based on the system bottleneck identification model, formulate scheduling rules through a policy generator, and create a resource configuration plan based on the resource thresholds and the scheduling rules; Construct a dynamic scheduler to convert the resource configuration scheme into execution instructions, design a unified resource allocation interface to support cross-platform scheduling, create a task planner to prioritize the execution instructions, construct a resource optimizer to perform load balancing and resource integration, and construct a task time matrix by calculating the estimated completion time of each execution instruction in each processing unit. Based on the task time matrix, select the processing unit with the minimum completion time to assign tasks. Use a dynamic time slice calculation module to dynamically adjust the size of the polling time slice according to the task priority. Use a task status monitor to track the running status of the execution instruction. Based on the running status, dynamically adjust the migration strategy of the task between processing units. Establish a virtualization manager to handle container creation, create a quota controller to manage the restriction parameters of the resource configuration scheme, and use an execution engine to send the optimized execution instructions to the chip platform. Load the monitoring data of the resource monitoring probe at runtime, analyze the system status through the system bottleneck identification model, query the resource usage indicator database to obtain historical data, select the corresponding optimization strategy according to the scheduling rules, build a feedback collection queue, use data analysis technology to evaluate the scheduling effect of the execution instruction, input the scheduling effect into the evaluation model for verification, and update the scheduling rules based on the verification results of the evaluation model.

2. The chip platform resource dynamic scheduling method according to claim 1, characterized in that: The resource monitoring probe is deployed to collect the operating status of the chip platform, a resource usage indicator database is constructed to record CPU utilization and memory bandwidth data, and the timing characteristics and change rules of the operating status are analyzed to establish a load model, including: Collect processor operating frequency data through performance counters, obtain processor status information using system call interfaces, deploy memory monitoring modules to record memory usage data, set network monitors to collect bandwidth data, store the operating frequency data, processor status information, memory usage data, and bandwidth data in a time series database, and establish data collection triggers to control the sampling frequency of the time series database; The data in the time series database is standardized, the standardized data is segmented using a time window method, a state transfer matrix is ​​constructed to describe the changing pattern of the segmented data, a data analysis method is applied to identify resource usage characteristics from the state transfer matrix, and a prediction model is established to analyze the resource usage characteristics.

3. The chip platform resource dynamic scheduling method according to claim 1, characterized in that: The method of using the load model to predict resource usage trends, using a performance evaluator to build a system bottleneck identification model, setting resource thresholds based on the system bottleneck identification model, formulating scheduling rules through a policy generator, and creating a resource configuration plan based on the resource thresholds and the scheduling rules includes: Input the output data of the load model into the performance evaluator, use a resource dependency graph to describe the relationship between system resources, build a performance scoring matrix based on the resource dependency graph, use a performance indicator weight vector to calculate the performance scores of each system, identify the bottleneck resources in the system according to the performance scores, and generate the system bottleneck identification model; Based on the bottleneck resources, an upper threshold and a lower threshold of resource usage are set, a resource scheduling policy library is constructed to store scheduling rule templates, the scheduling rule template is selected according to the upper threshold and the lower threshold, a scheduling rule including resource allocation parameters is generated, and the scheduling rule is applied to a resource configuration generator to create a resource configuration plan.

4. The chip platform resource dynamic scheduling method according to claim 1, characterized in that: The construction of the dynamic scheduler converts the resource configuration scheme into execution instructions, designs a unified resource allocation interface to support cross-platform scheduling, creates a task planner to prioritize the execution instructions, and constructs a resource optimizer to perform load balancing and resource integration, including: Parse the resource allocation parameters in the resource configuration scheme, construct an instruction conversion module to map the resource allocation parameters into a target platform instruction format, design a unified scheduling interface specification to define a resource operation instruction set, generate a cross-platform resource allocation instruction according to the instruction set, and encapsulate the resource allocation instruction into an execution instruction sequence; Obtain resource requirement information of the execution instruction sequence, calculate the resource occupancy ratio of each execution instruction, set the execution instruction priority based on the resource occupancy ratio, build a priority queue to store the execution instructions, use a load balancing algorithm to adjust the distribution of the execution instructions among processing units, and merge execution instructions with resource affinity to optimize resource utilization.

5. The chip platform resource dynamic scheduling method according to claim 1, characterized in that: The method comprises: constructing a task time matrix by calculating the estimated completion time of each execution instruction in each processing unit, selecting a processing unit with the minimum completion time to assign tasks based on the task time matrix, and dynamically adjusting the polling time slice size according to the task priority using a dynamic time slice calculation module, including: Extracting the computational complexity parameter of the execution instruction, obtaining the processing capability index of each processing unit, calculating the estimated execution time according to the computational complexity parameter and the processing capability index, establishing a task processing unit mapping table to record the estimated execution time, and generating a task time matrix including the estimated execution time; The step of dynamically adjusting the size of the polling time slice includes: reading the execution time estimate in the task time matrix, selecting the processing unit with the smallest execution time estimate as the target processing unit, obtaining the priority value of the execution instruction, calculating the time slice reference value based on the priority value, dynamically adjusting the time slice reference value according to the system load status, and allocating the adjusted time slice to the target processing unit.

6. The chip platform resource dynamic scheduling method according to claim 5, characterized in that: The method includes using a task status monitor to track the running status of the execution instruction, dynamically adjusting the migration strategy of the task between processing units based on the running status, establishing a virtualization manager to process container creation, creating a quota controller to manage the restriction parameters of the resource configuration scheme, and using an execution engine to send the optimized execution instruction to the chip platform, including: Collecting real-time operating parameters of the execution instruction, recording resource occupancy of the execution instruction on the target processing unit, detecting the load level of the target processing unit, triggering task migration when the load level exceeds a preset threshold, calculating the task migration overhead, selecting a target migration processing unit, and migrating the execution instruction to the target migration processing unit; Parse the resource limitation parameters in the resource configuration scheme, create a virtualized container isolation task running environment, set the resource quota limit of the virtualized container, build a resource usage quota control table, write the resource limitation parameters into the quota control table, and send the execution instruction and the quota control table to the target processing unit through the execution engine.

7. The chip platform resource dynamic scheduling method according to claim 6, characterized in that: The step of selecting a corresponding optimization strategy according to the scheduling rule, constructing a feedback collection queue, using data analysis technology to evaluate the scheduling effect of the execution instruction, inputting the scheduling effect into an evaluation model for verification, and updating the scheduling rule based on the verification result of the evaluation model includes: Read resource usage data from the resource usage quota control table, build a loop feedback queue to store the resource usage data, calculate the resource utilization efficiency of the target processing unit, match the resource utilization efficiency with the optimization target in the scheduling rule, and select the optimization strategy with the highest matching degree from the preset optimization strategy library; Extract performance indicators from the resource usage data, calculate the deviation between the actual completion time of the execution instruction and the estimated execution time, count the throughput data of the target processing unit, input the deviation and the throughput data into an evaluation model, judge the scheduling effect according to the output result of the evaluation model, and update the parameters of the scheduling rule based on the scheduling effect.

8. A chip platform resource dynamic scheduling device, characterized in that: The device comprises: A resource scheduling module is used to deploy resource monitoring probes to collect the operating status of the chip platform, build a resource usage indicator database to record CPU utilization and memory bandwidth data, analyze the timing characteristics and change rules of the operating status to establish a load model, use the load model to predict the resource usage trend, use a performance evaluator to build a system bottleneck identification model, set resource thresholds based on the system bottleneck identification model, formulate scheduling rules through a policy generator, and create a resource configuration plan based on the resource thresholds and the scheduling rules; A resource allocation module is used to build a dynamic scheduler to convert the resource configuration scheme into execution instructions, design a unified resource allocation interface to support cross-platform scheduling, create a task planner to prioritize the execution instructions, build a resource optimizer to perform load balancing and resource integration, build a task time matrix by calculating the estimated completion time of each execution instruction in each processing unit, select the processing unit with the minimum completion time based on the task time matrix to assign tasks, use a dynamic time slice calculation module to dynamically adjust the polling time slice size according to the task priority, use a task status monitor to track the running status of the execution instruction, dynamically adjust the migration strategy of the task between processing units based on the running status, establish a virtualization manager to handle container creation, create a quota controller to manage the restriction parameters of the resource configuration scheme, and use an execution engine to send the optimized execution instructions to the chip platform; A dynamic optimization module is used to load the monitoring data of the resource monitoring probe at runtime, analyze the system status through the system bottleneck identification model, query the resource usage indicator database to obtain historical data, select the corresponding optimization strategy according to the scheduling rules, build a feedback collection queue, use data analysis technology to evaluate the scheduling effect of the execution instruction, input the scheduling effect into the evaluation model for verification, and update the scheduling rules based on the verification results of the evaluation model.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the steps of the chip platform resource dynamic scheduling method described in any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the chip platform resource dynamic scheduling method described in any one of claims 1 to 7 are implemented.

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