Integrated circuit (IC) packages with wire bonding channels over a package

Abstract

Integrated circuit (IC) packages employing wire bond channels over a package substrate and related methods of manufacture. The IC package includes a first semiconductor die ("first die") and a first electronic device, each coupled to a package substrate. In order to provide a signal routing path between the first die and the first electronic device, the IC package includes a wire bonding channel, the wire bond channel includes a wire bond coupled between first and second metal pads coupled to the respective first die and first electronic device to provide a signal routing path between the first die and the first electronic device. The wire bond extends outside the package substrate in the vertical direction. The wire bond channel may be capable of supporting a more direct signal routing path between the first die and the first electronic device without having to wire such signal routing paths around KoZ in the package substrate.

Description

Background Art

[0001] I. Public Domain

[0002] The field of the present disclosure relates to integrated circuit (IC) packages including one or more semiconductor dies supported by a packaging substrate, and more particularly to communicatively coupling a semiconductor die in the IC package to another electronic device (eg, another die) in the IC package.

[0003] II. Background

[0004] Integrated circuits (ICs) are the cornerstone of electronic devices. ICs are packaged in IC packages (also referred to as "semiconductor packages" or "chip packages"). The IC package includes one or more semiconductor dies mounted on a package substrate and electrically coupled to the package substrate to provide physical support and electrical interfaces for the die(s). The die(s) are electrically connected to metal interconnects (e.g., metal traces, metal wires) in the top metallization layer of the package substrate. The package substrate may also include one or more other metallization layers, which include metal interconnects (e.g., metal traces, metal wires) with vertical interconnect paths (through holes) that couple these metal interconnects together between adjacent metallization layers to provide an electrical interface to the die(s) through the package substrate. The package substrate also includes a bottom external metallization layer, which includes metal interconnects coupled to external metal interconnects (e.g., ball grid array (BGA) interconnects) to provide an external interface between the die(s) in the IC package. External metal interconnects may also be coupled (eg, soldered) to traces in a printed circuit board (PCB) to attach the IC package to the PCB, thereby interfacing its die(s) with other circuitry coupled to the PCB.

[0005] A plurality of ICs may be mounted to a package substrate in an IC package. For example, an IC package may include a system-on-chip (SoC) die and a second die coupled to a package substrate. For example, the second die may include a security circuit, a memory, or other circuits that are desired to be provided in a die separated from the SoC in the IC package. In order to provide a communication interface to the second die, the second die is coupled to a metal line (e.g., a metal trace) in one or more metallization layers of the package substrate. These metal lines provide signal routing to and from the second die through the package substrate. For example, some of these metal trace lines may be routed and coupled to the SoC die to support die-to-die (D2D) communication between the SoC die and the second die. The second die may be placed on an external metallization layer of the package substrate or adjacent to the external metallization layer of the package substrate to allow tighter connectivity to the SoC die. The second die may also be coupled to a metal line in a lower metallization layer of the package substrate under the external metallization layer. Placing the second die on the package substrate provides a keep-out zone (KoZ) area in the package substrate, in which other metal lines used to route other signals to other electronic devices in the IC package may have to be avoided and routed around in the first horizontal direction (X-axis and Y-axis direction). For example, metal lines in the metallization layer of the package substrate that route signals between the SoC die and other electronic devices in the IC package may have to be routed around the KoZ area of ​​the second die in the package substrate. This results in a longer length of these signals carried on these other metal lines routed around the KoZ area, thereby increasing the signal path impedance, resulting in additional signal delays in these signals. In addition, the routing of metal lines around the KoZ area may require these metal lines to have more bends, thereby contributing to increased parasitic capacitance. The routing of metal lines around the KoZ area may also result in less efficient signal routing and use of routing space in the package substrate, which may result in an increase in the area (in the first horizontal direction, in the X-axis and Y-axis directions) and / or number (in the vertical height, the Z-axis direction) of the metallization layers required to provide sufficient signal routing in the package substrate, and an increase in cost.

[0006] Public Overview

[0007] Various aspects disclosed herein include an integrated circuit (IC) package that employs wire bonding channels on a packaging substrate. Related manufacturing methods are also disclosed. The IC package includes a first semiconductor die ("first die") (e.g., a system-on-chip (SoC) die) coupled to a packaging substrate extending in a first horizontal direction. The first die is coupled to metal interconnects in the metallization layer(s) of the packaging substrate for routing signals to and from the first die through metal lines in the metallization layer(s). The IC package also includes a first electronic device coupled to the packaging substrate. The first electronic device may be placed on the packaging substrate so that a keep-out zone (KoZ) in the packaging substrate will be located entirely or partially in a direct signal routing path between the first electronic device and the first die in the packaging substrate. For example, the KoZ may be the result of another electronic device placed on the packaging substrate between the first die and the first electronic device. In another example, the KoZ may be the result of other signal routing paths in the packaging substrate. In an exemplary aspect, in order to provide a signal routing path between a first tube core and a first electronic device in an IC package, the IC package includes a wire bonding channel coupled to the first tube core and the first electronic device. The wire bonding channel includes a first metal pad coupled to the package substrate and the first tube core. The wire bonding channel also includes a second metal pad coupled to the package substrate and the first electronic device. The wire bonding channel includes wire bonds, each wire bond is coupled to a corresponding first metal pad and a second metal pad to provide a signal routing path between the first metal pad and the second metal pad to provide a signal routing pad between the first tube core and the first electronic device. The wire bond extends from the first metal pad to the second metal pad outside the package substrate in a second vertical direction orthogonal to the first direction. In this way, the wire bonding channel can be able to support a more direct signal routing path between the first tube core and the first electronic device without having to route such signal routing path around the KoZ in the package substrate.

[0008] In one example, the IC package also includes a second electronic device (e.g., a second die or a deep trench capacitor (DTC)) coupled to the package substrate and adjacent to the first chip. The second electronic device is also coupled to a metal interconnect in the metallization layer(s) of the package substrate to provide a signal routing path to and from the second electronic device through metal lines in the metallization layer(s). The second electronic device is placed on the package substrate so that a signal routing KoZ for the second electronic device exists in the package substrate and is in whole or in part in a direct signal routing path between the first die and the first electronic device in the package substrate. In this regard, a first metal pad of a wire bonding channel is arranged adjacent to a first side of the second electronic device, between the first die and the second electronic device in a first horizontal direction of the package substrate. A second metal pad is arranged adjacent to a second side of the second electronic device and is coupled to the package substrate and the first electronic device. The wire bonding of the wire bonding channel extends from the first metal pad to the second metal pad outside the package substrate and in a second vertical direction above the second electronic device. In this way, the wire bond channel supports more direct signal routing between the first die and the first electronic device without having to provide a less direct signal routing path around a signal routing KoZ in the package substrate.

[0009] In another example, a packaging substrate of an IC package includes other signal routing paths in a metallization layer of the packaging substrate that provide a signal routing KoZ in the packaging substrate between a first metal pad and a second metal pad of a wire bonding channel in a first horizontal direction (X-axis and Y-axis directions). The wire bonding of the wire bonding channel is outside the packaging substrate and extends from the first metal pad to the second metal pad above the signal routing KoZ in a second vertical direction. In this way, the wire bonding channel can be able to support more direct signal routing between the first die and the first electronic device without having to provide a less direct signal routing path in the packaging substrate due to having to route around the signal routing KoZ in the packaging substrate.

[0010] In this regard, in an exemplary aspect, an IC package is provided. The IC package includes a package substrate, the package substrate including a first surface extending in a first direction. The IC package also includes a first tube core coupled to the first surface of the package substrate. The IC package also includes a wire bonding channel. The wire bonding channel includes one or more first metal pads, the one or more first metal pads are coupled to the first surface of the package substrate and coupled to the first tube core. The wire bonding channel also includes one or more second metal pads, the one or more second metal pads are coupled to the first surface of the package substrate. The wire bonding channel also includes one or more wire bonds, the one or more wire bonds are arranged outside the package substrate, and each of the one or more wire bonds couples a corresponding first metal pad of the one or more first metal pads to a corresponding second metal pad of the one or more second metal pads.

[0011] In another exemplary aspect, a method for manufacturing an integrated circuit (IC) package is provided. The method includes providing a package substrate, the package substrate including a first surface extending in a first direction. The method also includes coupling a first die to the first surface of the package substrate. The method also includes forming a wire bonding channel, including: forming one or more first metal pads coupled to the first surface of the package substrate and coupled to the first die; forming one or more second metal pads coupled to the first surface of the package substrate; coupling a first end of each of the one or more wire bonds to the one or more first metal pads outside the package substrate; and coupling a second end of each of the one or more wire bonds to the one or more second metal pads outside the package substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a top view of an exemplary integrated circuit (IC) package including a first semiconductor die ("die") and a first electronic device adjacent to each other and coupled to a first outer surface of a package substrate, wherein metallization layer(s) in the package substrate includes a signal routing path for the first electronic device routed in a first horizontal direction around a signal routing keep-out zone (KoZ) in the package substrate;

[0014] Figure 2A is a side view of an exemplary IC package including a first die and a first electronic device adjacent to each other and coupled to a first outer surface of a package substrate, and further including a wire bond channel including a wire bond extending at least partially over the first electronic device in a second vertical direction to support a more direct signal routing path between the first die and the first electronic device without having to route such signal routing path around a signal routing KoZ in the package substrate for the first electronic device;

[0015] Figure 2B yes Figure 2A A top view of the IC package in FIG.

[0016] Figure 2C yes Figure 2A A close-up top view of the IC package in Figure 1.

[0017] Figure 3 is a top view of another package substrate including a signal routing path in a metallization layer surrounding a signal routing KoZ wiring in the metallization layer;

[0018] Figure 4A is a side view of another exemplary IC package including a first die coupled to a first outer surface of a package substrate, and further including a wire bond channel including a wire bond extending from a first metal pad coupled to the first die to a second metal pad outside the package substrate and above a signal routing KoZ in the package substrate in a second vertical direction to support a more direct signal routing path between the first die and the second metal pad;

[0019] Figure 4B yes Figure 4A A top view of the IC package in FIG.

[0020] Figure 5 is a flow chart illustrating an exemplary manufacturing process for manufacturing an IC package, the IC package including a first die coupled to a first outer surface of a package substrate, and further including a wire bond channel including a wire bond extending from a first metal pad coupled to the first die to a second metal pad above a signal routing path KoZ in the package substrate outside the package substrate and in a second vertical direction to support a more direct signal routing path between the first die and the second metal pad, including but not limited to Figures 2A-2C and the IC packages in 4A-4B;

[0021] Figures 6A-6C is a flow chart illustrating another exemplary manufacturing process for manufacturing an IC package, the IC package including a first die coupled to a first outer surface of a package substrate, and further including a wire bond channel including a wire bond extending from a first metal pad coupled to the first die to a second metal pad above a signal routing path KoZ in the package substrate outside the package substrate and in a second vertical direction to support a more direct signal routing path between the first die and the second metal pad, including but not limited to Figures 2A-2C and the IC packages in 4A-4B;

[0022] Figures 7A-7F is based on Figures 6A-6Cexemplary manufacturing stages during the manufacture of an IC package of the exemplary manufacturing process of FIG.

[0023] Figure 8 is a block diagram of an exemplary processor-based system that may include components that may include an IC package including a first die coupled to a first outer surface of a package substrate, and further including a wire bond channel including a wire bond extending from a first metal pad coupled to the first die to a second metal pad above a signal routing KoZ in the package substrate outside the package substrate and in a second vertical direction to support a more direct signal routing path between the first die and the second metal pad, including but not limited to Figures 2A-2C , 4A-4B and 7A-7F and based on but not limited to Figure 5-6C IC packaging of any exemplary manufacturing process of; and

[0024] Fig. 9 is a block diagram of an exemplary wireless communication device including radio frequency (RF) components that may include an IC package including a first die coupled to a first outer surface of a package substrate, and further including a wire bond channel including a wire bond extending from a first metal pad coupled to the first die to a second metal pad above a signal routing path KoZ in the package substrate outside the package substrate and in a second vertical direction to support a more direct signal routing path between the first die and the second metal pad, including but not limited to Figures 2A-2C , 4A-4B and 7A-7F and based on but not limited to Figure 5-6C An IC package of any exemplary manufacturing process.

[0025] Detailed Description

[0026] Referring now to the accompanying drawings, several exemplary aspects of the present disclosure are described. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or superior to other aspects.

[0027] Various aspects disclosed herein include an integrated circuit (IC) package that employs wire bonding channels on a packaging substrate. Related manufacturing methods are also disclosed. The IC package includes a first semiconductor die ("first die") (e.g., a system-on-chip (SoC) die) coupled to a packaging substrate extending in a first horizontal direction. The first die is coupled to metal interconnects in the metallization layer(s) of the packaging substrate for routing signals to and from the first die through metal lines in the metallization layer(s). The IC package also includes a first electronic device coupled to the packaging substrate. The first electronic device may be placed on the packaging substrate so that a keep-out zone (KoZ) in the packaging substrate will be located entirely or partially in a direct signal routing path between the first electronic device and the first die in the packaging substrate. For example, the KoZ may be the result of another electronic device placed on the packaging substrate between the first die and the first electronic device. In another example, the KoZ may be the result of other signal routing paths in the packaging substrate. In an exemplary aspect, in order to provide a signal routing path between a first tube core and a first electronic device in an IC package, the IC package includes a wire bonding channel coupled to the first tube core and the first electronic device. The wire bonding channel includes a first metal pad coupled to the package substrate and the first tube core. The wire bonding channel also includes a second metal pad coupled to the package substrate and the first electronic device. The wire bonding channel includes wire bonds, each wire bond is coupled to a corresponding first metal pad and a second metal pad to provide a signal routing path between the first metal pad and the second metal pad to provide a signal routing pad between the first tube core and the first electronic device. The wire bond extends from the first metal pad to the second metal pad outside the package substrate in a second vertical direction orthogonal to the first direction. In this way, the wire bonding channel can be able to support a more direct signal routing path between the first tube core and the first electronic device without having to route such signal routing path around the KoZ in the package substrate.

[0028] In from Figure 2A Before discussing examples of IC packages that include wire bond channels coupled to a first die, wherein the wire bond channels include wire bonds that extend above a package substrate to support a more direct signal routing path to the first die, the following first describes an example of an IC package that includes a wire bond channel coupled to a first die. Figure 1 Examples of IC packages that include wire bonding channels external to a package substrate are described.

[0029] Figure 11 is a top view of an exemplary integrated circuit (IC) package 100, which includes a first semiconductor die ("die") 102 coupled to a packaging substrate 104. The first die 102 is coupled to a first outer surface 106 of the packaging substrate 104. For example, the first die 102 can be a system-on-chip (SoC) die. The first die 102 is coupled to an external metallization layer 108 of the packaging substrate 104. The external metallization layer 108 and other metallization layers in the packaging substrate 104 that are located below the external metallization layer 108 in a first vertical direction (Z-axis direction) include metal lines interconnected by metal interconnects to provide signal routing paths in the packaging substrate 104. The packaging substrate 104 includes metal lines that provide signal routing paths for communications to the first die 102. The IC package 100 also includes a second die 110 that is also coupled to the packaging substrate 104. For example, the second die 110 may include security circuitry, memory, or other circuitry that is desired to be provided in a separate die from the first die 102 in the IC package 100. The second die 110 is also coupled to an external metallization layer 108 of the package substrate 104. The package substrate 104 also includes metal lines that provide signal routing paths for communications to the second die 110. For example, some of the metal lines in the package substrate 104 may be coupled to both the first die 102 and the second die 110 to support die-to-die (D2D) communications between the first die 102 and the second die 110.

[0030] Continue to refer to Figure 1 , the second die 110 is placed on the package substrate 104 adjacent to the first die 102. Placing the second die 110 on the package substrate 104 may provide a keep-out zone (KoZ) area 112 in the outer metallization layer 108 and / or other metallization layers of the package substrate 104 below the second die 110 in a first vertical direction (Z-axis direction). Other metal lines used to route other signals from the first die 102 to other electronic devices in the IC package 100 may have to avoid and route around the KoZ area 112 in a first horizontal direction (X-axis and Y-axis directions). This Figure 1, where metal lines 114 (shown as hidden lines) in a metallization layer (such as an outer metallization layer 108) in a packaging substrate 104 and coupled to a first die 102 are routed around a KoZ region 112 in the packaging substrate 104. This results in the length of these metal lines 114 being longer than it would otherwise be if the metal lines 114 could be routed in the packaging substrate below the second die 110 (i.e., within the packaging substrate 104 in a vertical space (Z-axis) of the footprint of the second die 110), thereby increasing the impedance of the metal lines 114. This causes the signals carried on the metal lines 114 to experience additional delays. Furthermore, by bending the metal lines 114 around the KoZ region 112, the metal lines 114 may have increased parasitic capacitance, which also results in signal delays. Furthermore, the routing of the metal lines 114 around the KoZ region 112 may also result in less efficient signal routing and use of routing space in the packaging substrate 104. This may result in increased area (in the first horizontal direction, in the X and Y directions) and / or number (in the vertical height, in the Z direction) of metallization layers required to provide adequate signal routing in the packaging substrate 104, and increased cost.

[0031] Figure 2A and 2B 2 are respective side and top views of an exemplary IC package 200, the IC package 200 including a wire bonding channel 202 coupled to a first die 204 to provide a communication channel to the first die 204. The wire bonding channel 202 includes a wire bond 206, which extends over a package substrate 208 to support a more direct signal routing path to the first die 204. For example, the wire bonding channel 202 can be coupled to another component (the other component is coupled to the package substrate 208) to provide a communication link between the first die 204 and the other component. In this example, the first die 204 is coupled to a first surface 210 of the package substrate 208. As an example, the package substrate 208 can be a core package substrate or a coreless package substrate. The package substrate 208 can be formed by laminating metallization layers, or by a stacking process of forming metallization layers on top of each other. In this example, the first surface 210 is a planar surface or a substantially planar surface extending in a horizontal direction in the X-axis and Y-axis directions. For example, the first surface 210 may be an outer surface of the outer metallization layer 212 (1) of the package substrate 208. Figure 2A, the first die 204 can be coupled to a metal interconnect 214(1) in an external metallization layer 212(1) to couple the first die 204 to a package substrate 208, thereby providing a signal routing path between the package substrate 208 and the first die 204. As an example, the external metallization layer 212(1) can be formed as an embedded trace substrate (ETS) layer. The metal interconnect 214(1) forms or is coupled to a metal line 216(1) in the external metallization layer 212(1), and the metal line 216(1) provides a signal routing path in the package substrate 208. As an example, the metal line 216(1) can be formed as a redistribution line (RDL). The metal line 216(1) in the external metallization layer 212(1) can also be coupled to the metal lines 216(2)-216(4) in other metallization layers 212(2)-212(4) via metal interconnects 214(2)-214(4) (e.g., vias, metal pillars) to provide a signal routing path in the packaging substrate 208.

[0032] Continue to refer to Figure 2A and 2B , a second electronic device 218 in the form of a second die 220 may also be coupled to the first surface 210 of the packaging substrate 208. Alternatively, the second electronic device 218 may be a deep trench capacitor (DTC), which includes a capacitor formed in a trench embedded in a semiconductor substrate similar to the semiconductor substrate of the die. The second die 220 is arranged adjacent to the first die 204 on the first surface 210 of the packaging substrate 208. In this example, a first side 222 of the second die 220 is adjacent to the first die 204. The second die 220 is also coupled to a metal interconnect 214(1) in the external metallization layer 212(1) to couple the second die 220 to the packaging substrate 208, thereby providing a signal routing path between the packaging substrate 208 and the second die 220. The metal interconnect 214(1) is formed or coupled to a metal line 216(5) in the outer metallization layer 212(1) below the second die 220 in a second vertical direction (Z-axis direction), and the metal line 216(5) provides a signal routing path for the second die 220 in the package substrate 208. The metal line 216(5) in the outer metallization layer 212(1) can also be coupled to other metal lines 216(2)-216(4) in other metallization layers 212(2)-212(4) via a metal interconnect 214(2) (e.g., a via, a metal pillar) to provide a signal routing path in the package substrate 208. In this example, the second die 220 creates a KoZ region 224 in the package substrate 208, as shown in FIG. Figure 2A As shown in the side view of the IC package 200 in FIG. 1 , this is because the metal lines 216 ( 5 ), 216 ( 6 ) provided in the KoZ region 224 are dedicated to routing signals to the second die 220 . The KoZ region 224 is Figure 2B 2 is shown in hidden lines in the top view of the IC package 200 in . Thus, in this example, the KoZ area 224 is an area defined by metal lines 216 (5), 216 (6) in the metallization layers 212 (1), 212 (2) that are not used to route signals to other components independent of the second die 220. The KoZ area 224 extends in a first horizontal direction in the X-axis and Y-axis directions together with the package substrate 208. The KoZ area 224 also extends in a second vertical direction (Z-axis direction) within the package substrate 208. Therefore, the KoZ area 224 has a horizontal area footprint in the first horizontal direction in the X-axis and Y-axis directions, which extends in a vertical direction (Z-axis direction). Other signal routing paths that must pass within the area of ​​the KoZ area 224 must be routed outside the KoZ area 224 so as not to interfere with the signal routing paths provided by the metal lines 216 (5), 216 (6).

[0033] Continue to refer to Figure 2A and 2B In order to provide signal routing paths to the first die 204, these signal routing paths are desirably routed through the KoZ region 224 of the package substrate 208 to avoid having to route such signal routing paths around the KoZ region 224 (eg, Figure 1), a wire bonding channel 202 is provided. In this example, the wire bonding channel 202 is formed by a first metal pad 226(1) and a second metal pad 226(2) formed on the packaging substrate 208. For example, the first metal pad 226(1) and the second metal pad 226(2) can be formed on the first surface 210 of the packaging substrate 208. The first and second metal pads 226(1), 226(2) can be bonding pads made of metal, such as a lead material that can be bonded (e.g., welded) to a wire. The first metal pad 226(1) and the second metal pad 226(2) are coupled to corresponding metal lines 216(5) in the external metallization layer 212(1) of the packaging substrate 208 to provide a signal routing path between the first and second metal pads 226(1), 226(2) and the packaging substrate 208. In this example, the first metal pad 226(1) is located adjacent to the first die 204, between the first die 204 and the first side 222 of the second die 220. The second metal pad 226(2) is located adjacent to the second die 220, adjacent to the second side 222(2) of the second die 220 on the opposite side of the first side 222(1) of the second die 220. The first metal pad 226(1) is coupled to the first die 204 by being coupled to the metal interconnect 214(1) of the first metal line 216(1) exposed from the first surface 210 of the packaging substrate 208. The second metal pad 226(2) is coupled to the metal interconnect 214(1) of the metal line 216(1) exposed from the first surface 210 of the packaging substrate 208. Figure 2B As shown in Figure 2C As shown in more detail in the top view of the IC package 200 in FIG. 1 , wire bonds 206 are provided, which are metal wires coupled (e.g., bonded) to first and second metal pads 226(1), 226(2) at their respective first and second ends 228(1), 228(2) to provide a conductive connection between the first and second metal pads 226(1), 226(2). The wire bonds 206 are external to and outside of the package substrate 208. The wire bonds 206 in this example extend over the first surface 210 of the package substrate 208 and over the second die 220 in a second vertical direction (Z-axis direction) orthogonal to the first horizontal direction (X-axis and Y-axis directions) of the first surface 210. In this example, each wire bond 206 intersects a vertical plane P1 in the vertical direction (Z-axis direction), which also intersects the second die 220. The vertical plane P1 is orthogonal to the first horizontal direction (X-axis and Y-axis directions) of the package substrate 208. However, it is not required that each wire bond 206 intersect the vertical plane P1 that also intersects the second die 220 .

[0034] In this manner, the wire bonds 206 provide a signal routing path to the first die 204 that can extend outside of the packaging substrate 208 over the second die 220 to the second metal pads 226(2) to provide a more direct signal routing path between the first die 204 and the second metal pads 226(2). The signal routing path does not have to be routed around the KoZ region 224 in the packaging substrate 208 due to the presence of the second die 220 and the connectivity of the second die 220 to the metal lines 216(5), 216(6) in the packaging substrate 208. In this example, the wire bonds 206 are routed between the first and second metal pads 226(1), 226(2) in a direction that is different from the direction of signal routing over the metal line 216(1) between the first die 204 and the first metal pads 226(1).

[0035] A KoZ region may exist in a package substrate even if not directly beneath another component (such as a die) coupled to the package substrate. Wire bonding channels may also be provided in such a package substrate to avoid having to route signal routing paths around the KoZ region. In this regard, Figure 3 3 is a top view of another package substrate 300 that may be provided in an IC package, the IC package including metal lines 306 in the outer metallization layer 302 routed around a signal routing KoZ region 308 in the outer metallization layer 302. Other metal lines 309 are arranged in the outer metallization layer 302 forming the KoZ region 308. The metal lines 309 in the KoZ region 308 do not exist in the outer metallization layer 302 because the package substrate 300 is designed to be above the metal lines 306 in the vertical direction (Z-axis direction) ( Figure 3 Another die or other electronic component mounted on the package substrate 300 (outside the page in FIG. Figure 3 As shown in FIG, the package substrate 300 includes other metal lines 310 coupled to metal interconnects 312 as part of a landing area 314 for a die to be coupled to the outer metallization layer 302. These other metal lines 310 are routed around the KoZ region 308 to the other metal interconnects 312 in the outer metallization layer 302.

[0036] Figure 4A and 4B4 are respective side and top views of an exemplary IC package 400 that includes a wire bond channel 402 for providing a communication channel to a first die 404 without having to route the communication channel around a KoZ region in a package substrate 408 of the IC package 400. For example, it may be desirable to provide a signal routing path between the first die 404 and another component in the IC package 400 where a KoZ region 424 exists in the desired signal routing path, but this KoZ region is not due to metal lines present in the package substrate 408, but rather is due to placement of a second electronic component on the package substrate 408 above the KoZ region 424. The signal routing path between the first die 404 and such another component may include a signal routing path that extends both through the package substrate 408 and through the wire bond channel 402 that extends outside of the package substrate 408.

[0037] In this regard, if Figure 4A and 4B As shown in , the wire bonding channel 402 includes a wire bond 406 extending above the packaging substrate 408 to support a signal routing path to the first tube core 404. For example, the wire bonding channel 402 can be coupled to another component (the other component is coupled to the packaging substrate 408) to provide a communication link between the first tube core 404 and this other component. In this example, the first tube core 404 is coupled to the first surface 410 of the packaging substrate 408. As an example, the packaging substrate 408 can be a cored packaging substrate or a coreless packaging substrate. The packaging substrate 408 can be formed by laminating metallization layers, or by a stacking process of forming metallization layers on top of each other. In this example, the first surface 410 is a planar surface or a substantially planar surface extending in a horizontal direction in the X-axis and Y-axis directions. For example, the first surface 410 can be an outer surface of an outer metallization layer 412(1) of the packaging substrate 408. As an example, the outer metallization layer 412(1) can be formed as an ETS layer. As shown in FIG. Figure 4AAs shown in , the first die 404 can be coupled to a metal interconnect 414(1) in an external metallization layer 412(1) to couple the first die 404 to a packaging substrate 408, thereby providing a signal routing path between the packaging substrate 408 and the first die 404. The metal interconnect 414(1) forms or is coupled to a metal line 416(1) in the external metallization layer 412(1), and the metal line 416(1) provides a signal routing path in the packaging substrate 408. As an example, the first metal line 416(1) can be formed as an RDL. The first metal line 416(1) in the external metallization layer 412(1) can also be coupled to other metal lines 416(2)-416(4) in other metallization layers 412(2)-412(4) via metal interconnects 414(2)-414(4) (e.g., vias, metal pillars) to provide a signal routing path in the packaging substrate 408.

[0038] Reference Figure 4B , KoZ area 424 exists in the packaging substrate 408 because there are metal lines dedicated to routing signals that are not routed on the first metal line 416 (1). Therefore, the KoZ area 224 is an area defined by metal lines in the metallization layers 412 (1)-412 (4) for routing other signals except the signals routed on the first metal line 416 (1). The KoZ area 424 extends in a first horizontal direction in the X-axis and Y-axis directions together with the packaging substrate 408. The KoZ area 424 also extends in a second vertical direction (Z-axis direction) within the packaging substrate 408. Therefore, the KoZ area 424 has a horizontal area footprint in the first horizontal direction in the X-axis and Y-axis directions, and the horizontal area footprint extends in a vertical direction (Z-axis direction). Other signal routing paths that must pass within the area of ​​the KoZ area 424 must be routed outside the KoZ area 424.

[0039] Continue to refer to Figure 2A and 2B In order to provide signal routing paths to the first die 404, these signal routing paths are desirably routed through the KoZ region 424 of the package substrate 408 to avoid having to route such signal routing paths around the KoZ region 424 (eg, Figure 3), a wire bonding channel 402 is provided. In this example, the wire bonding channel 402 is formed by a first metal pad 426(1) and a second metal pad 426(2) formed on the packaging substrate 408. For example, the first metal pad 426(1) and the second metal pad 426(2) can be formed on the first surface 410 of the packaging substrate 408. The first and second metal pads 426(1), 426(2) can be bonding pads made of metal, such as a lead material that can be bonded (e.g., soldered) to a wire. The first metal pad 426(1) is coupled to a corresponding first metal wire 416(1) in an external metallization layer 412(1) of the packaging substrate 408 to provide a signal routing path between the first metal pad 426(1) and the first die 404. In this example, the first metal pad 426(1) is located adjacent to a first side 427(1) of the first die 404. The second metal pad 426(2) is located adjacent to the second side 427(2) of the first die 404. The first metal pad 426(1) is coupled to the first die 404 by being coupled to a metal interconnect 414(1) (coupled to the first metal line 416(1)), wherein the metal interconnect 414(1) is exposed from the first surface 410 of the package substrate 408. Figure 4B , the wire bonds 406 are metal wires coupled (e.g., bonded) to the first and second metal pads 426(1), 426(2) at their respective first and second ends 428(1), 428(2) to provide a conductive connection between the first and second metal pads 426(1), 426(2). The wire bonds 406 are external to and outside of the package substrate 408. The wire bonds 406 in this example extend over the first surface 410 of the package substrate 408 in a second vertical direction (Z-axis direction) orthogonal to the first horizontal direction (X-axis and Y-axis directions) of the first surface 410. In this example, each wire bond 406 intersects a vertical plane P2 in the vertical direction (Z-axis direction), which also intersects the KoZ region 424. The vertical plane P2 is orthogonal to the first horizontal direction (X-axis and Y-axis directions) of the package substrate 408. However, it is not required that each wire bond 406 intersect the vertical plane P2 that also intersects the KoZ region 424 .

[0040] In this manner, wire bonds 406 provide a signal routing path to first die 404 that can extend outside of package substrate 408 over KoZ region 424 to second metal pad 426(2) to provide a signal routing path between first die 404 and second metal pad 426(2). The signal routing path provided by wire bonds 406 does not have to be routed around KoZ region 424 in package substrate 408 due to the presence of KoZ region 424 in package substrate 408.

[0041] A manufacturing process may be employed to manufacture an IC package, the IC package comprising a first die coupled to a first outer surface of a package substrate, and further comprising a wire bond channel comprising a wire bond extending from a first metal pad coupled to the first die to a second metal pad outside the package substrate and in a vertical direction above a signal routing KoZ in the package substrate to support a more direct signal routing path between the first die and the second metal pad, including but not limited to Figures 2A-2C and the IC packages 200, 400 in 4A-4B. In this regard, Figure 5 is a flow chart illustrating an exemplary manufacturing process 500 for manufacturing an IC package, the IC package including a first die coupled to a first outer surface of a package substrate, and further including a wire bond channel including a wire bond extending from a first metal pad coupled to the first die to a second metal pad above a signal routing path KoZ in the package substrate outside the package substrate and in a vertical direction to support a more direct signal routing path between the first die and the second metal pad, including but not limited to Figures 2A-2C and IC packages in 4A-4B. Figures 2A-2C and IC packages 200 and 400 in 4A and 4B. Figure 5 The manufacturing process 500 in FIG. 5 is shown in FIG. 5 , but it is noted that the manufacturing process 500 is not limited to manufacturing similar Figures 2A-2C , and the IC packages 200 , 400 in 4A and 4B .

[0042] In this regard, if Figure 5 As shown in FIG. 5 , the first step of the manufacturing process 500 in this example may be to provide a package substrate 208, 408, wherein the package substrate 208, 408 includes a first surface 210, 410 ( Figure 5 The next step in the manufacturing process 500 may be to couple the first die 204, 404 to the first surface 210, 410 of the package substrate 208, 408 ( Figure 5 The next step in the manufacturing process 500 may be to form the wire bonding channels 202, 402 ( Figure 5 Forming the wire bond channel 202, 402 may include forming one or more first metal pads 226(1), 426(1) coupled to the first surface 210, 410 of the package substrate 208, 408 and coupled to the first die 204, 404 ( Figure 5 Forming the wire bonding channel 202, 402 may also include forming one or more second metal pads 226(2), 426(2) coupled to the first surface 210, 410 of the package substrate 208, 408 ( Figure 5 Forming the wire bond channel 202, 402 may also include coupling a first end 228(1), 428(1) of each of the one or more wire bonds 206, 406 to one or more first metal pads 226(1), 426(1) outside the package substrate 208, 408 ( Figure 5 Forming the wire bond channel 202, 402 may also include coupling the second end 228(2), 428(2) of each of the one or more wire bonds 206, 406 to the one or more second metal pads 226(2), 426(2) outside the package substrate 208, 408 ( Figure 5 514 in FIG.

[0043] Other manufacturing processes may be used to manufacture an IC package including a first die coupled to a first outer surface of a package substrate and further including a wire bond channel including a wire bond extending from a first metal pad coupled to the first die to a second metal pad outside the package substrate and in a vertical direction above a signal routing KoZ in the package substrate to support a more direct signal routing path between the first die and the second metal pad, including but not limited to Figures 2A-2C and the IC packages in 4A-4B. In this regard, Figures 6A-6C is a flow chart illustrating another exemplary manufacturing process 600 for manufacturing an IC package, the IC package including a first die coupled to a first outer surface of a package substrate, and further including a wire bond channel including a wire bond extending from a first metal pad coupled to the first die to a second metal pad above a signal routing path KoZ in the package substrate outside the package substrate and in a vertical direction to support a more direct signal routing path between the first die and the second metal pad, including but not limited to Figures 2A-2C and the IC packages in 4A-4B. Figures 7A-7F is based on Figures 6A-6C Exemplary manufacturing stages 700A-700F during the manufacture of an IC package in the manufacturing process 600. Figure 2A and 2C IC packaging 200 to discuss Figures 6A-6C The manufacturing process 600, and Figures 7A-7F 700A-700F in the manufacturing process, but note that this is not limiting. Note that the manufacturing process 600 can be used to form multiple IC packages 200 in the same process, which are subsequently singulated during manufacturing.

[0044] In this regard, if Fig. 7AAs shown in the manufacturing stage 700A in FIG. 1 , the first step in manufacturing the IC package 200 is to provide a package substrate 208 ( Fig. 6A 602 in FIG. Figure 7B As shown in manufacturing stage 700B in FIG. 1 , the next step in manufacturing IC package 200 is to place and couple first die 204 and second die 220 on first surface 210 of package substrate ( Fig. 6A 6. The die interconnect 230 of the first die 204 is coupled to the packaging substrate 208 to physically and electrically couple the first die 204 to the packaging substrate 208. The die interconnect 232 of the second die 220 is coupled to the packaging substrate 208 to physically and electrically couple the second die 220 to the packaging substrate 208.

[0045] like Figure 7C As shown in manufacturing stage 700C in FIG. 1 , the next step in manufacturing IC package 200 is to form first and second metal pads 226 ( 1 ), 226 ( 2 ) ( Figure 6B 6. The first metal pad 226(1) is coupled to the first die 204 through the package substrate 208. Wire bonds 206 are then coupled between the first and second metal pads 226(1), 226(2) to form wire bond channels 202. Wire bonds 206 are formed on the first surface 210 of the package substrate 208 and outside the package substrate 208, and on the second die 220. Subsequently, as shown in FIG. Fig.7D As shown in the manufacturing stage 700D in FIG. 1 , the next step in manufacturing the IC package 200 is to form an overmold 234 with an overmold material over the first and second dies 204, 220 and on the first surface 210 of the package substrate 208 to insulate and protect the first and second dies 204, 220 and form the IC package 200 ( Figure 6B 608 in FIG.

[0046] like Fig. 7E As shown in manufacturing stage 700E in FIG. 1 , the next step in manufacturing IC package 200 is to flip IC package 200 and form external interconnects 236 (e.g., solder bumps, ball grid array (BGA) interconnects) on and / or coupled to second external metallization layer 212 (4) of package substrate 208 to provide an external interface to IC package 200 ( Figure 6C 610 in FIG. 4 ). Then, as shown in FIG. Figure 7FAs shown in manufacturing stage 700F in FIG. 1 , the next step in manufacturing IC package 200 is to flip IC package 200 again after external interconnects 236 are formed on package substrate 208. As an example, IC package 200 and its external interconnects 236 may be mounted in a printed circuit board (PCB). If IC package 200 is formed on package substrate 208 at the same time as several other IC packages 200, IC package 200 may be singulated.

[0047] An IC package comprising a first die coupled to a first outer surface of a package substrate, and further comprising a wire bond channel comprising a wire bond extending from a first metal pad coupled to the first die to a second metal pad outside the package substrate and in a vertical direction above a signal routing KoZ in the package substrate to support a more direct signal routing path between the first die and the second metal pad, including but not limited to Figures 2A-2C , 4A-4B and 7A-7F and based on but not limited to Figure 5-6C Any exemplary manufacturing process in and IC packages that can be provided in or integrated into any processor-based device according to any aspect disclosed herein. Non-limiting examples include: set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, global positioning system (GPS) devices, mobile phones, cellular phones, smart phones, session initiation protocol (SIP) phones, tablet devices, tablet phones, servers, computers, portable computers, mobile computing devices, laptop computers, wearable computing devices (e.g., smart watches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multirotor aircraft.

[0048] In this regard, Figure 8 An example of a processor-based system 800 is illustrated that includes circuitry that may be provided in one or more IC packages 802(1)-802(7). The IC packages 802(1)-802(7) may include a first die coupled to a first outer surface of a package substrate, and further include a wire bond channel that includes a wire bond extending from a first metal pad coupled to the first die to a second metal pad above a signal routing KoZ in the package substrate in a vertical direction outside the package substrate to support a more direct signal routing path between the first die and the second metal pad, including but not limited to Figures 2A-2C, 4A-4B and 7A-7F and based on but not limited to Figure 5-6C 804 in an IC package of any exemplary manufacturing process. In this example, the processor-based system 800 may be formed as an IC 804 in an IC package 802 and formed as a system on a chip (SoC) 806. The processor-based system 800 includes a central processing unit (CPU) 808, which includes one or more processors 810, which may also be referred to as CPU cores or processor cores. The CPU 808 may have a cache memory 812 coupled to the CPU 808 for fast access to temporarily stored data. The CPU 808 is coupled to a system bus 814 and may couple master devices and slave devices included in the processor-based system 800 to each other. As is well known, the CPU 808 communicates with these other devices by exchanging address, control, and data information on the system bus 814. For example, the CPU 808 may communicate a bus transaction request to a memory controller 816, which is an example of a slave device. Although in Figure 8 Not illustrated in FIG. 8 , multiple system buses 814 may be provided, with each system bus 814 constituting a different fabric.

[0049] Other master devices and slave devices may be connected to the system bus 814. Figure 8 As illustrated in , by way of example, these devices may include a memory system 820 including a memory controller 816 and a memory array(s) 818, one or more input devices 822, one or more output devices 824, one or more network interface devices 826, and one or more display controllers 828. Each of the memory system(s) 820, the one or more input devices 822, the one or more output devices 824, the one or more network interface devices 826, and the one or more display controllers 828 may be provided in the same or different IC packages 802(2)-802(7). The input device(s) 822 may include any type of input device, including, but not limited to, input keys, switches, voice processors, etc. The output device(s) 824 may include any type of output device, including, but not limited to, audio, video, other visual indicators, etc. The network interface device(s) 826 may be any device configured to allow data exchange to and from a network 830. The network 830 may be any type of network, including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a Bluetooth® wireless network, or a wireless communications network. TM Network, and the Internet. Network interface device(s) 826 may be configured to support any type of communication protocol desired.

[0050] The CPU 808 may also be configured to access the display controller(s) 828 via the system bus 814 to control information sent to one or more displays 832. The display controller(s) 828 sends information to be displayed to the display(s) 832 via the one or more video processors 834, which processes the information to be displayed into a format suitable for the display(s) 832. As an example, the display controller(s) 828 and the video processor(s) 834 may be included as ICs in the same or different IC packages 802(2), 802(3), and in the same or different IC package 802 containing the CPU 808. The display(s) 832 may include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, a light emitting diode (LED) display, etc.

[0051] Fig. 9 An exemplary wireless communication device 900 is illustrated that includes a radio frequency (RF) component formed of one or more ICs 902, wherein any of the ICs 902 may be included in an IC package 903, the IC package 903 including a first die coupled to a first outer surface of a package substrate, and further including a wire bond channel including a wire bond extending from a first metal pad coupled to the first die to a second metal pad above a signal routing pad in the package substrate outside the package substrate and in a vertical direction to support a more direct signal routing path between the first die and the second metal pad, including but not limited to Figures 2A-2C , 4A-4B and 7A-7F and based on but not limited to Figure 5-6C As an example, the wireless communication device 900 may include or be provided in any of the above-mentioned devices. Fig. 9 As shown in , the wireless communication device 900 includes a transceiver 904 and a data processor 906. The data processor 906 may include a memory to store data and program codes. The transceiver 904 includes a transmitter 908 and a receiver 910 that support two-way communication. In general, the wireless communication device 900 may include any number of transmitters 908 and / or receivers 910 for any number of communication systems and frequency bands. All or part of the transceiver 904 may be implemented on one or more analog ICs, RF ICs (RFICs), mixed signal ICs, etc.

[0052] The transmitter 908 or the receiver 910 may be implemented using a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal is converted between RF and baseband in multiple stages, such as from RF to an intermediate frequency (IF) in one stage and then from IF to baseband in another stage for the receiver 910. In a direct conversion architecture, the signal is converted between RF and baseband in one stage. Superheterodyne and direct conversion architectures may use different circuit blocks and / or have different requirements. Fig. 9 In the wireless communication device 900 in FIG. 1 , the transmitter 908 and the receiver 910 are implemented using a direct conversion architecture.

[0053] In the transmit path, the data processor 906 processes the data to be transmitted and provides I and Q analog output signals to a transmitter 908. In the exemplary wireless communication device 900, the data processor 906 includes digital-to-analog converters (DACs) 912(1), 912(2) to convert the digital signals generated by the data processor 906 into I and Q analog output signals (e.g., I and Q output currents) for further processing.

[0054] Within the transmitter 908, low pass filters 914(1), 914(2) filter the I and Q analog output signals, respectively, to remove undesired signals caused by the preceding digital-to-analog conversion. Amplifiers (AMPs) 916(1), 916(2) amplify the signals from the low pass filters 914(1), 914(2), respectively, and provide I and Q baseband signals. An up converter 918 upconverts the I and Q baseband signals via mixers 920(1), 920(2) with I and Q TX LO signals from a transmit (TX) local oscillator (LO) signal generator 922 to provide an upconverted signal 924. A filter 926 filters the upconverted signal 924 to remove undesired signals caused by the upconversion and noise in the receive frequency band. A power amplifier (PA) 928 amplifies the upconverted signal 924 from the filter 926 to obtain a desired output power level and provide a transmit RF signal. The transmit RF signal is routed through a duplexer or switch 930 and transmitted via an antenna 932 .

[0055] In the receive path, antenna 932 receives signals transmitted by a base station and provides a received RF signal, which is routed through a duplexer or switch 930 and provided to a low noise amplifier (LNA) 934. The duplexer or switch 930 is designed to operate with a specific receive (RX) and TX duplexer frequency separation so that the RX signal is isolated from the TX signal. The received RF signal is amplified by LNA 934 and filtered by filter 936 to obtain the desired RF input signal. Down-conversion mixers 938 (1), 938 (2) mix the output of filter 936 with I and Q RX LO signals (i.e., LO_I and LO_Q) from RX LO signal generator 940 to generate I and Q baseband signals. The I and Q baseband signals are amplified by AMPs 942 (1), 942 (2) and further filtered by low pass filters 944 (1), 944 (2) to obtain I and Q analog input signals, which are provided to data processor 906. In this example, the data processor 906 includes analog-to-digital converters (ADCs) 946 ( 1 ), 946 ( 2 ) to convert analog input signals into digital signals to be further processed by the data processor 906 .

[0056] exist Fig. 9 In the wireless communication device 900 of FIG. 1 , the TX LO signal generator 922 generates I and Q TX LO signals for up-conversion, and the RX LO signal generator 940 generates I and Q RX LO signals for down-conversion. Each LO signal is a periodic signal with a specific base frequency. The TX phase-locked loop (PLL) circuit 948 receives timing information from the data processor 906 and generates a control signal for adjusting the frequency and / or phase of the TX LO signal from the TX LO signal generator 922. Similarly, the RX PLL circuit 950 receives timing information from the data processor 906 and generates a control signal for adjusting the frequency and / or phase of the RX LO signal from the RX LO signal generator 940.

[0057] Those skilled in the art will further appreciate that the various illustrative logic blocks, modules, circuits and algorithms described in conjunction with the aspects disclosed herein can be implemented as electronic hardware, instructions stored in a memory or in another computer-readable medium and executed by a processor or other processing device, or a combination of the two. The memory disclosed herein can be a memory of any type and size, and can be configured to store any type of information desired. In order to clearly explain this interchangeability, various illustrative components, frames, modules, circuits and steps have been generally described above in the form of their functionality. How such functionality is implemented depends on specific applications, design choices, and / or design constraints imposed on the overall system. The technician can implement the described functionality in different ways for each specific application, but such implementation decisions should not be interpreted as causing departure from the scope of the present disclosure.

[0058] The various illustrative logical blocks, modules, and circuits described in conjunction with the various aspects disclosed herein may be implemented or executed with a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in cooperation with a DSP core, or any other such configuration).

[0059] The various aspects disclosed herein may be implemented in hardware and instructions stored in hardware, and may reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable media known in the art. An exemplary storage medium is coupled to the processor so that the processor can read / write information from / to the storage medium. In an alternative, the storage medium may be integrated into the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. In an alternative, the processor and storage medium may reside in a remote station, a base station, or a server as discrete components.

[0060] It is also noted that the operation steps described in any exemplary aspect of this article are described in order to provide examples and discussions. The described operations can be performed in many different orders except for the order illustrated. In addition, the operation described in a single operation step can actually be performed in multiple different steps. In addition, one or more operation steps discussed in the exemplary aspects can be combined. It should be understood that, as is obvious to those skilled in the art, the operation steps illustrated in the flow chart can be modified in many different ways. Those skilled in the art will also understand that any of a variety of different technologies and techniques can be used to represent information and signals. For example, the data, instructions, commands, information, signals, bits, code elements and code chips that may be mentioned throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof.

[0061] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the universal principles defined herein may be applied to other variations. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but should be granted the broadest scope consistent with the principles and novel features disclosed herein.

[0062] Implementation examples are described in the following numbered clauses:

[0063] 1. An integrated circuit (IC) package, comprising:

[0064] A packaging substrate including a first surface extending in a first direction;

[0065] a first die coupled to a first surface of the package substrate;

[0066] Wire bonding channels, including:

[0067] one or more first metal pads coupled to the first surface of the package substrate and to the first die;

[0068] one or more second metal pads coupled to the first surface of the package substrate; and

[0069] One or more wire bonds are arranged outside the package substrate, each of the one or more wire bonds coupling a corresponding first metal pad of the one or more first metal pads to a corresponding second metal pad of the one or more second metal pads.

[0070] 2. The IC package of clause 1, wherein the one or more wire bonds extend over the first surface of the package substrate in a second direction orthogonal to the first direction.

[0071] 3. The IC package of clause 1 or 2, further comprising: a second electronic device coupled to the first surface of the package substrate, the second electronic device being adjacent to the first die;

[0072] At least a portion of at least one of the one or more wire bonds intersects a first vertical plane that intersects the second electronic device.

[0073] 4. The IC package of clause 3, wherein at least a portion of each of the one or more wire bonds intersects a vertical plane that intersects the second electronic device.

[0074] 5. An IC package as defined in clause 3 or 4, wherein:

[0075] The second electronic device includes a first side adjacent to the first die;

[0076] One or more first metal pads are arranged adjacent to the first die and between the first die and a first side of the second electronic device in a first direction; and

[0077] One or more second metal pads are disposed adjacent to a second side of the second electronic device.

[0078] 6. An IC package as claimed in any one of clauses 3 to 5, wherein:

[0079] The package substrate further includes an outer metallization layer adjacent to the first surface of the package substrate;

[0080] A second electronic device is coupled to the external metallization layer; and

[0081] The outer metallization layer includes a keep-out zone (KoZ) region including one or more first metal lines, wherein the KoZ region extends in a first direction and at least partially intersects a first plane orthogonal to the first direction.

[0082] 7. The IC package of any one of clauses 3 to 6, wherein: the second electronic device comprises a second die.

[0083] 8. The IC package of any of clauses 3 to 7, wherein: the second electronic device comprises a deep trench capacitor.

[0084] 9. An IC package as in clause 1, wherein:

[0085] The package substrate further includes: an outer metallization layer adjacent to the first surface of the package substrate; and

[0086] The outer metallization layer includes a keep-out zone (KoZ) region including one or more first metal lines extending in a first direction; and

[0087] At least a portion of at least one of the one or more wire bonds intersects a first vertical plane that is orthogonal to the first direction and intersects at least a portion of the KoZ region.

[0088] 10. The IC package of clause 9, wherein the IC package does not include a second electronic device coupled to the first surface of the package substrate that intersects the first vertical plane.

[0089] 11. An IC package as defined in clause 9 or 10, wherein:

[0090] The outer metallization layer includes one or more second metal lines coupled to the one or more first metal pads; and

[0091] The first die is coupled to one or more second metal lines.

[0092] 12. An IC package as defined in clause 11, wherein:

[0093] The one or more second metal lines extend in a third direction toward the one or more first metal pads; and

[0094] The one or more wire bonds extend from the one or more first metal pads toward the one or more second metal pads in a fourth direction different from the third direction.

[0095] 13. An IC package as claimed in any one of clauses 1 to 12, wherein:

[0096] One or more first metal pads are exposed from the first surface of the package substrate; and

[0097] One or more second metal pads are exposed from the first surface of the package substrate.

[0098] 14. An IC package as claimed in any one of clauses 1 to 13, wherein:

[0099] The package substrate includes a metallization layer including a plurality of metal lines;

[0100] The one or more first metal pads are coupled to the plurality of metal lines; and

[0101] The first die is coupled to a plurality of metal lines.

[0102] 15. An IC package as in any of clauses 1 to 14, the IC package being integrated into a device selected from the group consisting of a set-top box, an entertainment unit, a navigation device, a communication device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a tablet device, a tablet phone, a server, a computer, a portable computer, a mobile computing device, a wearable computing device, a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, an avionics system, a drone, and a multirotor aircraft.

[0103] 16. A method of manufacturing an integrated circuit (IC) package, comprising:

[0104] providing a packaging substrate, the packaging substrate comprising a first surface extending in a first direction;

[0105] coupling a first die to a first surface of a packaging substrate; and

[0106] Forming a wire bonding channel, including:

[0107] forming one or more first metal pads coupled to the first surface of the package substrate and to the first die;

[0108] forming one or more second metal pads coupled to the first surface of the package substrate;

[0109] coupling a first end of each of the one or more wire bonds to one or more first metal pads external to the packaging substrate; and

[0110] A second end of each of the one or more wire bonds is coupled to one or more second metal pads external to the package substrate.

[0111] 17. The method of clause 16, further comprising: extending one or more wire bonds over the first surface of the packaging substrate in a second direction orthogonal to the first direction.

[0112] 18. The method of clause 16 or 17, further comprising: coupling a second electronic device to the first surface of the packaging substrate and adjacent to the first die;

[0113] Wherein extending the one or more wire bonds further comprises: extending the one or more wire bonds, the one or more wire bonds at least partially intersecting a first vertical plane intersecting the second electronic device.

[0114] 19. A method according to clause 18, wherein:

[0115] Coupling the second electronic device to the first surface of the packaging substrate further includes: coupling a first side of the second electronic device adjacent to the first die;

[0116] Forming the one or more first metal pads further includes: forming the one or more first metal pads adjacent to the first die and in a first direction between the first die and the first side of the second electronic device; and

[0117] Forming the one or more second metal pads further includes forming the one or more second metal pads adjacent to the second side of the second electronic device.

[0118] 20. If the method of clause 18 or 19 is required,

[0119] The package substrate further includes: an outer metallization layer adjacent to the first surface of the package substrate, the outer metallization layer including a keep-out zone (KoZ) region, the KoZ region including one or more first metal lines, the KoZ region extending in a first direction; and

[0120] Coupling the second electronic device to the first surface of the packaging substrate further includes coupling the second electronic device to the external metallization layer such that the second electronic device at least partially intersects the first vertical plane.

[0121] 21. A method according to clause 16 or 17, wherein:

[0122] The package substrate further includes: an outer metallization layer adjacent to the first surface of the package substrate, the outer metallization layer including a keep-out zone (KoZ) region, the KoZ region including one or more first metal lines extending in a first direction; and

[0123] Extending the one or more wire bonds further includes extending the one or more wire bonds to at least partially intersect a first vertical plane that is orthogonal to the first direction and intersects at least a portion of the KoZ region.

[0124] 22. The method of clause 21, further comprising: not coupling the second electronic device to the first surface of the packaging substrate that intersects the first vertical plane.

[0125] 23. The method of claim 21 or 22, wherein:

[0126] Forming the one or more first metal pads further includes: coupling the one or more first metal pads to one or more second metal lines in an external metallization layer; and

[0127] Coupling the first die to the first surface of the package substrate further includes coupling the first die to one or more second metal lines.

[0128] 24. The method of any one of clauses 21 to 23, further comprising: not coupling the second electronic device to the first surface of the packaging substrate that intersects the first vertical plane.

Claims

1. An integrated circuit (IC) package, comprising: A packaging substrate comprising a first surface extending in a first direction; a first die coupled to the first surface of the packaging substrate; Wire bonding channels, including: one or more first metal pads coupled to the first surface of the package substrate and to the first die; one or more second metal pads coupled to the first surface of the packaging substrate; and One or more wire bonds are arranged outside the packaging substrate, and the one or more wire bonds each couple a corresponding first metal pad of the one or more first metal pads to a corresponding second metal pad of the one or more second metal pads. 2 . The IC package of claim 1 , wherein the one or more wire bonds extend over the first surface of the package substrate in a second direction orthogonal to the first direction.

3. The IC package of claim 1, further comprising: a second electronic device coupled to the first surface of the package substrate, the second electronic device being adjacent to the first die; Wherein at least a portion of at least one of the one or more wire bonds intersects a first vertical plane that intersects the second electronic device.

4. The IC package of claim 3, wherein at least a portion of each of the one or more wire bonds intersects a vertical plane that intersects the second electronic device.

5. The IC package of claim 3, wherein: The second electronic device includes a first side adjacent to the first die; The one or more first metal pads are arranged adjacent to the first die and between the first die and the first side of the second electronic device in the first direction; and The one or more second metal pads are arranged adjacent to a second side of the second electronic device.

6. The IC package of claim 3, wherein: The packaging substrate further includes an outer metallization layer, the outer metallization layer being adjacent to the first surface of the packaging substrate; The second electronic device is coupled to the external metallization layer; and The outer metallization layer includes a keep-out zone (KoZ) region including one or more first metal lines, wherein the KoZ region extends in the first direction and at least partially intersects a first plane orthogonal to the first direction.

7. The IC package of claim 3, wherein the second electronic device comprises a second die.

8. The IC package of claim 3, wherein the second electronic device comprises a deep trench capacitor.

9. The IC package of claim 1, wherein: The packaging substrate further includes an outer metallization layer adjacent to the first surface of the packaging substrate, and The outer metallization layer includes a keep-out zone (KoZ) region including one or more first metal lines extending in the first direction; and At least a portion of at least one of the one or more wire bonds intersects a first vertical plane that is orthogonal to the first direction and intersects at least a portion of the KoZ region.

10. The IC package of claim 9, wherein the IC package does not include a second electronic device coupled to the first surface of the package substrate that intersects the first vertical plane.

11. The IC package of claim 9, wherein: The outer metallization layer includes one or more second metal lines coupled to the one or more first metal pads; and The first die is coupled to the one or more second metal lines.

12. The IC package of claim 11, wherein: The one or more second metal lines extend in a third direction toward the one or more first metal pads; and The one or more wire bonds extend from the one or more first metal pads toward the one or more second metal pads in a fourth direction different from the third direction.

13. The IC package of claim 1, wherein: The one or more first metal pads are exposed from the first surface of the packaging substrate; and The one or more second metal pads are exposed from the first surface of the packaging substrate.

14. The IC package of claim 1, wherein: The packaging substrate includes a metallization layer, and the metallization layer includes a plurality of metal lines; The one or more first metal pads are coupled to the plurality of metal lines; and The first die is coupled to the plurality of metal lines.

15. The IC package of claim 1 , wherein the IC package is integrated into a device selected from the group consisting of a set-top box, an entertainment unit, a navigation device, a communication device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a tablet device, a tablet phone, a server, a computer, a portable computer, a mobile computing device, a wearable computing device, a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, an avionics system, a drone, and a multirotor aircraft.

16. A method of manufacturing an integrated circuit (IC) package, comprising: Providing a packaging substrate, the packaging substrate comprising a first surface extending in a first direction; coupling a first die to the first surface of the packaging substrate; as well as Forming a wire bonding channel, including: forming one or more first metal pads coupled to the first surface of the packaging substrate and to the first die; forming one or more second metal pads, the one or more second metal pads coupled to the first surface of the packaging substrate; coupling a first end of each of the one or more wire bonds to the one or more first metal pads externally of the packaging substrate; and A second end of each of the one or more wire bonds is coupled to the one or more second metal pads external to the package substrate.

17. The method of claim 16, further comprising: The one or more wire bonds extend over the first surface of the packaging substrate in a second direction orthogonal to the first direction.

18. The method of claim 16, further comprising: coupling a second electronic device to the first surface of the packaging substrate and adjacent to the first die; Wherein extending the one or more wire bonds further comprises: extending the one or more wire bonds, the one or more wire bonds at least partially intersecting a first vertical plane intersecting the second electronic device.

19. The method of claim 18, wherein: Coupling the second electronic device to the first surface of the packaging substrate further includes: coupling a first side of the second electronic device adjacent to the first die; Forming the one or more first metal pads further includes: forming the one or more first metal pads adjacent to the first die and between the first die and the first side of the second electronic device in the first direction; and Forming the one or more second metal pads further includes forming the one or more second metal pads adjacent to a second side of the second electronic device.

20. The method of claim 18, wherein: The package substrate further includes an external metallization layer, the external metallization layer is adjacent to the first surface of the package substrate, the external metallization layer includes a keep-out zone (KoZ) area, the KoZ area includes one or more first metal lines, and the KoZ area extends in the first direction; and Coupling the second electronic device to the first surface of the packaging substrate further includes coupling the second electronic device to the outer metallization layer such that the second electronic device at least partially intersects the first vertical plane.

21. The method of claim 16, wherein: The package substrate further includes an outer metallization layer, the outer metallization layer is adjacent to the first surface of the package substrate, the outer metallization layer includes a keep-out zone (KoZ) area, the KoZ area includes one or more first metal lines extending in the first direction; and Extending the one or more wire bonds further includes extending the one or more wire bonds to at least partially intersect a first vertical plane that is orthogonal to the first direction and intersects at least a portion of the KoZ region.

22. The method of claim 21, further comprising: A second electronic device is not coupled to the first surface of the packaging substrate that intersects the first vertical plane.

23. The method of claim 21, wherein: Forming the one or more first metal pads further comprises: coupling the one or more first metal pads to one or more second metal lines in the outer metallization layer; and Coupling the first die to the first surface of the packaging substrate further includes coupling the first die to the one or more second metal lines.

24. The method of claim 21, further comprising: A second electronic device is not coupled to the first surface of the packaging substrate that intersects the first vertical plane.

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