Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a substrate and a plurality of sub-pixels located on the substrate, the pixel circuit layer is arranged on one side of the substrate and comprises a first sub-pixel circuit, a second sub-pixel circuit and a third sub-pixel circuit; the planarization layer is arranged on the pixel circuit layer; the pixel definition layer is arranged on the planarization layer and is provided with a first sub-pixel opening, a second sub-pixel opening and a third sub-pixel opening; the pixel circuit layer comprises a first conductive layer, the first conductive layer comprises a plurality of first circuit patterns of a plurality of sub-pixels, and the orthographic projection of the plurality of first circuit patterns on the substrate is overlapped with the orthographic projection of at least one of the first sub-pixel opening, the second sub-pixel opening and the third sub-pixel opening on the substrate; a ratio of an overlapping area of the first circuit pattern and the third sub-pixel opening to an area of the third sub-pixel opening is smaller than a ratio of an overlapping area of the first circuit pattern and the first sub-pixel opening to an area of the first sub-pixel opening. The display panel can improve the flatness of the planarization layer.

Description

Display panel and display device Technical Field

[0001] Embodiments of the present disclosure relate to a display panel and a display device. Background Art

[0002] Among various display devices, organic light-emitting diode (OLED) display panels are widely used in the display field due to their advantages such as self-luminescence, wide viewing angle, and fast response speed. OLED display panels consist of multiple sub-pixels and typically include a pixel circuit layer, a light-emitting device layer, and a planarization layer located between the pixel circuit layer and the light-emitting device layer. The light-emitting devices require high surface flatness of the planarization layer. If the light-emitting devices are formed on an uneven surface, the light emission of the light-emitting devices may be uneven, thus affecting the display quality of the display panel.

[0003] Summary of the Invention

[0004] According to at least one embodiment of the present disclosure, a display panel is provided, comprising: a base substrate; a plurality of sub-pixels arranged on the base substrate, wherein each sub-pixel comprises a light-emitting device and a sub-pixel circuit for driving the light-emitting device to emit light, and the plurality of sub-pixels comprise a first sub-pixel, a second sub-pixel and a third sub-pixel for displaying different colors; a pixel circuit layer comprising sub-pixel circuits of the plurality of sub-pixels, and comprising a first sub-pixel circuit, a second sub-pixel circuit and a third sub-pixel circuit for driving the light-emitting devices of the first sub-pixel, the second sub-pixel and the third sub-pixel to emit light, respectively; a planarization layer arranged on a side of the pixel circuit layer away from the base substrate; and a pixel definition layer arranged on a side of the planarization layer away from the pixel circuit layer, the pixel definition layer having a plurality of sub-pixel openings, wherein each sub-pixel opening is configured to define a light-emitting area of ​​a corresponding sub-pixel, and at least a portion of the light-emitting device of each sub-pixel Located in corresponding sub-pixel openings, wherein the multiple sub-pixel openings include a first sub-pixel opening, a second sub-pixel opening and a third sub-pixel opening corresponding to the first sub-pixel, the second sub-pixel and the third sub-pixel respectively; wherein the pixel circuit layer includes a first conductive layer, the first conductive layer includes a plurality of first circuit patterns of the multiple sub-pixels, and the orthographic projections of the multiple first circuit patterns on the base substrate overlap with the orthographic projections of at least one of the first sub-pixel opening, the second sub-pixel opening and the third sub-pixel opening on the base substrate; and the ratio of the overlapping area of ​​the multiple first circuit patterns with the third sub-pixel opening to the area of ​​the third sub-pixel opening is smaller than the ratio of the overlapping area of ​​the multiple first circuit patterns with the first sub-pixel opening to the area of ​​the first sub-pixel opening or the ratio of the overlapping area of ​​the multiple first circuit patterns with the second sub-pixel opening to the area of ​​the second sub-pixel opening.

[0005] In the display panel provided according to at least one embodiment of the present disclosure, the orthographic projection of at least part of the third sub-pixel circuit on the base substrate is located outside the orthographic projection of the third sub-pixel opening on the base substrate, and overlaps with the orthographic projection of the first sub-pixel opening or the second sub-pixel opening on the base substrate.

[0006] In the display panel provided according to at least one embodiment of the present disclosure, each sub-pixel circuit includes a thin film transistor and a capacitor; each thin film transistor includes a gate, a source / drain and an active layer; each capacitor includes electrode plates opposite to each other; the pixel circuit layer also includes a plurality of routing lines connected to the plurality of thin film transistors and capacitors of the plurality of sub-pixel circuits, and the plurality of routing lines include one or more of gate signal lines, data signal lines, common electrode lines, detection signal lines, power supply voltage lines and auxiliary connection lines; and the pixel circuit layer includes a multi-layer circuit pattern, and the plurality of first circuit patterns of the first conductive layer include the gates or source / drain of the plurality of thin film transistors, and also include the electrode plates of the capacitor and one or more of the plurality of routing lines.

[0007] In the display panel provided according to at least one embodiment of the present disclosure, the pixel circuit layer includes multiple pattern layers, each pattern layer includes multiple patterns, and the first conductive layer is the topmost pattern layer among the multiple pattern layers that is closest to the light-emitting device in a direction perpendicular to the main surface of the base substrate, or the first conductive layer is located on the side of the topmost pattern layer among the multiple pattern layers that is away from the light-emitting device.

[0008] In the display panel provided according to at least one embodiment of the present disclosure, the pixel circuit layer also includes a second conductive layer and an active material layer, and each sub-pixel circuit includes a first circuit pattern located in the first conductive layer, a second circuit pattern located in the second conductive layer, and an active pattern located in the active material layer; and the first conductive layer is the layer where the gate of the thin film transistor of the sub-pixel circuit is located, the second conductive layer is the layer where the source and drain of the thin film transistor of the sub-pixel circuit are located, and the active material layer is the layer where the active layer of the thin film transistor of the sub-pixel circuit is located.

[0009] In the display panel provided according to at least one embodiment of the present disclosure, the sum of the overlapping areas of the multiple first circuit patterns of the multiple sub-pixels with the second sub-pixel opening and the third sub-pixel opening is smaller than the overlapping area of ​​the multiple first circuit patterns with the first sub-pixel opening.

[0010] In the display panel provided according to at least one embodiment of the present disclosure, the plurality of first circuit patterns include circuit patterns of the plurality of sub-pixels configured to be connected to gate scan signals.

[0011] In the display panel provided according to at least one embodiment of the present disclosure, at least a portion of the first circuit pattern of at least two of the first sub-pixel circuit, the second sub-pixel circuit, and the third sub-pixel circuit has an orthographic projection on the base substrate that overlaps with the orthographic projection of the first sub-pixel opening on the base substrate.

[0012] In the display panel provided according to at least one embodiment of the present disclosure, an orthographic projection of the first circuit pattern of the third sub-pixel on the base substrate is located outside an orthographic projection of the third sub-pixel opening on the base substrate.

[0013] In the display panel provided according to at least one embodiment of the present disclosure, the orthographic projection of the first circuit pattern of the second sub-pixel on the base substrate is located outside the orthographic projection of the second sub-pixel opening on the base substrate.

[0014] In the display panel provided according to at least one embodiment of the present disclosure, the orthographic projections of at least part of the first circuit pattern of the first sub-pixel, the first circuit pattern of the second sub-pixel, and the first circuit pattern of the third sub-pixel on the base substrate overlap with the orthographic projection of the first sub-pixel opening on the base substrate.

[0015] In the display panel provided according to at least one embodiment of the present disclosure, the orthographic projection of the second circuit pattern of the third sub-pixel on the base substrate is located outside the orthographic projection of the third sub-pixel opening on the base substrate, and overlaps with the orthographic projection of at least one of the first sub-pixel opening and the second sub-pixel opening on the base substrate.

[0016] According to at least one embodiment of the present disclosure, in the display panel provided, the plurality of second circuit patterns of the plurality of sub-pixels include circuit patterns configured to connect data signals.

[0017] In the display panel provided according to at least one embodiment of the present disclosure, the orthographic projection of a portion of the first conductive layer on the base substrate overlaps with the orthographic projection of the first sub-pixel opening on the base substrate, and the portion of the first conductive layer includes a plurality of traces, the plurality of traces have approximately the same line width, and the spacing between adjacent traces in the plurality of traces is approximately the same.

[0018] In the display panel provided according to at least one embodiment of the present disclosure, the difference between the line width of each of the multiple lines and the average line width of the multiple lines is less than 20% of the average line width, and the difference between the spacing between each two adjacent lines and the average spacing between different adjacent lines is less than 20% of the average spacing.

[0019] In the display panel provided according to at least one embodiment of the present disclosure, the second conductive layer includes a first part and a second part, the orthographic projections of the first part and the second part on the base substrate overlap with the orthographic projections of the first sub-pixel opening and the second sub-pixel opening on the base substrate respectively, and the first part includes a plurality of first routing lines, the plurality of first routing lines have substantially the same first line width as each other, and adjacent first routing lines have substantially the same first spacing; and the second part includes a plurality of second routing lines, the plurality of second routing lines have substantially the same second line width as each other, and adjacent second routing lines have substantially the same second spacing.

[0020] In the display panel provided according to at least one embodiment of the present disclosure, the first line width and the second line width are different from each other, and the first spacing and the second spacing are different from each other.

[0021] In the display panel provided according to at least one embodiment of the present disclosure, the orthographic projection of at least one of the active pattern of the second sub-pixel circuit and the active pattern of the third sub-pixel circuit on the base substrate overlaps with the orthographic projection of the first sub-pixel opening on the base substrate.

[0022] In the display panel provided according to at least one embodiment of the present disclosure, the orthographic projections of the active pattern of the second sub-pixel circuit and the active pattern of the third sub-pixel circuit on the base substrate are both located outside the orthographic projections of the second sub-pixel opening and the third sub-pixel opening on the base substrate.

[0023] In the display panel provided according to at least one embodiment of the present disclosure, the orthographic projections of the active patterns of the first to third sub-pixel circuits on the base substrate overlap with the orthographic projections of the first sub-pixel opening on the base substrate.

[0024] In the display panel provided according to at least one embodiment of the present disclosure, the orthographic projection of the active pattern of the second sub-pixel circuit on the base substrate is located outside the orthographic projection of the second sub-pixel opening on the base substrate, and the orthographic projections of the active pattern of the second sub-pixel circuit and the active pattern of the first sub-pixel circuit on the base substrate both overlap with the orthographic projection of the first sub-pixel opening on the base substrate.

[0025] In the display panel provided according to at least one embodiment of the present disclosure, the orthographic projection of the active pattern of the third sub-pixel circuit on the base substrate overlaps with the orthographic projection of the third sub-pixel opening on the base substrate, and the orthographic projection of the third sub-pixel opening on the base substrate is located within the orthographic projection range of the active pattern of the third sub-pixel circuit on the base substrate.

[0026] In the display panel provided according to at least one embodiment of the present disclosure, at least one of the first conductive layer, the second conductive layer and the active material layer includes a block pattern, and the orthographic projection of a portion of the block pattern on the base substrate overlaps with the orthographic projection of a sub-pixel opening on the base substrate; and the block pattern includes a main body and a plurality of strip-shaped portions, wherein the plurality of strip-shaped portions have hollow portions between them, and the plurality of strip-shaped portions are connected to each other through the main body, wherein the orthographic projection of the main body on the base substrate is outside the orthographic projection of the sub-pixel opening, and the orthographic projection of at least part of the plurality of strip-shaped portions on the base substrate overlaps with the orthographic projection of the sub-pixel opening.

[0027] In the display panel provided according to at least one embodiment of the present disclosure, the plurality of strip portions have substantially the same width as one another.

[0028] The display panel provided according to at least one embodiment of the present disclosure also includes at least one of the following: the first conductive layer also includes a first dummy pattern, which is arranged in the gap area of ​​the first circuit pattern of the multiple sub-pixels, and the orthographic projection of the first dummy pattern on the substrate overlaps with the orthographic projection of at least one of the first sub-pixel opening to the third sub-pixel opening on the substrate; the second conductive layer also includes a second dummy pattern, which is arranged in the gap area of ​​the second circuit pattern of the multiple sub-pixels, and the orthographic projection of the second dummy pattern on the substrate overlaps with the orthographic projection of at least one of the first sub-pixel opening to the third sub-pixel opening on the substrate; and the active material layer also includes a third dummy pattern, which is arranged in the gap area of ​​the active pattern of the multiple sub-pixels, and the orthographic projection of the third dummy pattern on the substrate overlaps with the orthographic projection of at least one of the first sub-pixel opening to the third sub-pixel opening on the substrate.

[0029] In the display panel provided according to at least one embodiment of the present disclosure, the first dummy pattern and the second dummy pattern are electrically floating or connected to a fixed potential.

[0030] In the display panel provided according to at least one embodiment of the present disclosure, the first circuit pattern includes a routing pattern adjacent to the first dummy pattern, the first dummy pattern and the routing pattern have approximately the same width, and the spacing between adjacent patterns in the first dummy pattern and the routing pattern is approximately the same.

[0031] In the display panel provided according to at least one embodiment of the present disclosure, the second circuit pattern includes a routing pattern adjacent to the second dummy pattern, the second dummy pattern and the routing pattern have approximately the same width, and the spacing between adjacent patterns in the second dummy pattern and the routing pattern is approximately the same.

[0032] In the display panel provided according to at least one embodiment of the present disclosure, the area of ​​the first sub-pixel opening is larger than the area of ​​the second sub-pixel opening, and the area of ​​the second sub-pixel opening is larger than the area of ​​the third sub-pixel opening.

[0033] In the display panel provided according to at least one embodiment of the present disclosure, the first sub-pixel is a blue sub-pixel, one of the second sub-pixel and the third sub-pixel is a green sub-pixel, and the other is a red sub-pixel.

[0034] In the display panel provided according to at least one embodiment of the present disclosure, the planarization layer includes a first flat portion, a second flat portion and a third flat portion, and the orthographic projections of the first sub-pixel opening, the second sub-pixel opening and the third sub-pixel opening on the base substrate are respectively located within the orthographic projection ranges of the first flat portion, the second flat portion and the third flat portion on the base substrate, wherein the first flat portion, the second flat portion and the third flat portion respectively have a first flat surface, a second flat surface and a third flat surface close to the light-emitting device, and at least two of the first flat surface, the second flat surface and the third flat surface are located at different horizontal heights relative to the main surface of the base substrate.

[0035] In the display panel provided according to at least one embodiment of the present disclosure, in a direction perpendicular to the main surface of the base substrate, the distance between the first flat surface and the main surface of the base substrate is greater than the distance between the second flat surface and the main surface of the base substrate.

[0036] In the display panel provided according to at least one embodiment of the present disclosure, in a direction perpendicular to the main surface of the base substrate, the distance between the second flat surface and the main surface of the base substrate is greater than or approximately equal to the distance between the third flat surface and the main surface of the base substrate.

[0037] At least one embodiment of the present disclosure provides a display panel, comprising: a base substrate; a plurality of sub-pixels arranged on the base substrate, wherein each sub-pixel comprises a light-emitting device and a sub-pixel circuit for driving the light-emitting device to emit light, and the plurality of sub-pixels comprise a first sub-pixel, a second sub-pixel, and a third sub-pixel for displaying different colors; a pixel circuit layer comprising sub-pixel circuits of the plurality of sub-pixels, and comprising a first sub-pixel circuit, a second sub-pixel circuit, and a third sub-pixel circuit for respectively driving the light-emitting devices of the first sub-pixel, the second sub-pixel, and the third sub-pixel to emit light; a planarization layer arranged on a side of the pixel circuit layer away from the base substrate; and a pixel definition layer arranged on a side of the planarization layer away from the pixel circuit layer, the pixel definition layer having a plurality of sub-pixel openings, wherein each sub-pixel opening is configured to define a corresponding sub-pixel a light-emitting area, and at least a portion of the light-emitting device of each sub-pixel is located in a corresponding sub-pixel opening, wherein the multiple sub-pixel openings include a first sub-pixel opening, a second sub-pixel opening and a third sub-pixel opening corresponding to the first sub-pixel, the second sub-pixel and the third sub-pixel, respectively; wherein the pixel circuit layer includes a plurality of pattern layers, a first pattern layer among the plurality of pattern layers includes a plurality of first patterns of the plurality of sub-pixels, and the orthographic projections of the plurality of first patterns on the base substrate overlap with the orthographic projections of at least one of the first sub-pixel opening, the second sub-pixel opening and the third sub-pixel opening on the base substrate; and an overlapping area of ​​the plurality of first patterns with the first sub-pixel opening is greater than an overlapping area of ​​the plurality of first patterns with the second sub-pixel opening or an overlapping area of ​​the plurality of first patterns with the third sub-pixel opening.

[0038] In the display panel provided according to at least one embodiment of the present disclosure, an overlapping area between the plurality of first patterns and at least one of the second sub-pixel opening and the third sub-pixel opening is zero.

[0039] In the display panel provided according to at least one embodiment of the present disclosure, the plurality of first patterns include circuit patterns for connecting the plurality of sub-pixels with the same signal.

[0040] In the display panel provided according to at least one embodiment of the present disclosure, the area of ​​the first sub-pixel opening is larger than the area of ​​the second sub-pixel opening, and the area of ​​the second sub-pixel opening is larger than the area of ​​the third sub-pixel opening.

[0041] In the display panel provided according to at least one embodiment of the present disclosure, the multiple pattern layers also include a second pattern layer, located on a side of the first pattern layer close to or away from the light-emitting device, the second pattern layer includes multiple second patterns of the multiple sub-pixels, and the overlapping area of ​​the multiple second patterns with the first sub-pixel opening is greater than the overlapping area of ​​the multiple second patterns with the second sub-pixel opening or the third sub-pixel opening.

[0042] In the display panel provided according to at least one embodiment of the present disclosure, an overlapping area between the plurality of second patterns and the second sub-pixel opening is zero.

[0043] In the display panel provided according to at least one embodiment of the present disclosure, an overlapping area between the plurality of second patterns and the third sub-pixel opening is zero or equal to an area of ​​the third sub-pixel opening.

[0044] In the display panel provided according to at least one embodiment of the present disclosure, the multiple pattern layers include one or more gate layers, one or more source-drain electrode layers, and one or more active material layers.

[0045] At least one embodiment of the present disclosure provides a display device, comprising any one of the display panels described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0047] FIG. 1A is a schematic cross-sectional view illustrating a patterned layer formed on a base substrate; and FIG. 1B is a schematic cross-sectional view illustrating a planarization layer formed on a base substrate having the patterned layer.

[0048] 2A and 2B illustrate schematic cross-sectional views of display panels according to some embodiments of the present disclosure.

[0049] 3A to 3E are schematic diagrams illustrating a planar arrangement of a first conductive layer and a plurality of sub-pixel openings in a pixel circuit layer of a display panel according to some embodiments of the present disclosure.

[0050] 4A to 4E are schematic diagrams illustrating a planar arrangement of a second conductive layer and a plurality of sub-pixel openings in a pixel circuit layer of a display panel according to some embodiments of the present disclosure.

[0051] 5A to 5C are schematic diagrams illustrating a planar arrangement of an active material layer and a plurality of sub-pixel openings in a pixel circuit layer of a display panel according to some embodiments of the present disclosure.

[0052] FIG6 is a schematic diagram showing a planar arrangement of a portion of a pixel circuit pattern and a sub-pixel opening in a pixel circuit layer of a display panel according to some embodiments of the present disclosure.

[0053] FIG. 7 shows a schematic plan view of a display panel according to some embodiments of the present disclosure.

[0054] FIG8 shows a schematic diagram of a display device according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0055] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0056] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0057] In various display devices, components such as pixel circuit devices (for example, thin film transistors, etc.), light-emitting devices, and photoelectric sensing elements may be included. These components generally include multiple layers of inorganic materials (for example, metals, semiconductors, insulating materials, etc.) and / or organic material layers, and these material layers are generally patterned, for example, having patterns in the shape of lines, blocks, strips, etc. These patterns may overlap with each other on the substrate, and the arrangement of each layer of patterns in different areas may be different, and the overlap of patterns in different areas may also be different, resulting in the overall pattern being uneven. In some embodiments, after each patterned layer is formed on the substrate, a flattening process is performed to provide a flat surface for subsequent processes. The flattening process generally includes coating a flattening material (for example, a photoresist material) on the substrate to cover the patterned layer; the coating process includes applying a liquid flattening material to the substrate, utilizing the leveling properties of the liquid flattening material to achieve a flattening effect, and then curing the flattening material to form a flattening layer. However, since the patterned layer has an uneven morphology, especially when the step difference of the patterned layer is too large, a single layer of planarizing material may be difficult to achieve the planarization requirements, or a sufficiently thick planarizing material may be required to achieve the required flatness, but this will increase the difficulty of subsequent processes.

[0058] For example, FIG. 1A is a schematic cross-sectional view illustrating a patterned layer formed on a base substrate; and FIG. 1B is a schematic cross-sectional view illustrating a planarization layer formed on a base substrate having the patterned layer.

[0059] As shown in FIG1A , one or more patterned layers are formed on a base substrate 10, for example, a first patterned layer 11 and a second patterned layer 12. Portions of the first patterned layer 11 and the second patterned layer 12 overlap each other in a direction perpendicular to the base substrate 10. The patterned layers 11 and 12 have an uneven morphology, and the highest point of the patterned layer is the overlap of the first patterned layer 11 and the second patterned layer 12, and the overlap has a step a1 compared to the surface of the base substrate 10. In the following, unless otherwise defined, the step of the patterned layer refers to the distance of the main surface of the patterned layer away from the base substrate compared to the main surface of the base substrate. It should be understood that there may be other insulating layers or functional layers between the first patterned layer 11 and the second patterned layer 12, and for the sake of simplicity of the drawings, FIG1A and FIG1B only show the patterned layers that will affect the flatness of the subsequently formed planarization layer.

[0060] As shown in FIG1B , a planarization layer 13 is formed on the base substrate 10 to cover the first patterned layer 11 and the second patterned layer 12. However, because the patterns of the first patterned layer 11 and the second patterned layer 12 have certain step differences compared to the base substrate 10, and the patterns are arranged differently in different areas of the base substrate 10, the formed planarization layer 13 still exhibits an uneven morphology overall.

[0061] In some embodiments, the surface topography of the planarization layer 13 (e.g., the surface height variation relative to the main surface of the substrate) may not be completely consistent with the topography of the underlying patterned layer. For example, the highest point on the surface of the planarization layer may not correspond to the location with the largest step difference on the patterned layer, but may instead correspond to a pattern-dense area on the patterned layer, e.g., where the pattern area and / or pattern overlap on the same layer is the largest. In areas where the patterns are more sparsely arranged, the height of the planarization layer overlying such areas is lower. For example, as shown in FIG1B , the planarization layer 13 located above the pattern-dense area 15 of the patterned layer has a higher height than other areas. The reason for the formation of such surface morphology of the planarization layer 13 is that the planarization process adopts a wet coating method to form a film, and utilizes the leveling properties of the material for planarization. The leveling properties of the material are related to the shape and area of ​​the bottom pattern. The denser the bottom pattern (that is, the larger the proportion of the pattern area), the more planarization material can be accumulated, so that the height of the formed planarization layer is also higher. In the sparse pattern area, the pattern area accounts for a small proportion, and the planarization material cannot be effectively retained at a higher position. Due to its leveling properties, the planarization material will flow toward the low-lying areas, so the height of the planarization layer in these areas is lower.

[0062] On the other hand, in the pattern-dense region 15 of the patterned layer, the planarization layer 13 has a relatively high flatness, that is, it has a relatively flat surface. In the pattern-dense region 16 of the patterned layer (e.g., a region substantially free of patterns), since there is substantially no pattern that results in an uneven topography in this region, the planarization layer 13 above this region also has a relatively high flatness. In this context, the flatness of a planarization layer refers to the degree of flatness of the planarization layer; that is, the higher the flatness, the flatter the surface of the planarization layer.

[0063] Furthermore, in some embodiments, adjusting the uniformity of the pattern arrangement of the patterned layer, such as setting the patterns to have equal line widths and spacings, can also improve the flatness of the planarization layer. In other words, the flatness of the planarization layer can be improved by adjusting the density and / or uniformity of the pattern arrangement of the patterned layer.

[0064] The OLED display panel includes multiple sub-pixels, and includes a pixel circuit layer, a light-emitting device layer, and a planarization layer arranged between the pixel circuit layer and the light-emitting device layer; in some embodiments, the planarization layer is configured to reduce or shield the impact of the morphology of multiple patterned layers in the pixel circuit layer on the light-emitting device, and provide a flat surface for the light-emitting device, so that at least the portion of the light-emitting device located in the light-emitting area is formed on a flat surface with higher flatness, thereby ensuring the uniformity of light emission in the light-emitting area of ​​each sub-pixel and improving the display quality of the display panel.

[0065] Based on existing planarization layer materials and process capabilities, it may not be possible to improve the planarization layer's flatness to meet the requirements of subsequent process steps and / or device performance simply by improving the planarization process. In the disclosed embodiments, by optimizing the arrangement of the pixel circuit patterns in the pixel circuit layer, the flatness of the surface of the planarization layer corresponding to each sub-pixel opening region can be improved. This allows at least the portion of the light-emitting device located within each sub-pixel opening region to be formed on a flat surface with a high degree of flatness. This in turn improves the uniformity of light emission from the light-emitting device within each sub-pixel light-emitting region and enhances the display quality of the display panel.

[0066] Figure 2A shows a schematic cross-sectional view of a display panel according to some embodiments of the present disclosure. Figure 2B shows another schematic cross-sectional view of a display panel according to some embodiments of the present disclosure.

[0067] 2A and 2B , in some embodiments, the display panel 500 includes a base substrate 100 and a plurality of pixel units arranged in an array on the base substrate 100, and each pixel unit may include a plurality of sub-pixels SP for displaying different colors. In some embodiments, each sub-pixel includes a light-emitting device LE and a sub-pixel circuit PC connected to each other, and the sub-pixel circuit PC is configured to drive the corresponding light-emitting device LE to emit light. FIG2A schematically shows a cross-sectional structure diagram of a sub-pixel SP. Each sub-pixel has a similar structure, but the positional relationship between the light-emitting device and the sub-pixel circuit of different sub-pixels may be different. FIG2B schematically shows a cross-sectional view of three sub-pixels in a pixel unit. It should be understood that the display panel 500 may include any suitable number of pixel units, and the number of sub-pixels included in each pixel unit is not limited.

[0068] 2A and 2B , in some embodiments, the display panel 500 includes a pixel circuit layer 110, a pixel definition layer 112, and a light-emitting device layer 116. The pixel circuit layer 110 is disposed on a side of the base substrate 100 and includes sub-pixel circuits PC for driving corresponding light-emitting devices to emit light. The pixel definition layer 112 can be disposed on a side of the pixel circuit layer 110 away from the base substrate 100 and has a plurality of sub-pixel openings OP, each of which is configured to define a light-emitting region LR of a corresponding sub-pixel. The light-emitting device layer 116 includes light-emitting devices LE for a plurality of sub-pixels SP, with at least a portion of the light-emitting device LE of each sub-pixel SP being located within the corresponding sub-pixel opening OP. That is, the light-emitting region LR of each sub-pixel includes the portion of the light-emitting device LE located within the corresponding sub-pixel opening OP.

[0069] In some embodiments, the sub-pixel circuit PC of each sub-pixel is disposed in the pixel circuit layer 110 and, for example, includes one or more thin-film transistors T and capacitors C. FIG2A schematically illustrates only one thin-film transistor T and one capacitor C, but it should be understood that each sub-pixel circuit may adopt any suitable circuit structure, such as a 2T1C, 3T1C, 6T1C, 7T1C, 8T1C, 10T1C, 6T2C, 7T2C, 8T2C, 10T2C, or other pixel circuit. The pixel circuit of each sub-pixel may be configured and adjusted according to product design and needs. For example, each thin-film transistor T includes a gate G, an active layer AL, a source S, and a drain D; in some embodiments, the source S and the drain D are collectively referred to as source / drain S / D. Each capacitor C may include electrode plates CE1 and CE2 facing each other.

[0070] In some embodiments, a plurality of conductive traces are further provided in the pixel circuit layer 110, such as one or more of a gate signal line, a data signal line, a common electrode line, a detection signal line, a power supply voltage line, an auxiliary connection line, and the like. The plurality of conductive traces are connected to the thin film transistors and capacitors of the corresponding sub-pixels to apply corresponding signals to the corresponding thin film transistors and capacitors and / or to connect the corresponding electrodes of the thin film transistors and capacitors to the common electrode terminal, the voltage terminal, and the like. The conductive traces in the pixel circuit layer may include any traces required for the pixel circuit, and the type and number of the conductive traces are not limited in the present disclosure. Each sub-pixel circuit includes a thin film transistor and a capacitor and at least a portion of the conductive traces connected to the thin film transistor and the capacitor.

[0071] The pixel circuit layer 110 includes a multi-layer circuit pattern and an active pattern (collectively referred to as a pixel circuit pattern). The multi-layer circuit pattern may, for example, include gate electrodes, source and drain electrodes, electrode plates of capacitors of thin-film transistors of multiple sub-pixel circuits, and one or more of the above-mentioned multiple conductive traces. The active pattern may include active layers of thin-film transistors of multiple sub-pixel circuits, or may also include component patterns such as electrode plates of capacitors.

[0072] Referring to Figure 2B, in some embodiments, the display substrate 500 may include sub-pixels SP1, SP2, and SP3 for displaying different colors. For example, sub-pixel SP1 may be a blue sub-pixel, and sub-pixels SP2 and SP3 may be green and red sub-pixels, respectively, or vice versa. Sub-pixel SP1 includes a light-emitting device LE1 and a sub-pixel circuit pc1 for driving light-emitting device LE1 to emit light; sub-pixel SP2 includes a light-emitting device LE2 and a sub-pixel circuit pc2 for driving light-emitting device LE2 to emit light; and sub-pixel SP3 includes a light-emitting device LE3 and a sub-pixel circuit pc3 for driving light-emitting device LE3 to emit light. In some embodiments, sub-pixels SP1, SP2, and SP3 may also be referred to as a first sub-pixel, a second sub-pixel, and a third sub-pixel, but the present disclosure is not limited thereto.

[0073] In some embodiments, the pixel definition layer 112 has sub-pixel openings OP1, OP2, and OP3. The sub-pixel openings OP1, OP2, and OP3 are configured to define the light-emitting regions LR1, LR2, and LR3 of the corresponding sub-pixels SP1, SP2, and SP3, respectively. At least a portion of the light-emitting devices LE1-LE3 of each sub-pixel SP1-SP3 is located within the corresponding sub-pixel openings OP1-OP3. In some embodiments, the sub-pixel openings OP1, OP2, and OP3 may also be referred to as the first sub-pixel opening, the second sub-pixel opening, and the third sub-pixel opening, but the present disclosure is not limited thereto.

[0074] In some embodiments, for example, because the materials of different color sub-pixels may have different performance (eg, luminous efficiency, lifespan, etc.), the area, shape, etc. of each sub-pixel opening (ie, light-emitting area) may be different.

[0075] For example, the sub-pixel openings OP1-OP3 may have different sizes (e.g., width, area, etc.). For example, the area of ​​the sub-pixel opening OP1 of the sub-pixel SP1 (e.g., the blue sub-pixel) may be larger than the areas of the sub-pixel openings OP2 and OP3 of the other sub-pixels (e.g., the green and red sub-pixels). The area of ​​the sub-pixel opening OP2 of the sub-pixel SP2 (e.g., the green sub-pixel) may be larger than the area of ​​the sub-pixel opening OP3 of the sub-pixel SP3 (e.g., the red sub-pixel). In other embodiments, the sub-pixel opening area of ​​the green sub-pixel may also be smaller than the sub-pixel opening area of ​​the red sub-pixel. In this document, unless otherwise defined, the size of the sub-pixel opening (e.g., width, area) refers to the size of the sub-pixel opening in a direction parallel to the main surface of the substrate, and the area of ​​the sub-pixel opening is equivalent to the area of ​​the orthographic projection of the sub-pixel opening on the main surface of the substrate; the orthographic projection of a component on the main surface of the substrate refers to the projection of the component on the substrate in a direction perpendicular to the main surface of the substrate.

[0076] In some embodiments, the pixel circuit layer 110 includes regions R1, R2, and R3 corresponding to the sub-pixel openings OP1, OP2, and OP3, respectively. The orthographic projections of the regions R1, R2, and R3 on the substrate 100 coincide with the orthographic projections of the sub-pixel openings OP1, OP2, and OP3 (i.e., the light-emitting regions LR1, LR2, and LR3) on the substrate 100. In this document, the orthographic projections of two components coincide with each other, indicating that the orthographic projections of the two components have the same boundaries. In some embodiments, the regions R1, R2, and R3 may also be referred to as the first region, the second region, and the third region of the pixel circuit layer 110, respectively.

[0077] In some embodiments, the pixel circuit pattern of the pixel circuit layer 110 includes multiple circuit patterns CP and an active pattern 101, and the density of the pixel circuit patterns of each layer may vary in different regions R1-R3 of the pixel circuit layer 110. The disclosed embodiments can optimize the arrangement of the pixel circuit patterns of each layer based on design differences such as the size of different sub-pixels, particularly optimizing the arrangement of the pixel circuit patterns in regions R1-R3 that overlap with the sub-pixel openings, thereby improving the flatness of the planarization layer above the pixel circuit layer in the corresponding region.

[0078] In this document, the density of pixel circuit patterns in each region represents the area ratio of the pixel circuit patterns within each region, that is, the ratio of the area of ​​the pixel circuit patterns within the region to the area of ​​the region. For each layer of pixel circuit patterns, the area of ​​the pixel circuit patterns within each region R1-R3 is equal to the area of ​​the orthographic projection of the pixel circuit patterns within each region on the substrate, and is also equal to the overlapping area of ​​the pixel circuit patterns in that layer and the corresponding sub-pixel openings. The area of ​​each region R1-R3 is equal to the area of ​​the orthographic projection of the corresponding sub-pixel openings OP1-OP3 on the substrate.

[0079] For example, the pixel circuit layer 110 includes a first conductive layer, which includes a plurality of first circuit patterns for a plurality of sub-pixels, wherein the density of the plurality of first circuit patterns in region R3 of the pixel circuit layer 110 may be less than the density in regions R1 or R2. For example, the orthographic projections of the plurality of first circuit patterns on the base substrate 100 overlap with the orthographic projection of at least one of the sub-pixel openings OP1 to OP3 on the base substrate; and the ratio of the overlapping area of ​​the plurality of first circuit patterns with the sub-pixel opening OP3 to the area of ​​the sub-pixel opening OP3 (i.e., equivalent to the density of the first circuit patterns in region R3) is less than the ratio of the overlapping area of ​​the plurality of first circuit patterns with the sub-pixel opening OP1 to the area of ​​the sub-pixel opening OP1 (i.e., equivalent to the density of the first circuit patterns in region R1) or the ratio of the overlapping area of ​​the plurality of first circuit patterns with the sub-pixel opening OP2 to the area of ​​the sub-pixel opening OP2 (i.e., equivalent to the density of the first circuit patterns in region R2). Here, the overlapping area of ​​the first circuit pattern and the sub-pixel openings OP1-OP3 refers to the area of ​​the overlapping portion of the orthographic projection of the first circuit pattern on the substrate and the orthographic projection of the corresponding sub-pixel openings OP1-OP3 on the substrate, and is equal to the orthographic projection area of ​​the first circuit pattern on the substrate within the corresponding region R1-R3. The first conductive layer may be the layer where the gate or the source and drain of the thin film transistors of the multiple sub-pixel circuits are located, and may also include an electrode plate of a capacitor and one or more of the multiple conductive traces. For example, the pixel circuit layer includes multiple pattern layers, each pattern layer includes multiple patterns, and the first conductive layer may be the topmost pattern layer of the multiple pattern layers that is closest to the light-emitting device layer in a direction perpendicular to the main surface of the substrate, or the first conductive layer is located on the side of the topmost pattern layer of the multiple pattern layers that is away from the light-emitting device.

[0080] In some embodiments, the overall density of at least two of the circuit patterns CP disposed in regions R1, R2, and R3 may differ from one another. For example, the overall density of the circuit patterns CP disposed in region R1 may be greater than the overall density of the circuit patterns CP disposed in region R2 or the overall density of the circuit patterns CP disposed in region R3. For example, the overall density of the circuit patterns disposed in region R2 may be greater than or substantially equal to the overall density of the circuit patterns disposed in region R3. In some embodiments, the pixel circuit layer includes multiple layers of circuit patterns, and the overall density of the circuit patterns within each region of the pixel circuit layer is the sum of the densities of the circuit patterns in each layer within each region.

[0081] In some embodiments, the sub-pixel circuit patterns of multiple sub-pixels are concentrated at positions corresponding to some sub-pixel openings (for example, the area directly below and the area nearby in the figure), and there is basically no circuit pattern below some sub-pixel openings, thereby improving the flatness of the bottom of each sub-pixel opening.

[0082] For example, in sub-pixels SP1 to SP3, part of the circuit patterns (e.g., most of the circuit patterns) of the sub-pixel circuits pc1-pc3 of these sub-pixels are concentrated in the area R1 below the sub-pixel opening OP1 and the area near it, part of the circuit patterns (e.g., a small part of the circuit patterns) are set in the area R2 below the sub-pixel opening OP2 and the area near it, and the area R3 below the sub-pixel opening OP3 may be substantially free of circuit patterns. In some embodiments, the density of the circuit patterns in each area may be roughly positively correlated with the size of the corresponding sub-pixel opening, that is, the larger the sub-pixel opening size, the higher the density of circuit patterns may be set in the corresponding area below it. In some embodiments, the density of the circuit patterns in the area corresponding to the smaller (e.g., smallest) sub-pixel opening OP3 may approach zero. However, the present disclosure is not limited to this.

[0083] In some embodiments, at least a portion of the orthographic projection of at least one of the sub-pixels SP1-SP3 on the substrate substrate is located outside the orthographic projection of the corresponding sub-pixel opening on the substrate substrate and may overlap with the orthographic projections of one or more other sub-pixel openings on the substrate substrate. For example, at least a portion of the orthographic projection of the sub-pixel circuit pc3 of sub-pixel SP3 on the substrate substrate 100 is located outside the orthographic projection of the sub-pixel opening OP3 on the substrate substrate 100 and may overlap with the orthographic projection of at least one of the sub-pixel openings OP1 and OP2 on the substrate substrate 100 and / or is located in a region proximal to the orthographic projection of the sub-pixel opening OP1 or OP2 on the substrate substrate 100. At least a portion of the orthographic projection of the sub-pixel circuit pc2 of sub-pixel SP2 on the substrate substrate 100 may be located outside the orthographic projection of the sub-pixel opening OP2 on the substrate substrate 100 and may overlap with the orthographic projection of the sub-pixel opening OP1 on the substrate substrate 100.

[0084] In some embodiments, the pixel circuit layer 110 includes an active material layer L0, a conductive layer L1, and a conductive layer L2. Conductive layer L1 and conductive layer L2 may be referred to as a first conductive layer and a second conductive layer, respectively, or vice versa. Active material layer L0 includes multiple active patterns 101 (or an active pattern group) for multiple sub-pixels, conductive layer L1 includes multiple circuit patterns 103 for multiple sub-pixels, and conductive layer L2 includes multiple circuit patterns 108 for multiple sub-pixels. Circuit patterns 103 and circuit patterns 108 may be referred to as a first circuit pattern and a second circuit pattern, respectively, or vice versa; the multiple circuit patterns 103 and the multiple circuit patterns 108 for multiple sub-pixels may be referred to as a first circuit pattern group and a second circuit pattern group, respectively, or vice versa. For example, conductive layer L1 is the layer where the gate G of the thin-film transistor T of the sub-pixel circuit is located, conductive layer L2 is the layer where the source and drain electrodes S / D of the thin-film transistor T of the sub-pixel circuit are located, and active material layer L0 is the layer where the active layer AL of the thin-film transistor T of each sub-pixel circuit is located. It should be understood that the number of material layers of the pixel circuit layer shown in the figure is only for illustration and the present disclosure is not limited thereto. For example, the pixel circuit layer may further include one or more other conductive layers in addition to the conductive layers L1 and L2.

[0085] The plurality of circuit patterns 103 may include circuit patterns having similar shapes, similar routing directions, and / or connecting the same type of signals to a plurality of sub-pixels. For example, the plurality of circuit patterns 103 include circuit patterns configured to connect gate scan signals to a plurality of sub-pixels. For example, the plurality of circuit patterns 103 may include gates G of a plurality of thin-film transistors of a plurality of sub-pixels and conductive routing lines such as gate signal lines, compensation signal lines, and auxiliary connection lines connected to these gates G, or may also include conductive patterns such as electrode plates and auxiliary cathodes connected to the cathodes of light-emitting devices; the plurality of circuit patterns 108 may include circuit patterns having similar shapes, similar routing directions, and / or connecting the same type of signals to a plurality of sub-pixels. For example, the plurality of circuit patterns 108 include circuit patterns configured to connect data signals to a plurality of sub-pixels. For example, the multiple circuit patterns 108 may include, for example, source / drain electrodes S / D of multiple thin-film transistors of multiple sub-pixels, as well as conductive traces such as data signal lines, auxiliary connection lines, and compensation signal lines connected to the source / drain electrodes S / D, or may further include electrode plates, auxiliary cathodes connected to the cathodes of the light-emitting devices, and the like; the multiple active patterns 101 may include, for example, active layers AL of multiple thin-film transistors of multiple sub-pixels. In some embodiments, the two electrode plates of the capacitor of each sub-pixel circuit may be located in two of the conductive layer L1, the conductive layer L2, and the active material layer L0, or one of the two electrode plates may be located in one of the conductive layer L1, the conductive layer L2, and the active material layer L0, while the other electrode plate may be located in another conductive layer (e.g., another conductive layer located between the conductive layer L1 and the conductive layer L2). The present disclosure does not limit the location of the electrode plates of the capacitor.

[0086] For example, the sub-pixel circuit of each sub-pixel may include a circuit pattern 103 located on conductive layer L1, a circuit pattern 108 located on conductive layer L2, and an active pattern 101 located on active material layer L0. In each sub-pixel circuit, circuit pattern 103 includes conductive traces such as a gate electrode and gate lines, second circuit pattern 103 includes conductive traces such as a source / drain electrode and data signal lines, and active pattern 101 may include active layer AL. At least one of circuit pattern 103, circuit pattern 108, and active pattern 101 may also include an electrode plate of a capacitor. The circuit patterns 103 of the multiple sub-pixel circuits constitute a first circuit pattern group located on conductive layer L1, the circuit patterns 108 of the multiple sub-pixel circuits constitute a second circuit pattern group located on conductive layer L2, and the active patterns 101 of the multiple sub-pixel circuits constitute an active pattern group located on active material layer L0.

[0087] In some embodiments, the display panel 500 further includes an insulating layer 102, an insulating layer 105, and a planarization layer 111 sequentially disposed on the base substrate 100. The insulating layer 102 is disposed on one side of the base substrate 100 and covers the sidewalls of the active material layer L0 and its surface away from the base substrate 100. The insulating layer 102 is located between the active material layer L0 and the conductive layer L1 and can serve as a gate insulation layer for multiple thin film transistors. The insulating layer 105 is disposed on the side of the conductive layer L1 away from the base substrate 100, for example, between the conductive layer L1 and the conductive layer L2, and covers the sidewalls of the conductive layer L1 and its surface away from the base substrate 100. The planarization layer 111 is disposed between the pixel circuit layer 110 and the pixel definition layer 112 (and the light-emitting device layer 116), for example, on the side of the conductive layer L2 away from the base substrate 100, and covers the sidewalls of the conductive layer L2 and its surface away from the base substrate 100. In other words, the active material layer L0 is located in the insulating layer 102, the first conductive layer 103 is located in the insulating layer 105, and the conductive layer L2 is located in the planarization layer 111. In some embodiments, a plurality of vias are further provided in the insulating layer 102, the insulating layer 105, and the planarization layer 111 to provide electrical connections between the layers in the pixel circuit layer and between the pixel circuit layer and the light-emitting device.

[0088] The planarization layer 111 is configured to provide a flat surface for the light-emitting device of each sub-pixel, for example, to provide a flat surface for at least the opening area of ​​each sub-pixel, so that the light-emitting device of each sub-pixel is formed on the flat surface, thereby improving the light uniformity of the light-emitting device of each sub-pixel.

[0089] In some embodiments, the flatness of the planarization layer 111 in each region is affected by the circuit patterns / active patterns of each layer in that region. For example, the arrangement of the active pattern 101 of the active material layer L0 directly affects the flatness of the insulating layer 102 in each region, and also affects the flatness of the overlying planarization layer 111. The arrangement of the circuit pattern 103 of the conductive layer L1 directly affects the flatness of the insulating layer 105 in each region, thereby affecting the flatness of the overlying planarization layer 111. The arrangement of the circuit pattern 108 of the conductive layer L2 directly affects the flatness of the planarization layer 111. The disclosed embodiment optimizes the arrangement of the pixel circuit patterns of each layer of the pixel circuit layer to minimize the impact of the pixel circuit patterns on the flatness of the planarization layer. This ensures that at least the portions of the planarization layer 111 located above regions R1-R3 of the pixel circuit layer have a high degree of flatness. This allows the light-emitting devices LE1 to LE3 to be formed on a flat surface with a high degree of flatness, thereby improving the uniformity of light emission of each sub-pixel.

[0090] 3A illustrates a schematic plan view of a plurality of circuit patterns 103 of a conductive layer L1 and a plurality of sub-pixel openings OP1-OP3 in a display panel according to some embodiments of the present disclosure. FIG3B illustrates a more detailed schematic plan view of a plurality of circuit patterns 103 of a conductive layer L1 and a plurality of sub-pixel openings OP1-OP3 in a display panel according to some embodiments of the present disclosure.

[0091] 2A , 3A , and 3B , in some embodiments, the density of the plurality of circuit patterns 103 in the respective regions R1 to R3 of the pixel circuit layer 110 is different from one another. For example, in the conductive layer L1 , the density of the circuit patterns 103 disposed in region R1 is greater than the density of the circuit patterns 103 disposed in regions R2 and R3. That is, the ratio of the area of ​​the orthographic projection of the circuit pattern 103 located in the region R1 on the substrate 100 (equivalent to the overlapping area of ​​the circuit pattern 103 and the sub-pixel opening OP1) to the area of ​​the orthographic projection of the region R1 on the substrate 100 (equivalent to the area of ​​the sub-pixel opening OP1) is greater than the ratio of the area of ​​the orthographic projection of the circuit pattern 103 located in the region R2 on the substrate 100 (equivalent to the overlapping area of ​​the circuit pattern 103 and the sub-pixel opening OP2) to the area of ​​the orthographic projection of the region R2 on the substrate 100 (equivalent to the area of ​​the sub-pixel opening OP2), and is greater than the ratio of the area of ​​the orthographic projection of the circuit pattern 103 located in the region R3 on the substrate 100 (equivalent to the overlapping area of ​​the circuit pattern 103 and the sub-pixel opening OP3) to the area of ​​the orthographic projection of the region R3 on the substrate 100 (equivalent to the area of ​​the sub-pixel opening OP3). As described above, the orthographic projections of regions R1 to R3 on the substrate 100 coincide with the orthographic projections of the sub-pixel openings OP1 to OP3 on the substrate 100; therefore, the areas of the orthographic projections of regions R1, R2, and R3 on the substrate 100 are respectively equal to the areas of the orthographic projections of the sub-pixel openings OP1 to OP3 on the substrate.

[0092] In some embodiments, the overlapping area between the plurality of circuit patterns 103 and the sub-pixel opening OP1 may be greater than the overlapping area between the plurality of circuit patterns 103 and the sub-pixel opening OP3 and / or greater than the overlapping area between the plurality of circuit patterns 103 and the sub-pixel opening OP2. In some embodiments, the overlapping area between the plurality of circuit patterns 103 and the sub-pixel opening OP1 may be greater than the sum of the overlapping area between the plurality of circuit patterns 103 and the sub-pixel opening OP3 and the overlapping area between the plurality of circuit patterns 103 and the sub-pixel opening OP2. For example, the overlapping area between the plurality of circuit patterns 103 and at least one of the sub-pixel openings OP2 and OP3 may be zero or close to zero. That is, the orthographic projections of the plurality of circuit patterns 103 on the base substrate 100 may not overlap with at least one of the orthographic projections of the sub-pixel opening OP2 and the sub-pixel opening OP3 on the base substrate.

[0093] For example, an orthographic projection of at least a portion of the circuit pattern 103 of at least two of the sub-pixel circuits pc1 to pc3 on the base substrate 100 may overlap with an orthographic projection of the sub-pixel opening OP1 on the base substrate 100 . For example, the orthographic projection of the circuit pattern 103 in the sub-pixel circuit pc3 of the sub-pixel SP3 on the substrate substrate 100 may be located outside the orthographic projection of the corresponding sub-pixel opening OP3 on the substrate substrate 100; the orthographic projection of the circuit pattern 103 in the sub-pixel circuit pc2 of the sub-pixel SP2 on the substrate substrate 100 may be located outside the orthographic projection of the corresponding sub-pixel opening OP2 on the substrate substrate 100; for example, the orthographic projection of the circuit pattern 103 of the sub-pixel circuit pc1 on the substrate substrate may overlap with the orthographic projection of the sub-pixel opening OP1 on the substrate substrate 100, and at least part of the orthographic projection of at least one of the circuit pattern 103 of the sub-pixel circuit pc2 and the circuit pattern 103 of the sub-pixel circuit pc3 on the substrate substrate 100 may also overlap with the orthographic projection of the sub-pixel opening OP1 on the substrate substrate 100 and / or be located in an orthographic projection area close to the sub-pixel opening OP1 on the substrate substrate 100.

[0094] In some embodiments, the circuit patterns 103 of sub-pixel circuits pc1 through pc3 may all be concentrated in region R1 corresponding to sub-pixel opening OP1 and in a region proximate to region R1, and at least one of regions R2 and R3 corresponding to sub-pixel openings OP2 and OP3 may be substantially free of circuit patterns 103. In some embodiments, the circuit patterns 103 that overlap sub-pixel opening OP1 in a direction perpendicular to the main surface of the substrate (i.e., the circuit patterns 103 located in region R1) may include the circuit pattern 103 of sub-pixel circuit pc1 and may also include circuit patterns 103 of one or more of sub-pixel circuits pc2 and pc3. It should be understood that the arrangement shown in the figures is merely illustrative and the present disclosure is not limited thereto. As long as the density of the circuit patterns 103 in each region is arranged in a similar manner as described above, the flatness of each sub-pixel opening region can be improved. When the number of circuit patterns in the conductive layer L1 is relatively small, the circuit patterns 103 of the sub-pixel circuits pc1-pc3 can be concentrated in the region corresponding to the same sub-pixel opening. In other cases where the number of patterns in the conductive layer L1 is large, the circuit patterns 103 of the multiple sub-pixel circuits pc1-pc3 can also be concentrated in the regions corresponding to two sub-pixel openings. In other words, the circuit patterns 103 of the multiple sub-pixel circuits pc1-pc3 can overlap with two of the sub-pixel openings OP1-OP3, while the circuit pattern 103 may not be provided in the region overlapping with the other sub-pixel opening.

[0095] 4A and 4B are plan views illustrating circuit patterns 108 of a plurality of sub-pixels and sub-pixel openings OP1 - OP3 in a conductive layer L2 in some embodiments of the present disclosure.

[0096] 2B , 4A, and 4B , in some embodiments, the circuit patterns 108 of the plurality of sub-pixels may have different densities in the regions R1-R3 of the pixel circuit layer 110. For example, the density of the circuit patterns 108 in region R3 may be lower than the density of the circuit patterns 108 in region R1 or the density of the circuit patterns 108 in region R2, and the densities of the circuit patterns 108 disposed in region R1 and region R2 may be the same or different.

[0097] That is, the ratio of the overlapping area of ​​the circuit pattern 108 of the plurality of sub-pixels and the sub-pixel opening OP3 to the area of ​​the sub-pixel opening OP3 is smaller than the ratio of the overlapping area of ​​the circuit pattern 108 of the plurality of sub-pixels and the sub-pixel opening OP2 to the area of ​​the sub-pixel opening OP2, and is smaller than the ratio of the overlapping area of ​​the circuit pattern 108 of the plurality of sub-pixels and the sub-pixel opening OP1 to the area of ​​the sub-pixel opening OP1. The ratio of the overlapping area of ​​the first circuit pattern 108 and the sub-pixel opening OP1 to the area of ​​the sub-pixel opening OP1 and the ratio of the overlapping area of ​​the circuit pattern 108 and the sub-pixel opening OP2 to the area of ​​the sub-pixel opening OP2 may be the same as or different from each other. In some embodiments, the overlapping area between the multiple circuit patterns 108 and the sub-pixel opening OP1 or OP2 is greater than the overlapping area between the multiple circuit patterns 108 and the sub-pixel opening OP3. For example, the overlapping area between the circuit patterns 108 of the multiple sub-pixels and the sub-pixel opening OP3 may be zero or approximately equal to zero; the overlapping area between the multiple circuit patterns 108 and the sub-pixel opening OP1 may be greater than the overlapping area between the multiple circuit patterns 108 and the sub-pixel opening OP2.

[0098] In some embodiments, the sub-pixel circuit pc3 may not be disposed in the region R3 corresponding to the sub-pixel opening OP3, and may, for example, be disposed in and / or near at least one of the regions R1 and R2 corresponding to the sub-pixel openings OP1 and OP2. That is, the orthographic projection of the circuit pattern 108 of the sub-pixel circuit pc3 on the substrate substrate 100 may not overlap with the orthographic projection of the sub-pixel opening OP3 on the substrate substrate 100, but may overlap with the orthographic projection of at least one of the sub-pixel openings OP1 and OP2 (e.g., the sub-pixel opening OP1) on the substrate substrate and / or may be near the orthographic projection of at least one of the sub-pixel openings OP1 and OP2 on the substrate substrate.

[0099] For example, as shown in FIG4A , the circuit pattern 108 overlapping with the sub-pixel opening OP1 may include at least a portion of the circuit pattern 108 of the sub-pixel circuit pc1 and may also include at least a portion of the circuit pattern of the sub-pixel circuit pc3. The circuit pattern 108 overlapping with the sub-pixel opening OP2 may include at least a portion of the circuit pattern 108 of the sub-pixel circuit pc2. It should be understood that the above arrangement is merely illustrative and the present disclosure is not limited thereto. As long as the density of the circuit pattern 108 in each region is arranged in the above manner or a similar manner, thereby improving the flatness of each sub-pixel opening region, the planarity of each sub-pixel opening region can be improved. For example, a portion of the sub-pixel circuit pc3 may also be arranged in region R2, or a portion of the sub-pixel circuit pc1 may also be arranged in region R2, and a portion of the sub-pixel circuit pc2 may also be arranged in region R1.

[0100] In the above-described embodiment, optimizing the arrangement of the circuit patterns in each layer includes arranging the circuit patterns in each layer by zones (i.e., concentrating multiple sub-pixel circuits in areas corresponding to some sub-pixel openings) to adjust the density of the circuit patterns in areas overlapping with the sub-pixel openings, thereby improving the flatness of each sub-pixel opening area. In other embodiments, optimizing the arrangement of the circuit patterns in each layer may alternatively or further include adjusting the uniformity of the arrangement of the circuit patterns in areas overlapping with corresponding sub-pixel openings to further improve the flatness of each sub-pixel opening area.

[0101] FIG. 3C shows a schematic planar arrangement diagram of a plurality of circuit patterns 103 and a plurality of sub-pixel openings OP1 - OP3 of the conductive layer L1 according to some other embodiments of the present disclosure.

[0102] Referring to FIG. 3C , in some embodiments, the orthographic projection of a portion of the conductive layer L1 on the substrate 100 overlaps the orthographic projection of the sub-pixel opening OP1 on the substrate 100. The portion of the conductive layer L1 may, for example, include multiple traces arranged with substantially equal line widths and spacings. For example, the portion of the conductive layer L1 may include multiple traces (or trace patterns) 103t in the circuit pattern 103 of multiple sub-pixels. The multiple traces 103t may include, for example, signal traces such as gate lines, but the present disclosure does not limit the types of the multiple traces. The line widths w1 of the multiple traces 103t may be substantially the same, and the spacing d1 between adjacent traces 103t may be substantially the same. The line widths w1 and spacing d1 may be substantially the same or different. In this context, "two or more values ​​being substantially the same" may include the values ​​being exactly the same, and also includes the case where the difference between each value and the average of the two or more values ​​is less than 5% to 20% of the average, for example, less than 5%, 10%, 15%, or 20% of the average. That is to say, the difference between the line width of each of the multiple routes and the average line width of the multiple routes is less than 5% to 20% of the average line width, and the difference between the spacing between each two adjacent routes and the average spacing between different adjacent routes is less than 5% to 20% of the average spacing.

[0103] For example, multiple traces 103t may extend parallel to one another along direction D1 and be arranged along direction D2. Directions D1 and D2 are both parallel to the main surface of the substrate, and directions D1 and D2 intersect each other, for example, are perpendicular to each other. The line width w1 of trace 103t refers to the width of trace 103t in direction D2, and the spacing d1 between adjacent traces 103t1 refers to the distance between two adjacent traces in direction D2, that is, the width of the gap between adjacent traces in direction D2.

[0104] In some embodiments, by setting equal line width spacing for multiple traces 103t overlapping the sub-pixel opening OP1 in the conductive layer L1, the uniformity of the circuit pattern distribution in the area is improved, thereby improving the flatness of the sub-pixel opening area corresponding to the planarization layer above the conductive layer L1.

[0105] FIG4C is a schematic diagram showing a planar arrangement of a circuit pattern of a second conductive layer and a plurality of sub-pixel openings according to some other embodiments of the present disclosure.

[0106] 2B and 4C , in some embodiments, in the conductive layer L2, the circuit pattern 108 of the plurality of sub-pixels includes a first portion P1 and a second portion P2. The orthographic projections of the first portion P1 and the second portion P2 on the base substrate 100 overlap with the orthographic projections of the sub-pixel openings OP1 and OP2 on the base substrate, respectively. For example, the first portion P1 may include at least a portion of the plurality of traces 108t1, and the second portion P2 may include at least a portion of the plurality of traces 108t2. The plurality of traces 108t1 and 108t2 may include, for example, conductive traces such as data signal lines connecting the source and drain electrodes of the thin-film transistors of the plurality of sub-pixels. The present disclosure does not limit the types of these traces.

[0107] In some embodiments, the plurality of traces 108t1 and 108t2 may extend substantially parallel to each other along direction D2 and be arranged along direction D1. The plurality of traces 108t1 overlapping the sub-pixel opening OP1 may have substantially the same line width w10 and be spaced apart from each other by a spacing d10. When the number of traces 108t1 is greater than two, the spacing d10 between adjacent traces 108t1 is substantially the same. The spacing d10 may be substantially the same as or different from the line width w10. The plurality of traces 108t2 overlapping the sub-pixel opening OP2 may have substantially the same line width w20 and be spaced apart from each other by a spacing d20. When the number of traces 108t1 is greater than two, the spacing d20 between adjacent traces 108t2 is substantially the same. The spacing d20 may be substantially the same as or different from the line width w20. In some embodiments, the line widths w10 and w20 of the plurality of traces 108 t 1 and 108 t 2 may be the same as or different from each other, and the spacings d10 and d20 may be the same as or different from each other.

[0108] In some embodiments, when arranging the plurality of circuit patterns 108 of the conductive layer L2, the plurality of traces within the plurality of circuit patterns 108 are categorized, and traces having similar characteristics (e.g., substantially the same line width and spacing) are concentrated below the same pixel opening, thereby minimizing the impact of the circuit patterns on the flatness of the planarization layer above. This allows the portion of the planarization layer below each sub-pixel opening to have a high degree of flatness, thereby allowing the light-emitting devices of the plurality of sub-pixels to be formed on a flat surface, thereby improving the uniformity of light emission across the sub-pixels. For example, the plurality of traces 108t1 are traces of the first type, and the plurality of traces 108t2 are traces of the second type, and the line width w10 and spacing d10 of the plurality of traces 108t1 are different from the line width w20 and spacing d20 of the plurality of traces 108t2.

[0109] FIG5A is a schematic diagram illustrating a planar arrangement of active material layers and sub-pixel openings in a display panel according to some embodiments of the present disclosure.

[0110] 5A , in some embodiments, in the active material layer L0, active patterns 101 of a plurality of sub-pixels may be concentrated in an area corresponding to the sub-pixel openings of a portion of sub-pixels (e.g., one or more sub-pixels), while no active pattern may be provided in an area corresponding to the sub-pixel openings of another portion of sub-pixels (e.g., one or more sub-pixels).

[0111] In some embodiments, the ratio of the overlapping area of ​​the active pattern of the plurality of sub-pixels with the second sub-pixel opening to the area of ​​the second sub-pixel opening is smaller than the ratio of the overlapping area of ​​the active pattern with the first sub-pixel opening to the area of ​​the first sub-pixel opening, and may be smaller than or equal to the ratio of the overlapping area of ​​the active pattern with the third sub-pixel opening to the area of ​​the third sub-pixel opening. The ratio of the overlapping area of ​​the active pattern with the third sub-pixel opening to the area of ​​the third sub-pixel opening may be smaller than or greater than the ratio of the overlapping area of ​​the active pattern with the first sub-pixel opening to the area of ​​the first sub-pixel opening.

[0112] For example, the active patterns 101 of the plurality of sub-pixels may include an active pattern 101a for sub-pixel circuit pc1, an active pattern 101b for sub-pixel circuit pc2, and an active pattern 101c for sub-pixel circuit pc3. The active pattern 101a for sub-pixel circuit pc1 may be disposed in a region corresponding to the sub-pixel opening OP1, for example, region R1 and / or a region adjacent to region R1. Furthermore, at least one of the active pattern 101b for sub-pixel circuit pc2 and the active pattern 101c for sub-pixel circuit pc3 may also be disposed in a region corresponding to the sub-pixel opening OP1. That is, the orthographic projections of the active pattern 101a and at least one of the active patterns 101b and 101c on the substrate 100 may overlap with the orthographic projection of the sub-pixel opening OP1 on the substrate 100.

[0113] For example, as shown in FIG5A , the active patterns 101a, 101b, and 101c of the sub-pixel circuits pc1, pc2, and pc3 may be concentrated in an area corresponding to the sub-pixel opening OP1, such as area R1 and / or an area near area R1. In some embodiments, substantially no active pattern may be disposed in areas R2 and R3 overlapping the sub-pixel openings OP2 and OP3.

[0114] In other words, in some embodiments, the orthographic projections of the active patterns 101b and 101c of the sub-pixel circuits pc2 and pc3 on the substrate substrate 100 may both be located outside the orthographic projections of the sub-pixel openings OP2 and OP3 on the substrate substrate 100, and the orthographic projections of the active patterns 101a, 101b and 101c of the sub-pixel circuits pc1, pc2 and pc3 on the substrate substrate 100 may all overlap (for example, partially overlap) with the orthographic projection of the sub-pixel opening OP1 on the substrate substrate 100.

[0115] In this embodiment, as shown in FIG5A , the density of the active patterns 101 disposed in region R1 is greater than the density of the active patterns 101 in regions R2 and R3. The density of the active patterns 101 in region R2 and the density of the active patterns in region R3 may be the same, for example, both are 0. That is, the ratio of the overlapping area of ​​the active patterns 101 of the plurality of sub-pixels with the sub-pixel opening OP1 to the area of ​​the sub-pixel opening OP1 is greater than the ratio of the overlapping area of ​​the active patterns 101 with the sub-pixel opening OP2 to the area of ​​the sub-pixel opening OP2, and is also greater than the ratio of the overlapping area of ​​the active patterns 101 with the sub-pixel opening OP3 to the area of ​​the sub-pixel opening OP3. The ratio of the overlapping area of ​​the active patterns 101 with the sub-pixel opening OP2 to the area of ​​the sub-pixel opening OP2 may be the same as the ratio of the overlapping area of ​​the active patterns 101 with the sub-pixel opening OP3 to the area of ​​the sub-pixel opening OP3, for example, both are 0.

[0116] For example, the overlap area between the active pattern 101 and the sub-pixel opening OP1 is greater than the overlap area between the active pattern 101 and the sub-pixel opening OP2 or OP3. The overlap area between the active pattern 101 and at least one of the sub-pixel openings OP2 and OP3 may be zero.

[0117] FIG5B is a schematic diagram showing a planar arrangement of an active pattern of an active material layer and openings of each sub-pixel according to some other embodiments of the present disclosure.

[0118] 5B , in some embodiments, in the active material layer L0 of the pixel circuit layer, no active pattern may be provided in the regions corresponding to some sub-pixel openings, a full-sheet active pattern may be provided in the regions corresponding to some sub-pixel openings, and multiple active patterns may be provided in the regions corresponding to other sub-pixel openings. For example, no active pattern may be provided in the region corresponding to sub-pixel opening OP2 (region R2 and / or the region nearby), multiple active patterns may be provided in the region corresponding to sub-pixel opening OP1 (region R1 and / or the region nearby), and the multiple active patterns may be spaced apart from each other; and a full-sheet active pattern may be provided in the region corresponding to sub-pixel opening OP3 (region R3 and / or the region nearby).

[0119] For example, at least a portion of the active pattern 101a of the sub-pixel circuit pc1 may be located in the region R1, and the orthographic projection of the active pattern 101a on the substrate substrate 100 overlaps with the orthographic projection of the sub-pixel opening OP1 on the substrate substrate 100; the orthographic projection of at least one of the active pattern 101b of the sub-pixel circuit pc2 and the active pattern 101c of the sub-pixel circuit pc3 on the substrate substrate 100 may overlap with the orthographic projection of the sub-pixel opening 101 on the substrate substrate.

[0120] For example, the orthographic projection of the active pattern 101b of the sub-pixel circuit pc2 on the substrate 100 may be outside the orthographic projection of the sub-pixel opening OP2 on the substrate 100, and the orthographic projections of the active pattern 101b of the sub-pixel circuit pc2 and the active pattern 101a of the sub-pixel circuit pc1 on the substrate 100 may both overlap with the orthographic projection of the sub-pixel opening OP1 on the substrate 100; the active patterns 101a and 101b are spaced apart from each other. The orthographic projection of the active pattern 101c of the sub-pixel circuit pc3 on the substrate 100 may overlap with the orthographic projection of the sub-pixel opening OP3 on the substrate 100, and the orthographic projection of the sub-pixel opening OP3 on the substrate 100 may be within the range of the orthographic projection of the active pattern 101c on the substrate 100.

[0121] In this embodiment, as shown in FIG5B , the density of the active patterns 101 disposed in region R3 of the pixel circuit layer may be greater than the density of the active patterns 101 in region R1, and the density of the active patterns 101 in region R1 may be greater than the density of the active patterns 101 in region R2. That is, the ratio of the overlapping area of ​​the active patterns 101 of the plurality of sub-pixels and the sub-pixel opening OP3 to the area of ​​the sub-pixel opening OP3 (i.e., 1) is greater than the ratio of the overlapping area of ​​the active patterns 101 and the sub-pixel opening OP1 to the area of ​​the sub-pixel opening OP1, and the ratio of the overlapping area of ​​the active patterns 101 and the sub-pixel opening OP1 to the area of ​​the sub-pixel opening OP1 is greater than the ratio of the overlapping area of ​​the active pattern 101 and the sub-pixel opening OP2 to the area of ​​the sub-pixel opening OP2 (e.g., 0).

[0122] As shown in Figures 5A and 5B, in some embodiments, the sizes of sub-pixel openings OP1, OP2, and OP3 are different from each other. For example, the area of ​​sub-pixel opening OP1 is larger than the area of ​​sub-pixel opening OP2, and the area of ​​sub-pixel opening OP2 is larger than the area of ​​sub-pixel opening OP3. In some embodiments, the region R3 corresponding to the sub-pixel opening OP3 with a smaller area may not be provided with an active pattern or may be provided with a whole active pattern. The region R1 corresponding to the sub-pixel opening OP1 with a larger area may be provided with multiple active patterns, and the multiple active patterns are spaced apart from each other. The region R2 corresponding to the sub-pixel opening OP2 with an intermediate area (i.e., an area at an intermediate level compared to other sub-pixel openings) may not be provided with an active pattern. However, the present disclosure is not limited to this.

[0123] For example, the overlapping area between the active pattern 101 and the sub-pixel opening OP2 may be smaller than the overlapping area between the active pattern 101 and the sub-pixel opening OP1 or the overlapping area between the active pattern 101 and the sub-pixel opening OP3. The overlapping area between the active pattern 101 and the sub-pixel opening OP1 may be larger than the overlapping area between the active pattern 101 and the sub-pixel opening OP3. For example, the overlapping area between the active pattern 101 and the sub-pixel opening OP3 may be equal to the area of ​​the sub-pixel opening OP3.

[0124] FIG6 is a plan view schematically illustrating a pixel circuit pattern and a sub-pixel opening according to some embodiments of the present disclosure.

[0125] In some embodiments, at least one of the conductive layer L1, the conductive layer L2, the active material layer L0, and / or other pattern layers includes a block pattern, and the orthographic projection of a portion of the block pattern on the base substrate 100 overlaps with the orthographic projection of a sub-pixel opening on the base substrate 100. In some embodiments, the block pattern is linearized for uniformity, that is, the portion of the block pattern overlapping the sub-pixel opening is split into multiple strip patterns, and the multiple strip patterns are further uniformly arranged, thereby improving the flatness of the area corresponding to the sub-pixel opening. The block pattern may, for example, include a square block pattern, a rectangular block pattern, a circular block pattern, an elliptical block pattern, or any other type of block pattern. In this article, a block pattern refers to a pattern whose ratio of its dimension along the first direction (e.g., width, length, etc.) to its dimension along the second direction (e.g., width, length, etc.) is in the range of 1:1 to 5:1 or 1:1 to 6:1, and the second direction is roughly perpendicular to the first direction; a strip pattern refers to a pattern whose ratio of its dimension along the first direction (e.g., length) to its dimension along the second direction (e.g., width) is greater than or equal to 10:1.

[0126] In some embodiments, when the overlapping area of ​​the block pattern and the sub-pixel opening occupies more than 10% of the sub-pixel opening area, the block pattern has a greater impact on the flatness of the area corresponding to the sub-pixel opening. At this time, the block pattern is designed to be linearly uniform, and the ratio of the overlapping area of ​​the block pattern and the sub-pixel opening to the sub-pixel opening area is reduced to below 10%, for example, below 8% or below 5%, thereby reducing the impact of the block pattern on the flatness of the area corresponding to the sub-pixel opening and improving the flatness of the planarization layer area corresponding to the sub-pixel opening.

[0127] In some embodiments, the block pattern may include at least one of one or more gate patterns, one or more source / drain patterns, one or more transfer electrode patterns, one or more active patterns, or other types of patterns. The block pattern may be a circuit pattern that connects gate scan signals, data signals, detection signals, compensation signals, ground signals, or any other type of signal. This disclosure does not limit the specific functions of the block pattern or the types of signals it connects.

[0128] 6 schematically illustrates the positional relationship between multiple patterns of the pattern layer L and the sub-pixel opening OP in the pixel circuit layer 110. The sub-pixel opening OP can be any of the sub-pixel openings OP1, OP2, and OP3 described above, and the pattern layer L can be any of the active material layer L0, the conductive layer L1, and the conductive layer L2.

[0129] Referring to Figure 6, in some embodiments, the orthographic projections of the multiple patterns ap and bp located in the pattern layer L on the substrate 100 overlap (e.g., partially overlap) with the orthographic projections of the sub-pixel opening OP on the substrate 100. In some embodiments, the pattern bp is a block pattern; in this context, a block pattern may include a completely continuous pattern block, as well as a pattern block with a hollowed-out portion in the middle. The pattern bp shown in Figure 6 is a block pattern that has been linearized for uniformity. For example, the pattern bp may include a main portion bp1 and an overlapping portion bp2 that are connected to each other; the overlapping portion bp2 is the portion that at least partially overlaps the sub-pixel opening OP. In some embodiments, the main portion bp1 is a continuous block, and the overlapping portion bp2 includes a plurality of strips t1. The strips t1 are spaced apart from each other and may extend substantially parallel to each other along a direction D2 and are arranged along a direction D1. In other words, the pattern bp has a hollowed-out portion th1 between the strips t1. The strips t1 are connected to the main portion bp1 and may be electrically connected to each other through the main portion bp1. In some embodiments, the overlapping portion bp2 may further include a strip portion t2 , the extension direction of the strip portion t2 may be different from (eg, perpendicular to) the extension direction of the strip portion t1 , and the strip portion t2 is connected to the plurality of strip portions t1 .

[0130] In some embodiments, the orthographic projection of the continuous block-shaped main portion bp1 on the substrate 100 may be located outside the orthographic projection of the sub-pixel opening OP on the substrate 100, and the orthographic projections of at least portions of the plurality of strip portions t1 on the substrate 100 overlap with the orthographic projection of the sub-pixel opening OP on the substrate 100. The orthographic projections of at least portions of the strip portions t2 on the substrate 100 may overlap with the orthographic projection of the sub-pixel opening OP on the substrate 100.

[0131] In some embodiments, at least the portions of the plurality of strip portions t1 overlapping the sub-pixel opening OP have substantially the same width w3; the intervals d3 between adjacent strip portions t1 may be substantially the same, that is, the widths of the plurality of hollow portions th1 overlapping the sub-pixel opening OP may be substantially the same.

[0132] In some embodiments, the other patterns ap overlapping the sub-pixel opening OP may include a plurality of stripe patterns dispersed from one another, a block pattern having a smaller area, and / or patterns of other shapes.

[0133] In some embodiments, for example, the block pattern 103p of the conductive layer L1 shown in Figure 3B and the block pattern 108p of the conductive layer L2 shown in Figure 4B can be designed with linear uniformity as shown in Figure 6, and the portions of the block patterns 103p and 108p that overlap with the corresponding sub-pixel openings can be patterned into multiple strips.

[0134] In this embodiment, the large-area block pattern in the area corresponding to the sub-pixel opening is linearized and uniformly arranged. For example, the part in the area corresponding to the sub-pixel opening is divided into multiple strip patterns. This prevents the flat layer above the large-area block pattern from having a larger step difference than the flat layer above other patterns, thereby preventing the flatness of the sub-pixel opening area from being affected. Such an arrangement can make the patterns in the area corresponding to the sub-pixel opening evenly distributed, thereby improving the flatness in the said area.

[0135] In some embodiments, dummy patterns may be further provided in each pattern layer of the pixel circuit layer. The dummy patterns may be provided in the gap regions between adjacent circuit patterns and / or adjacent active patterns, and may be provided in regions corresponding to one or more sub-pixel openings. For example, in each pattern layer, after the pixel circuit patterns are centrally provided in the regions corresponding to one or more sub-pixel openings, dummy patterns may be further provided in the gap regions of the pixel circuit patterns to adjust the density and / or uniformity of the overall pattern in the region overlapping with the corresponding sub-pixel openings, so that the multiple patterns in the region corresponding to each sub-pixel opening (i.e., the combination of the pixel circuit pattern and the dummy pattern) have a suitable density and / or uniformity as a whole (e.g., uniformly distributed in the region), thereby improving the flatness of the region corresponding to the sub-pixel opening, for example, so that the planarization layer in the region has a higher flatness and provides a flat surface for the light-emitting device, thereby improving the uniformity of the light-emitting device. In some embodiments, before providing the dummy patterns, the pixel circuit patterns may be uniformly provided, for example, the size spacing (e.g., the line width spacing) of the pixel circuit patterns overlapping with the same sub-pixel opening is set to be the same as each other. In some embodiments, the dummy pattern can be formed from the same material layer by the same patterning process as the pixel circuit pattern (e.g., conductive pattern, active pattern, etc.) of the same layer. In this article, the dummy pattern is electrically isolated from other pixel circuit patterns. For example, the dummy pattern can be electrically floating, that is, not connected to any other conductive member and / or voltage source; or, the dummy pattern can also be connected to a fixed potential, such as grounded or connected to a DC signal terminal. In some embodiments, in addition to improving the flatness of the area corresponding to the sub-pixel opening, the dummy pattern can also shield the signal crosstalk between adjacent circuit patterns. For example, after the pixel circuit patterns are concentrated in the area corresponding to one or more sub-pixel openings, the circuit patterns of different sub-pixel circuits may be close to each other, and the dummy pattern can be set between the circuit patterns of different sub-pixel circuits, thereby effectively avoiding the signal crosstalk between adjacent circuit patterns (e.g., between the circuit patterns of different sub-pixel circuits), thereby improving the reliability of the device.

[0136] 3D is a schematic plan view of a conductive layer L1 and a plurality of sub-pixel openings OP1-OP3 according to some embodiments of the present disclosure. The conductive layer L1 shown in FIG3D is, for example, the conductive layer L1 shown in FIG3B with a dummy pattern added thereto.

[0137] For example, as shown in FIG3D , conductive layer L1 includes circuit patterns 103 for multiple sub-pixels and one or more dummy patterns (or first dummy patterns) 103'. Multiple dummy patterns 103' are disposed in gaps between circuit patterns 103 (i.e., gaps between adjacent circuit patterns), and the orthographic projections of dummy patterns 103' on substrate 100 may overlap with the orthographic projections of at least one of sub-pixel openings OP1 to OP3 (e.g., sub-pixel opening OP1) on substrate 100. Dummy patterns 103' are configured to at least partially fill the gaps between circuit patterns 103 that overlap with the sub-pixel openings, thereby adjusting the density and / or uniformity of the overall pattern (i.e., the combination of circuit pattern 103 and dummy patterns 103') in region R1 that overlaps with the corresponding sub-pixel opening, thereby improving the flatness of the planarization layer above that region. In some embodiments, the shapes of dummy patterns 103' may include stripes, blocks, or any other suitable shape, and the sizes of different dummy patterns 103' may be the same or different. For example, the dummy pattern 103' may include a strip-shaped dummy pattern 103a' and a block-shaped dummy pattern 103b', wherein the strip-shaped dummy pattern 103a' may have the same or different size as the adjacent strip-shaped circuit pattern (e.g., a routing pattern), and the block-shaped dummy pattern 103b' may also have the same or different size as the adjacent block-shaped circuit pattern. The dummy pattern 103' may be set in any gap between multiple circuit patterns 103, for example, it may be set in the gap area of ​​the circuit pattern 103 of the same sub-pixel circuit and / or the gap area between the circuit patterns 103 of different sub-pixel circuits. The present disclosure does not limit the shape, size, and specific position of the dummy pattern 103', as long as at least a portion of the dummy pattern 103' is set in the area corresponding to the sub-pixel opening (e.g., at least one of the areas R1-R3) and improves the flatness of the area.

[0138] FIG. 3E illustrates a schematic plan view of a conductive layer L1 and a plurality of sub-pixel openings OP1 - OP3 according to some other embodiments of the present disclosure.

[0139] Referring to Figure 3E, in some embodiments, in the conductive layer L1, the circuit pattern 103 overlapping the sub-pixel opening OP1 may include a plurality of routing patterns 103t, and the dummy pattern 103a' is disposed in a gap region between the plurality of routing patterns 103t. For example, the dummy pattern 103a' may be arranged in a strip shape, i.e., a shape substantially the same as the routing pattern 103t. The plurality of routing patterns 103t and the dummy pattern 103a' may extend substantially parallel to each other along a direction D1 and be arranged along a direction D2. The width w1 of the routing pattern 103t and the width w2 of the dummy pattern 103a' may be substantially the same; the spacing d1' between adjacent patterns in the plurality of routing patterns 103t and the dummy pattern 103a' may be substantially the same. For example, the dummy pattern 103a' and the routing pattern 103t may be alternately arranged along the direction D2, that is, each dummy pattern 103a' may be arranged between two adjacent routing patterns 103t, and the spacing between the dummy pattern 103a' and the adjacent routing pattern 103t may be substantially the same. However, the present disclosure is not limited to this. In other embodiments, the plurality of routing patterns 103t and the dummy pattern 103a' may not be arranged in an alternating manner, and any other suitable arrangement may be adopted, as long as the overall pattern composed of the circuit pattern and the dummy pattern in the region R1 corresponding to the sub-pixel opening OP1 has a suitable density and is evenly arranged, so that the planarization layer located above the region R1 has a high degree of flatness.

[0140] In the embodiments shown in Figures 3D and 3E, the dummy pattern 103' and the circuit pattern 103 are disposed in the same layer and spaced apart from each other, and can be formed from the same conductive material layer using the same patterning process, thereby simplifying the manufacturing process. In some embodiments, the dummy pattern 103' is disposed in the region corresponding to the sub-pixel opening and where the circuit pattern 103 is disposed (e.g., region R1 and its vicinity), while the dummy pattern is not disposed in the region corresponding to the sub-pixel opening but where the circuit pattern 103 is not disposed (e.g., regions R2, R3 and their vicinity).

[0141] 4D and 4E are schematic plan views illustrating a conductive layer L2 and a plurality of sub-pixel openings OP1 - OP3 according to other embodiments of the present disclosure.

[0142] Referring to FIG4D , in some embodiments, the conductive layer L2 includes circuit patterns 108 for multiple sub-pixels and may further include one or more dummy patterns (or second dummy patterns) 108'. The dummy patterns 108' are disposed in gaps between the multiple circuit patterns 108, and at least a portion of the orthographic projections of the multiple dummy patterns 108' on the substrate 100 may overlap with the orthographic projections of at least one of the sub-pixel openings OP1-OP3 on the substrate. For example, the dummy patterns 108' may be disposed in regions corresponding to the sub-pixel openings OP1 and OP2 (regions R1 and R2 and / or the regions adjacent thereto). The dummy patterns 108' may be in the form of strips, blocks, or any other suitable shape, and the size of the dummy patterns 108' may be the same as or different from the size of the adjacent circuit patterns 108. The present disclosure does not limit the shape, size, or specific location of the dummy pattern 108', as long as at least a portion of the dummy pattern 108' is disposed in a region corresponding to a sub-pixel opening (e.g., at least one of regions R1-R3) and improves the flatness of that region. In some embodiments, if a circuit pattern 108 is not disposed in a region corresponding to a sub-pixel opening, no dummy pattern is disposed in that region. For example, if a circuit pattern 108 is not disposed in region R3 corresponding to sub-pixel opening OP3, no dummy pattern 108' is disposed in that region either.

[0143] 4E , in some embodiments, in the conductive layer L2, the dummy pattern 108' may be strip-shaped and disposed at the same line width as the trace patterns in the adjacent circuit pattern 108. For example, the circuit pattern 108 may include a plurality of trace patterns 108t1 and 108t2, and the dummy pattern 108' may include a strip-shaped dummy pattern 108a' and a dummy pattern 108b'; the dummy patterns 108a' and 108b' may also be referred to as dummy trace patterns.

[0144] For example, at least portions of the routing patterns 108t1 and 108t2 are located in regions R1 and R2 corresponding to the sub-pixel openings OP1 and OP2, respectively, and at least portions of the dummy patterns 108a' and 108b' are also located in regions R1 and R2 corresponding to the sub-pixel openings OP1 and OP2, respectively. One or more dummy patterns 108a' may be adjacent to the routing pattern 108t1, for example, disposed in gaps between the plurality of routing patterns 108t1. The line width w10' of the dummy pattern 108a' may be substantially the same as the line width w10 of the routing pattern 108t1. In region R1, the spacing d10' between adjacent dummy patterns 108a' and the routing pattern 108t1 may be substantially the same. One or more dummy patterns 108b' may be adjacent to the routing pattern 108t2, for example, disposed in a gap region between the plurality of routing patterns 108t2, and the line width w20' of the dummy pattern 108b' may be substantially the same as the line width w20 of the routing pattern 108t2. In region R2, the spacing d20' between adjacent patterns in the dummy pattern 108b' and the routing pattern 108t2 may be substantially the same. It should be understood that the number and specific locations of the routing patterns and dummy patterns in regions R1 and R2 shown in the figures are for illustrative purposes only and are not intended to be limiting. More or fewer routing patterns and / or dummy patterns may be disposed within these regions. For example, among multiple routing patterns, more than one dummy pattern may be set in the gap area between some adjacent routing patterns, and no dummy pattern may be set between some adjacent routing patterns; the dummy patterns and routing patterns in regions R1 and R2 may be arranged in any suitable manner, as long as the planarization layer above the region has a high degree of flatness.

[0145] In some embodiments, in the conductive layer L2, the dummy pattern 108' and the circuit pattern 108 are disposed in the same layer and spaced apart from each other, and can be formed from the same conductive material layer using the same patterning process, thereby simplifying the manufacturing process. In some embodiments, the dummy pattern 108' can be disposed in one or more of the regions corresponding to the sub-pixel openings and already having the circuit pattern 108 disposed thereon (e.g., regions R1 and R2 and their adjacent regions), while the dummy pattern 108' can be omitted from the regions corresponding to the sub-pixel openings but not having the circuit pattern 108 disposed thereon (e.g., region R3 and its adjacent regions).

[0146] FIG. 5C illustrates a schematic plan view of an active material layer L0 and a plurality of sub-pixel openings OP1 - OP3 according to some embodiments of the present disclosure.

[0147] Referring to FIG5C , in some embodiments, the active material layer L0 includes active patterns 101 for multiple sub-pixels and may further include one or more dummy patterns (or third dummy patterns) 101′. The dummy patterns 101′ are disposed in gaps between the active patterns 101 for the multiple sub-pixels. At least a portion of the dummy pattern 101′ may be disposed in a region corresponding to at least one of the multiple sub-pixel openings in the active material layer L0. That is, an orthographic projection of at least a portion of the dummy pattern 101′ on the base substrate 100 may overlap with an orthographic projection of one or more of the multiple sub-pixel openings OP1-OP3 on the base substrate 100. For example, as shown in FIG5C , the dummy pattern 101′ may be disposed in a region R1 corresponding to the sub-pixel opening OP1 and / or in a region adjacent to the region R1, and may be located in a gap between adjacent active patterns in the active pattern 101 and spaced apart from the active pattern 101. The shape of the dummy pattern 101' may include a strip, a block, an irregular shape, or any other suitable shape. The size of the dummy pattern 101' may be the same as or different from the size of the adjacent active pattern. The present disclosure does not limit the shape, size, and specific position of the dummy pattern 101', as long as at least a portion of the dummy pattern 101' is disposed in an area corresponding to the sub-pixel opening (e.g., one or more of the areas R1-R3) to adjust the density and / or uniformity of the overall pattern of the active material layer in the area, thereby improving the flatness of the planarization layer above the area.

[0148] The dummy patterns 101' and the active patterns 103 are disposed in the same layer and spaced apart from each other, and can be formed from the same active material using the same patterning process, thereby simplifying the manufacturing process. In some embodiments, dummy patterns may not be disposed in regions corresponding to sub-pixel openings and not provided with active patterns (e.g., regions R2 and R3 shown in FIG. 5C ), but the present disclosure is not limited thereto.

[0149] In other embodiments, for example, in the active material layer L0 shown in FIG5B , a dummy pattern may be provided between adjacent active patterns 101a and 101b in the region R1 corresponding to the sub-pixel opening OP1, and a dummy pattern may not be provided in the region R2 where no active pattern is provided and in the region R3 where a whole active pattern is provided.

[0150] It should be understood that in the embodiments of the present disclosure, each layer in the pixel circuit layer may be provided with or without a dummy pattern, depending on the arrangement of the pixel circuit patterns in that layer. When a dummy pattern is included in the pixel circuit layer, the dummy pattern may be provided in one or more layers of the pixel circuit layer, such as one or more of the active material layer L0, the first conductive layer L1, and the second conductive layer L2. That is, in some embodiments, the display panel may include one or more of the first dummy pattern, the second dummy pattern, and the third dummy pattern.

[0151] FIG7 illustrates a schematic planar arrangement of multiple stacked layers and multiple sub-pixel openings of a pixel circuit layer of a display panel according to some embodiments of the present disclosure. The arrangement of the sub-pixel openings OP1-OP3 and the active material layer L0 shown in FIG7 is similar to that shown in FIG5B . The arrangement of the active patterns of the active material layer L0 can be referred to above in connection with FIG5B and will not be further described here.

[0152] Referring to Figure 7, in some embodiments, the sub-pixel openings OP1-OP3 of different sub-pixels have different sizes and / or shapes, and the patterns of each layer of the pixel circuit layer (for example, the active material layer L0, the conductive layer L1, the conductive layer L2) can be optimized according to the characteristics of different sub-pixels, thereby improving the flatness of the planarization layer in the area corresponding to each sub-pixel opening OP1-OP3, so that the light-emitting device is formed on a flat surface, thereby improving the light-emitting uniformity of the light-emitting area of ​​each sub-pixel.

[0153] In some embodiments, the density of the circuit pattern set in the area corresponding to the sub-pixel opening with a larger size (e.g., sub-pixel opening OP1) in the pixel circuit layer may be greater than the density of the circuit pattern set in the area corresponding to other sub-pixel openings with smaller sizes (e.g., sub-pixel openings OP2 or OP3). In some embodiments, the density of the circuit pattern in areas R1 to R3 in the pixel circuit layer may be roughly positively correlated with the size of the sub-pixel openings OP1-OP3 corresponding to these areas. That is, the larger the sub-pixel opening size, the greater the density of the circuit pattern set in the area corresponding to the sub-pixel opening in the pixel circuit layer. However, the present disclosure is not limited to this. Here, the density of the circuit pattern in a certain area in the pixel circuit layer may include the density of the first circuit pattern in the first conductive layer in the area, the density of the second circuit pattern in the second conductive layer in the area, or the sum of the density of the first circuit pattern and the density of the second circuit pattern.

[0154] In some embodiments, dummy patterns may be provided in one or more of the active material layer L0, the conductive layer L1, and the conductive layer L2. At least a portion of the dummy patterns in each layer is located in the region corresponding to the sub-pixel opening. For example, the dummy patterns may be located in one or more of the regions R1-R3 of the pixel circuit layer and may extend into regions outside of these regions. In other embodiments, the dummy patterns may also be provided in other regions that do not overlap with the sub-pixel opening to improve the flatness of the planarization layer above these other regions, for example, to improve the overall flatness of the planarization layer.

[0155] For example, as shown in FIG7 , conductive layer L1 includes dummy patterns 103' positioned in the gaps between circuit pattern 103, and conductive layer L2 includes dummy patterns 108' positioned in the gaps between circuit pattern 108. The dummy patterns shown in the figure are for illustration only, and this disclosure does not limit the number, size, or specific location of the dummy patterns. In some embodiments, dummy patterns may also be positioned in the gaps between active patterns in the active material layer.

[0156] It should be understood that the above embodiment is described by taking the example that the pixel circuit layer 110 includes the active material layer L0, the conductive layer L1, and the conductive layer L2, and the type and quantity of the pattern layers included in the pixel circuit layer are not limited thereto.

[0157] For example, the pixel circuit layer includes multiple pattern layers, and the first pattern layer among the multiple pattern layers includes multiple first patterns of the multiple sub-pixels, and the orthographic projections of the multiple first patterns on the substrate overlap with the orthographic projections of at least one of the first sub-pixel opening, the second sub-pixel opening, and the third sub-pixel opening on the substrate; the overlapping area of ​​the multiple first patterns with the first sub-pixel opening is greater than the overlapping area of ​​the multiple first patterns with the second sub-pixel opening or the overlapping area of ​​the multiple first patterns with the third sub-pixel opening. For example, the overlapping area of ​​the multiple first patterns with at least one of the second sub-pixel opening and the third sub-pixel opening is zero. For example, the multiple pattern layers may include one or more gate layers, one or more source / drain metal layers, one or more active material layers, one or more transfer layers including transfer electrodes, and / or other pattern layers. For example, the multiple first patterns include circuit patterns of the multiple sub-pixels that connect the same signals (for example, gate scan signals, data signals, compensation signals, detection signals, etc.). The first pattern is, for example, the circuit pattern 103 or 108 , but may also be a pixel circuit pattern of other material layers.

[0158] In some embodiments, the multiple pattern layers further include a second pattern layer, which is located on a side of the first pattern layer close to or away from the light-emitting device, and the second pattern layer includes multiple second patterns of the multiple sub-pixels, and the overlapping area of ​​the multiple second patterns with the first sub-pixel opening is greater than the overlapping area of ​​the multiple second patterns with the second sub-pixel opening or the third sub-pixel opening. For example, the overlapping area of ​​the multiple second patterns with the second sub-pixel opening is zero. For example, the overlapping area of ​​the multiple second patterns with the third sub-pixel opening is zero or equal to the area of ​​the third sub-pixel opening. The second pattern is, for example, an active pattern located in an active material layer. In some embodiments, each of the multiple pattern layers can be arranged in one of the arrangement methods of the layers described with reference to the above embodiments, thereby improving the flatness of the planarization layer in the area corresponding to each sub-pixel opening.

[0159] In some embodiments, by concentrating the patterns (i.e., circuit patterns / active patterns, etc.) of each layer of the pixel circuit layer 110 in the area corresponding to a portion of the sub-pixel openings, a higher density of pixel circuit patterns is provided in that area, while no pixel circuit patterns are provided in the area corresponding to another portion of the sub-pixel openings; thereby minimizing the impact of the pixel circuit patterns on the flatness of the surface of the planarization layer in the area corresponding to the sub-pixel openings, and ensuring that at least the portion of the planarization layer corresponding to each sub-pixel opening has a high degree of flatness. In some embodiments, the arrangement of each layer of patterns in the pixel circuit layer 110 is optimized so that each layer of patterns has an appropriate density and / or uniformity in the area overlapping the sub-pixel openings, thereby improving the flatness of the planarization layer in the area corresponding to the sub-pixel openings. In some embodiments, due to the different densities of the pixel circuit patterns provided in each area corresponding to each sub-pixel opening, there may be a certain step difference between the portions of the planarization layer corresponding to different sub-pixel openings.

[0160] Returning to reference Figure 2B, for example, in some embodiments, the planarization layer 111 is disposed on the side of the pixel circuit layer 110 away from the base substrate 100 (i.e., above in the figure), and is located between the pixel circuit layer 110 and the pixel definition layer 112 / light-emitting device layer 116; the planarization layer 111 is configured to provide a flat surface for the components above it, so that the light-emitting device layer 116 is disposed on the flat surface, for example, at least the portion of the light-emitting device layer 116 located in the sub-pixel opening OP1 is formed on the flat surface, thereby ensuring the uniformity of light emission in the light-emitting areas of each sub-pixel.

[0161] In some embodiments, the density of the pixel circuit patterns provided in each region R1-R3 of the pixel circuit layer 110 is different from one another. For example, the overall density of the pixel circuit patterns in region R1 of the pixel circuit layer 110 is greater than the overall density of the pixel circuit patterns in region R2, and the overall density of the pixel circuit patterns in region R2 is greater than the overall density of the pixel circuit patterns in region R3. As a result, the portions of the planarization layer 111 corresponding to each region R1-R3 may have a certain step difference. Herein, the overall density of the pixel circuit patterns in a region of the pixel circuit layer refers to the sum of the densities of the patterns in each layer within that region.

[0162] For example, the planarization layer 111 includes a flat portion 111a, a flat portion 111b, and a flat portion 111c corresponding to regions R1, R2, and R3 of the pixel circuit layer and sub-pixel openings OP1, OP2, and OP3, respectively. Flat portions 111a, 111b, and 111c may also be referred to as a first flat portion, a second flat portion, and a third flat portion, respectively. Flat portions 111a-111c each provide a flat surface with high flatness for the light-emitting devices within the sub-pixel opening regions OP1-OP3. The orthographic projections of region R1 and sub-pixel opening OP1 onto substrate 100 may lie within the orthographic projection of flat portion 111a onto substrate 100; the orthographic projections of region R2 and sub-pixel opening OP2 onto substrate 100 may lie within the orthographic projection of flat portion 111b onto substrate 100; and the orthographic projections of region R3 and sub-pixel opening OP3 onto substrate 100 may lie within the orthographic projection of flat portion 111c onto substrate 100.

[0163] In some embodiments, different flat portions of the planarization layer 111 (e.g., at least two of the flat portions 111a to 111c) may have step differences; that is, the surfaces of the flat portions away from the substrate may be located at different heights relative to, for example, the main surface of the substrate 100. Herein, the height of each flat portion relative to the main surface of the substrate refers to the average height of the flat portion relative to the main surface of the substrate, that is, the average value of the heights of each flat portion relative to the main surface of the substrate in a direction perpendicular to the main surface of the substrate. For example, the flat portions 111a, 111b, and 111c may each have a flat surface S1, a flat surface S2, and a flat surface S3, respectively, located away from the substrate 100 and close to the pixel definition layer 112 and the light-emitting device layer 116. The flat surfaces S1, S2, and S3 may also be referred to as the first flat surface, the second flat surface, and the third flat surface, respectively. At least two of the flat surfaces S1-S3 may be located at different distances from the main surface of the substrate 100. In some embodiments, the height of the flat surfaces S1 - S3 relative to the main surface of the base substrate 100 may be substantially positively correlated with the overall density of the pixel circuit patterns and / or dummy patterns in the corresponding regions R1 - R3 in the pixel circuit layer 110 .

[0164] For example, the overall pattern density within region R1 of the pixel circuit layer 110 may be greater than the overall pattern density within regions R2 or R3, and the overall pattern density within region R2 may be greater than the overall pattern density within region R3. The distance H1 between the flat surface S1 and the main surface of the substrate 100 may be greater than the distance H2 between the flat surface S2 and the main surface of the substrate 100, and the distance H2 between the flat surface S2 and the main surface of the substrate 100 may be greater than the distance H3 between the flat surface S3 and the main surface of the substrate 100. Here, the distance between each flat surface and the main surface of the substrate is the average distance between each location on the flat surface and the main surface of the substrate in a direction perpendicular to the main surface of the substrate. In other embodiments, the overall pattern density within region R2 may be approximately equal to the overall pattern density within region R3, and the distance H2 between the flat surface S2 and the main surface of the substrate 100 may also be approximately equal to the distance H3 between the flat surface S3 and the main surface of the substrate 100. The aforementioned distances between the flat surfaces and the main surface of the substrate are distances in a direction perpendicular to the main surface of the substrate 100.

[0165] In some embodiments, at least the portion of the multiple light-emitting devices of the light-emitting device layer 116 that are arranged at the corresponding sub-pixel openings are located on the corresponding flat portion of the planarization layer. Since the flat portions of the planarization layer corresponding to the sub-pixel openings have a flat surface with a relatively high degree of flatness, the light-emitting devices in the light-emitting areas of each sub-pixel in the light-emitting device layer 116 are all arranged on the flat surface, thereby improving the uniformity of light emission of each sub-pixel and thereby improving the display quality of the display panel.

[0166] Referring to FIG. 2A , in some embodiments, the light-emitting device layer 116 includes light-emitting devices LE for a plurality of sub-pixels SP, and includes a first electrode layer, a light-emitting layer, and a second electrode layer, wherein the light-emitting layer is located between the first and second electrode layers. The light-emitting device LE for each sub-pixel SP may include a first electrode E1 located in the first electrode layer, a second electrode E2 located in the second electrode layer, and a light-emitting layer 113 located between the first and second electrodes. The first electrode layer is disposed on the planarization layer 111, and a sub-pixel opening OP in the pixel definition layer 112 may expose at least a portion of the first electrode E1. The light-emitting layer 113 is disposed on a side of the first electrode E1 away from the base substrate and may be disposed along a surface of the sub-pixel opening OP to cover the sidewalls of the pixel definition layer 112 and the surface of the first electrode E1 exposed by the sub-pixel opening OP. The light-emitting layer 113 may further extend to cover a portion of the surface (or top wall) of the pixel definition layer 112 away from the base substrate 100. The second electrode layer is located on a side of the light emitting layer 113 away from the first electrode layer, and may extend along a surface of the light emitting layer 113 and a surface of the pixel definition layer 112 away from the base substrate 100 , for example, extend continuously.

[0167] In some embodiments, the first electrode layer and the second electrode layer may each comprise a suitable electrode material such as a metal or metal oxide, and the light-emitting layer may comprise an organic light-emitting material. The first electrode E1 and the second electrode E2 may, for example, serve as the anode and cathode, respectively, of the light-emitting device LE. In some embodiments, the second electrode layer extends continuously between sub-pixel regions and serves as a common cathode for multiple sub-pixels.

[0168] In some embodiments, the first electrode E1 of the light-emitting device LE of each sub-pixel can be connected to the corresponding sub-pixel circuit PC through a via V1, for example, it can be connected to the source and drain (e.g., source S) of the thin film transistor T in the sub-pixel circuit PC. The via V1 can be located in the planarization layer 111 and extend through the planarization layer 111 to connect the first electrode E1 to the corresponding source and drain. In some embodiments, the via hole V1 and the sub-pixel opening OP are offset in a direction parallel to the main surface of the base substrate 100; that is, the via hole V1 is not arranged at a position directly below the sub-pixel opening OP in the figure; the orthographic projection of the via hole V1 on the main surface of the base substrate 100 may be located outside the orthographic projection of the sub-pixel opening OP on the main surface of the base substrate 100. In this way, the via hole V1 is prevented from affecting the flatness of the first electrode E1 in the light-emitting region LR, so that at least the portion of the first electrode E1 located in the light-emitting region LR has a flat surface on the side away from the base substrate 100, and thus the light-emitting layer 113 and the second electrode E2 formed on the first electrode E1 in the light-emitting region LR also have a higher flatness, thereby avoiding some problems caused by the unevenness of the light-emitting device in the light-emitting region LR, thereby improving the reliability of the light-emitting device and improving the uniformity of the light emission of each sub-pixel.

[0169] Referring to FIG2B , in some embodiments, the light-emitting device LE1 of sub-pixel SP1 includes a first electrode E1a, a light-emitting layer 113a, and a second electrode E2; the light-emitting device LE2 of sub-pixel SP2 includes a first electrode E1b, a light-emitting layer 113b, and a second electrode E2; and the light-emitting device LE3 of sub-pixel SP3 includes a first electrode E1c, a light-emitting layer 113c, and a third electrode E2. The first electrodes E1a-E1c of the light-emitting devices LE1 to LE3 are each connected to a corresponding sub-pixel circuit via a via. For simplicity, FIG2B does not specifically illustrate the vias connecting the first electrodes of each light-emitting device to the sub-pixel circuit.

[0170] Multiple light-emitting devices LE1 to LE3 are respectively disposed on multiple flat portions 111a-111c of the planarization layer 111. Due to the step differences between the multiple flat portions 111a-111c, the multiple light-emitting devices LE1 to LE3 also have step differences. For example, the light-emitting devices LE1, LE2, and LE3 are respectively disposed on the flat surfaces S1, S2, and S3 of the flat portions 111a, 111b, and 111c, and the first electrodes E1a, E1b, and E1c of the light-emitting devices LE1, LE2, and LE3 are respectively in direct contact with the flat surfaces S1, S2, and S3. In some embodiments, at least the portions of the first electrodes E1a, E1b, and E1c exposed by the sub-pixel opening OP1 are located on the corresponding flat surfaces S1, S2, and S3 to ensure the flatness of the first electrodes within each light-emitting area and other components of the light-emitting device above them, thereby improving the uniformity of light emission across each sub-pixel.

[0171] In some embodiments, the orthographic projections of at least the portions of the first electrodes E1a-E1c exposed by the corresponding sub-pixel openings OP1-OP3 on the substrate substrate 100 are located within the orthographic projections of the corresponding flat surfaces S1, S2, and S3 on the substrate substrate 100. In some embodiments, the orthographic projections of the entire electrodes of one or more of the first electrodes E1a-E1c on the substrate substrate 100 may be located within the orthographic projections of the corresponding flat surfaces S1-S3 on the substrate substrate 100. In some embodiments, one or more first electrodes may span multiple flat portions of the planarization layer 111, that is, they may contact multiple flat surfaces of the planarization layer at different levels, but the portions of the first electrodes exposed by the sub-pixel openings may be located on only one flat surface. For example, in some embodiments, because the sub-pixel circuitry of some sub-pixels is not disposed in the region corresponding to the corresponding sub-pixel opening, but rather in a region near other sub-pixel openings, the first electrodes in the light-emitting devices of these sub-pixels may need to extend a greater distance to connect to their sub-pixel circuitry. However, the present disclosure is not limited to this.

[0172] For example, the sub-pixel circuit pc3 of sub-pixel SP3 is not disposed in region R3 directly below sub-pixel opening OP3, but rather in a region closer to other sub-pixel openings OP1 and OP2. In this case, at least the portion of the first electrode E1c exposed by sub-pixel opening OP3 may be located on the flat surface S3 of the flat portion 111c, while the remaining portion of the first electrode E1c may extend from the flat surface S3 of the flat portion 111c to the flat surfaces S2 and / or S1 of the other flat portions 111b and / or 111a to connect to the sub-pixel circuit pc3 near the other sub-pixel openings. However, the present disclosure is not limited to this. In other embodiments, the first electrode E1c may be located on the first flat portion 111c without crossing over the other flat portions, and the corresponding circuit pattern of the sub-pixel circuit pc3 may extend from the region near the other sub-pixel openings to the region directly below the first electrode E1c and be connected to the first electrode E1c through a via.

[0173] 8 , in some embodiments, the present disclosure provides a display device 1000 comprising the display panel 500 of any of the aforementioned embodiments. The present disclosure optimizes the layout of the pixel circuit layer in the display panel 500 to improve the flatness of the area corresponding to each sub-pixel opening, thereby improving the uniformity of light emission from the light-emitting device in each sub-pixel. This can further enhance the display quality of the display panel 500 and the display device 1000.

[0174] An embodiment of the present disclosure provides a method for forming a display panel, comprising: providing a base substrate; forming a plurality of sub-pixels on the base substrate, wherein each sub-pixel includes a light-emitting device and a sub-pixel circuit for driving the light-emitting device to emit light, and the plurality of sub-pixels include a first sub-pixel, a second sub-pixel, and a third sub-pixel for displaying different colors, and forming the plurality of sub-pixels includes: forming a pixel circuit layer, the pixel circuit layer including sub-pixel circuits of the plurality of sub-pixels, and including a first sub-pixel circuit, a second sub-pixel circuit, and a third sub-pixel circuit for respectively driving the light-emitting devices of the first sub-pixel, the second sub-pixel, and the third sub-pixel to emit light; forming a planarization layer on a side of the pixel circuit layer away from the base substrate; and forming a pixel definition layer on a side of the planarization layer away from the pixel circuit layer, the pixel definition layer having a plurality of sub-pixel openings, wherein each sub-pixel opening is respectively configured to define a light-emitting area of ​​a corresponding sub-pixel, and each sub-pixel At least a portion of the light-emitting device is formed in corresponding sub-pixel openings, wherein the multiple sub-pixel openings include a first sub-pixel opening, a second sub-pixel opening and a third sub-pixel opening corresponding to the first sub-pixel, the second sub-pixel and the third sub-pixel respectively; wherein the pixel circuit layer includes a first conductive layer, the first conductive layer includes a plurality of first circuit patterns of the multiple sub-pixels, and the orthographic projections of the multiple first circuit patterns on the base substrate overlap with the orthographic projections of at least one of the first sub-pixel opening, the second sub-pixel opening and the third sub-pixel opening on the base substrate; the ratio of the overlapping area of ​​the multiple first circuit patterns with the third sub-pixel opening to the area of ​​the third sub-pixel opening is smaller than the ratio of the overlapping area of ​​the multiple first circuit patterns with the first sub-pixel opening to the area of ​​the first sub-pixel opening or the ratio of the overlapping area of ​​the multiple first circuit patterns with the second sub-pixel opening to the area of ​​the second sub-pixel opening.

[0175] For example, in the above-mentioned method for forming a display panel, forming the pixel circuit layer includes: forming an active material layer on one side of the base substrate; forming the first conductive layer on the side of the active material layer away from the base substrate; and forming a second conductive layer on the side of the first conductive layer away from the base substrate; wherein each sub-pixel circuit includes a first circuit pattern located on the first conductive layer, a second circuit pattern located on the second conductive layer, and an active pattern located on the active material layer.

[0176] For example, in the above method for forming the display panel, forming the first conductive layer includes arranging traces having substantially the same line width in a region corresponding to the same sub-pixel opening.

[0177] For example, in the above-mentioned method for forming a display panel, the second conductive layer includes a plurality of first routing lines and a plurality of second routing lines, the plurality of first routing lines have substantially the same first line width as each other, and the plurality of second routing lines have substantially the same second line width as each other; forming the second conductive layer includes forming the plurality of first routing lines in an area corresponding to the first sub-pixel opening, and forming the plurality of second routing lines in an area corresponding to the second sub-pixel opening.

[0178] For example, in the above-mentioned method for forming the display panel, forming the active material layer includes: forming the active patterns of the first sub-pixel circuit to the third sub-pixel circuit in the area corresponding to the first sub-pixel opening; or forming the active patterns of the first sub-pixel circuit and the second sub-pixel circuit in the area corresponding to the first sub-pixel opening, and forming the active pattern of the third sub-pixel circuit in the area corresponding to the third sub-pixel opening.

[0179] For example, in the above-mentioned method for forming the display panel, at least one of the following steps is also included: forming the first conductive layer also includes forming a first dummy pattern in the gap area of ​​the first circuit pattern of the multiple sub-pixels; forming the second conductive layer also includes forming a second dummy pattern in the gap area of ​​the second circuit pattern of the multiple sub-pixels; and forming the active material layer also includes forming a third dummy pattern in the gap area of ​​the active pattern of the multiple sub-pixels.

[0180] For example, in some embodiments, the present disclosure provides a method for forming a display panel, comprising the following steps: providing a substrate substrate 100; forming a plurality of sub-pixels on the substrate substrate, wherein each sub-pixel includes a light-emitting device and a sub-pixel circuit for driving the light-emitting device to emit light, and the plurality of sub-pixels include a plurality of sub-pixels for displaying different colors, and forming the plurality of sub-pixels includes: forming a pixel circuit layer 110 on one side of the substrate substrate 100, the pixel circuit layer 110 including sub-pixel circuits of the plurality of sub-pixels; and forming a pixel definition layer 112 and a light-emitting device layer 116 on a side of the pixel circuit layer 110 away from the substrate substrate 100. For example, after forming the pixel circuit layer 110, a planarization layer 111 is formed on a side of the pixel circuit layer 110 away from the base substrate 100; a first electrode layer is formed on a side of the planarization layer 111 away from the pixel circuit layer 110; a pixel definition material layer is formed on the planarization layer 110 to cover the first electrode layer, and the pixel definition material layer is patterned to form a pixel definition layer 112 having multiple sub-pixel openings, and the multiple sub-pixel openings of the pixel definition layer 112 expose at least part of the multiple first electrodes of the first electrode layer; and a light-emitting layer and a second electrode layer are formed on the first electrode layer and the pixel definition layer, and at least part of the light-emitting layer and the second electrode layer is filled in the sub-pixel openings, thereby forming multiple light-emitting devices.

[0181] In some embodiments, an encapsulation layer 118 may be formed on the side of the light-emitting device layer 116 away from the base substrate 100. The encapsulation layer 118 may include an organic insulating material, an inorganic insulating material, or a combination thereof. The encapsulation layer 118 may prevent water, oxygen, and the like from entering the light-emitting device layer and affecting the light emission of the light-emitting device. In some embodiments, the display panel may further include a touch structure layer formed on the side of the light-emitting device layer 116 away from the base substrate 100. For example, the touch structure layer may be located on the side of the encapsulation layer away from the base substrate to realize the touch function of the display panel. The touch structure may be any type of touch structure, such as a self-capacitive touch structure or a mutual-capacitive touch structure. For example, a self-capacitive touch structure or a mutual-capacitive touch structure may include at least one conductive layer, but the embodiments of the present disclosure do not limit the specific type and structure of the touch structure.

[0182] 2B , in some embodiments, forming the pixel circuit layer 110 may include the following steps: forming an active material layer L0 on one side of a base substrate 100; forming an insulating layer 102 to cover the sidewalls of the active material layer L0 and its surface away from the base substrate 100; forming a conductive layer L1 on the side of the active material layer L0 and the insulating layer 102 away from the base substrate 100; forming an insulating layer 105 to cover the sidewalls of the conductive layer L1 and its surface away from the base substrate; and forming a conductive layer L2 on the side of the conductive layer L1 and the insulating layer 105 away from the base substrate 100. The active material layer L0, the conductive layer L1, and the conductive layer L2 respectively include active patterns 101, circuit patterns 103, and circuit patterns 108 for multiple sub-pixels.

[0183] In some embodiments, when forming each layer of the pixel circuit layer 110, the layout of the pixel circuit patterns of each layer is optimized to improve the flatness of the area corresponding to each sub-pixel opening region of the planarization layer 111. The arrangement and related features of the pixel circuit patterns of each layer of the pixel circuit layer 100 can be referred to the contents described above with reference to Figures 2A to 7, and will not be repeated here.

[0184] Forming the conductive layer L1 and the conductive layer L2 may include arranging corresponding circuit patterns in regions corresponding to one or more sub-pixel openings. For example, forming the conductive layer L1 may include arranging lines having substantially the same line width in regions corresponding to the same pixel opening (e.g., sub-pixel opening OP1). In some embodiments, when a plurality of circuit patterns having different line widths are included in the conductive layer, the plurality of circuit patterns having different line widths may be classified, and circuit patterns having similar line widths (e.g., substantially the same) may be arranged in regions corresponding to the same sub-pixel opening. For example, forming the second conductive layer may include forming a plurality of first lines in a region corresponding to a first sub-pixel opening (e.g., sub-pixel opening OP1), and forming a plurality of second lines in a region corresponding to a second sub-pixel opening (e.g., sub-pixel opening OP2). The plurality of first lines may have substantially the same first line width spacing; the plurality of second lines may have substantially the same second line width spacing, and the first line width spacing may be different from the second line width spacing.

[0185] In some embodiments, forming a display panel according to an embodiment of the present disclosure may include at least one of the following steps: forming a conductive layer L1 further includes forming a first dummy pattern 103' in the gap region of the circuit pattern 103; forming a conductive layer L2 further includes forming a second dummy pattern 108' in the gap region of the circuit pattern 108; and forming an active material layer L0 further includes forming a third dummy pattern 101' in the gap region of the active pattern 101. In some embodiments, the active pattern may be provided after optimizing the layout of the various layers of the pixel circuit layer. The optimized layout may include concentrating the pixel circuit patterns of multiple sub-pixels in regions corresponding to some sub-pixel openings, and may or may not include arranging these pixel circuit patterns with equal line width spacing. If the pixel circuit patterns are not arranged with equal line width spacing, the density and uniformity of the overall pattern arrangement in the region corresponding to the corresponding sub-pixel opening can be adjusted by adjusting the number, size, shape, and positional relationship of the dummy patterns with respect to the pixel circuit patterns, thereby improving the flatness of the planarization layer above this region. When the pixel circuit pattern (for example, the routing pattern) is set with equal line width spacing, the dummy pattern can be set to have approximately the same line width as the adjacent routing pattern, and the spacing between the dummy pattern and the adjacent routing pattern can be set to be approximately the same as each other, thereby improving the density and uniformity of the overall pattern in the area, and further improving the flatness of the planarization layer above the area.

[0186] The specific features of the display panel formed by the method for forming a display panel according to an embodiment of the present disclosure can be referred to the contents described above with respect to Figures 2A to 7, and have the same technical effects as described above. The display panel and its formation method disclosed herein optimize the layout of the patterns of each layer of the pixel circuit layer to improve the flatness of the planarization layer in the corresponding area, so that the planarization layer has a flat surface with high flatness in at least the area corresponding to each sub-pixel opening, thereby forming at least the portion of the light-emitting device located within the light-emitting area on the flat surface, thereby ensuring the uniformity of light emission of each sub-pixel light-emitting device and improving the display quality of the display panel and display device.

[0187] It should be understood that the concepts of the present disclosure are described above using OLED devices as an example, and the concept of adjusting regional flatness by optimizing pattern arrangement can also be applied to other types of display devices and / or devices in other fields.

[0188] There are a few points to note:

[0189] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to conventional designs.

[0190] (2) Unless there is any conflict, the features of the same embodiment and different embodiments of the present disclosure may be combined with each other.

[0191] The above are only specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display panel, include: substrate substrate; A plurality of sub-pixels are arranged on the base substrate, wherein each sub-pixel includes a light-emitting device and a sub-pixel circuit for driving the light-emitting device to emit light, and the plurality of sub-pixels include a first sub-pixel, a second sub-pixel and a third sub-pixel for displaying different colors; a pixel circuit layer, comprising sub-pixel circuits of the plurality of sub-pixels, and comprising a first sub-pixel circuit, a second sub-pixel circuit and a third sub-pixel circuit, respectively used to drive the light-emitting devices of the first sub-pixel, the second sub-pixel and the third sub-pixel to emit light; A planarization layer, disposed on a side of the pixel circuit layer away from the base substrate; as well as a pixel definition layer, disposed on a side of the planarization layer away from the pixel circuit layer, the pixel definition layer having a plurality of sub-pixel openings, wherein each sub-pixel opening is configured to define a light-emitting area of ​​a corresponding sub-pixel, and at least a portion of the light-emitting device of each sub-pixel is located in the corresponding sub-pixel opening, wherein the plurality of sub-pixel openings include a first sub-pixel opening, a second sub-pixel opening, and a third sub-pixel opening corresponding to the first sub-pixel, the second sub-pixel, and the third sub-pixel, respectively; wherein the pixel circuit layer comprises a first conductive layer, the first conductive layer comprises a plurality of first circuit patterns of the plurality of sub-pixels, and an orthographic projection of the plurality of first circuit patterns on the base substrate overlaps with an orthographic projection of at least one of the first sub-pixel opening, the second sub-pixel opening, and the third sub-pixel opening on the base substrate; and The ratio of the overlapping area of ​​the multiple first circuit patterns with the third sub-pixel opening to the area of ​​the third sub-pixel opening is smaller than the ratio of the overlapping area of ​​the multiple first circuit patterns with the first sub-pixel opening to the area of ​​the first sub-pixel opening or the ratio of the overlapping area of ​​the multiple first circuit patterns with the second sub-pixel opening to the area of ​​the second sub-pixel opening.

2. The display panel according to claim 1, wherein the orthographic projection of at least part of the third sub-pixel circuit on the base substrate is located outside the orthographic projection of the third sub-pixel opening on the base substrate, and overlaps with the orthographic projection of the first sub-pixel opening or the second sub-pixel opening on the base substrate.

3. The display panel according to claim 1, wherein Each sub-pixel circuit includes a thin film transistor and a capacitor; each thin film transistor includes a gate, a source and a drain, and an active layer; each capacitor includes electrode plates facing each other; The pixel circuit layer further includes a plurality of wirings connected to a plurality of thin film transistors and capacitors of the plurality of sub-pixel circuits, and the plurality of wirings include one or more of gate signal lines, data signal lines, common electrode lines, detection signal lines, power supply voltage lines, and auxiliary connection lines; and The pixel circuit layer includes a multi-layer circuit pattern, and the plurality of first circuit patterns of the first conductive layer include gates or source and drain electrodes of the plurality of thin film transistors, and also include an electrode plate of the capacitor and one or more of the plurality of routing lines.

4. The display panel according to claim 1, wherein The pixel circuit layer includes multiple pattern layers, each pattern layer includes multiple patterns, and the first conductive layer is the topmost pattern layer among the multiple pattern layers that is closest to the light-emitting device in a direction perpendicular to the main surface of the substrate, or the first conductive layer is located on a side of the topmost pattern layer among the multiple pattern layers that is away from the light-emitting device.

5. The display panel according to claim 1, wherein The pixel circuit layer further includes a second conductive layer and an active material layer, and each sub-pixel circuit includes a first circuit pattern located in the first conductive layer, a second circuit pattern located in the second conductive layer, and an active pattern located in the active material layer; and The first conductive layer is the layer where the gate of the thin film transistor of the sub-pixel circuit is located, the second conductive layer is the layer where the source and drain of the thin film transistor of the sub-pixel circuit are located, and the active material layer is the layer where the active layer of the thin film transistor of the sub-pixel circuit is located. 6 . The display panel according to claim 5 , wherein the sum of overlapping areas of the plurality of first circuit patterns of the plurality of sub-pixels with the second sub-pixel opening and the third sub-pixel opening is smaller than the overlapping area of ​​the plurality of first circuit patterns with the first sub-pixel opening. 7 . The display panel of claim 6 , wherein the plurality of first circuit patterns include circuit patterns of the plurality of sub-pixels configured to be connected to a gate scan signal.

8. The display panel according to claim 5, wherein the orthographic projection of at least part of the first circuit pattern of at least two of the first sub-pixel circuit, the second sub-pixel circuit and the third sub-pixel circuit on the base substrate overlaps with the orthographic projection of the first sub-pixel opening on the base substrate. 9 . The display panel according to claim 5 , wherein an orthographic projection of the first circuit pattern of the third sub-pixel on the base substrate is located outside an orthographic projection of the third sub-pixel opening on the base substrate. 10 . The display panel according to claim 9 , wherein an orthographic projection of the first circuit pattern of the second sub-pixel on the base substrate is located outside an orthographic projection of the second sub-pixel opening on the base substrate.

11. The display panel according to claim 10, wherein the orthographic projections of at least part of the first circuit pattern of the first sub-pixel, the first circuit pattern of the second sub-pixel, and the first circuit pattern of the third sub-pixel on the base substrate overlap with the orthographic projection of the first sub-pixel opening on the base substrate.

12. The display panel according to claim 5, wherein The orthographic projection of the second circuit pattern of the third sub-pixel on the base substrate is outside the orthographic projection of the third sub-pixel opening on the base substrate, and overlaps with the orthographic projection of at least one of the first sub-pixel opening and the second sub-pixel opening on the base substrate. 13 . The display panel of claim 12 , wherein the plurality of second circuit patterns of the plurality of sub-pixels include circuit patterns configured to connect data signals.

14. The display panel according to claim 5, wherein the orthographic projection of a portion of the first conductive layer on the base substrate overlaps with the orthographic projection of the first sub-pixel opening on the base substrate, and the portion of the first conductive layer comprises a plurality of routing lines, the plurality of routing lines have approximately the same line width, and the spacing between adjacent routing lines in the plurality of routing lines is approximately the same.

15. The display panel according to claim 14, wherein the difference between the line width of each of the multiple routing lines and the average line width of the multiple routing lines is less than 20% of the average line width, and the difference between the spacing between every two adjacent routing lines and the average spacing between different adjacent routing lines is less than 20% of the average spacing.

16. The display panel according to claim 5, wherein The second conductive layer includes a first portion and a second portion, and the orthographic projections of the first portion and the second portion on the base substrate overlap with the orthographic projections of the first sub-pixel opening and the second sub-pixel opening on the base substrate, respectively; and The first portion includes a plurality of first routing lines, the plurality of first routing lines have substantially the same first line width, and adjacent first routing lines have substantially the same first spacing; and The second portion includes a plurality of second traces, the plurality of second traces having substantially the same The second line width is 200 mm, and adjacent second routing lines have substantially the same second spacing. 17 . The display panel according to claim 16 , wherein the first line width and the second line width are different from each other, and the first interval and the second interval are different from each other.

18. The display panel according to claim 5, wherein An orthographic projection of at least one of the active pattern of the second sub-pixel circuit and the active pattern of the third sub-pixel circuit on the base substrate overlaps with an orthographic projection of the first sub-pixel opening on the base substrate.

19. The display panel according to claim 5, wherein the orthographic projections of the active pattern of the second sub-pixel circuit and the active pattern of the third sub-pixel circuit on the base substrate are both located outside the orthographic projections of the second sub-pixel opening and the third sub-pixel opening on the base substrate. 20 . The display panel according to claim 19 , wherein the orthographic projections of the active patterns of the first sub-pixel circuit to the third sub-pixel circuit on the base substrate overlap with the orthographic projections of the first sub-pixel opening on the base substrate.

21. The display panel according to claim 5, wherein the orthographic projection of the active pattern of the second sub-pixel circuit on the substrate is outside the orthographic projection of the second sub-pixel opening on the substrate, and the orthographic projections of the active pattern of the second sub-pixel circuit and the active pattern of the first sub-pixel circuit on the substrate both overlap with the orthographic projection of the first sub-pixel opening on the substrate.

22. The display panel according to claim 21, wherein the orthographic projection of the active pattern of the third sub-pixel circuit on the substrate overlaps with the orthographic projection of the third sub-pixel opening on the substrate, and the orthographic projection of the third sub-pixel opening on the substrate is located within the orthographic projection range of the active pattern of the third sub-pixel circuit on the substrate.

23. The display panel according to claim 5, wherein At least one of the first conductive layer, the second conductive layer and the active material layer comprises a block pattern, and an orthographic projection of a portion of the block pattern on the base substrate overlaps with an orthographic projection of a sub-pixel opening on the base substrate; and The block pattern includes a main body and a plurality of strip-shaped parts, wherein a hollow portion is provided between the plurality of strip-shaped parts, and the plurality of strip-shaped parts are connected to each other through the main body, wherein the orthographic projection of the main body on the substrate is located outside the orthographic projection of the sub-pixel opening, and the plurality of strip-shaped parts are The orthographic projection of at least a portion of the shaped portion on the base substrate overlaps with the orthographic projection of the sub-pixel opening. The display panel according to claim 23 , wherein the plurality of strip portions have substantially the same width as each other.

25. The display panel according to claim 5, further comprising at least one of the following: The first conductive layer further includes a first dummy pattern, which is disposed in a gap region of the first circuit pattern of the plurality of sub-pixels, and an orthographic projection of the first dummy pattern on the base substrate overlaps an orthographic projection of at least one of the first sub-pixel opening to the third sub-pixel opening on the base substrate; The second conductive layer further includes a second dummy pattern disposed in a gap region of the second circuit pattern of the plurality of sub-pixels, and an orthographic projection of the second dummy pattern on the base substrate overlaps an orthographic projection of at least one of the first sub-pixel opening to the third sub-pixel opening on the base substrate; and The active material layer also includes a third dummy pattern, which is arranged in the gap area of ​​the active patterns of the multiple sub-pixels, and the orthographic projection of the third dummy pattern on the base substrate overlaps with the orthographic projection of at least one of the first sub-pixel opening to the third sub-pixel opening on the base substrate. 26 . The display panel according to claim 25 , wherein the first dummy pattern and the second dummy pattern are electrically floating or connected to a fixed potential.

27. The display panel according to claim 25, wherein the first circuit pattern comprises a routing pattern adjacent to the first dummy pattern, the first dummy pattern and the routing pattern have substantially the same width, and intervals between adjacent patterns in the first dummy pattern and the routing pattern are substantially the same as each other.

28. The display panel according to claim 25, wherein the second circuit pattern comprises a routing pattern adjacent to the second dummy pattern, the second dummy pattern and the routing pattern have substantially the same width, and intervals between adjacent patterns in the second dummy pattern and the routing pattern are substantially the same as each other.

29. The display panel according to any one of claims 1-28, wherein the area of ​​the first sub-pixel opening is larger than the area of ​​the second sub-pixel opening, and the area of ​​the second sub-pixel opening is larger than the area of ​​the third sub-pixel opening. 30 . The display panel according to claim 29 , wherein the first sub-pixel is a blue sub-pixel, one of the second sub-pixel and the third sub-pixel is a green sub-pixel, and the other is a red sub-pixel.

31. The display panel according to any one of claims 1 to 28, wherein the planarization layer comprises a first planar portion, a second planar portion and a third planar portion, and the orthographic projections of the first sub-pixel opening, the second sub-pixel opening and the third sub-pixel opening on the base substrate are respectively located within the orthographic projection ranges of the first planar portion, the second planar portion and the third planar portion on the base substrate, The first flat portion, the second flat portion, and the third flat portion respectively have a first flat surface, a second flat surface, and a third flat surface close to the light-emitting device, and at least two of the first flat surface, the second flat surface, and the third flat surface are located at different horizontal heights relative to the main surface of the substrate.

32. The display panel of claim 31, wherein in a direction perpendicular to a major surface of the base substrate, a distance between the first flat surface and the major surface of the base substrate is greater than a distance between the second flat surface and the major surface of the base substrate.

33. A display panel according to claim 32, wherein in a direction perpendicular to the main surface of the base substrate, the distance between the second flat surface and the main surface of the base substrate is greater than or approximately equal to the distance between the third flat surface and the main surface of the base substrate.

34. A display panel, include: substrate substrate; A plurality of sub-pixels are arranged on the base substrate, wherein each sub-pixel includes a light-emitting device and a sub-pixel circuit for driving the light-emitting device to emit light, and the plurality of sub-pixels include a first sub-pixel, a second sub-pixel and a third sub-pixel for displaying different colors; a pixel circuit layer, comprising sub-pixel circuits of the plurality of sub-pixels, and comprising a first sub-pixel circuit, a second sub-pixel circuit and a third sub-pixel circuit, respectively used to drive the light-emitting devices of the first sub-pixel, the second sub-pixel and the third sub-pixel to emit light; A planarization layer, disposed on a side of the pixel circuit layer away from the base substrate; as well as A pixel definition layer is disposed on a side of the planarization layer away from the pixel circuit layer, and the pixel definition layer has a plurality of sub-pixel openings, wherein each sub-pixel opening is configured to define a corresponding sub-pixel a light-emitting area of ​​a pixel, and at least a portion of the light-emitting device of each sub-pixel is located in a corresponding sub-pixel opening, wherein the plurality of sub-pixel openings include a first sub-pixel opening, a second sub-pixel opening, and a third sub-pixel opening corresponding to the first sub-pixel, the second sub-pixel, and the third sub-pixel, respectively; wherein the pixel circuit layer comprises a plurality of pattern layers, a first pattern layer among the plurality of pattern layers comprises a plurality of first patterns of the plurality of sub-pixels, and an orthographic projection of the plurality of first patterns on the base substrate overlaps with an orthographic projection of at least one of the first sub-pixel opening, the second sub-pixel opening, and the third sub-pixel opening on the base substrate; and An overlapping area between the plurality of first patterns and the first sub-pixel opening is greater than an overlapping area between the plurality of first patterns and the second sub-pixel opening or an overlapping area between the plurality of first patterns and the third sub-pixel opening. 35 . The display panel according to claim 34 , wherein an overlapping area of ​​the plurality of first patterns and at least one of the second sub-pixel opening and the third sub-pixel opening is zero. 36 . The display panel according to claim 34 , wherein the plurality of first patterns include circuit patterns for connecting the same signals of the plurality of sub-pixels.

37. The display panel according to any one of claims 34 to 36, wherein the area of ​​the first sub-pixel opening is larger than the area of ​​the second sub-pixel opening, and the area of ​​the second sub-pixel opening is larger than the area of ​​the third sub-pixel opening.

38. The display panel according to claim 37, wherein the multiple pattern layers further include a second pattern layer, located on a side of the first pattern layer close to or away from the light-emitting device, the second pattern layer including a plurality of second patterns of the plurality of sub-pixels, and an overlapping area between the plurality of second patterns and the first sub-pixel opening is greater than an overlapping area between the plurality of second patterns and the second sub-pixel opening or the third sub-pixel opening. 39 . The display panel according to claim 38 , wherein an overlapping area between the plurality of second patterns and the second sub-pixel opening is zero. 40 . The display panel according to claim 38 , wherein an overlapping area between the plurality of second patterns and the third sub-pixel opening is zero or equal to an area of ​​the third sub-pixel opening.

41. The display panel according to claim 38, wherein the plurality of pattern layers comprises one or more gate layers, one or more source-drain electrode layers, and one or more active material layers.

42. A display device comprising the display panel according to any one of claims 1 to 41.

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