A full signal debugging method and system based on scan chain
By utilizing the chip's own scan chain and netlist structure and combined with clock control, the full signal debugging of the internal signals of complex chips is achieved, and the problems of difficulty, high cost and strong intrusion in the existing technology are solved, and low-cost, non-invasive dynamic signal monitoring is achieved.
Patent Information
- Application Number
- CN202411877098.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-19
- Publication Date
- 2025-04-25
- Estimated Expiration
- 2044-12-19
AI Technical Summary
The prior art is difficult to effectively debug signals inside complex chips, especially those with dynamic changes. The traditional methods are costly and invasive, and cannot obtain enough signal values.
By using the scan chain that comes with the chip, the FF value on all scan chains in the chip is obtained, the values of all signals on the RTL are obtained by combining the netlist structure, and the dynamically changing signal values are obtained by controlling the clock to realize the debugging of the full signal.
It realizes the low-cost and non-invasive acquisition of the values of all signals in the chip, including dynamically changing signals, and there is no limit on the number of signals, solving the high cost and invasive problems of traditional methods.
Smart Images
Figure CN119335370B_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a full-signal debugging method and system based on scan chain. Background Art
[0002] As chips become larger and larger, and designs become more and more complex, debugging internal chip signals becomes increasingly difficult. Current debugging is mainly based on existing designs, obtaining chip internal information through register access, or deriving internal signals by injecting stimulation into the input PAD and then observing the signal from the output PAD. However, many internal chip signals cannot be obtained through this method, and the jump status of internal signals cannot be obtained.
[0003] When a chip has a problem, it is necessary to debug the internal signal, but it is difficult to obtain enough signal values for debugging internal signals, especially dynamically changing values. For example, an image processing chip inputs a frame of image. If the information obtained after the chip is processed is found to be problematic, it is necessary to debug the internal signal of the chip. For ASIC, a specific signal can be observed through FIB, but the disadvantages are also obvious. First, the cost is very high, second, the number of signals that can be observed is limited, and third, it is destructive to the chip itself. Summary of the invention
[0004] The purpose of the present invention is to provide a technical solution of a full-signal debugging method and system based on scan chain to address the deficiencies in the prior art. By utilizing the scan chain provided by the chip, the FF values on all scanchains in the chip are obtained, and the values of all signals on the RTL are obtained by combining the netlist structure. By controlling the clock, the dynamically changing values of all signals on the dynamically changing RTL can be obtained, which has the following advantages: first, the cost is low because the scan chain provided by the chip is utilized; second, the number of observed signals is not limited, and the values of all signals in the chip can be observed, and they are dynamically changing values; third, it is non-invasive to the chip and will not damage the chip itself.
[0005] In order to solve the above technical problems, the present invention adopts the following technical solutions:
[0006] A full signal debugging method based on scan chain, characterized by comprising the following steps:
[0007] S0, set the acquisition depth;
[0008] S1, the control chip is in function mode, CLOCK MANAGEMENT controls FUNC_CLK to flip once and then stop at a low level;
[0009] S2, the control chip is in the internal full signal debugging mode, and the signal values of all SDFFs in the chip are obtained through PAD_SO by unloading the scan chain circuit;
[0010] S3. Combine the netlist structure to derive the signal values of all signals on the RTL to achieve full signal debugging.
[0011] A full-signal debugging system based on scan chain, characterized by: including a SCAN MANAGEMENT circuit, a CLOCK MANAGEMENT circuit, a shift capture circuit and a netlist parsing algorithm unit:
[0012] SCAN MANAGEMENT circuit, used to control the chip in function mode, SCAN_MODE or internal_SCAN_MODE;
[0013] CLOCK MANAGEMENT circuit, used to control the flipping of FUNC_CLK and internal_SCAN_CLK;
[0014] The shift capture circuit is used to control the chip to be in an internal full-signal debugging mode, and obtain the signal values of all SDFFs in the chip through PAD_SO by means of the scan chain circuit unloading method;
[0015] The netlist parsing algorithm unit is used to derive the signal values of all signals on the RTL based on the netlist structure to achieve full signal debugging.
[0016] The present invention has the following beneficial effects due to the adoption of the above technical solution:
[0017] The present invention obtains the FF values on all scan chains in the chip by utilizing the scan chain provided by the chip, and obtains the values of all signals on the RTL by combining the netlist structure. By controlling the clock, the dynamically changing values of all signals on the dynamically changing RTL can be obtained, and the present invention has the following advantages: first, the cost is low because the scan chain provided by the chip is utilized; second, the number of observed signals is not limited, and the values of all signals in the chip can be observed, and the values are dynamically changing values; third, the present invention is non-invasive to the chip and will not damage the chip itself. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] The present invention will be further described below in conjunction with the accompanying drawings:
[0019] Figure 1 It is a flowchart of a full signal debugging method based on scan chain and a debugging method in a system of the present invention;
[0020] Figure 2 This is a circuit diagram for full signal debugging in the chip of the present invention. DETAILED DESCRIPTION
[0021] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.
[0022] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only embodiments of a part of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.
[0023] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.
[0024] The definitions of the professional terms used in this invention are shown in Table 1:
[0025] Abbreviations Chinese scan chain Scan Chain Debug debug RTL Register transaction level ASIC Application Specific Integrated Circuit FIB Focused Ion beam SDFF DFF with scan function mode Functional Mode SCAN_MODE Scan Mode SI Scan input Scan chain input SE Scan Enable SO Scan output Scan chain output PAD The pins for the chip to interact with the outside world CLOCK clock PC Personal Computer JTAG Boundary Scan Test PCIe High-speed serial computer expansion bus standard USB Universal Serial Bus Ethernet Ethernet ATE Automatic test equipment FUNC_CLK Clock in functional mode SCAN_CLK Clock in scan mode DFF trigger CLOCK MANAGEMENT Clock Management internal_SCAN_MODE Internal Scan Mode shift capture Shift capture internal_SCAN_CLK Internal scan clock fulldebugmux Selection circuit for full signal debugging PAD_SO Scan output pin clk Abbreviation for clock D pin Data input of the trigger Q pin Output of the trigger unload uninstall SCAN MANAGEMENT Scan Management load load capture capture input pattern Input Model PAD_SI Scan input pin output pattern Output Model shift Shift Interface control Interface Control internal scan Internal Scan FF register PAD_PC Pins for connecting to a personal computer
[0026] Table 1 Definitions of professional terms
[0027] When the chip used in the present invention is in ATE testing, SCAN_MODE is 1, internal_SCAN_MODE is 0, CLK comes from SCAN_CLK of ATE, and SE and SI both come from ATE.
[0028] The scan chain test is divided into three steps: load → capture → unload. Load is to input the input pattern into the scan chain through PAD_SI; capture is to input the result of each level of combinational logic into the next level SDFF; unload is to output the data in the scan chain serially to obtain the output pattern.
[0029] When the chip is in internal full signal debugging mode, SCAN_MODE is 0, internal_SCAN_MODE is 1, and CLK comes from internal_SCAN_CLK of CLOCK MANAGEMENT. Use the unloading stage of the scan chain (the load and capture stages of the scan chain are not needed) to shift the signal value of the internal SDFF to the shift capture circuit, thereby obtaining the signal value of all internal SDFFs.
[0030] like Figure 1 and Figure 2 As shown, a full signal debugging method based on scan chain of the present invention includes the following steps:
[0031] S0, on the PC side, set the sampling depth of the signal through the interface control circuit;
[0032] S1, the control chip is in function mode, CLOCK MANAGEMENT flips once through FUNC_CLK and then stops at a low level;
[0033] When the chip is in function mode, SCAN_MODE and internal_SCAN_MODE are 0, and CLK comes from FUNC_CLK.
[0034] S2, the control chip is in the internal full signal debugging mode, and the signal values of all SDFFs in the chip are obtained through PAD_SO by unloading the scan chain circuit;
[0035] The scan chain circuit adds a selection circuit fulldebugmux to form the scan chain into a loop so that the signal value in the function mode can be restored to the signal value in the previous function mode after the internal scan is completed. The signal values of all SDFFs inside the chip are obtained through the shift capture circuit, and an SDFF value is sampled in each cycle of internal_SCAN_CLK to obtain the signal value of the internal SDFF.
[0036] The present invention takes a scan chain consisting of 4 FFs as an example, and the D end of SDFF1 / 2 / 3 / 4 is an internal signal that needs to be observed.
[0037] Through the SCAN MANEGEMENT circuit, control SCAN_MODE to 0 and internal_SCAN_MODE to 1, so that the chip is in internal full-signal debugging mode.
[0038] Through the CLOCK MANEGEMENT circuit, the internal_SCAN_CLK is flipped, and the value of SDFF1 is transferred to SDFF2, the value of SDFF2 is transferred to SDFF3, the value of SDFF3 is transferred to SDFF4, the value of SDFF4 is transferred to SDFF1, and at the same time to the shiftcapture circuit, and the value of the D pin of SDFF4 in function mode is sampled. At the same time, the Q pin of SDFF1 becomes the value of the Q pin of SDFF4 in function mode.
[0039] If internal_SCAN_CLK is flipped again, the value of SDFF1 is transferred to SDFF2, the value of SDFF2 is transferred to SDFF3, the value of SDFF3 is transferred to SDFF4, the value of SDFF4 is transferred to SDFF1, and at the same time, it is transferred to the shift capture circuit and sampled to the value of D pin of SDFF3 in function mode. At the same time, Q pin of SDFF1 becomes the value of Q pin of SDFF3 in function mode, and Q pin of SDFF2 becomes the value of Q pin of SDFF4 in function mode.
[0040] By analogy, when the fourth beat is flipped, the Q pin of SDFF1 becomes the value of the Q pin of SDFF1 in function mode, the Q pin of SDFF2 becomes the value of the Q pin of SDFF2 in function mode, the Q pin of SDFF3 becomes the value of the Q pin of SDFF3 in function mode, and the Q pin of SDFF4 becomes the value of the Q pin of SDFF4 in function mode. That is, the value of the register is restored so that the function mode can continue to work normally in the next beat.
[0041] At the same time, the shift capture circuit collects the value of the D pin of SDFF4 / SDFF3 / SDFF2 / SDFF1 respectively.
[0042] In this way, all internal signal values of the first FUNC_CLK in function mode are obtained.
[0043] Similarly, switch the chip back to function mode, use CLOCK MANAGEMENT to flip FUNC_CLK once, and get all signal values of the second cycle. In this way, you can get the signal values of all signals inside the chip for many consecutive FUNC_CLK cycles.
[0044] SCAN MANAGEMENT CIRCUIT:
[0045] Generate internal_SCAN_MODE according to the previous steps to select whether to use the ATE's SCAN CLOCK or the internal_SCAN_CLK generated by the internal CLOCK MANAGEMENT when the scan chain is shifted; at the same time, generate SCAN_MODE to switch function mode and SCAN_MODE (including standard ATE SCAN_MODE and internal_SCAN_MODE in this method).
[0046] S3. The above signal values are transmitted back to the PC through the external interface control circuit to determine the sampling depth. If not, return to step S1. If so, derive the signal values of all signals on the RTL in combination with the netlist structure to achieve full signal debugging.
[0047] The external interface control circuit includes PAD_PC and interface control. This is related to the interface of the chip itself, with multiplexing as the main principle. For example, if the chip itself has a USB interface, the USB interface is used; generally speaking, it can be JTAG / PCIe / USB / Ethernet, and the main purpose is to communicate with the PC, control the full signal debugging mode of the chip, and transmit data to the PC after data acquisition.
[0048] This method uses the scan chain built into the chip to obtain the FF values on all scan chains in the chip, and combines the netlist structure to reversely infer the values of all signals on the RTL; by controlling the clock, the dynamically changing values of all signals on the dynamically changing RTL can be obtained, which has the following advantages: First, the cost is low because the scan chain built into the chip is used; second, the number of observed signals is not limited, and the values of all signals in the chip can be observed, and they are dynamically changing values; third, it is non-invasive to the chip and will not damage the chip itself.
[0049] The present invention discloses a full-signal debugging system based on scan chain, comprising a SCAN MANAGEMENT circuit, a CLOCK MANAGEMENT circuit, a shift capture circuit and a netlist parsing algorithm unit.
[0050] SCAN MANAGEMENT circuit is used to control the chip to be in function mode, SCAN_MODE or internal_SCAN_MODE.
[0051] CLOCK MANAGEMENT circuit, used to control the flipping of FUNC_CLK and internal_SCAN_CLK.
[0052] When the chip is in function mode, SCAN_MODE and internal_SCAN_MODE are 0, and CLK comes from FUNC_CLK.
[0053] The shift capture circuit is used to control the chip to be in an internal full-signal debugging mode, and obtain the signal values of all SDFFs in the chip through PAD_SO by means of the scan chain circuit unloading method;
[0054] The scan chain circuit adds a selection circuit fulldebugmux to form the scan chain into a loop so that the signal value in the function mode can be restored to the signal value in the previous function mode after the internal scan is completed. The signal values of all SDFFs inside the chip are obtained through the shift capture circuit, and an SDFF value is sampled in each cycle of internal_SCAN_CLK to obtain the signal value of the internal SDFF.
[0055] The present invention takes a scan chain consisting of 4 FFs as an example, and the D end of SDFF1 / 2 / 3 / 4 is an internal signal that needs to be observed.
[0056] Through the SCAN MANEGEMENT circuit, control SCAN_MODE to 0 and internal_SCAN_MODE to 1, so that the chip is in internal full-signal debugging mode.
[0057] Through the CLOCK MANEGEMENT circuit, the internal_SCAN_CLK is flipped, and the value of SDFF1 is transferred to SDFF2, the value of SDFF2 is transferred to SDFF3, the value of SDFF3 is transferred to SDFF4, the value of SDFF4 is transferred to SDFF1, and at the same time to the shiftcapture circuit, and the value of the D pin of SDFF4 in function mode is sampled. At the same time, the Q pin of SDFF1 becomes the value of the Q pin of SDFF4 in function mode.
[0058] If internal_SCAN_CLK is flipped again, the value of SDFF1 is transferred to SDFF2, the value of SDFF2 is transferred to SDFF3, the value of SDFF3 is transferred to SDFF4, the value of SDFF4 is transferred to SDFF1, and at the same time, it is transferred to the shift capture circuit and sampled to the value of D pin of SDFF3 in function mode. At the same time, Q pin of SDFF1 becomes the value of Q pin of SDFF3 in function mode, and Q pin of SDFF2 becomes the value of Q pin of SDFF4 in function mode.
[0059] By analogy, when the fourth beat is flipped, the Q pin of SDFF1 becomes the value of the Q pin of SDFF1 in function mode, the Q pin of SDFF2 becomes the value of the Q pin of SDFF2 in function mode, the Q pin of SDFF3 becomes the value of the Q pin of SDFF3 in function mode, and the Q pin of SDFF4 becomes the value of the Q pin of SDFF4 in function mode. That is, the value of the register is restored so that the function mode can continue to work normally in the next beat.
[0060] At the same time, the shift capture circuit collects the value of the D pin of SDFF4 / SDFF3 / SDFF2 / SDFF1 respectively.
[0061] In this way, all internal signal values of the first FUNC_CLK in function mode are obtained.
[0062] Similarly, switch the chip back to function mode, use CLOCK MANAGEMENT to flip FUNC_CLK once, and get all signal values of the second cycle. In this way, you can get the signal values of all signals inside the chip for many consecutive FUNC_CLK cycles.
[0063] SCAN MANAGEMENT CIRCUIT:
[0064] Generate internal_SCAN_MODE according to the previous steps to select whether to use the ATE's SCAN CLOCK or the internal_SCAN_CLK generated by the internal CLOCK MANAGEMENT when the scan chain is shifted; at the same time, generate SCAN_MODE to switch function mode and SCAN_MODE (including standard ATE SCAN_MODE and internal_SCAN_MODE in this method).
[0065] The netlist parsing algorithm unit is used to determine the sampling depth. If not, it returns to the mode selection unit. If so, it derives the signal values of all signals on the RTL in combination with the netlist structure to achieve full signal debugging.
[0066] The external interface control circuit includes PAD_PC and interface control. This is related to the interface of the chip itself, with multiplexing as the main principle. For example, if the chip itself has a USB interface, the USB interface is used; generally speaking, it can be JTAG / PCIe / USB / Ethernet, and the main purpose is to communicate with the PC, control the full signal debugging mode of the chip, and transmit data to the PC after data acquisition.
[0067] The above are only specific embodiments of the present invention, but the technical features of the present invention are not limited thereto. Any simple changes, equivalent replacements or modifications made based on the present invention to achieve basically the same technical effects are all included in the protection scope of the present invention.
Claims
1. A full signal debugging method based on scan chain, characterized in that The steps include: S0, set the acquisition depth; S1, the control chip is in function mode, CLOCK MANAGEMENT controls FUNC_CLK to flip once and then stop at a low level; S2, the control chip is in the internal full-signal debugging mode, and the load and capture stages of the scan chain are not needed. The signal values of all SDFFs inside the chip are obtained through the unloading method of the scan chain circuit through PAD_SO; when the chip is in the internal full-signal debugging mode, SCAN_MODE is 0, internal_SCAN_MODE is 1, and CLK comes from internal_SCAN_CLK of CLOCKMANAGEMENT; the scan chain circuit adds a selection circuit fulldebugmux to form a loop of the scan chain, so that the signal value in the function mode can be restored to the signal value of the previous function mode after the internal scan is completed. The signal values of all SDFFs inside the chip are obtained through the shift capture circuit, and a SDFF value is sampled in each cycle of internal_SCAN_CLK to obtain the signal value of the internal SDFF; S3. Combine the netlist structure to derive the signal values of all signals on the RTL to achieve full signal debugging.
2. The full signal debugging method based on scan chain according to claim 1, characterized in that: When the chip in step S1 is in function mode, SCAN_MODE and internal_SCAN_MODE are 0, and CLK comes from FUNC_CLK.
3. A full signal debugging system based on scan chain, characterized in that: Including SCAN MANAGEMENT circuit, CLOCK MANAGEMENT circuit, shift capture circuit and netlist parsing algorithm unit: SCAN MANAGEMENT circuit, used to control the chip in function mode, SCAN_MODE or internal_SCAN_MODE; CLOCK MANAGEMENT circuit, used to control the flipping of FUNC_CLK and internal_SCAN_CLK; The shift capture circuit is used to control the chip to be in the internal full-signal debugging mode. The load and capture stages of the scan chain are not needed. The signal values of all SDFFs in the chip are obtained through the unloading mode of the scan chain circuit via PAD_SO. When the chip is in the internal full-signal debugging mode, SCAN_MODE is 0, internal_SCAN_MODE is 1, and CLK comes from internal_SCAN_CLK of CLOCK MANAGEMENT. The scan chain circuit adds a selection circuit fulldebugmux to form a loop of the scan chain so that the signal value in the function mode can be restored to the signal value of the previous function mode after the internalscan is completed. The signal values of all SDFFs in the chip are obtained through the shift capture circuit, and the value of one SDFF is sampled in each cycle of internal_SCAN_CLK to obtain the signal value of the internal SDFF. The netlist parsing algorithm unit is used to derive the signal values of all signals on the RTL based on the netlist structure to achieve full signal debugging.
4. The full-signal debugging system based on scan chain according to claim 3, characterized in that: When the chip is in function mode, SCAN_MODE and internal_SCAN_MODE are 0, and CLK comes from FUNC_CLK.
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