Memory controller and control method

Abstract

The invention provides a memory controller and a control method. The memory controller comprises a plurality of voltage conversion circuits, an inspection circuit and a selection circuit. The voltage conversion circuit is configured to receive an external voltage and convert the external voltage into a plurality of supply voltages. The voltage conversion circuit detects the levels of the power voltages generated by the voltage conversion circuit respectively so as to generate a plurality of power confirmation signals. The checking circuit is coupled to the voltage conversion circuit. The inspection circuit is configured to generate a first inspection signal corresponding to an internal power supply voltage of the power supply voltages and a second inspection signal corresponding to all the power supply voltages according to the power supply confirmation signal. The selection circuit is used for selectively outputting the first inspection signal or the second inspection signal as a reset confirmation signal.

Description

Technical Field

[0001] The present invention relates to a controller and a method, and in particular to a memory controller and a control method. Background Art

[0002] In the application of flash memory controller, in response to different specifications and system requirements of host devices, the flash memory controller needs to perform voltage conversion according to different specifications to adaptively drive the operation of the flash memory. Therefore, when the flash memory is started or restarted, how the flash memory controller can quickly and efficiently confirm whether the converted voltages are ready has become one of the issues to be solved in the related field. Summary of the invention

[0003] The present invention provides a memory controller and a control method, which can effectively and efficiently confirm whether the converted voltages are ready when the flash memory is started or restarted.

[0004] The memory controller of the present invention includes a plurality of voltage conversion circuits, a check circuit and a selection circuit. The voltage conversion circuit is configured to receive an external voltage and convert it into a plurality of power supply voltages respectively. The voltage conversion circuit detects the levels of the power supply voltages generated by it respectively to generate a plurality of power supply confirmation signals. The check circuit is coupled to the voltage conversion circuit. The check circuit is used to generate a first check signal and a second check signal according to the power supply confirmation signal, wherein the first check signal corresponds to an internal power supply voltage in the power supply voltage, and the second check signal corresponds to all power supply voltages. The selection circuit is used to selectively output the first check signal or the second check signal as a reset confirmation signal.

[0005] The control method of the present invention is suitable for driving a flash memory. The control method includes receiving an external voltage and converting the external voltage into a plurality of power supply voltages; detecting the levels of the power supply voltages to generate a plurality of power supply confirmation signals corresponding to each other; generating a first check signal and a second check signal according to the power supply confirmation signal, wherein the first check signal corresponds to an internal power supply voltage in the power supply voltage, and the second check signal corresponds to all power supply voltages; and selectively outputting the first check signal or the second check signal as a reset confirmation signal.

[0006] Based on the above, the memory controller and control method of the present invention provide a method of checking the power supply voltage by software or hardware, and provide a flexible and fast flash memory startup or restart process. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the present invention.

[0008] Figure 1 is a circuit block diagram of a memory controller according to an embodiment of the present invention;

[0009] Figure 2 is a circuit block diagram of a memory controller according to an embodiment of the present invention;

[0010] Figure 3 This is a flow chart of a control method according to an embodiment of the present invention;

[0011] Figure 4 The figure is a flow chart of a control method according to an embodiment of the present invention.

[0012] Description of Figure Numbers

[0013] 10: Host device;

[0014] 11, 21: memory controller;

[0015] 12: Flash memory;

[0016] 110, 210: Check the circuit;

[0017] 111, 211: Select circuit;

[0018] 112: processor;

[0019] 2100: voltage level setting circuit;

[0020] 2101: confirmation result judgment circuit;

[0021] 2110~2112: Door;

[0022] DS1, DS2: Check signal;

[0023] DS2_Cont: check result custom signal;

[0024] LDO1~LDOx: voltage conversion circuit;

[0025] MS: mode selection signal;

[0026] RSC: reset confirmation signal;

[0027] S1, S2, S3: setting signal;

[0028] S2_En: mode enable signal;

[0029] S31-S34, S41-S46: steps;

[0030] VC1~VCx: power confirmation signal;

[0031] Vext: external voltage;

[0032] VS: conversion setting signal;

[0033] VS1~VSx: power supply voltage. DETAILED DESCRIPTION

[0034] Figure 1 FIG. 1 is a circuit block diagram of a memory controller 11 according to an embodiment of the present invention. Generally speaking, the memory controller 11 is coupled between the flash memory 12 and the host device 10. The memory controller 11 can receive the external voltage Vext provided by the host device 10 and the external input setting signals S1 and S2 to convert the external voltage Vext into a suitable voltage level accordingly, thereby driving the operation of the flash memory 12 and the internal circuit of the memory controller 11. In actual applications, the external voltage Vext provided by host devices 10 of different specifications is different. Therefore, the memory controller 10 connected between the host device 10 and the flash memory 12 plays an important role, and is responsible for adaptively performing voltage conversion between the host device 10 and the flash memory 12 of different specifications and voltage requirements, so as to better drive the flash memory 12, thereby increasing the system compatibility of the flash memory 12.

[0035] Specifically, the host device 10 may be a host device 10 that complies with Secure Digital (SD) memory card, embedded MultiMedia Card (embedded MultiMedia Card, eMMC), Universal Serial Bus (USB), Universal Flash Storage (UFS), Non-Volatile Memory Express (NVMe), or other suitable specifications. Further, the host device 10 can provide an external voltage Vext to the memory controller 11. At the same time, the first setting signal S1 and the second setting signal S2 are input externally to the memory controller 11 to indicate the voltage combination set by the user or required by the system.

[0036] In some embodiments, the memory controller 11 can receive the external voltage Vext and generate the appropriate first power voltage VS1 and second power voltage VS2 according to the first setting signal S1, which are respectively used to drive the core circuit blocks in the flash memory 12. On the other hand, each time the memory controller 11 is started or restarted, it is necessary to recheck the voltage of the external voltage Vext to confirm that the levels of the converted multiple power voltages have reached the system requirements. In this embodiment, the memory controller 11 can also operate in different modes according to the second setting signal S2, and check the levels of the converted multiple power voltages VS1~VSx (including the first power voltage VS1 and the second power voltage VS2) in different ways according to the setting. When operating in the first mode, the memory controller 11 can check all the converted power voltages VS1~VSx one by one through its internal processor 112 in a software operation manner. When operating in the second mode, the memory controller 11 can check the converted power voltages VS1~VSx in a hardware manner through its internal circuit.

[0037] In some embodiments, the memory controller 11 includes a plurality of voltage conversion circuits LDO1-LDOx, a check circuit 110, a selection circuit 111, and a processor 112. The voltage conversion circuits LDO1-LDOx can be used to receive an external voltage Vext to generate a plurality of power supply voltages VS1-VSx, including a first power supply voltage VS1, a second power supply voltage VS2, and a third power supply voltage VS3. The first power supply voltage VS1 and the second power supply voltage VS2 can be provided to the flash memory 12 for driving, and are used to drive the flash memory core circuit block and the input-output circuit block, for example. The third power supply voltage VS3 (i.e., the internal power supply voltage) can be provided to the memory controller 11 for driving, and is, for example, a basic power supply voltage for driving the memory controller 11 to operate. In some embodiments, each voltage conversion circuit LDO1-LDOx can be, for example, a low dropout circuit, a buck converter, or other suitable circuits, which are used to step down the external voltage Vext to an appropriate voltage level. In this embodiment, the number x of the voltage conversion circuits LDO1 -LDOx can be adjusted according to the number of power supply voltages required by the system or the number of divided voltage domains.

[0038] Furthermore, the inspection circuit 110 is coupled to the voltage conversion circuits LDO1-LDOx. The inspection circuit 110 can generate a plurality of conversion setting signals VS according to the first setting signal S1 to control and set the operation of the voltage conversion circuits LDO1-LDOx, so that the voltage conversion circuits LDO1-LDOx can convert and generate appropriate power supply voltages that meet the specifications of the flash memory 12 according to the specifications of the host device 10 and the flash memory 12. In detail, each voltage conversion circuit LDO1-LDOx can operate independently and generate a separate power supply voltage, which can have the same or different voltage levels. The first voltage conversion circuit LDO1 and the second voltage conversion circuit LDO2 (not explicitly marked in the figure) in the voltage conversion circuits LDO1-LDOx are Figure 1 ), can generate power supply voltages VS1 and VS2 respectively, for driving the core circuit block and the input / output circuit block in the flash memory 12 respectively. Figure 1 In the embodiment of the present invention, the memory controller 11 can generate the third power supply voltage VS3 required by the memory controller 11. In addition, each time the memory controller 11 is started or restarted, it is affected by the power failure of the external voltage Vext, and the memory controller 11 also needs to confirm whether each power supply voltage VS1-VSx has reached or exceeded its corresponding voltage threshold. More specifically, the voltage conversion circuits LDO1-LDOx can sense the power supply voltages VS1-VSx generated by themselves, respectively, to determine whether each power supply voltage VS1-VSx exceeds its corresponding voltage threshold, and generate corresponding power confirmation signals VC1-VCx accordingly.

[0039] In some embodiments, the first setting signal S1 and the second setting signal S2 may be provided in real time by an external device or written in advance to the memory controller 11, thereby controlling the operation of the memory controller 11. For example, the first setting signal S1 and the second setting signal S2 may be obtained by reading a pre-written electronic fuse. Alternatively, the first setting signal S1 and the second setting signal S2 may be obtained by reading a voltage level connected to a bonding wire on a corresponding pad. Alternatively, the first setting signal S1 and the second setting signal S2 may be provided in real time by an external device that is the same as or different from the host device 10.

[0040] Furthermore, the inspection circuit 110 is coupled to the voltage conversion circuits LDO1-LDOx, and the inspection circuit 110 can generate a first inspection signal DS1 and a second inspection signal DS2 according to the power confirmation signals VC1-VCx, wherein the first inspection signal DS1 corresponds to the third power confirmation signal VC3, which includes inspection information of the third power voltage VS3 that can be used to drive the processor 112. The second inspection signal DS2 corresponds to the power confirmation signals VC1-VCx of all power voltages VS1-VSx, which includes inspection information of all power voltages VS1-VSx. Further, the inspection circuit 110 can also generate a mode selection signal MS according to the second setting signal S2, and provide the mode selection signal MS, the first inspection signal DS1 and the second inspection signal DS2 to the selection circuit 111.

[0041] The selection circuit 111 is coupled to the inspection circuit 110. The selection circuit 111 can select the first inspection signal DS1 or the second inspection signal DS as the reset confirmation signal RSC according to the mode selection signal MS, and output it to the processor 112. More specifically, when the memory controller 11 is operated in the first mode, the processor 112 is used to check the power confirmation signals VC1-VCx. In this case, in order to ensure that the processor 112 can first obtain a stable power supply voltage for inspection, the inspection circuit 110 can first only check the power supply voltage received by the processor 112. In this embodiment, the processor 112 requires a third power supply voltage VS3 to operate. Therefore, the inspection circuit 110 outputs the power confirmation signal VC3 generated by the voltage conversion circuit LDO3 checking the third power supply voltage VS3 as the first inspection signal DS1, and provides it to the selection circuit 111. In addition, when the memory controller 11 is operated in the second mode, the inspection circuit 110 checks all the power confirmation signals VC1-VCx in a hardware circuit manner, and generates the second inspection signal DS2 according to all the power confirmation signals VC1-VCx.

[0042] On the other hand, the second setting signal S2 indicates whether the memory controller 11 is to check the power supply voltages VS1-VSx by software or hardware. In this case, the checking circuit 110 can generate a mode selection signal MS according to the second setting signal S2 to inform the selection circuit 111 whether the host device 10 is to instruct the software or hardware to check the power supply voltages VS1-VSx. When the second setting signal S2 indicates that the power supply voltages VS1-VSx are to be checked by software, the memory controller 11 will be controlled to operate in the first mode, and the selection circuit 111 will output the first check signal DS1 as the reset confirmation signal RSC according to the mode selection signal MS, so that the processor 112 checks all the power confirmation signals VC1-VCx after the reset confirmation signal RSC indicates that the third power supply voltage VS3 is ready. In addition, when the second setting signal S2 indicates that the power supply voltages VS1-VSx are to be checked by hardware, the memory controller 11 will be controlled to operate in the second mode, and the checking circuit 110 will simultaneously check all the power confirmation signals VC1-VCx and generate the corresponding second check signal DS2 accordingly. The selection circuit 111 outputs the second check signal DS2 as the reset confirmation signal RSC in the second mode according to the mode selection signal MS, thereby indicating the processor 112 the check result of the check circuit 110 .

[0043] Under the control of the reset confirmation signal RSC, the processor 112 performs operations corresponding to the first mode and the second mode. Specifically, when the memory controller 11 operates in the first mode and the reset confirmation signal RSC indicates that the basic working voltage VS3 is ready, the processor 112 executes a software program to sequentially check the power confirmation signals VC1-VCx to ensure that the driving and read / write operations of the flash memory 12 are performed after each power supply voltage VS1-VSx is greater than or equal to its corresponding voltage threshold. In addition, when the memory controller 11 operates in the second mode and the reset confirmation signal RSC indicates that all power supply voltages VS1-VSx are ready, the processor 112 can immediately start driving and performing read / write operations of the flash memory 12.

[0044] Figure 2 FIG. 1 is a circuit block diagram of a memory controller 21 according to an embodiment of the present invention. Figure 2 The memory controller 21 is similar to Figure 1 The memory controller 11 is used to illustrate the internal circuit structure of the inspection circuit 210 and the selection circuit 211 in the memory controller 21, so the same elements are marked with the same symbols and are not further described here.

[0045] In this embodiment, the memory controller 21 includes a check circuit 210, a selection circuit 211, a processor 112, and voltage conversion circuits LDO1-LDOx. Further, the check circuit 210 includes a voltage level setting circuit 2100 and a confirmation result judgment circuit 2101. In detail, the voltage level setting circuit 2100 receives a first setting signal S1 and a second setting signal S2. The voltage level setting circuit 2100 can generate a conversion setting signal VS according to the first setting signal, and adaptively adjust the voltage conversion circuit LDO1-LDOx to generate the power supply voltage VS1-VSx required by the system. Further, the voltage level setting circuit 2100 can provide mode information MI to the confirmation result judgment circuit 2101 according to the second setting signal S2.

[0046] In this embodiment, in addition to receiving the power confirmation signals VC1-VCx and the mode information MI related to the second setting signal S2 from the voltage level setting circuit 2100, the power confirmation signals VC1-VCx also receive the third setting signal S3 from the host device 10, and the mode enable signal S2_En and the check result custom signal DS2_Cont are received by the processor 112. In detail, the third setting signal S3 includes the output time of the reset confirmation signal RSC, that is, how long the calculation time needs to wait after starting or restarting before outputting the calculated reset confirmation signal RSC. Generally speaking, the output time of the reset confirmation signal RSC is related to the climbing slope and confirmation time required for the power confirmation signals VC1-VCx. The mode enable signal S2_En includes information about whether the memory controller 21 is allowed to be operated in the second mode, that is, whether the memory controller 21 is open to perform the power voltage confirmation judgment in hardware. Finally, the check result custom signal DS2_Cont is open to define the power confirmation signal to be checked by the memory controller 21 in the second mode by the system or the user. For example, in some embodiments, the confirmation result judgment circuit 2101 can receive all power confirmation signals VC1-VCx through an AND gate to determine whether all power confirmation signals VC1-VCx are ready, and generate the second inspection signal DS2 accordingly. However, in some other embodiments, the confirmation result judgment circuit 2101 can of course only select a part of the selected power confirmation signals from the power confirmation signals VC1-VCx according to the inspection result custom signal DS2_Cont, and then determine whether the selected power confirmation signals are ready, and generate the second inspection signal DS2 accordingly.

[0047] The selection circuit 211 includes an AND gate 2110, an XOR gate 2111, and an OR gate 2112. The first input terminal of the AND gate 2110 receives the mode information MI and the second input terminal receives the first check signal DS1. The first input terminal of the XOR gate 2111 receives the mode information MI and the second input terminal receives the second check signal DS2. In addition, the output terminals of the AND gate 2110 and the XOR gate 2111 are respectively connected to the first input terminal and the second input terminal of the OR gate 2112 to generate the reset confirmation signal RSC at the output terminal of the OR gate 2112. In detail, when the mode enable signal S2_En indicates that the memory controller 21 opens the second mode, the selection circuit 211 will selectively select the first check signal DS1 or the second check signal DS2 as the reset confirmation signal RSC according to the control of the second setting signal S2. On the contrary, when the mode enable signal S2_En indicates that the memory controller 21 does not open the second mode, the confirmation result judgment circuit 2101 can only operate the mode selection signal MS in the first mode according to the mode enable signal S2_En, so that the selection circuit 211 outputs the first check signal DS1 as the reset confirmation signal RSC. Figure 2 FIG. 2 shows an implementation of the selection circuit 211 using an AND gate 2110, an XOR gate 2111, and an OR gate 2112. However, it should be understood that Figure 3 The circuit structure in the embodiment is only one of the various embodiments of the present invention. A person skilled in the art can change the circuit structure by himself, and the same operation result can be achieved by different circuit structures. For example, the selection circuit 211 can also be implemented by a multiplexer, as long as it can selectively output the first check signal DS1 or the second check signal DS2 as the reset confirmation signal RSC.

[0048] Figure 3 The figure is a flow chart of a control method according to an embodiment of the present invention. Figure 3 The flowchart shown can be applied to Figure 1 , Figure 2 The memory controllers 11 and 21 shown in FIG. 1 and the operation contents of the memory controllers 11 and 21 can be summarized as follows: Figure 3 Flowchart shown. Figure 3The flowchart shown includes steps S31 to S34. In step S31, the memory controller 11 / 21 can receive an external voltage Vext and convert the external voltage Vext into multiple power supply voltages VS1 to VSx. In step S32, the memory controller 11 / 21 can detect the levels of the converted power supply voltages VS1 to VSx to generate corresponding power supply confirmation signals VC1 to VCx. In step S33, the memory controller 11 / 21 can generate a first check signal DS1 and a second check signal DS2 based on the power supply confirmation signals VC1 to VCx, wherein the first check signal DS1 corresponds to a third power supply voltage VS3 among the power supply voltages, and the second check signal DS2 corresponds to all power supply voltages. Finally, the memory controller 11 / 21 can selectively output the first check signal DS1 or the second check signal DS2 as a reset confirmation signal RSC. About Figure 3 For details of the control method shown, please refer to the description of the memory controllers 11 and 21 in the above paragraphs, which will not be elaborated here.

[0049] Figure 4 The figure is a flow chart of a control method according to an embodiment of the present invention. Figure 4 The flowchart shown can be applied to Figure 1 , Figure 2 The memory controllers 11 and 21 shown in FIG. 1 and the operation contents of the memory controllers 11 and 21 can also be summarized as follows: Figure 4 Flowchart shown. Figure 4The flowchart shown includes steps S41 to S46. In step S41, the memory controller 11 / 21 can set the first voltage conversion circuit LDO1 and the second voltage conversion circuit LDO2 in the voltage conversion circuits LDO1 to LDOx for driving the flash memory 12 according to the first setting signal S1. In step S42, the memory controller 11 / 21 can receive an external voltage Vext and convert the external voltage Vext into a plurality of power supply voltages VS1 to VSx. In step S43, the memory controller 11 / 21 can detect the levels of the power supply voltages VS1 to VSx to generate corresponding power confirmation signals VC1 to VCx. In step S44, the memory controller 11 / 21 can determine in which operation mode the memory controller 11 / 21 is controlled according to the second setting signal. When the memory controller 11 / 21 determines that the memory controller 11 / 21 is controlled in the first mode, it enters step S45, and the memory controller 11 / 21 can check the power supply voltages VS1 to VSx in software through the processor 112. On the contrary, when the memory controller 11 / 21 determines that the memory controller 11 / 21 is controlled in the second mode, the process proceeds to step S46 , and the memory controller 11 / 21 may check the power supply voltages VS1 ˜VSx in a hardware manner through the checking circuit 110 .

[0050] In summary, the memory controller and control method of the present invention provide a method for checking the power supply voltage by software or hardware. Compared with the process of checking all power supply voltages one by one in sequence by software through a processor, checking the power supply voltage by hardware can save the process of checking all power supply voltages one by one, and effectively improve the checking speed after the memory controller is started or restarted.

Claims

1. A memory controller, comprising: A plurality of voltage conversion circuits are configured to receive external voltages and convert them into a plurality of power supply voltages respectively, and the plurality of voltage conversion circuits respectively detect the levels of the plurality of power supply voltages generated thereby to generate a plurality of power supply confirmation signals; a check circuit coupled to the plurality of voltage conversion circuits, the check circuit being configured to generate a first check signal and a second check signal according to the plurality of power confirmation signals, wherein the first check signal corresponds to an internal power voltage among the plurality of power voltages, and the second check signal corresponds to all of the plurality of power voltages; as well as The selection circuit is used for selectively outputting the first inspection signal or the second inspection signal as a reset confirmation signal.

2. The memory controller according to claim 1, wherein the inspection circuit is used to receive a first setting signal to set a first voltage conversion circuit and a second voltage conversion circuit among the plurality of voltage conversion circuits for generating a first power supply voltage and a second power supply voltage to drive a flash memory, so that the levels of the first power supply voltage and the second power supply voltage meet the specifications of the flash memory.

3. The memory controller according to claim 1 , further comprising a processor, wherein the checking circuit is further configured to receive a second setting signal to indicate whether the memory controller is operating in the first mode or the second mode, wherein when the memory controller is operating in the first mode, the processor is configured to check the plurality of power confirmation signals, and When the memory controller operates in the second mode, the checking circuit is used to check the plurality of power confirmation signals.

4. The memory controller of claim 3, wherein the internal power supply is used to drive the processor.

5. The memory controller according to claim 3, wherein the inspection circuit is further configured to generate a mode selection signal to the selection circuit according to the second setting signal, wherein when the memory controller operates in the first mode, the selection circuit selects the first check signal as the reset confirmation signal according to the mode selection signal, and provides the reset confirmation signal to the processor, and When the memory controller operates in the second mode, the selection circuit selects the second check signal as the reset confirmation signal according to the mode selection signal, and provides the reset confirmation signal to the processor.

6. The memory controller according to claim 5, wherein when the memory controller is operating in the first mode, the processor sequentially confirms the multiple power confirmation signals after the first check signal indicates that the internal power voltage is greater than a first voltage threshold to determine whether the multiple power voltages are respectively greater than multiple voltage thresholds.

7. The memory controller according to claim 5, wherein when the memory controller is operating in the second mode, the checking circuit first simultaneously checks whether the multiple power confirmation signals are respectively greater than multiple voltage thresholds, and then generates the second checking signal indicating that the multiple power supply voltages are respectively greater than the multiple voltage thresholds.

8. The memory controller of claim 1 , wherein the selection circuit comprises: An AND gate having a first input terminal for receiving a mode selection signal, a second input terminal for receiving the first inspection signal, and an output terminal for generating a first operation signal; an XOR gate having a first input terminal for receiving the mode selection signal, a second input terminal for receiving the second inspection signal, and an output terminal for generating a second operation signal; The OR gate has a first input terminal for receiving the first operation signal, a second input terminal for receiving the second operation signal, and an output terminal for generating the reset confirmation signal. 9 . The memory controller according to claim 2 , wherein the checking circuit further receives a third setting signal for setting an output time of the checking circuit generating the reset confirmation signal.

10. The memory controller according to claim 9, wherein the checking circuit comprises: a voltage level setting circuit, wherein the voltage level setting circuit generates a plurality of voltage setting signals according to the first setting signal to respectively set the plurality of voltage conversion circuits; as well as The confirmation result judgment circuit receives the multiple power confirmation signals to generate the first inspection signal according to the power confirmation signal corresponding to the internal power voltage among the multiple power confirmation signals, and generates the second inspection signal according to all the multiple power confirmation signals.

11. A control method, applicable to driving a flash memory, the control method comprising: receiving an external voltage and converting the external voltage into a plurality of power supply voltages; Detecting the levels of the plurality of power supply voltages to generate a plurality of corresponding power supply confirmation signals; generating a first check signal and a second check signal according to the plurality of power confirmation signals, wherein the first check signal corresponds to an internal power supply voltage among the plurality of power supply voltages, and the second check signal corresponds to all of the plurality of power supply voltages; as well as The first check signal or the second check signal is selectively output as a reset confirmation signal.

12. The control method according to claim 11 further comprises receiving a first setting signal for setting a first voltage conversion circuit and a second voltage conversion circuit for generating a first power supply voltage and a second power supply voltage to drive the flash memory, so that the levels of the first power supply voltage and the second power supply voltage meet the specifications of the flash memory.

13. The control method according to claim 11, further comprising receiving a second setting signal to indicate operation in the first mode or the second mode, wherein when operating in the first mode, the processor is used to check the plurality of power confirmation signals, and When operating in the second mode, the checking circuit is used to check the plurality of power confirmation signals.

14. The control method according to claim 13, further comprising generating a mode selection signal according to the second setting signal, wherein when operating in the first mode, the first check signal is selected as the reset confirmation signal according to the mode selection signal, and the reset confirmation signal is provided to the processor, and When operating in the second mode, the second check signal is selected as the reset confirmation signal according to the mode selection signal, and the reset confirmation signal is provided to the processor.

15. The control method according to claim 14, wherein when operating in the first mode, after the first check signal indicates that the internal power supply voltage is greater than a first voltage threshold, the processor sequentially confirms the multiple power supply confirmation signals to determine whether the multiple power supply voltages are respectively greater than multiple voltage thresholds.

16. The control method according to claim 14, wherein when operating in the second mode, the inspection circuit first simultaneously checks whether the multiple power supply confirmation signals are respectively greater than multiple voltage thresholds, and then generates the second inspection signal indicating that the multiple power supply voltages are respectively greater than the multiple voltage thresholds. 17 . The control method according to claim 12 , further comprising receiving a third setting signal for setting an output time of generating the reset confirmation signal.

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