Embedded CGRA secondary memory design method oriented to context switching

Abstract

The invention provides a context switching-oriented embedded CGRA secondary memory design method, which comprises the following steps of: 1, determining a basic CGRA hardware architecture according to an actual multi-task requirement; 2, an open source CGRA modeling tool OpenCGRA is utilized, and on the basis of the selected basic CGRA hardware architecture, the CGRA hardware architecture is described through a PyMTL3 language; step 3, modifying a basic component library Memprovided by the OpenCGRA, adding a component through a PyMTL3 language, and completing a secondary design of a data memory in each Tile to obtain an embedded CGRA; 4, performing sequential logic design of state transition and state output and combinational logic design of state switching aiming at all working states of the finite-state machine in the secondary memory, and describing by using a PyMTL3 language; and step 5, generating a synthesizable Verilog code by using the OpenCGRA. According to the invention, stagnation of the task during context switching can be avoided, so that the task throughput rate is improved.

Description

Technical Field

[0001] The invention relates to an embedded CGRA secondary memory design method oriented to context switching, belonging to the technical field of coarse-grained reconfigurable architecture memory design. Background Art

[0002] A coarse-grained reconfigurable architecture (CGRA) is defined as a group of interconnected processing unit arrays (TileArray), whose computing functions and routing directions can be flexibly reconfigured along the spatial and temporal dimensions, and cooperate with each other to achieve specified computing functions. CGRA not only provides computing performance and energy efficiency close to ASIC, but its coarse-grained reconfigurability (Word-Level) can also bring development efficiency better than FPGA. With the end of Dennard scaling and the decline of Moore's Law, embedded fields such as aerospace, measurement, autonomous driving, and medical care pay more and more attention to the performance and energy efficiency of processors. At the same time, in order to cater to the rapid iteration and update of algorithms, processors should also have high programming efficiency. Therefore, CGRA has a good development prospect in the embedded field.

[0003] Processors in the embedded field often face workloads with mixed tasks. For example, deep learning-based face recognition in access control systems may consist of multiple convolution, activation, batch normalization, and pooling layers, and different layers are executed in a pipelined manner as tasks with data dependencies. Automotive electronic control units (ECS) need to process independent tasks from video, audio, and data analysis collected by sensors around the vehicle in parallel. Therefore, how to efficiently perform multiple tasks on processors has always been the focus of many studies. Since the throughput of some tasks varies with the input density and the tasks have random initialization or destruction time, dynamic resource allocation has become one of the important technologies to maximize processor resource utilization and improve task throughput. Correspondingly, as an emerging architecture in the embedded field, CGRA's multi-task dynamic resource allocation method has also received widespread attention from researchers in recent years.

[0004] In the embedded CGRA architecture, dynamic resource allocation for multiple tasks will lead to large-scale mismatch of configuration instructions and data stored in CGRATile. For example, before dynamic resource allocation, three tiles (3-L) in the shape of "L" are allocated to the current task, and after dynamic resource allocation, four tiles (4-S) in the shape of "field" are allocated to the current task. However, the configuration instructions and data of these two resource allocation situations will be stored in different tiles under the static planning of the CGRA compiler, which makes 4-S unable to directly use the configuration instructions and data of 3-L. Therefore, after dynamic resource allocation, the configuration instructions and data required by 4-S need to be reloaded into the configuration memory and data memory of the corresponding four tiles before execution can begin. This step is called "context switching", and all tasks with resource allocation changes need to be executed. However, existing CGRA multi-tasking research mainly focuses on compilers and schedulers, lacking efficient memory design for context switching, which causes each task to stagnate after resource allocation until the corresponding configuration instructions and data are reloaded, which seriously limits the task throughput. Summary of the invention

[0005] The present invention aims to solve the technical problem that tasks stagnate during context switching, and further proposes an embedded CGRA secondary memory design method for context switching.

[0006] The technical solution adopted by the present invention to solve the above problems is: the present invention proposes an embedded CGRA secondary memory design method for context switching, comprising:

[0007] Step 1: Determine the basic CGRA hardware architecture based on actual multi-task requirements;

[0008] Step 2: Using the open source CGRA modeling tool OpenCGRA, based on the selected basic CGRA hardware architecture, describe the CGRA hardware architecture using the PyMTL3 language;

[0009] Step 3: Modify the basic component library Mem provided by OpenCGRA, add components through PyMTL3 language, complete the secondary design of data memory in each Tile, and obtain embedded CGRA;

[0010] Step 4: Design the sequential logic of state transfer and state output and the combinational logic of state switching for all working states of the finite state machine in the CGRA in the secondary memory, and describe them in PyMTL3 language;

[0011] Step 5: Use OpenCGRA to generate synthesizable Verilog code to implement alternate reading and writing of memory group data after context switching.

[0012] Optionally, the basic CGRA hardware architecture in step 1 includes: size, topological connection relationship between tiles, size of data memory and configuration memory in tiles, complexity of functional units, and number of registers

[0013] Optionally, the description of the CGRA hardware architecture in step 2 specifically includes:

[0014] Use the basic component library provided by the modeling tool to build the CGRA hardware architecture.

[0015] Optionally, the two-level design of the data memory in each Tile in step 3 specifically includes a first-level memory and a second-level memory;

[0016] The first-level memory design specifically includes: dividing the data memory into memory group A and memory group B, writing the first round of data to memory group A, reading the first round of data from memory group A to perform calculations when the embedded CGRA is running, and writing the second round of data to memory group B at the same time. When all the first round of data in memory group A is read out, directly switch to memory group B to read the second round of data, and write the third round of data to memory group A, and repeat the above steps to perform alternating read and write operations;

[0017] The second-level memory design specifically includes: dividing memory group A and memory group B into sub-memory group A1, sub-memory group A2, sub-memory group B1 and sub-memory group B2 respectively, so that the alternating read and write operations are only for sub-memory group A1 and sub-memory group B1. When the dynamic resource allocation performs context switching, the first round of data is read from sub-memory group A1 and the second round of data is written to sub-memory group B1 at the same time, and the remaining data of the first round of data that can be processed under the new resource allocation decision is temporarily written to sub-memory group A2. After the writing is completed, the read operation on sub-memory group A1 will be switched to sub-memory group A2, and the written data will be processed under the new resource allocation decision. After the processing is completed, an alternating operation is performed to read the second round of data from sub-memory group B1 and write the third round of data to sub-memory group A1 at the same time.

[0018] Optionally, the components added in step 3 include a Mux, eight Demuxes, an AXI-Lite receiver, and an AXI-Stream receiver.

[0019] Optionally, all working states of the finite state machine in step 4 include: a normal working state of reading sub-memory group A and writing sub-memory group B, a context switching state, and a working state after context switching, and a normal working state of reading sub-memory group B and writing sub-memory group A, a context switching state, and a working state after context switching;

[0020] The input data of the finite state machine includes: memory access signals from the Tile functional unit, AXI-Lite receiver data and AXI-Stream receiver data;

[0021] The memory access signals from the Tile functional unit include write enable wrEn_FU, write address wrAddr_FU, write data wrData_FU and read address rdAddr_FU;

[0022] The AXI-Lite receiver data includes the registers Reg_DRA and Reg_ADDR configured by the XI-Lite bus. The size of Reg_DRA is 1 bit, which is used to notify the finite state machine to perform dynamic resource allocation. The size of Reg_ADDR is 16 bits, which is used to specify the maximum address of the data written to the sub-memory group A2 and the sub-memory group B2 and processed under the new resource allocation decision.

[0023] The AXI-Stream receiver data includes write enable wrEn_MM, write address wrAddr_MM, and write data wrData_MM. The data written to sub-memory group A2 and sub-memory group B2 are received through the AXI-Stream bus. After decoding by the AXI-Stream receiver, the write enable wrEn_MM, write address wrAddr_MM, and write data wrData_MM are obtained.

[0024] Optionally, in step 4, sequential logic design of state transfer and state output and combinatorial logic design of state switching are performed, and described in PyMTL3 language, specifically including:

[0025] Step 4.1: When the finite state machine is in normal working state, the data of sub-memory group A1 is read and written into sub-memory group B1 at the same time. When dynamic resource allocation is triggered, the context switching state is entered;

[0026] Step 4.2: When the finite state machine is in the context switching state, the data of sub-memory group A1 is read and written into sub-memory group B1 and sub-memory group A2. When the written data reaches the preset value, the state after the context switching is entered;

[0027] Step 4.3: When the finite state machine is in the state after context switching, the data written to the sub-memory group A2 is read, and when the reading is completed, the reverse transmission state is entered;

[0028] Step 4.4: Repeat steps 4.1 to 4.4, read data from sub-memory group B, write data to sub-memory group A, and obtain the normal working state, context switching state, and working state after context switching of reading sub-memory group B and writing sub-memory group A.

[0029] Step 4.5: Infinitely loop step 4.1-step 4.4 to obtain the output of all states of the finite state machine.

[0030] Optionally, the outputs of the finite state machine in all states in step 4.5 include a mode signal of 8 bits, memory access signals for group A and group B, write enable wrEn_A / B, write address wrAddr_A / B, write data wrData_A / B, read address rdAddr_A / B, read data rdData_A / B, mode[15:0] and mode[17:16], wherein mode[15:0] is used to control eight Demux respectively, and direct the correct input signal to the correct sub-memory group according to the current state of the finite state machine, and mode[17:16] is used to control Mux.

[0031] The beneficial effects of the present invention are:

[0032] 1. With the support of the context switching-oriented embedded CGRA secondary memory design designed by the present invention, context switching will not cause stagnation of tasks, thereby improving task throughput.

[0033] 2. GEMVER, GESUMMV, and SYMM can achieve 15.8 times, 23.2 times, and 17.9 times throughput improvements after adopting the embedded CGRA secondary memory designed by the present invention for context switching. At the same time, within 5 input data after triggering resource allocation, an average resource allocation decision target throughput of more than 98.2% can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 A block diagram of the embedded CGRA multi-level memory design for context switching provided by the present invention;

[0035] Figure 2 The state transition diagram of the finite state machine provided by the present invention. DETAILED DESCRIPTION

[0036] Specific implementation method 1: In this implementation method, CGRA is a coarse-grained reconfigurable architecture.

[0037] Combination Figure 1-2 This embodiment is described. The steps of the embedded CGRA multi-level memory design method for context switching described in this embodiment include:

[0038] S1: Determine the basic CGRA hardware architecture based on actual multi-task requirements;

[0039] S101: Determine the basic CGRA hardware architecture, including determining the size of the CGRA processing unit array, the topological connection relationship between tiles, the size of the data memory and configuration memory in the tile, the complexity of the functional unit, and the number of registers.

[0040] S102: According to Figure 1The secondary memory architecture shown in the figure modifies the basic component library Mem provided by OpenCGRA, and adds AXI-Lite receiver, AXI-Stream receiver, Demux, Mux and other components through the PyMTL3 language;

[0041] S103: At the first level, the data memory is divided into two groups of sub-memories, memory group A and memory group B;

[0042] Due to the power consumption and area limitations of chips in embedded scenarios, the data memory size of each Tile is generally 1KB, which is difficult to store all the data required for task calculation, especially for tasks with streaming input such as satellite-borne target detection, access control, systems, urban pollution monitoring, etc. Therefore, Figure 1 As shown, this implementation method divides 1KB data memory into memory group A and memory group B, each of which is 512Bytes. Before CGRA runs, the first round of data is first written to memory group A. When CGRA runs, the first round of data is first read from memory group A to carry out calculations, and the second round of data is written to memory group B. When the first round of data in memory group A is read out, it can be directly switched to memory group B to read the second round of data, and the third round of data can be written to memory group A, alternating in sequence. By repeating the above alternating read and write operations, CGRA is able to continuously process streaming input data;

[0043] S104: At the second level, memory group A and memory group B are further divided into two groups of sub-memory, group 1 and group 2. The four groups of sub-memory, sub-memory group A1, sub-memory group A2, sub-memory group B1 and sub-memory group B2, have independent read and write signal lines, including write enable wrEn, write address wrAddr, write data wrData, read address rdAddr, and read data rdData, and perform read and write operations under the control of a finite state machine to hide the context switching delay.

[0044] When reading and writing data in memory group A and memory group B alternately, if dynamic resource allocation occurs, context switching will force task execution to stagnate. The task can continue to execute only after the corresponding data under the newly allocated resources is reloaded to the memory group A and memory group B of the correct tiles. To solve this problem, Figure 1As shown, this embodiment further divides group A and group B into memory group 1 and memory group 2, and makes the alternating read and write operations only for sub-memory group A1 and sub-memory group B1. When the context is switched during dynamic resource allocation, for example, the first round of data is being read from sub-memory group A1 and the second round of data is being written to sub-memory group B1 at the same time, the original operation will continue, and the remaining data of the first round of data that can be processed under the new resource allocation decision will be temporarily written to sub-memory group A2. After the writing is completed, the read operation for sub-memory group A1 will be switched to sub-memory group A2, and the written data will be processed under the new resource allocation decision. After the processing is completed, an alternating operation is performed to read the second round of data from sub-memory group B1 and write the third round of data to sub-memory group A1 at the same time. With the support of the above-mentioned secondary memory, context switching will not cause stagnation to the task, thereby improving the task throughput.

[0045] S2: According to Figure 2 The state transition diagram of the finite state machine shown in the figure is used to perform the sequential logic design of state transition and state output, as well as the combinational logic design of state switching, and is described in PyMTL3 language;

[0046] S201: The input of the finite state machine includes: (1) memory access signals from the independent routing network (FU), including write enable wrEn_FU, write address wrAddr_FU, write data wrData_FU, and read address rdAddr_FU; (2) registers Reg_DRA and Reg_ADDR configured by the AXI-Lite bus, where Reg_DRA is 1 bit in size and is used to notify the finite state machine of dynamic resource allocation, and Reg_ADDR is 16 bits in size and is used to specify the maximum address of data written to sub-memory group A2 or sub-memory group B2 that can be processed under the new resource allocation decision; (3) data written to sub-memory group A2 or sub-memory group B2 is received through the AXI-Stream bus, and the write enable wrEn_MM, write address wrAddr_MM, and write data wrData_MM are obtained after decoding by the receiver. The output of the finite state machine includes a mode signal of 18 bits, memory access signals for group A and group B, write enable wrEn_A / B, write address wrAddr_A / B, write data wrData_A / B, read address rdAddr_A / B and read data rdData_A / B; mode[15:0] is used to control eight Demux respectively, and guide the correct input signal to the correct sub-memory group according to the current state of the finite state machine. Mode[17:16] is used to control Mux, and select the output signal of the correct sub-memory group as the read result of the data memory according to the current state of the finite state machine.

[0047] S202: The state of the finite state machine is as follows: Figure 2 As shown, reset forces the state to IDLE, and the definition and jump logic of all states are as follows:

[0048] RA1_WB1: Normal working state, reading sub-memory group A1 and writing sub-memory group B1. When dynamic resource allocation is triggered (Reg_DRA=1'd1), enter RA1_WA2_WB1 state, otherwise maintain this state unchanged;

[0049] RA1_WA2_WB1: context switching state, continue to read sub-memory group A1 and write sub-memory group B1 at the same time, but write sub-memory group A2 at the same time. The write address wrAddr_A2 is generated by the counter incrementing by one. When the target write data amount (wrAddr_A2 = Reg_DRA) is reached, enter the RA2_WB1 state, otherwise maintain this state unchanged;

[0050] Enter RA2_WB1: Working state after context switching: read the data written to sub-memory A2. When the reading is completed, enter RB1_WA1 state, otherwise maintain the current state unchanged;

[0051] RB1_WA1, RB1_WB2_WA1, RB2_WA1: The meaning is similar to the above status, but read from memory group B and write to memory group A.

[0052] Through the above operations, the present invention can perform read and write operations under the control of a finite state machine, hiding context switching delays to avoid task stagnation during context switching, thereby improving task throughput.

[0053] Example

[0054] In order to verify the technical effect of the present invention, this embodiment adopts the following experimental settings:

[0055] (1) CGRA architecture: The size of the CGRA processing unit array is 16 times 16, with a total of 256 tiles. The data memory size of each tile is 1KB, the configuration memory size is 512Bytes, and the topology of the interconnection between tiles is "orthogonal + diagonal".

[0056] (2) Data-intensive tasks: Three computing tasks in the field of matrix multiplication were selected from the open source CGRA task set Polybench, namely, multi-matrix-vector multiplication (GEMVER), sum matrix-vector multiplication (GESUMMV), and symmetric matrix multiplication (SYMM).

[0057] (3) Resource allocation decision: Before resource allocation, the three tasks are equally divided into 16x16 CGRAs, and each is executed on 85 tiles. The resource allocation decision is that one task absorbs half of the resources from the other two tasks to improve its own throughput, that is, GEMVER, GESUMMV, and SYMM will be executed in 170 tiles in turn. The C language source code of the three tasks will be compiled through MLIR and LLVM, and pre-mapped under the above resource allocation decision for query during task execution.

[0058] Experimental results: Under the above experimental settings, GEMVER, GESUMMV, and SYMM can bring 15.8 times, 23.2 times, and 17.9 times throughput improvements after using secondary memory. At the same time, within 5 input data after triggering resource allocation, an average resource allocation decision target throughput of more than 98.2% can be achieved.

[0059] The above is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement made to the above embodiments without departing from the content of the technical solution of the present invention, based on the technical essence of the present invention, within the spirit and principles of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims

1. A context switching-oriented embedded CGRA secondary memory design method, characterized in that: The steps of the embedded CGRA secondary memory design method for context switching include: Step 1: Determine the basic CGRA hardware architecture based on actual multi-task requirements; Step 2: Using the open source CGRA modeling tool OpenCGRA, based on the selected basic CGRA hardware architecture, describe the CGRA hardware architecture using the PyMTL3 language; Step 3: Modify the basic component library Mem provided by OpenCGRA, add components through PyMTL3 language, complete the secondary design of data memory in each Tile, and obtain embedded CGRA; Step 4: Design the sequential logic of state transfer and state output and the combinational logic of state switching for all working states of the finite state machine in the CGRA in the secondary memory, and describe them in PyMTL3 language; Step 5: Use OpenCGRA to generate synthesizable Verilog code to implement alternate reading and writing of memory group data after context switching.

2. The context switching-oriented embedded CGRA secondary memory design method according to claim 1, characterized in that: The basic CGRA hardware architecture in step 1 includes: size, topological connection relationship between tiles, size of data memory and configuration memory within tiles, complexity of functional units, and number of registers.

3. The context switching-oriented embedded CGRA secondary memory design method according to claim 1, characterized in that: The description of the CGRA hardware architecture in step 2 specifically includes: Use the basic component library provided by the modeling tool to build the CGRA hardware architecture.

4. The method for designing an embedded CGRA secondary memory for context switching according to claim 1, characterized in that: The two-level design of the data memory in each tile in step 3 specifically includes a first-level memory and a second-level memory; The first-level memory design specifically includes: dividing the data memory into memory group A and memory group B, writing the first round of data to memory group A, reading the first round of data from memory group A to perform calculations when the embedded CGRA is running, and writing the second round of data to memory group B at the same time, when all the first round of data in memory group A is read out, directly switching to memory group B to read the second round of data, and writing the third round of data to memory group A, and repeating the above steps to perform alternating read and write operations; The second-level memory design specifically includes: dividing memory group A and memory group B into sub-memory group A1, sub-memory group A2, sub-memory group B1 and sub-memory group B2 respectively, so that the alternating read and write operations are only for sub-memory group A1 and sub-memory group B1. When the dynamic resource allocation performs context switching, the first round of data is read from sub-memory group A1 and the second round of data is written to sub-memory group B1 at the same time, and the remaining data of the first round of data that can be processed under the new resource allocation decision is temporarily written to sub-memory group A2. After the writing is completed, the read operation on sub-memory group A1 will be switched to sub-memory group A2, and the written data will be processed under the new resource allocation decision. After the processing is completed, an alternating operation is performed to read the second round of data from sub-memory group B1 and write the third round of data to sub-memory group A1 at the same time.

5. The method for designing an embedded CGRA secondary memory for context switching according to claim 1, characterized in that: The components added in step 3 include a Mux, eight Demuxes, an AXI-Lite receiver, and an AXI-Stream receiver.

6. The context switching-oriented embedded CGRA secondary memory design method according to claim 1, characterized in that: All working states of the finite state machine in step 4 include: a normal working state of reading sub-memory group A and writing sub-memory group B, a context switching state, a working state after context switching, and a normal working state of reading sub-memory group B and writing sub-memory group A, a context switching state, and a working state after context switching; The input data of the finite state machine includes: memory access signals from the Tile functional unit, AXI-Lite receiver data and AXI-Stream receiver data; The memory access signal from the Tile functional unit includes a write enable wrEn_FU, a write address wrAddr_FU, a write data wrData_FU and a read address rdAddr_FU; The AXI-Lite receiver data includes registers Reg_DRA and Reg_ADDR configured by the AXI-Lite bus, wherein the size of Reg_DRA is 1 bit and is used to notify the finite state machine to perform dynamic resource allocation, and the size of Reg_ADDR is 16 bits and is used to specify the maximum address of data written to the sub-memory group A2 and the sub-memory group B2 and processed under the new resource allocation decision; The AXI-Stream receiver data includes write enable wrEn_MM, write address wrAddr_MM, and write data wrData_MM. The data written to sub-memory group A2 and sub-memory group B2 are received through the AXI-Stream bus. After decoding by the AXI-Stream receiver, write enable wrEn_MM, write address wrAddr_MM, and write data wrData_MM are obtained.

7. The method for designing an embedded CGRA secondary memory for context switching according to claim 1, characterized in that: In step 4, the sequential logic design of state transfer and state output and the combinatorial logic design of state switching are performed, and described in PyMTL3 language, including: Step 4.1: When the finite state machine is in normal working state, the data of sub-memory group A1 is read and written into sub-memory group B1 at the same time. When dynamic resource allocation is triggered, the context switching state is entered; Step 4.2: When the finite state machine is in the context switching state, the data of sub-memory group A1 is read and written into sub-memory group B1 and sub-memory group A2. When the written data reaches the preset value, the state after the context switching is entered; Step 4.3: When the finite state machine is in the state after context switching, the data written to the sub-memory group A2 is read, and when the reading is completed, the reverse transmission state is entered; Step 4.4: Repeat steps 4.1 to 4.4, read data from sub-memory group B, write data to sub-memory group A, and obtain the normal working status, context switching status, and working status after context switching of reading sub-memory group B and writing sub-memory group A. Step 4.5: Infinitely loop step 4.1-step 4.4 to obtain the output of the finite state machine in all states.

8. The context switching-oriented embedded CGRA secondary memory design method according to claim 7, characterized in that: The outputs of the finite state machine in all states in step 4.5 include a mode signal of 8 bits, memory access signals for group A and group B, write enable wrEn_A / B, write address wrAddr_A / B, write data wrData_A / B, read address rdAddr_A / B, read data rdData_A / B, mode[15:0] and mode[17:16]. The mode[15:0] is used to control eight Demux respectively, and direct the correct input signal to the correct sub-memory group according to the current state of the finite state machine. The mode[17:16] is used to control Mux.

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