PCIE device, method for accelerating enumeration of PCIE device, electronic device and storage medium
By using identification data to identify available registers in the configuration space of the PCIE device, the problem of long PCIE device enumeration time in the prior art is solved, and the effect of accelerating enumeration and reducing system startup time is achieved.
Patent Information
- Application Number
- CN202411422004.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-11
- Publication Date
- 2025-01-21
AI Technical Summary
When the existing PCIE device enumeration method has a large number of devices, the system startup time is long.
By using identification data in the configuration space of the PCIE device, including multiple register usage status identifications, available registers are identified and unavailable registers are avoided from being detected.
Accelerated the lift process of the PCIE device and reduced the start time of the system.
Smart Images
Figure CN119336690A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of computer technology, and in particular to a PCIE device, a method for accelerating the enumeration of a PCIE device, an electronic device and a storage medium. Background Art
[0002] In modern computer systems, PCI-Express (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard that is widely used between various electronic devices to achieve fast data transmission. During the system startup process of an electronic device, firmware such as BIOS (Basic Input Output System) or UEFI (Unified Extensible Firmware Interface) is responsible for enumerating and initializing PCIE devices to ensure that the system can identify and correctly configure these devices. Among them, the firmware needs to allocate a target address of the corresponding bit width size from the system's available PCIE address space to the PCIE device so that the electronic device system can communicate with the PCIE device through the target address.
[0003] Currently, the enumeration method of PCIE devices includes performing a detection process on all registers in the configuration space of each PCIE device, and the detection process includes the steps of reading the type and address bit width of the register, writing all 1s to the register, and reading the register again to determine the bit width of the target address that needs to be allocated.
[0004] However, when the number of PCIE devices is large, the system startup time is often long. For example, for a full topology PCIE structure, there are 65536 devices in total, and a total of 458752 registers need to be detected. The enumeration process of PCIE devices consumes a lot of time, which greatly increases the system startup time. Summary of the invention
[0005] In view of the deficiencies in the prior art, the present application provides a PCIE device, a method for accelerating the enumeration of PCIE devices, an electronic device and a storage medium. By including identification data of multiple register usage status identifiers, the register usage status identifiers correspond one-to-one to the registers to be identified, and the available registers in the PCIE device can be identified according to the identification data, without detecting the unavailable registers in the PCIE device, and the enumeration of the PCIE device can be accelerated, thereby reducing the system startup time.
[0006] To solve the above problems, the present invention provides the following technical solutions:
[0007] In a first aspect, an embodiment of the present application provides a PCIE device, the PCIE device comprising a configuration space, the configuration space comprising a plurality of registers to be identified and a configuration register, the configuration register comprising identification data, the identification data comprising a plurality of register usage status identifiers, the register usage status identifiers corresponding one-to-one to the registers to be identified;
[0008] When the register use status identifier is a first preset identifier, the register use status identifier indicates that the corresponding register is an available register;
[0009] When the register use status identifier is a second preset identifier, the register use status identifier indicates that the corresponding register is an unavailable register.
[0010] In some implementations, the identification data further includes a plurality of register address bit width identifiers, the register address bit width identifiers correspond one-to-one to the available registers, and the register address bit width identifiers are used to indicate the bit width of the target address to be allocated to the corresponding register.
[0011] In some implementations, the identification data further includes a ROM register existence status identification, and the ROM register existence status identification is used to indicate whether a ROM register exists in the configuration space.
[0012] In some implementations, the identification data further includes a pointer to an address where the identification data of the next PCIE device is located.
[0013] In a second aspect, an embodiment of the present application provides a method for accelerating enumeration of PCIE devices, which is applied to an electronic device, wherein the electronic device includes at least one PCIE device according to any one of claims 1 to 4, and the method includes:
[0014] When enumerating the PCIE device, reading identification data in the configuration space of the PCIE device, the identification data being used to identify whether each register to be identified in the PCIE device is available;
[0015] Identify available registers in the PCIE device according to the identification data;
[0016] The bit width of the target address to which each of the available registers needs to be allocated is determined.
[0017] In some implementations, the identification data further includes a plurality of register address bit width identifiers, the register address bit width identifiers correspond one-to-one to the available registers, and identifying the available registers in the PCIE device according to the identification data includes:
[0018] When the register address bit width identifier indicates that the address bit width of the corresponding available register is the first preset bit width, the next register of the currently available register determined according to the preset recognition order is identified as the available register.
[0019] In some implementations, the identification data further includes a plurality of register address bit width identifiers, the register address bit width identifiers correspond one-to-one to the available registers, and determining the bit width of the target address to be allocated to each of the available registers includes:
[0020] For each of the available registers, the bit width of the target address to be allocated to the available register is determined according to a preset value of a register address bit width identifier corresponding to the available register.
[0021] In some implementations, the identification data further includes a pointer to an address where the identification data of the next PCIE device is located. After determining the bit width of the target address to be allocated to each of the available registers, the method further includes:
[0022] The identification data of the next PCIE device is read from the address pointed to by the pointer of the current identification data.
[0023] In a third aspect, an embodiment of the present application provides an electronic device, the electronic device comprising:
[0024] at least one processor; and,
[0025] a memory communicatively connected to the at least one processor; wherein,
[0026] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the method for accelerating the enumeration of PCIE devices as described in the second aspect.
[0027] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores an executable program, and the executable program is executed by a processor to implement the method for accelerating the enumeration of PCIE devices as described in the second aspect.
[0028] The present application provides a PCIE device, a method for accelerating the enumeration of a PCIE device, an electronic device, and a storage medium. The present application includes a plurality of register usage status identifiers through identification data, and the register usage status identifiers correspond one-to-one to the registers to be identified. The available registers in the PCIE device can be identified according to the identification data, and there is no need to detect unavailable registers in the PCIE device. The enumeration of the PCIE device can be accelerated, thereby reducing the system startup time. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] Figure 1 It is a structural diagram of the PCIE device provided in an embodiment of the present application.
[0030] Figure 2 It is a schematic diagram of the structure of the identification data provided in the embodiment of the present application.
[0031] Figure 3 It is a flowchart of a method for accelerating the enumeration of PCIE devices provided in an embodiment of the present application.
[0032] Figure 4 It is a structural schematic diagram of an electronic device provided in an embodiment of the present application.
[0033] Figure 5 It is a structural block diagram of a computer-readable storage medium provided in an embodiment of the present application. DETAILED DESCRIPTION
[0034] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0035] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.
[0036] The present application provides a PCIE device, a method for accelerating the enumeration of a PCIE device, an electronic device, and a storage medium. By including identification data with a plurality of register usage status identifiers, the register usage status identifiers correspond one-to-one to the registers to be identified, and the available registers in the PCIE device can be identified according to the identification data, without detecting the unavailable registers in the PCIE device, and the enumeration of the PCIE device can be accelerated, thereby reducing the system startup time.
[0037] The PCIE device provided by the present application will be described in detail below with reference to the accompanying drawings.
[0038] See also Figure 1 , Figure 1 Schematic diagram of the structure of the PCIE device provided in the embodiment of the present application. Figure 1As shown, in some implementations, a PCIE device 1 (such as a PCIe endpoint device) includes a configuration space 10, the configuration space 10 includes a plurality of registers 11 to be identified and a configuration register 12, and the configuration register 12 includes identification data.
[0039] Optionally, the configuration space 10 also includes other registers.
[0040] Optionally, the number of registers to be identified is more than 2, for example, 2, 3, 4, 5, 6 or 7, etc.
[0041] In some implementations, the plurality of registers to be identified include six BAR (Base Address Register) registers. The BAR registers are used to store a target address so that the PCIE device communicates with the processor through the target address.
[0042] Optionally, the multiple registers to be identified further include a ROM (Read-Only Memory) register. The ROM register can also be used to store the target address.
[0043] like Figure 1 As shown, in some embodiments, each register 11 to be identified has a unique number. For example, register 111 is numbered 1, register 112 is numbered 2, register 113 is numbered 3, register 114 is numbered 4, register 115 is numbered 5, register 116 is numbered 6, and register 117 is numbered 7. Registers 111, 112, 113, 114, 115, and 116 are BAR registers, and register 117 is a ROM register.
[0044] In some implementations, the identification data includes a plurality of register usage status identifications, and the register usage status identifications correspond one-to-one to the registers to be identified.
[0045] In some implementations, the identification data further includes a plurality of register address bit width identifiers, the register address bit width identifiers correspond one-to-one to available registers, and the register address bit width identifiers are used to indicate the bit width of the target address to be allocated to the corresponding register.
[0046] See also Figure 2 , Figure 2 is a schematic diagram of the structure of the identification data provided in the embodiment of the present application. Figure 2As shown, in some embodiments, the identification data 120 includes a plurality of register attribute identifiers 123, each register attribute identifier 123 includes a register usage status identifier 1231 and a register address bit width identifier 1232, and the register attribute identifier 123 corresponds to the register to be identified one by one. The register usage status identifier 1231 and the register address bit width identifier 1232 included in a register attribute identifier 123 correspond to the same register.
[0047] Optionally, the register usage status identifier 1231 occupies one bit, and the register address bit width identifier 1232 occupies one bit.
[0048] In some implementations, when the register usage status identifier is a first preset identifier, the register usage status identifier indicates that the corresponding register is an available register.
[0049] Optionally, the value of the first preset identifier is 1 or 0.
[0050] In some implementations, when the register usage status identifier is a second preset identifier, the register usage status identifier indicates that the corresponding register is an unavailable register.
[0051] Optionally, when the value of the first preset identifier is 1, the value of the second preset identifier is 0. When the value of the first preset identifier is 0, the value of the second preset identifier is 1.
[0052] In some implementations, when the register address bit width identifier is the third preset identifier, the register address bit width identifier indicates that the bit width of the target address that needs to be allocated to the corresponding register is the first preset bit width.
[0053] Optionally, the value of the third preset identifier is 1 or 0.
[0054] Optionally, the first preset bit width is 64 bits.
[0055] In some implementations, when the register address bit width identifier is the fourth preset identifier, the register address bit width identifier indicates that the bit width of the target address that needs to be allocated to the corresponding register is the second preset bit width.
[0056] Optionally, when the value of the third preset identifier is 1, the value of the fourth preset identifier is 0. When the value of the third preset identifier is 0, the value of the fourth preset identifier is 1.
[0057] Optionally, the second preset bit width is different from the first preset bit width.
[0058] Optionally, the second preset bit width is 32 bits.
[0059] In some implementations, the register usage status flag and the register address bit width flag in the identification data are set according to a preset rule.
[0060] like Figure 2 As shown, in some embodiments, in the identification data 120, multiple register attribute identifications 123 are arranged from low bits to high bits according to the numbering order of the corresponding registers from small to large, and in each register attribute identification 123, the register usage status identification 1231 is located at the low bit, and the register address bit width identification 1232 is located at the high bit. For example, the register attribute identification 123A corresponds to the register 111, the register attribute identification 123B corresponds to the register 112, the register attribute identification 123C corresponds to the register 113, the register attribute identification 123D corresponds to the register 114, the register attribute identification 123E corresponds to the register 115, the register attribute identification 123F corresponds to the register 116, and the register attribute identification 123G corresponds to the register 117. The register usage status identification 1231 in the register attribute identification 123A is located at the low bit, and the register address bit width identification 1232 is located at the high bit, and the same is true for other register attribute identifications.
[0061] In some implementations, in the identification data, multiple register attribute identifications are arranged from low bits to high bits in the order of the corresponding register numbers from large to small.
[0062] In some implementations, in each register attribute identifier, the register usage status identifier is located at a high bit position, and the register address bit width identifier is located at a low bit position.
[0063] In some implementations, when the register usage status flag indicates that the corresponding register is an unavailable register, the flag data does not include a register address bit width flag corresponding to the register.
[0064] In some implementations, when the register usage status flag indicates that the corresponding register is an unavailable register, the flag data also includes a register address bit width flag corresponding to the register, but the register address bit width flag does not need to be read.
[0065] like Figure 2 As shown, in some implementations, the identification data 120 also includes a function usage identification 121 .
[0066] In some implementations, when the function usage status identifier is the fifth preset identifier, the step of identifying the available registers in the PCIE device according to the identifier file is executed; otherwise, the step of identifying the available registers in the PCIE device according to the identifier file is not executed, but a detection process is performed once for all registers to be identified in the configuration space of each PCIE device. In this way, the user can be provided with the option of not using the identifier data, thereby meeting different usage requirements.
[0067] like Figure 2 As shown, optionally, the function usage status identifier 121 occupies one bit.
[0068] Optionally, the value of the fifth preset identifier is 1 or 0.
[0069] like Figure 2 As shown, in some implementations, the identification data 120 further includes a ROM register existence status identification 122 , and the ROM register existence status identification 122 is used to indicate whether a ROM register exists in the configuration space 10 .
[0070] In some implementations, when the ROM register existence status flag is a sixth preset flag, the ROM register existence status flag indicates that the ROM register exists in the configuration space, otherwise it indicates that the ROM register does not exist in the configuration space.
[0071] Optionally, the ROM register existence status flag 122 occupies one bit.
[0072] Optionally, the value of the sixth preset identifier is 1 or 0.
[0073] In some embodiments, when the ROM register existence status flag indicates that the ROM register exists in the configuration space, the identification data also includes a register usage status flag corresponding to the ROM register. When the register usage status flag corresponding to the ROM register indicates that the ROM register is an available register, the identification data also includes a register address bit width flag corresponding to the ROM register.
[0074] like Figure 2 As shown, in some embodiments, when the ROM register existence status identifier 122 indicates that a ROM register exists in the configuration space 10, the identification data 120 also includes a register attribute identifier 123G, and the register attribute identifier 123G includes a register usage status identifier and a register address bit width identifier corresponding to the ROM register.
[0075] In some implementations, the electronic device includes a plurality of PCIE devices, and therefore identification data of the plurality of PCIE devices needs to be read.
[0076] like Figure 2As shown, in some implementations, the identification data also includes a pointer 124 pointing to the address where the identification data of the next PCIE device is located.
[0077] like Figure 2 As shown, optionally, the pointer 124 occupies 8 bits.
[0078] Optionally, the address where the identification data of the next PCIE device is located is the address where the identification data of the current PCIE device is located plus a preset address offset.
[0079] Optionally, the preset address offset is 4Kb.
[0080] like Figure 2 As shown, in some embodiments, the identification data further includes an identification ID 125 uniquely corresponding to the identification data. The identification ID 125 is used to distinguish different identification data.
[0081] Optionally, identification ID125 occupies 8 bits.
[0082] like Figure 2 As shown, in some implementations, the identification data also includes a reserved field, and the reserved field is used to expand the function of the identification data.
[0083] Optionally, the reserved field is all 0s.
[0084] The present application also provides a method for accelerating the enumeration of PCIE devices, which is applied to an electronic device, and the electronic device includes at least one PCIE device as described above.
[0085] See also Figure 3 , Figure 3 1 is a flow chart of a method for accelerating the enumeration of PCIE devices provided in an embodiment of the present application. Figure 3 As shown, the method for accelerating the enumeration of PCIE devices includes: steps S100 to S300.
[0086] Step S100: when enumerating PCIE devices, reading identification data in the configuration space of the PCIE devices.
[0087] Optionally, the identification data is used to identify whether each register to be identified in the PCIE device is available.
[0088] Please refer to the above description for the content of the identification data, which will not be repeated here.
[0089] In some implementations, when the identification data includes a function usage status identifier, the function usage status identifier in the identification data is first read. When the function usage status identifier is the fifth preset identifier, step S200 is continued to be executed, otherwise step S200 is not executed, but a detection process is performed once for all registers to be identified in the configuration space of each PCIE device.
[0090] Step S200: Identify available registers in the PCIE device according to the identification data.
[0091] As described above, in some embodiments, the identification data further includes multiple register address width identifiers, and the register address width identifiers correspond to available registers one by one. In this way, there is no need to detect unavailable registers in the PCIE device, which can speed up the enumeration of the PCIE device, thereby reducing the system startup time.
[0092] In some embodiments, step S200 includes step (200.1) to step (200.2).
[0093] (200.1) Read the ROM register existence status flag, and determine whether the ROM register exists in the configuration space according to the ROM register existence status flag.
[0094] In some implementations, when the ROM register existence status flag is a sixth preset flag, it is determined that the ROM register exists in the configuration space; otherwise, it is determined that the ROM register does not exist in the configuration space.
[0095] (200.2) Read the register usage status identifier according to a preset reading order, and identify whether the register corresponding to each register usage status identifier is an available register.
[0096] In some implementations, multiple register attribute identifiers are read in a reading order from low bits to high bits. When reading each register attribute identifier, the register usage status identifier in the register attribute identifier is read first, and then the register address bit width identifier is read.
[0097] like Figure 2 As shown, illustratively, register attribute identification 123A, register attribute identification 123B, register attribute identification 123C, register attribute identification 123D, register attribute identification 123E and register attribute identification 123F are read in sequence from low bits to high bits.
[0098] In some implementations, when it is determined that a ROM register exists in the configuration space, the register usage status identifier corresponding to the ROM register is read, for example, the register usage status identifier in the register attribute identifier 123G is read.
[0099] In some implementations, when the register usage status identifier is a first preset identifier, the register corresponding to the register usage status identifier is identified as an available register. Optionally, at this time, the register address bit width identifier corresponding to the available register is first read, and then the next register usage status identifier is read according to a preset reading order.
[0100] Exemplarily, when the register usage status identifier 1231 in the register attribute identifier 123A is the first preset identifier, the register address bit width identifier 1232 in the register attribute identifier 123A is read first, and then the register usage status identifier in the register attribute identifier 123B is read.
[0101] In some embodiments, when the register address width identifier indicates that the address width of the corresponding available register is the first preset width, the next register of the currently available register determined according to the preset recognition order is identified as an available register. In this way, when the register address width identifier indicates that the address width of the corresponding available register is the first preset width, the next register does not need to be identified, which can further speed up the enumeration of PCIE devices and reduce system startup time.
[0102] Optionally, the first preset bit width is 64 bits.
[0103] In some embodiments, when the bit width of the target address exceeds the bit width of the address that can be stored in one register, at least two registers are required to store the target address. For example, if the bit width of the address that can be stored in one register is 32 bits, when the bit width of the target address corresponding to the currently available register is 64 bits, two registers are required to store the target address. Therefore, the next register is also an available register. At this time, the register usage status flag corresponding to the next register can be directly read according to the preset reading order to directly identify the next register.
[0104] Optionally, the preset identification order is the ascending numbering order of the registers. For example, the identification order is to identify register 111, register 112, register 113, register 114, register 115, register 116 and register 117 in sequence.
[0105] Optionally, the preset identification order is a descending numbering order of the registers.
[0106] In some implementations, when the register usage status identifier is the second preset identifier, the register corresponding to the register usage status identifier is identified as an unavailable register. Optionally, at this time, the next register usage status identifier may be directly read according to a preset reading order.
[0107] Step S300: Determine the bit width of the target address to be allocated to each available register.
[0108] In some implementations, a detection process is performed once for each available register, thereby determining the bit width of the target address to be allocated to each available register. In this way, the original operation process in the electronic device does not need to be changed, and the compatibility of the method can be improved.
[0109] In some implementations, for each available register, the bit width of the target address to be allocated to the available register is determined according to the preset value of the register address bit width identifier corresponding to the available register. In this way, there is no need to perform a detection process for each available register, which can further speed up the enumeration of PCIE devices, thereby reducing the system startup time.
[0110] In some implementations, when the register address bit width identifier is a value of a third preset identifier, the register address bit width identifier indicates that the bit width of the target address to be allocated to the corresponding register is the first preset bit width.
[0111] Optionally, the value of the third preset identifier is 1 or 0.
[0112] In some implementations, when the register address bit width identifier is the fourth preset identifier, the register address bit width identifier indicates that the bit width of the target address that needs to be allocated to the corresponding register is the second preset bit width.
[0113] Optionally, when the value of the third preset identifier is 1, the value of the fourth preset identifier is 0. When the value of the third preset identifier is 0, the value of the fourth preset identifier is 1.
[0114] Optionally, the second preset bit width is 32 bits.
[0115] In some embodiments, when the register address bit width identifier indicates that the address bit width of the corresponding available register is a first preset bit width, the next register of the currently available register determined according to a preset identification order is identified as an available register, and the bit width of the target address to be assigned to the next register is also determined to be the first preset bit width.
[0116] Optionally, the first preset bit width is 64 bits.
[0117] Optionally, the electronic device allocates the lower 32 bits of a 64-bit target address to a currently available register, and allocates the upper 32 bits of the target address to a register next to the currently available register.
[0118] In some embodiments, there is a read-only bit in the register. The electronic device allocates the target address of the corresponding bit width of the register to the register according to the 4K alignment rule, and the values of the target address in the read-only bit are all 0. After reading the target address in the register, the electronic device sets all the read-only bits in the read address to 0. In this way, it can be ensured that the target address stored in the register is completely consistent with the address obtained by reading the register, so that the electronic device can communicate normally with the PCIE device through the target address.
[0119] As described above, in some implementations, the identification data further includes a pointer to the address where the identification data of the next PCIE device is located.
[0120] In some embodiments, after determining the bit width of the target address to be allocated to each available register, the method further includes: reading the identification data of the next PCIE device from the address pointed to by the pointer of the current identification data. In this way, the next PCIE device can be operated immediately after the operation on the current PCIE device is completed, which can further speed up the enumeration of PCIE devices, thereby further reducing the system startup time.
[0121] In summary, the PCIE device and the method for accelerating the enumeration of PCIE devices provided in the embodiments of the present application include the following advantages:
[0122] 1. The identification data includes multiple register usage status identifications, and the register usage status identifications correspond to the registers to be identified one by one. The available registers in the PCIE device can be identified according to the identification data, and the unavailable registers in the PCIE device do not need to be detected. The enumeration of the PCIE device can be accelerated, thereby reducing the system startup time.
[0123] 2. The identification data also includes multiple register address bit width identifiers, and the register address bit width identifiers correspond to the available registers one by one. The bit width of the target address to be allocated to the available register can be determined according to the preset value of the register address bit width identifier corresponding to the available register. There is no need to perform a detection process for each available register, which can further accelerate the enumeration of PCIE devices, thereby reducing the system startup time.
[0124] 3. By including the functional usage identification in the identification data, the user can be provided with the option of not using the identification data, thereby meeting different usage requirements.
[0125] 4. When the register address bit width identifier indicates that the address bit width of the corresponding available register is the first preset bit width, the next register of the currently available register determined according to the preset recognition order is identified as an available register. At this time, there is no need to identify the next register, which can further accelerate the enumeration of PCIE devices and reduce the system startup time.
[0126] See also Figure 4 , Figure 4 Schematic diagram of the structure of an electronic device provided in an embodiment of the present application. Figure 4 As shown, the electronic device 400 includes: one or more processors 410 and a memory 420, Figure 4 A processor 410 is taken as an example.
[0127] In some implementations, the processor 410 and the memory 420 may be connected via a bus or other means. Figure 4 The example of connecting through bus is taken in the following.
[0128] In some embodiments, the processor 410 is used to read identification data in the configuration space of the PCIE device when enumerating the PCIE device, the identification data being used to identify whether each register to be identified in the PCIE device is available; identify the available registers in the PCIE device according to the identification data; and determine the bit width of the target address to be assigned to each available register.
[0129] In some embodiments, the memory 420, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer executable programs and modules, such as program instructions / modules of the method for accelerating the enumeration of PCIE devices in the embodiment of the present application. The processor 410 executes various functional applications and data processing of the electronic device 400 by running the non-volatile software programs, instructions and modules stored in the memory 420, that is, the method for accelerating the enumeration of PCIE devices in the above method embodiment is implemented.
[0130] In some embodiments, the memory 420 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the electronic device 400, etc. In addition, the memory 420 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory 420 may optionally include a memory remotely arranged relative to the processor 410, and these remote memories may be connected to the controller via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.
[0131] In some embodiments, one or more modules are stored in the memory 420, and when executed by one or more processors 410, the method of accelerating the enumeration of PCIE devices in any of the above method embodiments is executed, for example, the method described above is executed. Figure 3 The method comprises steps S100 to S300.
[0132] In some embodiments, the electronic device may be a chip. Preferably, the chip may be a data processor (Data Processing Unit, DPU) chip used in a data center.
[0133] In some embodiments, the electronic device may be a network interface card, which includes a chip as described in the foregoing embodiments and multiple interfaces (eg, a PCI E interface, a PCI interface, and a USB interface, etc.), and the chip communicates externally through the interface.
[0134] In some embodiments, the electronic device may be a server used in a data center, the server including a central processing unit and a chip as described in the foregoing embodiments, the chip being used to dispatch messages to the central processing unit or the chip itself for processing, and the central processing unit being used to process messages dispatched by the data processor.
[0135] Please refer to Figure 5 , Figure 5 The computer-readable storage medium 500 stores a program code 510, which can be called by a processor to execute the method for accelerating the enumeration of PCIE devices described in the above method embodiment.
[0136] The computer-readable storage medium 500 may be an electronic memory such as a flash memory, an EEPROM (electrically erasable programmable read-only memory), an EPROM, a hard disk, or a ROM. Optionally, the computer-readable storage medium includes a non-volatile computer-readable medium (non transitory computer readable storage medium). The computer-readable storage medium 500 has storage space for program codes that execute any method steps in the above-mentioned method for accelerating the enumeration of PCIE devices. These program codes can be read from or written to one or more computer program products. The program code can be compressed, for example, in an appropriate form.
[0137] In some implementations, the embodiments of the present application further provide a computer program product, including a computer program, which implements the above-mentioned method of accelerating the enumeration of PCIE devices when executed by a processor.
[0138] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a computer-readable storage medium 500. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memory. Non-volatile memory may include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory may include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited thereto. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited thereto.
[0139] In summary, the present application provides a PCIE device, a method for accelerating the enumeration of a PCIE device, an electronic device, and a storage medium, wherein the PCIE device includes a configuration space, the configuration space includes a plurality of registers to be identified and a configuration register, the configuration register includes identification data, the identification data includes a plurality of register usage status identifiers, the register usage status identifiers correspond one-to-one with the registers to be identified; when the register usage status identifier is a first preset identifier, the register usage status identifier indicates that the corresponding register is an available register; when the register usage status identifier is a second preset identifier, the register usage status identifier indicates that the corresponding register is an unavailable register. The present application includes a plurality of register usage status identifiers through identification data, and the register usage status identifiers correspond one-to-one with the registers to be identified, and can identify the available registers in the PCIE device according to the identification data, without detecting the unavailable registers in the PCIE device, and can accelerate the enumeration of the PCIE device, thereby reducing the system startup time.
[0140] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.
Claims
1. A PCIE device, characterized in that: The PCIE device includes a configuration space, the configuration space includes a plurality of registers to be identified and a configuration register, the configuration register includes identification data, the identification data includes a plurality of register usage status identifiers, and the register usage status identifiers correspond one to one to the registers to be identified; When the register use status identifier is a first preset identifier, the register use status identifier indicates that the corresponding register is an available register; When the register use status identifier is a second preset identifier, the register use status identifier indicates that the corresponding register is an unavailable register.
2. The PCIE device according to claim 1, characterized in that: The identification data further includes a plurality of register address bit width identifiers, the register address bit width identifiers correspond one-to-one to the available registers, and the register address bit width identifiers are used to indicate the bit width of the target address to be allocated to the corresponding register.
3. The PCIE device according to claim 1 or 2, characterized in that: The identification data also includes a ROM register existence status identification, and the ROM register existence status identification is used to indicate whether there is a ROM register in the configuration space.
4. The PCIE device according to claim 1, characterized in that: The identification data also includes a pointer pointing to the address where the identification data of the next PCIE device is located.
5. A method for accelerating the enumeration of PCIE devices, characterized in that: Applied to an electronic device, the electronic device includes at least one PCIE device according to any one of claims 1 to 4, and the method includes: When enumerating the PCIE device, reading identification data in the configuration space of the PCIE device, the identification data being used to identify whether each register to be identified in the PCIE device is available; Identify available registers in the PCIE device according to the identification data; The bit width of the target address to which each of the available registers needs to be allocated is determined.
6. The method for accelerating enumeration of PCIE devices according to claim 5, characterized in that: The identification data further includes a plurality of register address bit width identifiers, the register address bit width identifiers correspond one-to-one to the available registers, and the identifying the available registers in the PCIE device according to the identification data includes: When the register address bit width identifier indicates that the address bit width of the corresponding available register is the first preset bit width, the next register of the currently available register determined according to the preset recognition order is identified as the available register.
7. The method for accelerating enumeration of PCIE devices according to claim 5, characterized in that: The identification data further includes a plurality of register address bit width identifiers, the register address bit width identifiers correspond one-to-one to the available registers, and the determining the bit width of the target address to be allocated to each of the available registers includes: For each of the available registers, the bit width of the target address to be allocated to the available register is determined according to a preset value of a register address bit width identifier corresponding to the available register.
8. The method for accelerating enumeration of PCIE devices according to any one of claims 5 to 7, characterized in that: The identification data also includes a pointer to an address where the identification data of the next PCIE device is located. After determining the bit width of the target address to be allocated to each of the available registers, the method further includes: The identification data of the next PCIE device is read from the address pointed to by the pointer of the current identification data.
9. An electronic device, characterized in that: The electronic device comprises: at least one processor; and, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the method for accelerating the enumeration of PCIE devices as described in any one of claims 5 to 8.
10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores an executable program, and the executable program is executed by a processor to implement the method for accelerating the enumeration of PCIE devices as described in any one of claims 5 to 8.