Processor and correction method for data transmission between chips of processor

Abstract

The present application relates to a processor and a correction method for data transmission between cores of the processor. Based on the present application, any of the at least two cores packaged by the processor may include an analog receiving circuit and a logic sorting circuit. Among them, the analog receiving circuit can sample and obtain multiple data fragment sequences that are transmitted in parallel to the core by other cores through multiple physical layer channels respectively; the analog receiving circuit can also use analog correction to perform offset correction on data fragment sequences with data misalignment and offset during sampling, so as to enable multiple data fragment sequences to be sampled in parallel in an aligned state; even if the offset correction of any data fragment sequence by analog correction leaves residual correction offset, the correction residual offset can be eliminated by performing shift sorting on the data fragment sequence by the logic sorting circuit using logic correction. Thus, the correct communication data packet can be obtained by reorganizing the data of the aligned multiple data fragment sequences.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and in particular to a processor and a method for correcting data transmission between chips of the processor. Background Art

[0002] Chiplet technology can regard an integrated circuit die as a chip, and can package at least two chips into a processor, for example, a SoC (System-on-Chip) processor. Among them, a processor packaged with at least two chips can be called a multi-chip processor, and compared with a processor that only packages one integrated circuit die, a processor that packages at least two chips has higher integration and computing power.

[0003] Communication data packets can be transmitted between any two cores in the processor. Any core that is the sender of the communication data packet can split the communication data packet into multiple data fragment sequences, and transmit the multiple data fragment sequences in parallel to another core that is the receiver through multiple physical layer channels. Accordingly, any core that is the receiver can sample multiple data fragment sequences transmitted in parallel through multiple physical layer channels, and if multiple aligned data fragment sequences can be sampled, then the communication data packet of the sender can be restored by reorganizing the aligned multiple data fragment sequences.

[0004] However, the parallel transmission of multiple data fragment sequences on multiple physical layer channels may cause data misalignment due to certain factors at the physical layer. In this case, the core particle as the receiving party cannot restore the communication data packet by data reassembly.

[0005] As can be seen above, there may be a risk that communication data packets cannot be correctly transmitted between cores in the processor, resulting in low reliability of data transmission between cores of the processor. Therefore, how to improve the reliability of data transmission between cores of the processor has become a technical problem to be solved. Summary of the invention

[0006] Embodiments of the present application provide a processor and a method for correcting data transmission between chiplets of the processor, which are helpful to improve the reliability of data transmission between chiplets of the processor.

[0007] In one embodiment of the present application, a processor is provided, wherein at least two core particles are encapsulated in the processor, the at least two core particles are interconnected via a plurality of physical layer channels, and any one of the at least two core particles that is a receiver of a communication data packet includes an analog receiving circuit and a logic sorting circuit;

[0008] The analog receiving circuit is used to perform parallel sampling based on analog deskew on the multiple data slice sequences transmitted in parallel by the multiple physical layer channels; wherein the analog deskew is used to perform offset correction on the data slice sequence having data misalignment offset relative to the reference reference in any physical layer channel during the process of obtaining the multiple data slice sequences from the multiple physical layer channels through the parallel sampling;

[0009] The logic sorting circuit is used for: if a data slice sequence obtained from any physical layer channel still has a correction residual offset relative to the reference datum after the offset correction of the analog correction, then digital correction is performed on the data slice sequence with the correction residual offset; wherein the digital correction is used to align the data slice sequence with the reference datum through shift sorting.

[0010] In some examples, optionally, the parallel sampling generates multiple sampling slice sequences corresponding to the multiple physical layer channels respectively, the sampling slice sequence corresponding to each physical layer channel of the multiple physical layer channels is aligned with the reference datum, and the correction residual offset includes: a slice misalignment offset between a data slice sequence and a sampling slice sequence corresponding to the same physical layer channel; the digital correction of any data slice sequence with the correction residual offset includes: shifting and arranging the sampling slice sequence corresponding to the same physical layer channel as the data slice sequence.

[0011] In some examples, optionally, if there is a slice misalignment offset caused by the correction residual offset between the data slice sequence and the sampling slice sequence corresponding to the same physical layer channel, then any data slice in the data slice sequence is distributed across slices among adjacent sampling slices in the sampling slice sequence corresponding to the same physical layer channel as the data slice sequence; the digital correction shifts and arranges the sampling slice sequence corresponding to the same physical layer channel as any data slice sequence, including: performing cross-slice shift and arrangement on the adjacent sampling slices in the sampling slice sequence.

[0012] In some examples, optionally, the digital deskew arranges the cross-slice shift of the adjacent sampling slices in any sampling slice sequence, including: shifting and integrating the fragments of the cross-slice distribution of the adjacent sampling slices in the sampling slice sequence of the same data slice into a sampling slice located at the front end of the adjacent sampling slices.

[0013] In some examples, optionally, any data slice sequence is transmitted sequentially through the corresponding physical layer channels among the multiple physical layer channels; the parallel sampling includes: performing continuous periodic sampling on the corresponding data slice sequence transmitted sequentially through each physical layer channel among the multiple physical layer channels; wherein each sampling slice in the sampling slice sequence corresponding to any physical layer channel is generated sequentially in a continuous unit sampling period; the logic sorting circuit is used for: if the data slice sequence obtained from any physical layer channel has the correction residual offset, then, caching each sampling slice generated sequentially in the sampling slice sequence corresponding to the same physical layer channel as the data slice sequence slice by slice; wherein the adjacent sampling slices include: a sampling slice currently cached, and a sampling slice cached before the sampling slice; and a sampling slice located at the front end of the adjacent sampling slices is the first sampling slice cached among the adjacent sampling slices.

[0014] In some examples, optionally, the slice length of the sampling slice is an integer multiple of the slice length of the data slice.

[0015] In some examples, optionally, the adjacent sampling slices having the same data slice distributed across the slices include two consecutive sampling slices.

[0016] In some examples, optionally, the analog receiving circuit is also used to: perform the parallel sampling of the test fragment sequences transmitted in parallel on the multiple physical layer channels respectively before performing the parallel sampling on the multiple data fragment sequences transmitted in parallel on the multiple physical layer channels; the logic sorting circuit is also used to: verify the analog deskew using the test fragment sequences obtained from the multiple physical layer channels through the parallel sampling before the analog receiving circuit performs the parallel sampling on the multiple data fragment sequences transmitted in parallel on the multiple physical layer channels; wherein the verification of the analog deskew includes: detecting whether the test fragment sequences obtained from the multiple physical layer channels have the correction residual offset remaining after the offset correction by the analog deskew; and activating or deactivating the digital deskew using the verification result of the analog deskew; wherein, if the verification result indicates that the test fragment sequence obtained from any physical layer channel has the correction residual offset, then the digital deskew is activated; and if the verification result indicates that the test fragment sequence obtained from each physical layer channel does not have the correction residual offset, then the digital deskew is deactivated.

[0017] In some examples, optionally, verification of the analog deskew using the test segment sequence occurs during a transmission idle period after parameter training of the analog receiving circuit is completed; wherein the parameter training is used to configure circuit parameters of the analog receiving circuit, and the correction amplitude and correction direction of the offset correction of the analog deskew are determined by the circuit parameters.

[0018] In some examples, optionally, the verification of the simulated deskew using the test fragment sequence occurs during a transmission idle period of the multiple physical layer channels.

[0019] In some examples, optionally, the logic sorting circuit is also used to: obtain a sequence calibration pattern of the test slice sequence before verifying the analog deskew; wherein the sequence calibration pattern is used to characterize the standard numerical arrangement of the test slice sequence when aligned with the reference datum; the verification of the analog deskew by the logic sorting circuit includes: comparing the test slice sequence obtained from the multiple physical layer channels through the parallel sampling with the sequence calibration pattern; wherein the offset between the test slice sequence obtained through the parallel sampling and the sequence calibration pattern is used to characterize the correction residual offset.

[0020] In some examples, optionally, the test slice sequence includes a plurality of identical test slices arranged consecutively, the test slices include a plurality of binary data bits, the values ​​of the plurality of binary data bits are not all the same, and the different data values ​​of the plurality of binary data bits adopt a non-uniformly staggered numerical distribution in the test slices.

[0021] In some examples, optionally, the multiple data fragmentation sequences are obtained by splitting the communication data packet from the communication data packet by the coreparticle that is the sender of the communication data packet among the at least two coreparticles before parallel transmission; the multiple data fragmentation sequences are used to restore the communication data packet by the coreparticle that is the receiver of the communication data packet among the at least two coreparticles through data reorganization after the parallel sampling while aligning with the reference benchmark; and the digital deskew occurs before the data reorganization is performed.

[0022] In another embodiment of the present application, a method for correcting data transmission between cores of a processor is provided, wherein at least two cores are encapsulated in the processor; the at least two cores are interconnected through a plurality of physical layer channels; any one of the at least two cores that is a receiver of a communication data packet comprises an analog receiving circuit, the analog receiving circuit is used to perform parallel sampling based on analog correction on a plurality of data fragment sequences transmitted in parallel by the plurality of physical layer channels, and the analog correction is used to perform offset correction on a data fragment sequence in any physical layer channel that has a data misalignment offset relative to the reference reference in the process of obtaining the plurality of data fragment sequences from the plurality of physical layer channels through the parallel sampling;

[0023] The correction method comprises the following steps performed by the corelet of the at least two corelets that is the receiver of the communication data packet:

[0024] Acquire sampling results of the analog receiving circuit for the multiple data slices; wherein the data slice sequence obtained from any physical layer channel in the sampling results has a correction residual offset relative to the reference reference after the offset correction by the analog deskew;

[0025] Digital deskew is performed on the data slice sequence with the correction residual offset; wherein the digital deskew is used to align the data slice sequence with the correction residual offset with the reference datum through shift arrangement in the sampling result.

[0026] In some examples, optionally, the sampling results of the multiple data slices by the analog receiving circuit include: multiple sampling slice sequences corresponding to the multiple physical layer channels respectively; wherein the sampling slice sequence corresponding to each physical layer channel of the multiple physical layer channels is aligned with the reference datum, and the correction residual offset includes: the slice misalignment offset between the data slice sequence and the sampling slice sequence corresponding to the same physical layer channel; the digital correction of the data slice sequence with the correction residual offset includes: shifting and arranging the sampling slice sequence corresponding to the same physical layer channel as the data slice sequence with the correction residual offset.

[0027] In some examples, optionally, if there is a slice misalignment offset caused by the correction residual offset between the data slice sequence and the sampling slice sequence corresponding to the same physical layer channel, then any data slice in the data slice sequence is distributed across slices among adjacent sampling slices in the sampling slice sequence corresponding to the same physical layer channel as the data slice sequence; the shifting and arranging of the sampling slice sequence corresponding to the same physical layer channel as the data slice sequence with the correction residual offset includes: in the sampling slice sequence corresponding to the same physical layer channel as the data slice sequence with the correction residual offset, shifting and arranging the adjacent sampling slices having the same data slice distributed across slices across slices.

[0028] In some examples, optionally, in the sampling slice sequence corresponding to the same physical layer channel of the data slice sequence with the corrected residual offset, the adjacent sampling slices having the same data slice distributed across slices are shifted and sorted across slices, including: shifting and integrating the slice fragments of the adjacent sampling slices of the same data slice distributed across slices in the sampling slice sequence into a sampling slice at the front end of the adjacent sampling slices.

[0029] In some examples, optionally, any data slice sequence is transmitted sequentially through the corresponding physical layer channels among the multiple physical layer channels; the parallel sampling includes: performing continuous periodic sampling on the corresponding data slice sequence transmitted sequentially through each physical layer channel among the multiple physical layer channels; wherein each sampling slice in the sampling slice sequence corresponding to any physical layer channel is generated sequentially in a continuous unit sampling period; the correction method also includes: caching each sampling slice generated sequentially in the sampling slice sequence corresponding to the same physical layer channel as the data slice sequence slice by slice; wherein the adjacent sampling slices include: a sampling slice currently cached, and a sampling slice cached before the sampling slice; and a sampling slice located at the front end of the adjacent sampling slices is the first sampling slice cached among the adjacent sampling slices.

[0030] In some examples, optionally, the analog receiving circuit is also used to: perform the parallel sampling on the test slice sequences transmitted in parallel on the multiple physical layer channels respectively before performing the parallel sampling on the multiple data slice sequences transmitted in parallel on the multiple physical layer channels; the correction method also includes: before the analog receiving circuit performs the parallel sampling on the multiple data slice sequences transmitted in parallel on the multiple physical layer channels: using the test slice sequences obtained from the multiple physical layer channels through the parallel sampling to verify the analog correction; wherein the verification of the analog correction includes: detecting whether the test slice sequences obtained from the multiple physical layer channels have the correction residual offset remaining after the offset correction of the analog correction; and, the verification result of the analog correction is used to predict whether the sampling result includes a data slice sequence with the correction residual offset.

[0031] Based on the above-mentioned embodiments of the present application, any of the at least two cores of the processor package may include an analog receiving circuit and a logic sorting circuit. Among them, the analog receiving circuit can obtain multiple data fragment sequences transmitted in parallel to the core by other cores through multiple physical layer channels through parallel sampling of multiple physical layer channels; in the process of obtaining multiple data fragment sequences through parallel sampling, the analog receiving circuit can use analog deflection correction to implement offset correction on any data fragment sequence with data misalignment offset, so as to enable multiple data fragment sequences to be sampled in parallel in an aligned state with an alignment reference benchmark; even if the offset correction of any data fragment sequence by analog deflection correction leaves a residual correction offset relative to the reference benchmark, the logical sorting circuit can implement shift sorting on the data fragment sequence using logical deflection correction to eliminate the residual correction offset of the data fragment sequence. Based on the deflection correction method with the offset correction of analog deflection correction as the main method and the shift sorting of digital deflection correction as the supplement, it is possible to enable multiple data fragment sequences obtained by any core through parallel sampling to be aligned with the reference benchmark used to achieve data reorganization, thereby obtaining a correct communication data packet through data reorganization. Furthermore, it helps to improve the reliability of data transmission between processor chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The following drawings are only used to illustrate and explain the present application, and do not limit the scope of the present application:

[0033] Figure 1 A schematic diagram of the inter-chiplet transmission principle in the processor according to an embodiment of the present application;

[0034] Figure 2 A schematic diagram of a core particle simulation correction principle in a processor according to an embodiment of the present application;

[0035] Figure 3A schematic diagram of a first failure example of core simulation correction in a processor according to an embodiment of the present application;

[0036] Figure 4 A schematic diagram of a second failure example of core simulation correction in a processor according to an embodiment of the present application;

[0037] Figure 5 A schematic diagram of a digital deflection correction principle of a chip in a processor according to an embodiment of the present application;

[0038] Figure 6 A schematic diagram of a first correction example of a chip digital correction in a processor according to an embodiment of the present application;

[0039] Figure 7 A schematic diagram of a second correction example of the digital correction of the core in the processor according to an embodiment of the present application;

[0040] Figure 8 A schematic diagram of a first slice data structure of a test slice sequence for verifying chip simulation correction in a processor according to an embodiment of the present application;

[0041] Fig. 9 A schematic diagram of a second slice data structure of a test slice sequence for verifying chip simulation correction in a processor according to an embodiment of the present application;

[0042] Fig.10 The present invention is a schematic diagram of an exemplary flow chart of a method for correcting the deviation of data between chiplets of a processor in an embodiment of the present application. DETAILED DESCRIPTION

[0043] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below with reference to the accompanying drawings and examples.

[0044] Figure 1 Schematic diagram of the inter-chiplet transmission principle in the processor of the embodiment of the present application. Figure 1 In an embodiment of the present application, at least two core particles may be encapsulated in a processor, and any two core particles may be interconnected through a plurality of physical layer channels Lane_1 to Lane_n (n is a positive integer greater than or equal to 2), and the plurality of physical layer channels Lane_1 to Lane_n (n is a positive integer greater than or equal to 2) are used to realize parallel data transmission between the two core particles.

[0045] Exemplarily, in the embodiments of the present application, the processor may refer to any device with processing capability, for example, the processor may be any one of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), an NPU (Neural Network Processing Unit), a DPU (Deep Learning Processing Unit), an APU (Accelerated Processing Unit), and a GPGPU (General-Purpose computing on Graphics Processing Units). The examples given here are merely for the purpose of facilitating the understanding of the meaning of the processor involved in the embodiments of the present application, and are not intended to impose unnecessary restrictions on the type of processor.

[0046] For example, in the graphical representation of the embodiment of the present application, any two core particles interconnected by multiple physical layer channels Lane_1 to Lane_n in the processor are respectively represented by core particle i and core particle j (i and j are different positive integers). Core particle i can generally refer to a data sender transmitted in parallel through multiple physical layer channels Lane_1 to Lane_n, and core particle j can generally refer to a receiver of a communication data packet transmitted in parallel through multiple physical layer channels Lane_1 to Lane_n.

[0047] Exemplarily, in an embodiment of the present application, multiple physical layer channels Lane_1~Lane_n may be duplex or half-duplex channels, and the roles of data senders and receivers of communication data packets of any two cores in the processor may change according to the transmission direction.

[0048] For example, in an embodiment of the present application, data parallel transmission between chiplets i and chiplets j in a processor through multiple physical layer channels Lane_1 to Lane_n can be implemented based on the UCIe (Universal chiplet interconnectexpress) protocol. In this case, the number of channels n of the multiple physical layer channels Lane_1 to Lane_n can be 16, 32, or 64.

[0049] Exemplarily, in an embodiment of the present application, the communication data packet provided by the core i of the data sender may include protocol layer data, and the communication data packet provided by the core i of the data sender may be mapped from the protocol layer to the physical layer where multiple physical layer channels Lane_1~Lane_n are located. For example, the protocol layer data packet may include the operation data of the HSIO (Host System Interface Output) controller, and the protocol layer data packet may be mapped from the protocol layer to the physical layer where multiple physical layer channels Lane_1~Lane_n are located, packet by packet, in units of flits (lightweight packets).

[0050] Exemplarily, in an embodiment of the present application, a communication data packet provided by a core i of a data sender may be split into multiple data fragment sequences {B1}~{Bn}. For example, each flit (lightweight packet) in the communication data packet may be split into multiple data fragment sequences {B1}~{Bn} and mapped to the physical layer; the multiple data fragment sequences {B1}~{Bn} mapped to the physical layer may be respectively transmitted in parallel to a core j of a receiver of the communication data packet through corresponding multiple physical layer channels Lane_1~Lane_n; and, the multiple data fragment sequences {B1}~{Bn} are used to restore the communication data packet by the core j of the receiver of the communication data packet through data reorganization when the reference datum is aligned.

[0051] Exemplarily, in an embodiment of the present application, a communication data packet may be divided into a slice matrix of m×n data slices, and a plurality of data slice sequences {B1}~{Bn} may respectively include a corresponding column of data slices in the n columns of data slices. Wherein, m is a positive integer greater than or equal to 1. For example, if a flit packet is divided into m×n data slices, then m may be determined according to the data volume of the flit packet, the number of channels n of the plurality of physical layer channels Lane_1~Lane_n, and the slice length of the data slice.

[0052] Exemplarily, in an embodiment of the present application, the slice lengths of each data slice in the multiple data slice sequences {B1}~{Bn} obtained by dividing the communication data packet may be the same, and the slice transmission duration of each data slice in the corresponding physical layer channel Lane_k (k is a positive integer greater than or equal to 1 and less than or equal to n) is the same, that is, the slice transmission duration of each data slice in the corresponding physical layer channel Lane_k is a set number t_data UI (Unit Interval). For example, the slice length of each data slice may be one Byte, and one data bit of each data slice may occupy one UI in the transmission of the corresponding physical layer channel Lane_k, and the slice transmission duration of each data slice in the corresponding physical layer channel Lane_k is 8 (that is, the set number t_data is 8) UI.

[0053] For example, in the embodiments of the present application, due to the parallel transmission of multiple data fragment sequences {B1}~{Bn} in multiple physical layer channels Lane_1~Lane_n, there may be data misalignment and offset. Therefore, the embodiments of the present application attempt to provide a correction function for the physical layer sampling of the core j of the receiver of the communication data packet, so as to enable multiple data fragment sequences {B1}~{Bn} with data misalignment and offset to be sampled in parallel in an aligned state.

[0054] Figure 2 Schematic diagram of the core simulation correction principle in the processor of the embodiment of the present application. Figure 2 In an embodiment of the present application, any core j in the processor that can serve as a receiver of a communication data packet may include an analog receiving circuit, which is used to perform parallel sampling based on analog correction on multiple data fragment sequences transmitted in parallel on multiple physical layer channels Lane_1~Lane_n.

[0055] Exemplarily, in an embodiment of the present application, the analog receiving circuit may include a PMA (Physical Media Attachment).

[0056] Exemplarily, in an embodiment of the present application, as described above, before parallel transmission, multiple data fragment sequences {B1}~{Bn} are obtained by splitting the communication data packet from the core i which is different from the sender of the communication data packet; and after the multiple data fragment sequences {B1}~{Bn} are acquired by the core j which is the receiver through parallel transmission and parallel sampling, they can be used to restore the communication data packet by the core j which is the receiver through data reorganization in the case of aligning the reference datum. Therefore, the analog deskew implemented by the analog receiving circuit is used to: in the process of obtaining multiple data fragment sequences {B1}~{Bn} from multiple physical layer channels Lane_1~Lane_n through parallel sampling, offset correction is performed on the data fragment sequence {Bk} in any physical layer channel Lane_k which has data misalignment offset relative to the reference datum.

[0057] Exemplarily, in an embodiment of the present application, the analog deflection function of the analog receiving circuit can be configured by the circuit parameters of the analog receiving circuit. For example, the correction amplitude and correction direction of the offset correction of the analog deflection correction can be determined by the circuit parameters of the analog receiving circuit, and the circuit parameters of the analog receiving circuit can be configured by a parameter training process.

[0058] Exemplarily, in an embodiment of the present application, analog deskew can utilize Per-Lane-Deskew technology to calibrate the actual channel data capture time of the analog receiving circuit at the physical layer for the corresponding data fragment sequence {Bk} transmitted in any physical layer channel Lane_k.

[0059] Exemplarily, in an embodiment of the present application, relative to the actual capture time of the channel data at the physical layer, the reference benchmark can be considered as the reference time of the logical layer. Based on the Per-Lane-Deskew technology, the same reference time of the logical layer can be mapped at the physical layer to the actual capture time of the channel data that allows differences between multiple physical layer channels Lane_1~Lane_n, and the difference can be used to compensate for the delay difference of multiple physical layer channels Lane_1~Lane_n during parallel transmission. Therefore, by associating the mapping of the actual capture time of the channel data that allows differences at the physical layer with the same reference time of the logical layer, it can be facilitated that multiple data fragment sequences {B1}~{Bn} obtained from multiple physical layer channels Lane_1~Lane_n through parallel sampling are aligned with the reference time represented by the reference benchmark at the logical layer.

[0060] Exemplarily, in an embodiment of the present application, the reference reference may be represented by a reference reference signal Sig_align received by an analog receiving circuit, and at least one of a rising edge and a falling edge of the reference reference signal Sig_align may be used to represent the reference time of the logic layer. For example, the reference reference signal Sig_align may use a Valid signal, and the Valid signal is used to represent whether the data currently transmitted in the multiple physical layer channels Lane_1 to Lane_n is valid data that should be sampled.

[0061] Based on the above-mentioned embodiments of the present application, in the process of obtaining multiple data fragment sequences {B1}~{Bn} through parallel sampling, the analog receiving circuit of the core j as the receiver of the communication data packet can use analog deskew to perform offset correction on any data fragment sequence with data misalignment and offset, thereby enabling multiple data fragment sequences {B1}~{Bn} to be sampled in parallel by the core j as the receiver of the communication data packet in an aligned state of an alignment reference benchmark, and further, it can help the core j as the receiver of the communication data packet to obtain the correct communication data packet through data reorganization.

[0062] For example, in an embodiment of the present application, the analog deskew implemented based on the circuit parameter configuration may have the risk of deskew failure, and the higher the transmission rate of the parallel transmission of multiple physical layer channels Lane_1~Lane_n, the higher the risk of deskew failure. For example, the offset correction of the analog deskew implemented by the Per-Lane-Deskew technology is limited. If the data misalignment offset of the data segment sequence {Bk} transmitted in any physical layer channel Lane_k exceeds the maximum amplitude of the offset correction of the analog deskew, then even if the same reference time of the reference reference at the logical layer can be mapped to the actual capture time of the channel data with differences at the physical layer, the analog deskew of the analog receiving circuit will still have deskew failure for the data segment sequence {Bk} of the physical layer channel Lane_k.

[0063] Exemplarily, in an embodiment of the present application, the failure of the analog deskew of the analog receiving circuit may result in: after the data fragment sequence {Bk} obtained by the analog receiving circuit from any physical layer channel Lane_k is offset-corrected by the analog deskew, there is still a correction residual offset relative to the reference datum, for example, the correction residual offset may be greater than or equal to 1 UI and less than the set number of UIs t_data occupied by a single data fragment. Thus, any data fragment sequence {Bk} with a correction residual offset cannot be aligned with other data fragment sequences, thereby causing multiple data fragment sequences {B1}~{Bn} to be unable to perform data reorganization in a state of aligning with the reference datum, and further, the correction residual offset still causes the core particle j as the receiver of the communication data packet to be unable to restore the communication data packet provided by the core particle i of the data sender through data reorganization.

[0064] Figure 3 This is a schematic diagram of a first failure example of the chip simulation correction in the processor of the embodiment of the present application. Figure 3 As shown, among the multiple data slice sequences {B1}-{Bn} sampled by the analog receiving circuit, the data slice sequence {B2} is shifted forward relative to the reference datum, and the data slice sequence {B2} has a correction residual offset with an offset of 1 UI.

[0065] Figure 4 This is a schematic diagram of a second failure example of the chip simulation correction in the processor of the embodiment of the present application. Figure 4 As shown, among the multiple data slice sequences {B1}-{Bn} sampled by the analog receiving circuit, the data slice sequence {B2} is offset backward relative to the reference datum, and the data slice sequence {B2} has a correction residual offset of 2 UI.

[0066] For example, in an embodiment of the present application, if the analog deflection correction of the analog receiving circuit fails, you can try to retrain the parameters of the analog receiving circuit to repair it. Each parameter retraining (Retrain) takes about "hundreds of milliseconds". Alternatively, it is possible that the failure of deflection correction cannot be repaired even after repeating the parameter training several times. To this end, any core j in the processor of the embodiment of the present application that can serve as the receiver of the communication data packet may also include a logic sorting circuit.

[0067] Illustratively, in an embodiment of the present application, the logic sorting circuit may include NPL (Near pad logic), and the NPL of the logic sorting circuit and the PMA of the analog receiving circuit both belong to the physical layer.

[0068] Exemplarily, in an embodiment of the present application, the logic sorting circuit of core j can be used for: if the data segment sequence {Bk} obtained from any physical layer channel Lane_k still has a correction residual offset relative to a reference benchmark after the offset correction by the analog correction of the analog receiving circuit, then there is no need to re-train the parameters of the analog receiving circuit, and digital correction can be implemented on any data segment sequence {Bk} with a correction residual offset.

[0069] Exemplarily, in an embodiment of the present application, the logic sorting circuit of the core particle j performs digital correction on any data segment sequence {Bk} with a correction residual offset, which can occur before the core particle j uses multiple data segment sequences {B1}~{Bn} obtained by parallel sampling to reorganize data.

[0070] Figure 5 This is a schematic diagram of the digital correction principle of the core in the processor of the embodiment of the present application. Figure 5 Taking any data segment sequence {Bk} including {B2} with correction residual offset as an example, the digital correction implemented by the logic sorting circuit of core particle j can be used to: align any data segment sequence {Bk} with correction residual offset with the reference benchmark during data reorganization through shift sorting.

[0071] Based on the above-mentioned embodiments of the present application, even if the analog deskew of the analog receiving circuit corrects the offset of any data segment sequence {Bk}, and a correction residual offset relative to the reference benchmark remains, the correction residual offset of the data segment sequence {Bk} can be eliminated by the logic sorting circuit using logic deskew to perform shift sorting on the data segment sequence {Bk}. Therefore, based on the deskew method that mainly uses the offset correction of analog deskew and supplemented by the shift sorting of digital deskew, it is possible to cause multiple data segment sequences obtained by parallel sampling of any core particle j to be aligned with the reference benchmark used to achieve data reorganization, thereby obtaining the correct communication data packet through data reorganization. Furthermore, it helps to improve the reliability of data transmission between core particles of the processor.

[0072] Figure 6 Schematic diagram of a first correction example of chip digital correction in the processor according to an embodiment of the present application. Figure 7 This is a schematic diagram of a second correction example of the digital correction of the core in the processor of the embodiment of the present application. Figure 6 and Figure 7 In the embodiment of the present application, the parallel sampling of the analog receiving circuit can generate multiple sampling slice sequences corresponding to multiple physical layer channels Lane_1~Lane_n respectively. Among them, each sampling slice in the sampling slice sequence corresponding to any physical layer channel Lane_k is in a continuous unit sampling period (such as Figure 3 and Figure 4The sampling slice sequences corresponding to each physical layer channel Lane_k of the multiple physical layer channels Lane_1~Lane_n are aligned with the reference datum.

[0073] Exemplarily, in an embodiment of the present application, the core j as the receiver of the communication data packet may also include a data reorganization circuit for performing data reorganization using the sampling results of parallel sampling of multiple data fragment sequences {B1}~{Bn} (i.e., multiple groups of sampling fragments corresponding to multiple physical layer channels Lane_1~Lane_n, respectively).

[0074] Exemplarily, in an embodiment of the present application, the correction residual offset of the data slice sequence {Bk} obtained from any physical layer channel Lane_k may include: the slice misalignment offset between the data slice sequence {Bk} and the sampling slice sequence corresponding to the same physical layer channel Lane_k. Figure 6 The correction residual offset is shown in Figure 3 The fragment misalignment caused by the forward offset shown in the figure. Figure 7 The correction residual offset is shown in Figure 4 The backward offset case shown results in the misalignment of the fragments.

[0075] For example, in the embodiment of the present application, the slice length of the sampling slice generated by the analog receiving circuit may be an integer multiple of the slice length of the data slice (for example, Figure 3 2 times as shown or Figure 4 1 times as shown), that is, the slice transmission duration of the sampling slice can be a set number t_sp UI, and t_sp can be an integer multiple of t_data (for example, 2 times or 1 times).

[0076] Exemplarily, in an embodiment of the present application, the digital deflection of any data slice sequence {Bk} having a correction residual offset by a logic sorting circuit may include: shifting and sorting the sampling slice sequence corresponding to the same physical layer channel Lane_k as the data slice sequence {Bk}.

[0077] Exemplarily, in an embodiment of the present application, if there is a slice misalignment offset caused by the correction residual offset between the data slice sequence {Bk} and the sampling slice sequence corresponding to the same physical layer channel Lane_k, then, Figure 6 and Figure 7 As shown, no matter the case of forward offset or backward offset, any data slice in the data slice sequence {Bk} will be distributed across adjacent sampling slices in the sampling slice sequence of the same physical layer channel Lane_k corresponding to the data slice sequence {Bk}.

[0078] Exemplarily, in an embodiment of the present application, if there is a slice misalignment offset caused by the correction residual offset between the data slice sequence {Bk} and the sampling slice sequence corresponding to the same physical layer channel Lane_k, then any data slice in the data slice sequence {Bk} is distributed across slices between two adjacent sampling slices in the sampling slice sequence of the same physical layer channel Lane_k corresponding to the data slice sequence {Bk}.

[0079] Exemplarily, in an embodiment of the present application, when the logic sorting circuit implements digital correction on any data slice sequence {Bk} with a correction residual offset, the shift sorting of the sampling slice sequence corresponding to the same physical layer channel Lane_k as the data slice sequence {Bk} may include: performing cross-slice shift sorting on adjacent sampling slices (for example, two adjacent sampling slices) in the sampling slice sequence.

[0080] Exemplarily, in an embodiment of the present application, when the logic sorting circuit implements digital deskew on any data slice sequence {Bk} with a correction residual offset, the cross-slice shift sorting of adjacent sampling slices (for example, two adjacent sampling slices) in the sampling slice sequence corresponding to the same physical layer channel Lane_k as the data slice sequence {Bk} includes: shifting and integrating the cross-slice distribution of adjacent sampling slices (for example, two adjacent sampling slices) of the same data slice in the sampling slice sequence to a sampling slice located at the front end of the adjacent sampling slices (for example, two adjacent sampling slices) where the slice is located.

[0081] Exemplarily, in an embodiment of the present application, as described above, any data slice sequence {Bk} is sequentially transmitted through the corresponding physical layer channel Lane_k, and the parallel sampling of the analog receiving circuit can perform continuous periodic sampling on the corresponding data slice sequence {Bk} sequentially transmitted by each physical layer channel Lane_k, and each sampling slice in the sampling slice sequence corresponding to any physical layer channel Lane_k is sequentially generated in a continuous unit sampling period. In this case, if the data slice sequence {Bk} obtained from any physical layer channel Lane_k has the corrected residual offset, then, as Figure 6 and Figure 7 As shown, the logic sorting circuit can also be used to cache each sampling slice sequentially generated in the sampling slice sequence corresponding to the same physical layer channel Lane_k as the data slice sequence {Bk}.

[0082] Exemplarily, in an embodiment of the present application, if each sampling slice generated sequentially in a sampling slice sequence is cached slice by slice, then when the logic sorting circuit performs cross-slice shift sorting on adjacent sampling slices (for example, two adjacent sampling slices) in a sampling slice sequence corresponding to the same physical layer channel Lane_k as an arbitrary data slice sequence {Bk}, each group of adjacent sampling slices (for example, two adjacent sampling slices) may include: a sampling slice currently cached, and a sampling slice cached before the sampling slice, and a sampling slice located at the front end of the adjacent sampling slices (for example, two adjacent sampling slices) is the sampling slice that is cached first among the adjacent sampling slices (for example, two adjacent sampling slices).

[0083] For example, in the embodiments of the present application, Figure 6 As shown, assuming that the data slice sequence {Bk} (for example, {B2}) is shifted forward by p UIs due to the correction of the residual offset compared to the sampling slice sequence corresponding to the same physical layer channel Lane_k, p is a positive integer greater than or equal to 1 and less than the set number t_data (for example, 8). Then, when the slice fragments of adjacent sampling slices (for example, two adjacent sampling slices) of the same data slice in the sampling slice sequence are shifted and integrated to the frontmost sampling slice, the slice value Bk_aligned[t_sp-1:0] of the frontmost sampling slice after being assigned values ​​across slices can be as shown in expression (1):

[0084] Bk_aligned[t_sp-1:0]={ Bk_cur [t_sp-1-p:0], Bk_delay[p-1:0]}

[0085] Among them, Bk_cur[] represents the value of the current cached sampling slice during cross-slice sorting, t_sp-1 represents the highest bit of the sampling slice, and Bk_delay[] represents the cached value of the frontmost sampling slice before being assigned a value by cross-slice sorting.

[0086] For example, in Figure 6 In the example, the length of the sampling slice is twice the length of the data slice (ie, t_sp = t_data × 2 = 16), and p is 1. Then, expression (1) can be expressed as:

[0087] Bk_aligned[15:0]={ Bk_cur [14:0], Bk_delay[0]}

[0088] For example, in the embodiments of the present application, Figure 7As shown, it is assumed that the data slice sequence {Bk} (for example, {B2}) is offset backward by q UIs due to the correction of residual offset compared to the sampling slice sequence corresponding to the same physical layer channel Lane_k, where q is a positive integer greater than or equal to 1 and less than the set number t_data (for example, 8) ( Figure 7 In the example, q is 2. Then, when the segment fragments of adjacent sampling slices (for example, two adjacent sampling slices) of the same data slice in the sampling slice sequence are shifted and integrated to the frontmost sampling slice, the slice value Bk_aligned[t_sp-1:0] of the frontmost sampling slice after being arranged and assigned across slices can be as shown in expression (2):

[0089] Bk_aligned[t_sp-1:0]={ Bk_delay[q-1:0], Bk_cur [t_sp-1-q:0]}

[0090] Among them, Bk_cur[] represents the value of the current cached sampling slice during cross-slice sorting, t_sp-1 represents the highest bit of the sampling slice, and Bk_delay[] represents the cached value of the frontmost sampling slice before being assigned a value by cross-slice sorting.

[0091] For example, in Figure 7 In the example, the lengths of the sampling slice and the data slice are the same (i.e., t_sp=t_data=8), and q is 2. Then, expression (2) can be expressed as:

[0092] Bk_aligned[7:0]={ Bk_delay[1:0], Bk_cur[5:0]}

[0093] Exemplarily, in an embodiment of the present application, the digital deskew of the logic sorting circuit of core j can be activated only when a correction residual offset exists in the data segment sequence {Bk} obtained from any physical layer channel Lane_k through parallel sampling, and can be deactivated when no correction residual offset exists in the data segment sequences {B1}~{Bn} respectively obtained from multiple physical layer channels Lane_1~Lane_n through parallel sampling.

[0094] Exemplarily, in an embodiment of the present application, the logic sorting circuit of core j can verify the analog deskew of the analog receiving circuit to predict whether there will be correction residual offset in the data segment sequences {B1}~{Bn} to be obtained from multiple physical layer channels Lane_1~Lane_n respectively through parallel sampling.

[0095] Exemplarily, in an embodiment of the present application, the analog receiving circuit of core particle j can also be used for: before performing parallel sampling based on analog deskew on multiple data fragment sequences {B1}~{Bn} transmitted in parallel on multiple physical layer channels Lane_1~Lane_n, performing parallel sampling based on analog deskew on a test fragment sequence transmitted in parallel on each physical layer channel in the multiple physical layer channels Lane_1~Lane_n; wherein the test fragment sequence cyclically transmitted on each physical layer channel in the multiple physical layer channels Lane_1~Lane_n can be initiated by core particle i which is the data sender of the multiple data fragment sequences {B1}~{Bn}.

[0096] Exemplarily, in an embodiment of the present application, the logic arrangement circuit of the core particle j may also be used before the analog receiving circuit performs parallel sampling based on analog de-skew on a plurality of data fragment sequences {B1}~{Bn} transmitted in parallel by a plurality of physical layer channels Lane_1~Lane_n:

[0097] Verify the analog deskew of the analog receiving circuit by using a test slice sequence obtained from multiple physical layer channels Lane_1 to Lane_n through parallel sampling based on analog deskew; wherein the verification of the analog deskew of the analog receiving circuit may include: detecting whether the test slice sequence obtained from the multiple physical layer channels Lane_1 to Lane_n has a correction residual offset remaining after the offset correction of the analog deskew;

[0098] Utilize the verification result of analog deskew of the analog receiving circuit to activate or deactivate digital deskew; wherein, if the verification result indicates that the test slice sequence obtained from any physical layer channel Lane_k has a correction residual offset, then it can be predicted that the data slice sequence {Bk} that the analog receiving circuit is about to sample from the physical layer channel Lane_k will have a correction residual offset, and thus the digital deskew can be activated; if the verification result indicates that the test slice sequence obtained from each physical layer channel Lane_k does not have the correction residual offset, then it can be predicted that the data slice sequences {B1}~{Bn} that the analog receiving circuit is about to obtain from multiple physical layer channels Lane_1~Lane_n through parallel sampling will not have a correction residual offset, and thus the digital deskew can be deactivated.

[0099] Exemplarily, in an embodiment of the present application, the verification of the analog deskew of the analog receiving circuit using the test slice sequence may occur in a transmission idle period after the training of the parameters of the analog receiving circuit is completed. Alternatively, the verification of the analog deskew of the analog receiving circuit using the test slice sequence may also occur in a transmission idle period of multiple physical layer channels Lane_1 to Lane_n.

[0100] Exemplarily, in an embodiment of the present application, the logic sorting circuit of core particle j can also be used to: obtain a sequence calibration pattern of the test slice sequence before verifying the analog deskew of the analog receiving circuit; wherein the sequence calibration pattern is used to characterize the standard numerical arrangement of the test slice sequence when it is aligned with the reference datum, and the sequence calibration pattern can also be provided by core particle i as the data sender of multiple data slice sequences {B1}~{Bn}, and the sequence calibration pattern can be obtained from core particle i through any fidelity transmission method. In this case, the verification of the analog deskew of the analog receiving circuit by the logic sorting circuit of core particle j may include: comparing the test slice sequence obtained from multiple physical layer channels Lane_1~Lane_n through parallel sampling based on analog deskew with the sequence calibration pattern; wherein the offset from any physical layer channel Lane_k and the sequence calibration pattern through parallel sampling based on analog deskew is used to characterize the possible correction residual offset of the data slice sequence {Bk} that the analog receiving circuit is about to sample from the physical layer channel Lane_k.

[0101] Exemplarily, in an embodiment of the present application, a test slice sequence may include a plurality of identical test slices arranged in series, the slice length of each test slice may be the same as the slice length of the sampling slice, and a sequence calibration pattern may be used to characterize the standard numerical arrangement of a single test slice in the test slice sequence when aligned with a reference datum.

[0102] Exemplarily, in an embodiment of the present application, a test slice in a test slice sequence may include multiple binary data bits, and the values ​​of the multiple binary data bits are not all the same. In this case, the logic sorting circuit can be used to determine the verification result of the analog correction of the analog receiving circuit by comparing the actual numerical distribution of the binary values ​​of the test slice in a single sampling slice with the standard numerical arrangement of the test slice sequence represented by the sequence calibration pattern when aligned with the reference benchmark.

[0103] Figure 8 This is a schematic diagram of the first slice data structure of the test slice sequence used to verify the chip simulation correction in the processor of the embodiment of the present application. Figure 8 , similar to Figure 3 and Figure 6 , Figure 8 In the example, the length of the sampling slice is twice the length of the data slice (ie, t_sp = t_data × 2 = 16), and, Figure 8 In the first slice data structure shown, different data values ​​of multiple binary data bits can be evenly interleaved in the test slice, for example Figure 8 “0000111100001111” shown in.

[0104] For example, in the embodiments of the present application, Figure 8 The hexadecimal numbers listed in can be seen, such as Figure 8 The "0000111100001111" shown can generate 8 different combinations of value distributions, and the 8 different combinations of value distributions can be used to distinguish the offset of the correction residual offset within the range of ±4 UI, where the "+" of the offset indicates a forward offset, and the "-" indicates a backward offset.

[0105] Fig. 9 This is a schematic diagram of the second slice data structure of the test slice sequence used to verify the chip simulation correction in the processor of the embodiment of the present application. Fig. 9 , similar to Figure 3 and Figure 6 , Fig. 9 Take the example that the length of the sampling slice is twice the length of the data slice (ie, t_sp = t_data × 2 = 16), and, Fig. 9 In the second shard data structure shown, different data values ​​of multiple binary data bits may be distributed in a non-uniformly interleaved manner in the test shard, for example Fig. 9 “1001111100000001” shown in .

[0106] For example, in the embodiments of the present application, Fig. 9 The hexadecimal numbers listed in can be seen, such as Fig. 9 The "1001111100000001" shown can generate 15 different combinations of value distributions, and the 15 different combinations of value distributions can be used to distinguish the offset of the correction residual offset within the range of ±7 UI, where the "+" of the offset indicates a forward offset, and the "-" indicates a backward offset.

[0107] Compared to Figure 8 The test slices with uniformly staggered values ​​are shown, such as Fig. 9 The test slices with non-uniform interleaving of the values ​​shown can predict a larger shift in the corrected residual shift.

[0108] In another embodiment of the present application, a method for correcting data transmission between chiplets of a processor is provided. The method for correcting data transmission between chiplets of a processor is applicable to a processor packaged with at least two chiplets.

[0109] Exemplarily, in an embodiment of the present application, as described above, at least two core particles in a processor to which the correction method is applied are interconnected via a plurality of physical layer channels; any core particle among the at least two core particles that is a receiver of a communication data packet may include an analog receiving circuit, which may be used to perform parallel sampling based on analog correction on a plurality of data fragment sequences transmitted in parallel via a plurality of physical layer channels.

[0110] Exemplarily, in an embodiment of the present application, as described above, multiple data fragment sequences are split from a communication data packet by other core particles of at least two core particles that serve as data senders before parallel transmission, and multiple data fragment sequences can be used to restore the communication data packet by the core particles that serve as receivers of the communication data packet through data reorganization under the condition of alignment with a reference benchmark after being sampled in parallel by the core particles that serve as receivers of the communication data packet.

[0111] Fig.10 This is an exemplary flow chart of a method for correcting the data transmission between chiplets of a processor in an embodiment of the present application. Fig.10 In an embodiment of the present application, the de-skew method may be executed by any corelet of at least two corelets that is a receiver of the communication data packet, and the de-skew method may include the following steps executed by the corelet (for example, before data reorganization):

[0112] S1010: Obtain sampling results of multiple data slices transmitted in parallel by multiple physical layer channels by an analog receiving circuit; wherein the sampling results are obtained by parallel sampling based on analog deskew; the analog deskew is used to perform offset correction on a data slice sequence in any physical layer channel that has a data misalignment offset relative to a reference datum in the process of obtaining multiple data slice sequences from multiple physical layer channels by parallel sampling; and, in the sampling results, the data slice sequence obtained from any physical layer channel has a correction residual offset relative to the reference datum after the offset correction by the analog deskew.

[0113] S1030: Perform digital deskew on the data slice sequence with the correction residual offset in the sampling result; wherein the digital deskew is used to align the data slice sequence with the correction residual offset with the reference datum by shifting and arranging in the sampling result.

[0114] Based on the above-mentioned embodiments of the present application, any of the at least two core particles of the processor package may have an analog receiving circuit; the analog receiving circuit may obtain multiple data slice sequences transmitted in parallel to the core particle through multiple physical layer channels by other core particles through multiple physical layer channels through parallel sampling; in the process of obtaining multiple data slice sequences through parallel sampling, the analog receiving circuit may use analog deskew to perform offset correction on any data slice sequence with data misalignment and offset, so as to enable multiple data slice sequences to be sampled in parallel in an aligned state with respect to an alignment reference benchmark; even if the offset correction of any data slice sequence by analog deskew leaves a residual correction offset relative to the reference benchmark, the correction method for data transmission between core particles of the processor in the embodiment of the present application may use logical deskew to perform shift sorting on the data slice sequence, and may also eliminate the residual correction offset of the data slice sequence. Based on the correction method based on offset correction of analog correction and supplemented by shift arrangement of digital correction, multiple data fragment sequences obtained by parallel sampling of any core can be aligned with the reference benchmark used to achieve data reorganization, so as to obtain the correct communication data packet through data reorganization. In turn, it helps to improve the reliability of data transmission between cores of the processor.

[0115] Exemplarily, in an embodiment of the present application, the sampling result of the analog receiving circuit for multiple data slices may include: multiple sampling slice sequences corresponding to multiple physical layer channels respectively; wherein the sampling slice sequence corresponding to each physical layer channel of the multiple physical layer channels is aligned with the reference datum, and data reorganization is implemented using multiple groups of sampling slices corresponding to the multiple physical layer channels respectively; and the corrected residual offset of the data slice sequence obtained from any physical layer channel in the sampling result may include: the slice misalignment offset between the data slice sequence corresponding to the same physical layer channel and the sampling slice sequence. In this case, S1030 may include: shifting and arranging the sampling slice sequence corresponding to the same physical layer channel as the data slice sequence with the corrected residual offset.

[0116] Exemplarily, in an embodiment of the present application, if there is a slice misalignment offset caused by a correction residual offset between a data slice sequence and a sampling slice sequence corresponding to the same physical layer channel, then any data slice in the data slice sequence is distributed across slices with adjacent sampling slices in the sampling slice sequence corresponding to the same physical layer channel as the data slice sequence. In this case, the process of shifting and arranging in S1030 may include: in the sampling slice sequence corresponding to the same physical layer channel as the data slice sequence with the correction residual offset, performing cross-slice shifting and arranging on adjacent sampling slices (for example, two consecutive sampling slices) with the same data slice distributed across slices.

[0117] Exemplarily, in an embodiment of the present application, the process of shifting and sorting adjacent sampling slices that have the same data slice distributed across slices across slices, S1030 may include: shifting and integrating the slice fragments of adjacent sampling slices of the same data slice distributed across slices in the sampling slice sequence into a sampling slice at the front end of the adjacent sampling slices.

[0118] Exemplarily, in an embodiment of the present application, any data slice sequence is sequentially transmitted through a corresponding physical layer channel in a plurality of physical layer channels; the parallel sampling of the analog receiving circuit based on analog deflection correction may include: continuous periodic sampling of the corresponding data slice sequence sequentially transmitted by each physical layer channel in the plurality of physical layer channels; wherein each sampling slice in the sampling slice sequence corresponding to any physical layer channel is sequentially generated in a continuous unit sampling cycle. In this case, the deflection correction method for data transmission between core particles of the processor in an embodiment of the present application may also include: caching each sampling slice sequentially generated in the sampling slice sequence corresponding to the same physical layer channel as the data slice sequence with the correction reference offset; wherein the adjacent sampling slices targeted by the cross-slice shift arrangement may include: a sampling slice currently cached, and a sampling slice cached before the sampling slice; and, the sampling slice located at the front end of the adjacent sampling slices targeted by the cross-slice shift arrangement is the first sampling slice cached in the group of adjacent sampling slices.

[0119] Exemplarily, in an embodiment of the present application, before parallel sampling of a plurality of data fragment sequences transmitted in parallel by a plurality of physical layer channels, the method for correcting the data transmission between chiplets of the processor may further include:

[0120] Performing parallel sampling based on analog deskew on the test fragment sequences transmitted in parallel in each of the multiple physical layer channels; wherein the test fragment sequences cyclically transmitted in each of the multiple physical layer channels may be initiated by a core particle as a data sender of the multiple data fragment sequences;

[0121] Verifying analog deskew of an analog receiving circuit using a test slice sequence obtained from a plurality of physical layer channels through parallel sampling based on analog deskew; wherein the verification of analog deskew of the analog receiving circuit may include: detecting whether there is a correction residual offset remaining after offset correction by analog deskew in the test slice sequence obtained from the plurality of physical layer channels;

[0122] Utilize the verification result of analog deskew of the analog receiving circuit to activate or deactivate digital deskew; wherein, if the verification result indicates that the test slice sequence obtained from any physical layer channel has a correction residual offset, then it can be predicted that the data slice sequence that the analog receiving circuit is about to sample from the physical layer channel will have a correction residual offset, and thus the digital deskew can be activated; if the verification result indicates that the test slice sequence obtained from each physical layer channel does not have the correction residual offset, then it can be predicted that the data slice sequences that the analog receiving circuit is about to obtain from multiple physical layer channels through parallel sampling will not have a correction residual offset, and thus the digital deskew can be deactivated.

[0123] Exemplarily, in an embodiment of the present application, a correction method for data transmission between cores of a processor utilizes a test slice sequence to verify the timing of simulating correction, as well as the data structure of the test slices in the test slice sequence, which can all be found in the previous description and will not be repeated here.

[0124] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A processor, characterized in that: At least two cores are encapsulated in the processor, the at least two cores are interconnected via a plurality of physical layer channels, and any one of the at least two cores that is a receiver of a communication data packet includes an analog receiving circuit and a logic sorting circuit; The analog receiving circuit is used to: perform parallel sampling based on analog deskew on the multiple data slice sequences transmitted in parallel by the multiple physical layer channels; wherein the analog deskew is used to perform offset correction on the data slice sequences with data misalignment offset relative to the reference datum in any physical layer channel in the process of obtaining the multiple data slice sequences from the multiple physical layer channels through the parallel sampling, and the offset correction is used to make the multiple data slice sequences with the data misalignment offset be sampled in parallel in an aligned state with the reference datum; The logic sorting circuit is used for: if a data slice sequence obtained from any physical layer channel still has a correction residual offset relative to the reference datum after the offset correction of the analog correction, then digital correction is performed on the data slice sequence with the correction residual offset; wherein the digital correction is used to align the data slice sequence with the reference datum through shift sorting.

2. The processor according to claim 1, characterized in that The parallel sampling generates a plurality of sampling slice sequences corresponding to the plurality of physical layer channels respectively, the sampling slice sequence corresponding to each physical layer channel of the plurality of physical layer channels is aligned with the reference datum, and the correction residual offset includes: a slice misalignment offset between a data slice sequence and a sampling slice sequence corresponding to the same physical layer channel; The digital deflection correction of any data slice sequence having the correction residual offset includes: shifting and arranging the sampling slice sequence corresponding to the same physical layer channel as the data slice sequence.

3. The processor according to claim 2, characterized in that If there is a slice misalignment offset caused by the correction residual offset between the data slice sequence and the sampling slice sequence corresponding to the same physical layer channel, then any data slice in the data slice sequence is distributed across slices with adjacent sampling slices in the sampling slice sequence corresponding to the same physical layer channel as the data slice sequence; The digital deskew shifts and arranges the sampling slice sequence corresponding to the same physical layer channel as any data slice sequence, including: performing cross-slice shifting and arranging on the adjacent sampling slices in the sampling slice sequence.

4. The processor according to claim 3, characterized in that The digital deskew arranges the cross-slice shift of the adjacent sampling slices in any sampling slice sequence, including: shifting and integrating the slice fragments of the adjacent sampling slices across the slices of the same data slice in the sampling slice sequence to a sampling slice located at the front end of the adjacent sampling slices.

5. The processor according to claim 4, characterized in that Any data fragment sequence is sequentially transmitted through corresponding physical layer channels among the multiple physical layer channels; The parallel sampling includes: performing continuous periodic sampling on a corresponding data slice sequence sequentially transmitted by each physical layer channel of the plurality of physical layer channels; wherein each sampling slice in the sampling slice sequence corresponding to any physical layer channel is sequentially generated in a continuous unit sampling period; The logic sorting circuit is used for: if the data slice sequence obtained from any physical layer channel has the correction residual offset, then, each sampling slice generated sequentially in the sampling slice sequence corresponding to the same physical layer channel of the data slice sequence is cached slice by slice; wherein the adjacent sampling slices include: a sampling slice currently cached, and a sampling slice cached before the sampling slice; and a sampling slice located at the front end of the adjacent sampling slices is a sampling slice cached first among the adjacent sampling slices.

6. The processor according to claim 1, wherein: The analog receiving circuit is further used for: before performing the parallel sampling on the multiple data slice sequences transmitted in parallel on the multiple physical layer channels, performing the parallel sampling on the test slice sequences transmitted in parallel on the multiple physical layer channels respectively; The logic sorting circuit is also used for, before the analog receiving circuit performs the parallel sampling on the multiple data slice sequences transmitted in parallel by the multiple physical layer channels: Verifying the analog deskew using the test slice sequence obtained from the multiple physical layer channels through the parallel sampling; wherein the verification of the analog deskew includes: detecting whether the test slice sequence obtained from the multiple physical layer channels has the correction residual offset remaining after the offset correction of the analog deskew; Utilizing the verification result of the analog deskew, the digital deskew is activated or deactivated; wherein, if the verification result indicates that the test slice sequence obtained from any physical layer channel has the correction residual offset, then the digital deskew is activated; if the verification result indicates that the test slice sequence obtained from each physical layer channel does not have the correction residual offset, then the digital deskew is deactivated.

7. The processor according to claim 6, characterized in that Verifying the analog deskew using the test slice sequence occurs in a transmission idle period after parameter training of the analog receiving circuit is completed; wherein the parameter training is used to configure circuit parameters of the analog receiving circuit, and the correction amplitude and correction direction of the offset correction of the analog deskew are determined by the circuit parameters; or, The verification of the simulated deskew using the test fragment sequence occurs within a transmission idle period of the plurality of physical layer channels.

8. The processor according to claim 6, characterized in that The logic arrangement circuit is further used to: before verifying the simulated deflection correction, obtain a sequence calibration pattern of the test slice sequence; wherein the sequence calibration pattern is used to characterize a standard numerical arrangement of the test slice sequence when it is aligned with the reference datum; The verification of the analog correction by the logic sorting circuit includes: comparing the test slice sequence obtained from the multiple physical layer channels through the parallel sampling with the sequence calibration pattern; wherein the offset between the test slice sequence obtained by the parallel sampling and the sequence calibration pattern is used to characterize the correction residual offset.

9. The processor according to claim 8, characterized in that The test slice sequence includes a plurality of identical test slices arranged in succession, the test slices include a plurality of binary data bits, the values ​​of the plurality of binary data bits are not all the same, and the different data values ​​of the plurality of binary data bits adopt a non-uniformly staggered numerical distribution in the test slices.

10. The processor according to claim 1, wherein: The plurality of data fragment sequences are obtained by splitting the communication data packet from the communication data packet by the corelet of the at least two corelets that is the sender of the communication data packet before the parallel transmission; The plurality of data fragment sequences are used, after the parallel sampling, to restore the communication data packet by the corelet as the receiver of the communication data packet among the at least two corelets through data reorganization in the case of aligning the reference datum; The digital deskew occurs before the data reorganization is performed.

11. A method for correcting data transmission between chips of a processor, characterized in that: At least two cores are encapsulated in the processor; the at least two cores are interconnected through a plurality of physical layer channels; any one of the at least two cores that is a receiver of a communication data packet comprises an analog receiving circuit, the analog receiving circuit is used to perform parallel sampling based on analog deflection correction on a plurality of data fragment sequences transmitted in parallel by the plurality of physical layer channels, the analog deflection correction is used to perform offset correction on a data fragment sequence that has a data misalignment offset relative to a reference datum in any physical layer channel during the process of obtaining the plurality of data fragment sequences from the plurality of physical layer channels through the parallel sampling, and the offset correction is used to enable the plurality of data fragment sequences that have the data misalignment offset to be sampled in parallel in an aligned state aligned with the reference datum; The correction method comprises the following steps performed by the corelet of the at least two corelets that is the receiver of the communication data packet: Acquire sampling results of the analog receiving circuit for the multiple data slices; wherein the data slice sequence obtained from any physical layer channel in the sampling result has a residual correction offset relative to the reference reference after the offset correction by the analog deskew; Digital deskew is performed on the data slice sequence with the correction residual offset; wherein the digital deskew is used to align the data slice sequence with the correction residual offset with the reference datum through shift arrangement in the sampling result.

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