Display device

Abstract

A display device includes: a display panel including a display area including sub-pixels; a data driver supplying a data voltage to each of the sub-pixels through a data line; a gate driver supplying a bias gate signal to each of the sub-pixels; and a driving controller that compensates a data voltage written in a second region of the display region to which the bias gate signal is applied, based on a first data voltage corresponding to a gradation of a first region of the display region and a second data voltage corresponding to a gradation of a region of the display region different from the first region, the bias gate signal has an activation level in a first period in which the data voltage is written in the first region.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2023-0095400 filed on Jul. 21, 2023 and all rights arising therefrom, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] The present invention relates generally to a display device, and more particularly, to a display device and a driving method thereof. Background Art

[0003] The display device may include a display panel including a plurality of sub-pixels and a display panel driver driving the display panel. The display panel driver may display an image on the display panel using input image data received from an external processor. The processor may generate input image data by rendering raw data, and a rendering time for generating input image data corresponding to a frame may vary depending on the type or characteristics of the image. The display panel driver may change a driving frequency in response to the rendering time.

[0004] When the display device is driven at a low driving frequency, one frame may include an effective period in which a data voltage is written and a blank period in which no data voltage is written. During the blank period, the brightness of the display device may increase due to leakage current and / or hysteresis characteristics of the driving transistor compared to the effective period. To improve this, the display device may supply a bias voltage to the driving transistor in each of the effective period and the blank period.

[0005] One pixel row may be connected to the same data line. In addition, when the data voltage changes rapidly, it may affect other pixel rows in which the data voltage is not written. As a result, mura may appear in a partial area of ​​the display panel. Summary of the invention

[0006] The embodiment provides a display device with minimized speckles.

[0007] The embodiment further provides a method for driving the display device.

[0008] An embodiment provides a display device, including: a display panel including a display area including sub-pixels; a data driver that provides a data voltage to each of the sub-pixels through a data line; a gate driver that provides a bias gate signal to each of the sub-pixels; and a drive controller that compensates for a data voltage written in a second area of ​​the display area to which a bias gate signal is applied, based on a first data voltage corresponding to a grayscale of a first area of ​​the display area and a second data voltage corresponding to a grayscale of an area of ​​the display area different from the first area, the bias gate signal having an activation level in a first period in which the data voltage is written in the first area.

[0009] In an embodiment, a difference between a grayscale of the first region and a grayscale of a region different from the first region may be greater than a reference grayscale.

[0010] In an embodiment, the driving controller may compensate for the data voltage written in the second region based on a difference between the first data voltage and the second data voltage.

[0011] In an embodiment, the driving controller may determine a compensation voltage by applying a weight to a difference between the first data voltage and the second data voltage, and may compensate for the data voltage written in the second region based on the compensation voltage.

[0012] In an embodiment, each of the sub-pixels may include a light emitting element, and the weight may be determined based on a capacitance between an anode electrode of the light emitting element and a data line and an internal capacitance of the light emitting element.

[0013] In an embodiment, the weight may increase as the capacitance between the anode electrode of the light emitting element and the data line increases, and may decrease as the internal capacitance of the light emitting element increases.

[0014] In an embodiment, each of the sub-pixels may include a driving transistor and a storage capacitor, and the weight may be determined based on a capacitance between a first electrode of the driving transistor and a data line and a capacitance of the storage capacitor.

[0015] In an embodiment, the weight may increase as the capacitance between the first electrode of the driving transistor and the data line increases, and may decrease as the capacitance of the storage capacitor increases.

[0016] In an embodiment, the weight may increase as the driving frequency of the display panel increases.

[0017] In an embodiment, the display device may further include: an emission driver providing an emission signal to each of the sub-pixels, wherein the weight may increase as an off duty ratio of the emission signal increases.

[0018] In an embodiment, the driving controller may compensate the data voltage written in the second region by adding a compensated grayscale corresponding to the compensation voltage to the grayscale of the second region.

[0019] In an embodiment, the driving controller may compensate for a data voltage written in a third region different from the second region and to which a bias gate signal having an activation level in the first period is applied.

[0020] In an embodiment, the driving controller may generate a first compensation voltage by applying a first weight to a difference between a first data voltage and a second data voltage, compensate a data voltage written in the second region based on the first compensation voltage, generate a second compensation voltage by applying a second weight to a difference between the first data voltage and the second data voltage, and compensate the data voltage written in the third region based on the second compensation voltage.

[0021] In an embodiment, the second region may be closer to the first region than the third region, and the first compensation voltage may be greater than the second compensation voltage.

[0022] Another embodiment provides a driving method for a display device, comprising: calculating the grayscale of a first area of ​​a display area and the grayscale of an area of ​​the display area different from the first area based on input image data; determining a first data voltage based on the grayscale of the first area; determining a second data voltage based on the grayscale of the area different from the first area; and compensating a data voltage written in a second area of ​​the display area to which a bias gate signal is applied based on the first data voltage and the second data voltage, the bias gate signal having an activation level in a first period in which the data voltage is written in the first area.

[0023] In an embodiment, the first data voltage and the second data voltage may be determined based on a lookup table including data voltages according to grayscales.

[0024] In an embodiment, a difference between a grayscale of the first region and a grayscale of a region different from the first region may be greater than a reference grayscale.

[0025] In an embodiment, the data voltage written in the second region may be compensated based on a difference between the first data voltage and the second data voltage.

[0026] In an embodiment, the compensating of the data voltage written in the second region may include: determining a compensation voltage by applying a weight to a difference between the first data voltage and the second data voltage; and compensating the data voltage written in the second region based on the compensation voltage.

[0027] In an embodiment, the data voltage written in the second region may be compensated by adding a compensation grayscale corresponding to the compensation voltage to the grayscale of the second region.

[0028] The display device according to the embodiment may minimize spots by compensating a data voltage in a region where spots occur, the spots occurring due to a region where a grayscale change occurs.

[0029] In addition, the scope of the present invention is not limited to the above-described embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1A schematic block diagram of a display device according to an embodiment is illustrated.

[0031] Figure 2 FIG. 1 shows a schematic diagram of an embodiment of the present invention. Figure 1 A schematic circuit diagram of an example of a sub-pixel of a display device.

[0032] Figure 3 The diagram shows a case where a current is driven during an effective period according to an embodiment. Figure 2 An example timing diagram of a sub-pixel.

[0033] Figure 4 The diagram shows a case where a plurality of circuits are driven in a blank period according to an embodiment. Figure 2 An example timing diagram of a sub-pixel.

[0034] Figure 5 The diagram shows a change in the embodiment Figure 1 A timing diagram of an example of a driving frequency of a display device.

[0035] Figure 6 FIG. 1 shows a diagram according to an embodiment of the present invention. Figure 1 A timing diagram of an example of a display device compensating for a second area.

[0036] Figure 7 FIG. 1 shows a diagram of a method according to an embodiment of the present invention. Figure 1 A timing diagram of an example in which a display device drives a display panel in two cycles.

[0037] Figure 8 FIG. 1 shows a schematic diagram of an embodiment of the present invention. Figure 1 A block diagram of an example of a driving controller for a display device.

[0038] Fig. 9 A timing diagram illustrating an example in which a display device compensates for a second area and a third area according to an embodiment is illustrated.

[0039] Fig.10 FIG. 1 shows a diagram of a method according to an embodiment of the present invention. Fig. 9 A timing diagram of an example in which a display device drives a display panel in three cycles.

[0040] Fig.11 FIG. 1 shows a schematic diagram of an embodiment of the present invention. Fig. 9 A block diagram of an example of a driving controller for a display device.

[0041] Fig.12 A block diagram of a driving controller of a display device according to an embodiment is illustrated.

[0042] Fig.13 A flowchart illustrating a driving method of a display device according to an embodiment.

[0043] Fig.14A block diagram of an electronic device according to an embodiment is illustrated.

[0044] Fig.15 FIG. 1 shows a diagram of a method according to an embodiment of the present invention. Fig.14 The electronic device is implemented as an example of a smart phone. DETAILED DESCRIPTION

[0045] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following description is intended to provide enough disclosure to enable understanding of the present invention. In addition, the present invention can be implemented in different forms and is not limited to the embodiments set forth herein. The embodiments described herein are provided for the purpose of describing the present invention in sufficient detail so that those skilled in the art can easily practice the present invention.

[0046] Throughout the specification, when describing an element "connected" to another element, this includes not only "direct connection", but also "indirect connection" and another device between them. The terms used in this article are for the purpose of describing a specific embodiment, and are not intended to limit the scope of the present invention. Throughout the specification, unless explicitly described to the contrary, the word "include" and variants such as "comprise" or "contain" will be understood to imply the inclusion of stated elements, but do not exclude any other elements. For the purpose of this disclosure, "at least one of X, Y and Z" and "at least one selected from the group consisting of X, Y and Z" can be interpreted as only X, only Y, only Z or any combination of two or more of X, Y and Z (such as, for example, XYZ, XYY, YZ and ZZ). As used in this article, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0047] Although the terms first, second, etc. can be used to describe various constituent elements in this article, these constituent elements should not be limited by these terms. These terms are used to distinguish one constituent element from another constituent element. Therefore, without departing from the teaching of the present disclosure, the first constituent element discussed below can be referred to as the second constituent element.

[0048] Spatially relative terms such as "below," "below," "lower," "above," and "upper" may be used herein for descriptive purposes, and thereby describe the relationship of one element or feature to another (or some) element or feature as illustrated in the accompanying drawings. In addition to the orientation depicted in the accompanying drawings, spatially relative terms are intended to cover different orientations of the device in use, operation, and / or manufacture. For example, if the device in the accompanying drawings is flipped, the elements described as being "below" or "below" other elements or features will then be oriented "above" the other elements or features. Therefore, the term "below" can cover both the orientation above and below. In addition, the device can be oriented in other ways (e.g., rotated approximately 90 degrees or in other orientations), and therefore, the spatially relative descriptors used in this article are interpreted accordingly.

[0049] Various embodiments may be described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments. Therefore, variations in the shapes of the illustrations as a result of, for example, manufacturing techniques and / or tolerances are anticipated. Therefore, the embodiments disclosed herein should not be construed as limited to the shapes of the specific illustrated regions, but are to include deviations in shapes resulting from, for example, manufacturing. Therefore, the regions illustrated in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device and are not intended to be limiting.

[0050] The same number refers to the same element from beginning to end. In the accompanying drawings, for the sake of clarity, the thickness of certain lines, layers, components, elements or features may be exaggerated. It will be understood that although the terms "first", "second", etc. can be used to describe various elements in this article, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of the present invention, the "first" element discussed below may also be referred to as the "second" element.

[0051] The terms used in this article are only for the purpose of describing specific embodiments and are not intended to be limiting. As used in this article, "one", "the (said)" and "at least one" do not represent a limit to quantity, and are intended to include both the singular and the plural, unless the context clearly indicates otherwise. For example, "element" has the same meaning as "at least one element", unless the context clearly indicates otherwise. "At least one" should not be interpreted as limiting "one". "Or" means "and / or". As used in this article, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0052] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0053] Figure 1 A schematic block diagram of a display device according to an embodiment is illustrated.

[0054] refer to Figure 1 , the display device may include a display panel 100, a driving controller 200, a gate driver 300, a data driver 400, and an emission driver 500. In an embodiment, the driving controller 200 and the data driver 400 may be integrated on a single chip.

[0055] In an embodiment, the display panel 100 may include a display area DA displaying an image and a non-display area NDA disposed adjacent to the display area DA. In an embodiment, the gate driver 300 and the emission driver 500 may be installed in the non-display area NDA.

[0056] In an embodiment, the display panel 100 may include a plurality of gate lines GL, a plurality of data lines DL, a plurality of emission lines EL, and a plurality of sub-pixels SP electrically connected to the gate lines GL, the data lines DL, and the emission lines EL. The gate lines GL and the emission lines EL may extend in a first direction DR1, and the data lines DL may extend in a second direction DR2 crossing the first direction DR1.

[0057] In an embodiment, the drive controller 200 may receive input image data IMG and an input control signal CONT from a main processor (e.g., a graphics processing unit (GPU), etc.). For example, the input image data IMG may include red image data, green image data, and blue image data. In an embodiment, the input image data IMG may further include white image data. As another example, the input image data IMG may include magenta image data, yellow image data, and cyan image data. The input control signal CONT may include a main clock signal and a data enable signal. The input control signal CONT may further include a vertical synchronization signal and a horizontal synchronization signal.

[0058] In an embodiment, the driving controller 200 may generate a first control signal CONT1 , a second control signal CONT2 , a third control signal CONT3 , and a data signal DATA based on input image data IMG and an input control signal CONT.

[0059] In an embodiment, the driving controller 200 may generate a first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT to output it to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0060] In an embodiment, the driving controller 200 may generate a second control signal CONT2 for controlling the operation of the data driver 400 based on the input control signal CONT to output it to the data driver 400. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0061] In an embodiment, the driving controller 200 may receive input image data IMG and an input control signal CONT to generate a data signal DATA. The driving controller 200 may output the data signal DATA to the data driver 400.

[0062] In an embodiment, the driving controller 200 may generate a third control signal CONT3 for controlling the operation of the emission driver 500 based on the input control signal CONT to output it to the emission driver 500. The third control signal CONT3 may include a vertical start signal and an emission clock signal.

[0063] In an embodiment, the gate driver 300 may generate a gate signal for driving the gate line GL in response to the first control signal CONT1 received from the driving controller 200. The gate driver 300 may output the gate signal to the gate line GL. For example, the gate driver 300 may sequentially output the gate signal to the gate line GL.

[0064] In an embodiment, the data driver 400 may receive the second control signal CONT2 and the data signal DATA from the driving controller 200. The data driver 400 may generate a data voltage obtained by converting the data signal DATA into an analog voltage. The data driver 400 may output the data voltage to the data line DL.

[0065] In an embodiment, the emission driver 500 may generate an emission signal for driving the emission line EL in response to the third control signal CONT3 received from the driving controller 200. The emission driver 500 may output the emission signal to the emission line EL. For example, the emission driver 500 may sequentially output the emission signal to the emission line EL.

[0066] Figure 2 FIG. 1 shows a schematic diagram of an embodiment of the present invention. Figure 1 A schematic circuit diagram of an example of a sub-pixel of a display device.

[0067] In the examples and with reference to Figure 1 and Figure 2, each of the sub-pixels SP may include: a first transistor T1 (i.e., a driving transistor), including a control electrode connected to the first node N1, a first electrode connected to the second node N2, and a second electrode connected to the third node N3; a second transistor T2, including a control electrode receiving a write gate signal GW[n], a first electrode receiving a data voltage VDATA, and a second electrode connected to the second node N2; a third transistor T3, including a control electrode receiving a compensation gate signal GC[n], a first electrode connected to the third node N3, and a second electrode connected to the first node N1; a fourth transistor T4, including a control electrode receiving an initialization gate signal GI[n], a first electrode receiving a first initialization voltage VINT, and a second electrode connected to the first node N1; a fifth transistor T5, including a control electrode receiving an emission signal EM[n], a first electrode receiving a first power supply voltage ELVDD (e.g., a high power supply voltage), and a second electrode connected to the first node N1. A sixth transistor T6 includes a control electrode receiving an emission signal EM[n], a first electrode connected to a third node N3, and a second electrode connected to a fourth node N4; a seventh transistor T7 includes a control electrode receiving a bias gate signal GB[n], a first electrode receiving a second initialization voltage VAINT, and a second electrode connected to a fourth node N4; an eighth transistor T8 includes a control electrode receiving a bias gate signal GB[n], a first electrode receiving a bias voltage VOBS, and a second electrode connected to a second node N2; a storage capacitor CST includes a first electrode receiving a first power supply voltage ELVDD and a second electrode connected to a first node N1; and a light emitting element EE includes a first electrode (i.e., an anode electrode) connected to a fourth node N4 and a second electrode receiving a second power supply voltage ELVSS (e.g., a low power supply voltage). However, the present invention is not limited to this subpixel structure.

[0068] In an embodiment, a first parasitic capacitor CP1 may be formed between the data line DL and a first electrode (ie, anode electrode) of the light emitting element EE. In addition, a second parasitic capacitor CP2 may be formed between the data line DL and a first electrode of the first transistor T1 (ie, driving transistor).

[0069] In an embodiment, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 may be implemented as p-channel metal oxide semiconductor (PMOS) transistors. In the present embodiment, the low voltage level may be an activation level, and the high voltage level may be a deactivation level. For example, when the signal applied to the control electrode of the PMOS transistor has a low voltage level, the PMOS transistor may be turned on. In another example, when the signal applied to the control electrode of the PMOS transistor has a high voltage level, the PMOS transistor may be turned off.

[0070] In an embodiment, the third transistor T3 and the fourth transistor T4 can be implemented as n-channel metal oxide semiconductor (NMOS) transistors. In the present embodiment, the low voltage level can be a deactivation level, and the high voltage level can be an activation level. For example, when the signal applied to the control electrode of the NMOS transistor has a low voltage level, the NMOS transistor can be turned off. In another example, when the signal applied to the control electrode of the NMOS transistor has a high voltage level, the NMOS transistor can be turned on. That is, the activation level and the deactivation level can be determined according to the type of transistor.

[0071] However, the present invention is not limited thereto. For example, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 may be implemented as NMOS transistors. For example, the third transistor T3 and the fourth transistor T4 may be implemented as PMOS transistors.

[0072] Figure 3 The diagram shows a case where a current is driven during an effective period according to an embodiment. Figure 2 An example timing diagram of a sub-pixel, and Figure 4 The diagram shows a case where a plurality of circuits are driven in a blank period according to an embodiment. Figure 2 An example timing diagram of a sub-pixel.

[0073] In the examples and with reference to Figure 2 and Figure 3 The effective period ACTP may include an emission period EP and a non-emission period NEP. The non-emission period NEP of the effective period ACTP may include a bias period BP, an initialization period IP, and a data writing period WP.

[0074] In an embodiment, in the bias period BP, the bias gate signal GB[n] and the compensation gate signal GC[n] have an activation level, and the third transistor T3, the seventh transistor T7, and the eighth transistor T8 may be turned on. Accordingly, the second initialization voltage VAINT (i.e., the anode initialization voltage) may be applied to the first electrode (i.e., the anode electrode) of the light emitting element EE. That is, the internal capacitor CE of the light emitting element EE may be initialized. In addition, the bias voltage VOBS may be transmitted to the first node N1 through the second node N2. Accordingly, the voltage difference between the first node N1 and the third node N3 of the first transistor T1 may be reduced to the threshold voltage level of the first transistor T1, and the bias of the first transistor T1 may be initialized.

[0075] In an embodiment, in the initialization period IP, the initialization gate signal GI[n] may have an activation level, and the fourth transistor T4 may be turned on. Accordingly, the first initialization voltage VINT may be applied to the first node N1. That is, the control electrode of the first transistor T1 (ie, the storage capacitor CST) may be initialized.

[0076] In an embodiment, in the data write period WP, ​​the write gate signal GW[n] and the compensation gate signal GC[n] have an activation level, and the second transistor T2 and the third transistor T3 may be turned on. Accordingly, the data voltage VDATA may be written to the storage capacitor CST.

[0077] In an embodiment, in the emission period EP, the emission signal EM[n] has an activation level, and the fifth transistor T5 and the sixth transistor T6 may be turned on. Accordingly, the first power supply voltage ELVDD is applied to the first transistor T1 to generate a drive current, and the drive current may be applied to the light emitting element EE. That is, the light emitting element EE may emit light having a brightness corresponding to the drive current.

[0078] In the examples and with reference to Figure 2 and Figure 4 , the blank period BLKP may include a non-emission period NEP and an emission period EP. In the non-emission period NEP of the blank period BLKP, the compensation gate signal GC[n], the initialization gate signal GI[n], and the write gate signal GW[n] may have a deactivated level. That is, the data voltage VDATA may not be written in the blank period BLKP.

[0079] Figure 5 The diagram shows a change in the embodiment Figure 1 A timing diagram of an example of a driving frequency of a display device.

[0080] In the examples and with reference to Figure 5 , a frame FR may include a subframe ACTP and a BLKP. Here, a subframe means an effective period ACTP or a blank period BLKP. In the effective period ACTP of a frame FR, a data voltage may be written. In the blank period BLKP of a frame FR, no data voltage may be written. The display device may change the driving frequency of the display panel by adjusting the number of repetitions of the blank period BLKP.

[0081] In an embodiment, when the driving frequency is 240 Hz, one frame FR may include one active period ACTP and one blank period BLKP. In an embodiment, when the driving frequency is 120 Hz, one frame FR may include one active period ACTP and three blank periods BLKP. In an embodiment, although not in Figure 5As shown in FIG. 1 , however, when the driving frequency is 480 Hz, one frame FR may include one effective period ACTP.

[0082] Figure 6 FIG. 1 shows a diagram of a method according to an embodiment of the present invention. Figure 1 An example of a display device compensating a second area, Figure 7 FIG. 1 shows a diagram of a method according to an embodiment of the present invention. Figure 1 A timing diagram of an example in which a display device drives a display panel in two cycles, and Figure 8 FIG. 1 shows a schematic diagram of an embodiment of the present invention. Figure 1 A block diagram of an example of a driving controller for a display device.

[0083] In an embodiment, Figure 6 The left display area DA of exemplifies a case where the data voltage VDATA is not compensated, and Figure 6 The right display area DA of exemplifies a situation in which the data voltage VDATA is compensated.

[0084] In an embodiment, Figure 7 The first area A1 includes sub-pixels of the nth pixel row, the n+1th pixel row, and the n+2th pixel row, and the second area A2 includes sub-pixels of the mth pixel row, the m+1th pixel row, and the m+2th pixel row. Here, n is a positive integer, and m is a positive integer greater than n.

[0085] In the examples and with reference to Figure 6 and Figure 7 The driving controller 200 can compensate the data voltage VDATA written in the second area A2 of the display area DA to which the bias gate signal (e.g., GB[m], GB[m+1], and GB[m+2]) is applied based on the first data voltage corresponding to the grayscale of the first area A1 of the display area DA and the second data voltage corresponding to the grayscale of the area of ​​the display area DA different from the first area A1, and the bias gate signal (e.g., GB[m], GB[m+1], and GB[m+2]) has an activation level in the first period P1 in which the data voltage VDATA is written in the first area A1.

[0086] In an embodiment, the difference between the grayscale of the first area A1 and the grayscale of an area different from the first area A1 may be greater than a reference grayscale. The reference grayscale may have a predetermined value. For example, the grayscale difference between the first area A1 and an area located adjacent to the first area A1 may be greater than the reference grayscale. That is, the first area A1 may be an area having a large grayscale difference with an adjacent area.

[0087] For example, in the embodiments and as Figure 2As shown in , when the first transistor T1 is a PMOS transistor, the lower the grayscale, the larger the data voltage VDATA corresponding to the grayscale. Figure 6 As shown in , it is assumed that the grayscale of the first area A1 is lower than the grayscale of the area different from the first area A1. In this case, the data voltage VDATA may be reduced at the end of the first area A1. In addition, as the data voltage VDATA decreases, the voltage of the first electrode (i.e., the anode electrode) of the light emitting element EE may decrease due to coupling and due to the first parasitic capacitor CP1. In addition, after the voltage of the first electrode (i.e., the anode electrode) of the light emitting element EE decreases, the brightness of the area without the bias period (e.g., the second area A2) may decrease. Accordingly, the drive controller 200 can compensate for the decrease in brightness by compensating for the data voltage VDATA written in the area where the brightness decreases.

[0088] In an embodiment, when the display device drives the display panel in 2 cycles, an area in which the brightness is reduced may appear. Here, 2-cycle driving means that two areas of the display area DA display different subframes. In this case, the disabling timing of the bias gate signal (GB[n], GB[n+1], GB[n+2], ..., GB[m], GB[m+1], GB[m+2]) and the deactivation timing of the emission signal (EM[n], EM[n+1], EM[n+2], ..., EM[m], EM[m+1], EM[m+2]) can overlap with these two areas.

[0089] In the examples and with reference to Figure 2 and Figures 6 to 8 , the driving controller 200 may include a grayscale extractor 210 , a voltage difference calculator 220 , a compensation voltage determiner 230 , and a compensation grayscale determiner 240 .

[0090] In an embodiment, the grayscale extractor 210 may calculate the grayscale GLL of the first area A1 and the grayscale GBG of the area other than the first area A1 based on the input image data IMG. In an embodiment, the grayscale GLL of the first area A1 and the grayscale GBG of the area other than the first area A1 are illustrated to be constant, but the present invention is not limited thereto. For example, the drive controller 200 may compensate the data voltage VDATA written in the second area A2 based on the first data voltage corresponding to the average value of the grayscale GLL in the first area A1 and the second data voltage corresponding to the average value of the grayscale GBG in the area different from the first area A1.

[0091] In an embodiment, the driving controller 200 may include a frame buffer or a line buffer. The driving controller 200 may store input image data of one frame or input image data of a pixel row in the frame buffer or the line buffer.

[0092] In an embodiment, the voltage difference calculator 220 may determine the first and second data voltages based on the grayscale GLL of the first area A1 and the grayscale GBG of areas other than the first area A1. In addition, the voltage difference calculator 220 may calculate the difference VD between the first and second data voltages.

[0093] In an embodiment, the first data voltage and the second data voltage may be determined based on a lookup table LUT including data voltages VDATA according to grayscales. For example, the voltage difference calculator 220 may determine the data voltage VDATA corresponding to the grayscale GLL of the first area A1 as the first data voltage by using the lookup table LUT. For example, the voltage difference calculator 220 may determine the data voltage VDATA corresponding to the grayscale GBG of an area other than the first area A1 as the second data voltage by using the lookup table LUT.

[0094] In an embodiment, the compensation voltage determiner 230 may determine the compensation voltage CV based on the difference VD between the first data voltage and the second data voltage. The compensation voltage determiner 230 may determine the compensation voltage CV by applying the capacitance weight CW to the difference VD between the first data voltage and the second data voltage. For example, the compensation voltage CV may be the product of the difference VD between the first data voltage and the second data voltage and the capacitance weight CW.

[0095] In an embodiment, the capacitance weight CW may be determined based on the capacitance between the first electrode (i.e., anode electrode) of the light emitting element EE and the data line DL (i.e., the capacitance of the first parasitic capacitor CP1) and the internal capacitance of the light emitting element EE (i.e., the capacitance of the internal capacitor CE of the light emitting element EE). For example, the capacitance weight CW may increase as the capacitance between the first electrode of the light emitting element EE and the data line DL increases, and may decrease as the internal capacitance of the light emitting element EE increases. For example, the capacitance weight CW may be a value obtained by dividing the capacitance between the first electrode of the light emitting element EE and the data line DL by the internal capacitance of the light emitting element EE. Here, the capacitance between the first electrode of the light emitting element EE and the data line DL and the internal capacitance of the light emitting element EE may be determined experimentally.

[0096] In an embodiment, the capacitance weight CW may be determined based on the capacitance between the first electrode of the first transistor T1 (i.e., the driving transistor) and the data line DL (i.e., the capacitance of the second parasitic capacitor CP2) and the capacitance of the storage capacitor CST. For example, the capacitance weight CW may increase as the capacitance between the first electrode of the first transistor T1 and the data line DL increases, and may decrease as the capacitance of the storage capacitor CST increases. For example, the capacitance weight CW may be a value obtained by dividing the capacitance between the first electrode of the first transistor T1 and the data line DL by the capacitance of the storage capacitor CST and the capacitance of the first electrode of the first transistor T1, excluding the capacitance between the first electrode of the first transistor T1 and the data line DL. Here, the capacitance between the first electrode of the first transistor T1 and the data line DL, the capacitance of the storage capacitor CST, and the capacitance of the first electrode of the first transistor T1, excluding the capacitance between the first electrode of the first transistor T1 and the data line DL, may be determined experimentally.

[0097] In an embodiment, the compensation grayscale determiner 240 may determine the compensation grayscale CG based on the compensation voltage CV. For example, the compensation grayscale determiner 240 may determine the grayscale corresponding to the compensation voltage CV as the compensation grayscale CG by using a lookup table LUT.

[0098] In an embodiment, the driving controller 200 may compensate the data voltage VDATA written in the second area A2 based on the compensation grayscale CG. For example, the driving controller 200 may add the compensation grayscale CG corresponding to the compensation voltage CV to the grayscale of the second area A2 to compensate the data voltage VDATA written in the second area A2. In another example, Figure 6 As shown in , when the compensation grayscale CG is added to the grayscale of the second area A2, the data voltage VDATA of the second area A2 may be reduced by the compensation voltage CV.

[0099] Fig. 9 A timing diagram illustrating an example in which a display device compensates for a second area and a third area according to an embodiment, Fig.10 FIG. 1 shows a diagram of a method according to an embodiment of the present invention. Fig. 9 A timing diagram of an example in which a display device drives a display panel in three cycles, and Fig.11 FIG. 1 shows a schematic diagram of an embodiment of the present invention. Fig. 9 A block diagram of an example of a driving controller for a display device.

[0100] Since the display device according to the embodiment is different from the Figure 1 The display devices of EMBODIMENTS 1 and 2 are substantially the same, and thus the same figure numerals and reference symbols are used for the same or similar constituent elements, and redundant descriptions are omitted.

[0101] In an embodiment, Fig. 9 The left display area DA of exemplifies a case where the data voltage VDATA is not compensated, and Fig. 9 The right display area DA of exemplifies a situation in which the data voltage VDATA is compensated.

[0102] In an embodiment, Fig.10 The first area A1 shown in the figure includes sub-pixels of the n-th pixel row, the n+1-th pixel row, and the n+2-th pixel row, the second area A2 includes sub-pixels of the m-th pixel row, the m+1-th pixel row, and the m+2-th pixel row, and the third area A3 includes sub-pixels of the k-th pixel row, the k+1-th pixel row, and the k+2-th pixel row. Here, n is a positive integer, m is a positive integer greater than n, and k is a positive integer greater than m. That is, the second area A2 can be closer to the first area A1 than the third area A3.

[0103] In the examples and with reference to Fig. 9 and Fig.10 , the driving controller 200 can compensate the data voltage VDATA written in the second area A2 and the third area A3 of the display area DA to which the bias gate signal (e.g., GB[m], GB[m+1], GB[m+2], GB[k], GB[k+1] and GB[k+2]) is applied based on the first data voltage and the second data voltage, and the bias gate signal (e.g., GB[m], GB[m+1], GB[m+2], GB[k], GB[k+1] and GB[k+2]) has an activation level in the first period P1 in which the data voltage VDATA is written in the first area A1.

[0104] In an embodiment, when the display device drives the display panel in 3 cycles, two areas where the brightness is reduced may appear. Here, 3-cycle driving means that three areas of the display area DA display different subframes. In this case, the disable timing of the bias gate signal (GB[n], GB[n+1], GB[n+2], ..., GB[m], GB[m+1], GB[m+2]) and the deactivation timing of the emission signal (EM[n], EM[n+1], EM[n+2], ..., EM[m], EM[m+1], EM[m+2]) can overlap with these three areas.

[0105] In the examples and with reference to Figure 2 and Figures 9 to 11, the compensation voltage determiner 230 may apply the first capacitance weight CW1 to the difference VD between the first data voltage and the second data voltage to determine the first compensation voltage CV1. For example, the first compensation voltage CV1 may be the product of the difference VD between the first data voltage and the second data voltage and the first capacitance weight CW1. The compensation voltage determiner 230 may determine the second compensation voltage CV2 by applying the second capacitance weight CW2 to the difference VD between the first data voltage and the second data voltage. For example, the second compensation voltage CV2 may be the product of the difference VD between the first data voltage and the second data voltage and the second capacitance weight CW2.

[0106] In an embodiment, the capacitance weights CW1 and CW2 may be determined based on the capacitance between the first electrode (i.e., anode electrode) of the light emitting element EE and the data line DL (i.e., the capacitance of the first parasitic capacitor CP1) and the internal capacitance of the light emitting element EE (i.e., the capacitance of the internal capacitor CE of the light emitting element EE). For example, the capacitance weights CW1 and CW2 may increase as the capacitance between the first electrode of the light emitting element EE and the data line DL increases, and may decrease as the internal capacitance of the light emitting element EE increases.

[0107] In an embodiment, the capacitance weights CW1 and CW2 may be determined based on the capacitance between the first electrode of the first transistor T1 (i.e., the driving transistor) and the data line DL (i.e., the capacitance of the second parasitic capacitor CP2) and the capacitance of the storage capacitor CST. For example, the capacitance weights CW1 and CW2 may increase as the capacitance between the first electrode of the first transistor T1 and the data line DL increases, and may decrease as the capacitance of the storage capacitor CST increases. In an embodiment, the capacitance weights CW1 and CW2 may decrease as the capacitance of the first electrode of the first transistor T1, in addition to the capacitance between the first electrode of the first transistor T1 and the data line DL, increases.

[0108] In an embodiment, the second area A2 may be closer to the first area A1 than the third area A3. Accordingly, the reduction in brightness in the second area A2 may be greater than the reduction in brightness in the third area A3. Accordingly, the first capacitance weight CW1 may be greater than the second capacitance weight CW2, and the first compensation voltage CV1 may be greater than the second compensation voltage CV2.

[0109] In an embodiment, the compensation grayscale determiner 240 may determine the compensation grayscales CG1 and CG2 based on the compensation voltages CV1 and CV2. For example, the compensation grayscale determiner 240 may determine the grayscale corresponding to the first compensation voltage CV1 as the first compensation grayscale CG1 by using a lookup table LUT. In another example, the compensation grayscale determiner 240 may determine the grayscale corresponding to the second compensation voltage CV2 as the second compensation grayscale CG2 by using a lookup table LUT.

[0110] In an embodiment, the driving controller 200 may compensate the data voltage VDATA written in the second area A2 based on the first compensation grayscale CG1. For example, the driving controller 200 may add the first compensation grayscale CG1 corresponding to the first compensation voltage CV1 to the grayscale of the second area A2 to compensate the data voltage VDATA written in the second area A2. Fig. 9 As shown in FIG. 1 , when the first compensation grayscale CG1 is added to the grayscale of the second area A2 , the data voltage VDATA of the second area A2 may be reduced by the first compensation voltage CV1 .

[0111] In an embodiment, the driving controller 200 may compensate the data voltage VDATA written in the third area A3 based on the second compensation grayscale CG2. For example, the driving controller 200 may add the second compensation grayscale CG2 corresponding to the second compensation voltage CV2 to the grayscale of the third area A3 to compensate the data voltage VDATA written in the third area A3. Fig. 9 As shown in FIG. 1 , when the second compensation grayscale CG2 is added to the grayscale of the third area A3 , the data voltage VDATA of the third area A3 may be reduced by the second compensation voltage CV2 .

[0112] In the embodiment, it is illustrated that the display panel 100 is driven in three cycles, but the present invention is not limited to the number of cycles.

[0113] Fig.12 A block diagram of a driving controller of a display device according to an embodiment is illustrated.

[0114] In the embodiment, since the display device is connected to the display device in addition to the frequency weight FW and the dimming weight DW, Figure 1 The configuration of the display device in FIG. 1 is substantially the same, and thus the same figure numerals and reference symbols are used for the same or similar constituent elements, and repeated descriptions are omitted.

[0115] In the examples and with reference to Figure 2 and Fig.12 , the compensation voltage determiner 230 may determine the compensation voltage CV based on the difference VD between the first data voltage and the second data voltage. The compensation voltage determiner 230 may determine the compensation voltage CV by applying the weights CW, FW, and DW to the difference VD between the first data voltage and the second data voltage. For example, the compensation voltage CV may be the product of the difference VD between the first data voltage and the second data voltage and the weights CW, FW, and DW.

[0116] In the embodiment, it is described that the weights CW, FW and DW include all the capacitance weights CW, frequency weights FW and dimming weights DW, and the present invention is not limited thereto. For example, the compensation voltage determiner 230 can determine the compensation voltage CV by applying at least one of the capacitance weights CW, frequency weights FW and dimming weights DW.

[0117] In an embodiment, the weights CW, FW, and DW may include a capacitance weight CW, a frequency weight FW, and a dimming weight DW. The capacitance weight CW may be related to the reference Figures 6 to 8 The weights described are essentially the same.

[0118] In an embodiment, the driving controller 200 may further include a frequency weight determiner 250 and a dimming weight determiner 260 .

[0119] In an embodiment, the frequency weight determiner 250 may determine the frequency weight FW based on the driving frequency DF of the display panel. As the driving frequency DF increases, the brightness reduction may increase. Accordingly, the frequency weight FW may increase as the driving frequency increases.

[0120] In an embodiment, the dimming weight determiner 260 may determine the dimming weight DW based on the cut-off duty cycle AOR of the emission signal EM[n]. As the cut-off duty cycle AOR of the emission signal EM[n] increases, the brightness reduction may increase. Accordingly, the dimming weight DW may increase as the cut-off duty cycle AOR of the emission signal EM[n] increases.

[0121] Fig.13 A flowchart illustrating a driving method of a display device according to an embodiment.

[0122] In the examples and with reference to Fig.13 , the driving method of the display device may include: calculating the grayscale of a first area of ​​the display area and the grayscale of an area of ​​the display area different from the first area based on input image data (step S100); determining a first data voltage based on the grayscale of the first area (step S200); determining a second data voltage based on the grayscale of the area different from the first area (step S300); and compensating a data voltage written in a second area of ​​the display area to which a bias gate signal is applied based on the first data voltage and the second data voltage (step S400), the bias gate signal having an activation level in a first period in which the data voltage is written in the first area. Steps S100 to S400 may be performed by Figure 1 The display device is implemented.

[0123] Fig.14 A block diagram of an electronic device according to an embodiment is shown, and Fig.15 FIG. 1 shows a diagram of a method according to an embodiment of the present invention. Fig.14 The electronic device is implemented as an example of a smart phone.

[0124] In the examples and with reference to Fig.14 and Fig.15 , the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output device (I / O device) 1040, a power supply device 1050, and a display device 1060. In this case, the display device 1060 may be Figure 1 In addition, the electronic device 1000 may further include several ports capable of communicating with a video card, a sound card, a memory card, a USB device, etc. or with other systems. Fig.15 As shown in , the electronic device 1000 may be implemented as a smart phone. However, this is an example, and the electronic device 1000 is not limited thereto. For example, the electronic device 1000 may be implemented as a mobile phone, a videophone, a smart tablet, a smart watch, a tablet PC, a vehicle navigation, a computer monitor, a laptop computer, or a head-mounted display device, etc.

[0125] In an embodiment, the processor 1010 can perform a specific calculation or task. In some embodiments, the processor 1010 can be a microprocessor, a central processing unit, or an application processor. The processor 1010 can be connected to other components through an address bus, a control bus, and a data bus. In some embodiments, the processor 1010 can also be connected to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0126] In an embodiment, the memory device 1020 may store data required for the operation of the electronic device 1000. For example, the memory device 1020 may include a non-volatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, and a ferroelectric random access memory (FRAM) device, and / or a volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, and a mobile DRAM device.

[0127] In an embodiment, the storage device 1030 may include a solid state drive (SSD), a hard disk drive (HDD), a CD-ROM, and the like.

[0128] In an embodiment, the input / output device 1040 may include input devices such as a keyboard, a keypad, a touch pad, a touch screen, and a mouse, and output devices such as a speaker and a printer, etc. In some embodiments, the display device 1060 may be included in the input / output device 1040 .

[0129] In an embodiment, the power supply device 1050 may supply power required for the operation of the electronic device 1000. For example, the power supply device 1050 may be a power management integrated circuit (PMIC).

[0130] In an embodiment, the display device 1060 may display an image corresponding to the visual information of the electronic device 1000. In this case, the display device 1060 may be an organic light-emitting display device or a quantum dot light-emitting display device, but is not limited thereto. The display device 1060 may be connected to other constituent elements via a bus or other communication links.

[0131] In an embodiment, the present invention can be applied to a display device and an electronic device including the display device. For example, the present invention can be applied to a digital TV, a 3D TV, a mobile phone, a smart phone, a tablet computer, a VR device, a PC, a home electronic device, a laptop computer, a PDA, a PMP, a digital camera, a music player, a portable game console, and a navigation system, etc.

[0132] Although the present invention has been specifically shown and described with reference to the embodiments of the present invention, it will be appreciated by those of ordinary skill in the art that various changes may be made to it in form and detail without departing from the spirit or scope of the present invention. Therefore, it should be understood that the foregoing is an illustration of various embodiments and should not be construed as being limited to the disclosed specific embodiments, and modifications to the present invention are intended to be included within the scope of the present invention. In addition, embodiments or parts of embodiments may be combined in whole or in part without departing from the scope of the present invention.

Claims

1. A display device, comprising: A display panel including a display area including sub-pixels; a data driver that supplies a data voltage to each of the sub-pixels through a data line; a gate driver that provides a bias gate signal to each of the sub-pixels; as well as A driving controller that compensates the data voltage written in a second area of ​​the display area to which the bias gate signal is applied, based on a first data voltage corresponding to the grayscale of a first area of ​​the display area and a second data voltage corresponding to the grayscale of an area of ​​the display area different from the first area, the bias gate signal having an activation level in a first period in which the data voltage is written in the first area.

2. The display device according to claim 1, wherein: A difference between the grayscale of the first area and the grayscale of the area other than the first area is greater than a reference grayscale.

3. The display device according to claim 1 or 2, wherein: The driving controller compensates the data voltage written in the second area based on a difference between the first data voltage and the second data voltage.

4. The display device according to claim 3, wherein: The driving controller determines a compensation voltage by applying a weight to the difference between the first data voltage and the second data voltage, and compensates the data voltage written in the second region based on the compensation voltage.

5. The display device according to claim 4, wherein: Each of the sub-pixels includes a light emitting element, and The weight is determined based on the capacitance between the anode electrode of the light emitting element and the data line and the internal capacitance of the light emitting element.

6. The display device according to claim 5, wherein: The weight increases as the capacitance between the anode electrode of the light emitting element and the data line increases, and decreases as the internal capacitance of the light emitting element increases.

7. The display device according to claim 4, wherein: Each of the sub-pixels includes a driving transistor and a storage capacitor, and The weight is determined based on a capacitance between the first electrode of the driving transistor and the data line and a capacitance of the storage capacitor.

8. The display device according to claim 7, wherein: The weight increases as the capacitance between the first electrode of the driving transistor and the data line increases, and decreases as the capacitance of the storage capacitor increases.

9. The display device according to claim 4, wherein: The weight increases as a driving frequency of the display panel increases.

10. The display device according to claim 4, further comprising: an emission driver that provides an emission signal to each of the sub-pixels, The weight increases as the cutoff duty cycle of the transmit signal increases.

11. The display device according to claim 4, wherein: The driving controller compensates the data voltage written in the second area by adding a compensated grayscale corresponding to the compensation voltage to a grayscale of the second area.

12. The display device according to claim 1, wherein: The driving controller compensates the data voltage written in a third region different from the second region and to which the bias gate signal having the activation level in the first period is applied.

13. The display device according to claim 12, wherein: The driving controller generates a first compensation voltage by applying a first weight to a difference between the first data voltage and the second data voltage, compensates the data voltage written in the second region based on the first compensation voltage, generates a second compensation voltage by applying a second weight to the difference between the first data voltage and the second data voltage, and compensates the data voltage written in the third region based on the second compensation voltage.

14. The display device according to claim 13, wherein: The second region is closer to the first region than the third region, and The first compensation voltage is greater than the second compensation voltage.

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