Monitoring control signals for power switches in half-bridge for motor control or other applications

Abstract

The invention relates to a monitoring control or other application monitoring a control signal of a power switch in a half-bridge. In some examples, the present disclosure describes a method of controlling a high-side power switch and a low-side power switch arranged in a half-bridge configuration. The method may include driving a gate of a high side power switch based on a high side pulse modulation (PM) signal; driving a gate of the low-side power switch based on the low-side PM signal; and monitoring the high side PM signal and the low side PM signal. The high-side PM signal and the low-side PM signal are configured to turn on and off the high-side power switch and the low-side power switch in a complementary manner, and the monitoring may include: detecting one or more signal missing in the high-side PM signal or the low-side PM signal; and generate a fault signal in response to detecting the one or more signal missing.

Description

Technical Field

[0001] The present disclosure relates to driver circuits for power switches, and more particularly, to techniques and circuits for monitoring the operation of power switches configured in a half-bridge. Background Art

[0002] Power switches are widely used in a variety of applications to control the power to be delivered to a load. As an example, a power switch may include a field effect transistor (FET), an insulated gate bipolar transistor (IGBT), a bipolar junction transistor (BJT), or other types of power transistors. Examples of FETs may include, but are not limited to, junction field effect transistors (JFETs), metal oxide semiconductor FETs (MOSFETs), dual gate MOSFETs, insulated gate bipolar transistors (IGBTs), any other type of FET, or any combination of these. Examples of MOSFETs may include, but are not limited to, PMOS, NMOS, DMOS, or any other type of MOSFET, or any combination of these. MOSFETs may be formed of silicon, gallium nitride, silicon carbide, or other materials.

[0003] The power switch is usually controlled by a driver circuit via a pulse modulation (PM) signal. The PM signal usually refers to a pulse width modulation (PWM) signal, a pulse frequency modulation (PFM) signal, a pulse duration modulation signal, a pulse density modulation signal, or other types of modulation control signals used to control the power switch. The PM control signal can be generated by a processor and transmitted to the driver circuit. The driver circuit can amplify the PM control signal to generate a PM drive signal, which can be applied to the gate of the power switch to control the on / off of the power switch, and thereby control the average amount of power delivered to the load by the power switch. The on / off of the power switch effectively chops its power delivery into discrete parts. The average value of the voltage and / or current fed to the load can be controlled by quickly turning the switch on and off. The longer the period of time when the switch is on is compared to the time when it is off, the higher the total power supplied to the load.

[0004] In many applications, two different power switches are configured in a high-side and low-side configuration, and the on-off switching of the two power switches is synchronized to deliver the desired power to a switch node located between the high-side switch and the low-side switch. In addition, in some systems, different groups of high-side switches and low-side switches can be used to control multi-phase devices, such as different phases of a multi-phase motor. Summary of the invention

[0005] The present disclosure describes circuits and techniques for monitoring control signals of power switches, for example, so-called pulse modulation (PM) signals associated with high-side power switches and low-side power switches arranged in a half-bridge configuration. According to the present disclosure, the half-bridge circuit is controlled in a complementary manner, so that the low-side power switch is turned on when the high-side power switch is disconnected and the high-side power switch is turned on when the low-side power switch is disconnected. The technology of the present disclosure may include monitoring a PM signal associated with a driver circuit, which controls the high-side power switch and the low-side power switch of the half-bridge circuit. During normal operation, it is expected that when the high-side power switch is disconnected by the PM signal control, the low-side power switch is turned on by the PM signal control, and when the low-side power switch is disconnected by the PM signal control, the high-side power switch is turned on by the PM signal control. According to the present disclosure, the driver circuit can be configured to detect one or more signal absences in the high-side PM signal or the low-side PM signal. The driver circuit can also be configured to generate a fault signal in response to detecting one or more signal absences. In this case, one or more missing PM signals on the high side or the low side can indicate a problem with the circuit or the PM signal.

[0006] In some examples, the present disclosure describes a driver circuit configured to control a high-side power switch and a low-side power switch arranged in a half-bridge configuration. The driver circuit may include a high-side driver configured to drive a gate of the high-side power switch based on a high-side PM signal, and a low-side driver configured to drive a gate of the low-side power switch based on a low-side PM signal. The driver circuit may also include a logic circuit configured to monitor the high-side PM signal and the low-side PM signal. The high-side PM signal and the low-side PM signal are configured to turn on and off the high-side power switch and the low-side power switch in a complementary manner. The logic circuit is configured to detect one or more signal absences in the high-side PM signal or the low-side PM signal and generate a fault signal in response to detecting one or more signal absences.

[0007] In some examples, the present disclosure describes a method for controlling a high-side power switch and a low-side power switch arranged in a half-bridge configuration. The method includes: driving the gate of the high-side power switch based on a high-side PM signal; driving the gate of the low-side power switch based on a low-side PM signal; and monitoring the high-side PM signal and the low-side PM signal. The high-side PM signal and the low-side PM signal are configured to turn on and off the high-side power switch and the low-side power switch in a complementary manner. Monitoring the high-side PM signal and the low-side PM signal includes detecting one or more signal absences in the high-side PM signal or the low-side PM signal; and generating a fault signal in response to detecting one or more signal absences.

[0008] In some examples, the present disclosure describes a system comprising: a three-phase motor; and a plurality of half-bridge circuits, each comprising a high-side power switch and a low-side power switch arranged in a half-bridge configuration, wherein each of the half-bridge circuits controls a corresponding phase of the three-phase motor. For each half-bridge circuit of the plurality of half-bridge circuits, a corresponding driver circuit is configured to control a high-side power switch and a low-side power switch, and a processor is configured to generate a control signal for each corresponding driver circuit in the corresponding driver circuit. According to the present disclosure, each corresponding driver circuit in the corresponding driver includes a logic circuit configured to monitor a high-side PM signal and a low-side PM signal. The high-side PM signal and the low-side PM signal are configured to turn on and off the high-side power switch and the low-side power switch in a complementary manner, and the logic circuit is configured to detect one or more signal absences in the high-side PM signal or the low-side PM signal and generate a fault signal in response to detecting one or more signal absences.

[0009] The details of these and other examples are set forth in the drawings and the description that follows.Other features, objects, and advantages will become apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a block diagram illustrating a bridge driver circuit configured to control power switches of an external half-bridge circuit.

[0011] Figure 2 is another block diagram illustrating a bridge driver circuit configured to control a power switch of an external half-bridge circuit.

[0012] Figure 3 is another block diagram illustrating a bridge driver circuit configured to control a power switch of an external half-bridge circuit.

[0013] Figure 4 is a circuit diagram showing three half bridges arranged to control the operation of a three-phase motor.

[0014] Figure 5 is a timing diagram illustrating pulse modulation (PM) signals associated with controlling a high-side power switch and a low-side power switch of an external half-bridge circuit.

[0015] Figure 6 is a timing diagram showing the PM signal and signal loss on the high side.

[0016] Figure 7 is a timing diagram showing the PM signal and the signal loss on the low side.

[0017] Figure 8 is a diagram of a system consistent with one or more examples of the present disclosure.

[0018] Fig. 9 and Fig.10 is a flow chart illustrating a technique according to the present disclosure. DETAILED DESCRIPTION

[0019] The present disclosure describes circuits and techniques for monitoring control signals of power switches, for example, so-called pulse modulation (PM) signals associated with high-side power switches and low-side power switches arranged in a half-bridge configuration. The techniques can be used to monitor motors or other applications using half-bridge circuits. For motor control, the techniques can be applied by one or more driver circuits that control several different half-bridge circuits to control different phases of a multi-phase motor. A half-bridge circuit is also referred to herein as a "half-bridge".

[0020] According to the present disclosure, a half-bridge circuit is controlled in a complementary manner, wherein the low-side power switch is turned on when the high-side power switch is turned off and the high-side power switch is turned on when the low-side power switch is turned off. The technology disclosed herein may include monitoring a PM signal associated with a driver circuit of a high-side power switch and a low-side power switch of a half-bridge circuit. It is expected that when the high-side power switch is turned off by the PM signal control, the low-side power switch is turned on by the PM signal control, and when the low-side power switch is turned off by the PM signal control, the high-side power switch is turned on by the PM signal control. The driver circuit may be configured to detect one or more signal absences in the high-side PM signal or the low-side PM signal. The driver circuit may also be configured to generate a fault signal in response to detecting one or more signal absences.

[0021] In some cases, a single missing PM signal in the high side or low side may indicate a circuit problem or a signaling problem. However, generating a fault in response to a single missing PM signal may also cause a false alarm or abnormal failure. Therefore, in some examples, a counter can be used to detect consecutive instances of a missing (but expected) high-side PM signal or a low-side PM signal. In this case, the driver circuit can be configured to generate a fault signal in response to detecting multiple consecutive signal absences (e.g., two or more consecutive signal absences), which may indicate a signaling problem in the driver circuit or elsewhere.

[0022] The PM signal can include an input control signal from a processor to a driver circuit, an input signal from a digital core of a driver circuit to a high-side driver and a low-side driver, or an output signal from a high-side driver and a low-side driver. These different locations of monitoring the PM signal can provide different advantages and disadvantages relative to each other. In some cases, monitoring can be performed at each PM signal of these different PM signals, which can help to pinpoint circuit elements or locations that may cause problems. When detecting output signals from a high-side driver and a low-side driver, the level shifting operation can also be expected to improve monitoring of signals within a smaller voltage range defined by a drive signal applied to the gate of the power switch. Several different examples are described in more detail below.

[0023] Figure 1 It is a block diagram of a bridge driver circuit 102 configured to control a power switch 142 and a power switch 144 of an external half-bridge circuit 104. The power switch 142 and the power switch 144 are arranged in a half-bridge configuration. The high-side power switch 142 can be coupled to a first power supply side (e.g., power supply voltage), and the low-side power switch 144 can be coupled to a second power supply side (e.g., ground). The switch node 145 between the high-side power switch 142 and the low-side power switch 144 can correspond to a control node of another device. For example, the switch node 145 can be connected to a multi-phase motor and the external half-bridge circuit 104 can be configured to control the phase of the multi-phase motor.

[0024] The bridge driver circuit 102 includes a high-side driver 120 configured to drive the gate of the high-side power switch 142 based on the high-side pulse PM signal, and the bridge driver circuit 102 also includes a low-side driver 122 configured to drive the gate of the low-side power switch 144 based on the low-side PM signal. The high-side PM signal and the low-side PM signal are generally configured to turn on and off the high-side power switch 142 and the low-side power switch 144 in a complementary manner. In other words, in the complementary manner of operation, the low-side power switch 144 is controlled to be turned on when the high-side power switch 142 is controlled to be turned off, and the high-side power switch 142 is controlled to be turned on when the low-side power switch 144 is controlled to be turned off.

[0025] exist Figure 1 In the example shown in FIG. 1 , the bridge driver circuit 102 includes a digital core 110, which may include a digital interface (not shown in FIG. 1 ) with an external processor. Figure 1 ). The external processor can be connected to the bridge driver circuit 102 via input pins 132 and 134 to the digital core 110. The high-side driver 120 and the low-side driver 122 can be connected to the digital core via pins 136 and 138. (Not shown in FIG. Figure 1The ) output pins in can connect the high-side driver 120 to the high-side power switch 142, and can connect the low-side driver 122 to the low-side power switch 144.

[0026] The high-side driver 120 and the low-side driver 122 can be configured to generate PM drive signals (e.g., PWM_drive_HS and PWM_drive_LS) based on the PM control signals (e.g., PWM_out_HS and PWM_out_LS). The high-side driver 120 and the low-side driver 122 can each include, for example, an amplifier, a DC / DC power converter, a regulator, and / or one or more power switches, which can generate PM drive signals at voltage levels required to control the high-side power switch 142 and the low-side power switch 144.

[0027] PM signal generally refers to Figure 1 , or any of the PWM signals shown in . Thus, the PM signal can take different forms (e.g., different voltage levels or amplitudes) as the signal propagates through the bridge driver circuit 102. In general, however, the PM signal typically includes a square wave that defines a high level (on) and a low level (off). For example, the PM signal can include PWM_in_HS and PWM_in_LS, PWM_out_HS and PWM_out_LS, or PWM_drive_HS and PWM_drive_LS. The present disclosure describes monitoring the PM signal to detect unexpected absences, and monitoring different types of PM signals can have different benefits.

[0028] exist Figure 1 In the example shown in , digital core 110 includes logic circuit 112, and logic circuit 112 is configured to monitor high-side PM signal and low-side PM signal. In this example, the monitored signal corresponds to PMW_in_HS and PWM_in_LS received from an external processor at input pin 132, input pin 134. Logic circuit 112 is configured to detect one or more signal absences in high-side PM signal or low-side PM signal and generate a fault signal (e.g., return to an external processor or to another controller) in response to detecting one or more signal absences. For example, logic circuit 112 can be configured to transmit the fault signal to the processor.

[0029] In some cases, a single missing PM signal in the high side or low side may indicate a circuit problem or a signal transmission problem. However, generating a fault in response to a single missing PM signal may also cause a false alarm or abnormal abnormality. Therefore, in order to reduce possible false alarms, the logic circuit 112 includes a counter 114, which is configured to count consecutive signal absences in the high-side PM signal or the low-side PM signal, and the logic circuit 112 can be configured to generate a fault signal in response to the count value of the counter 114 reaching a count threshold. In this way, the counter 114 operates as a filtering mechanism, which requires a continuous signal missing (although expected) PM signal before the logic circuit 112 generates a fault signal. The count threshold can be, for example, greater than 1 and less than 8. For motor control applications, a count threshold of 3 is generally sufficient for quickly identifying problems while also limiting false alarms.

[0030] In addition, Figure 1 In the example shown in , the high-side driver 120 is configured to generate a high-side PM drive signal (PWM_drive_HS) based on a high-side PM control signal (PWM_out_HS) output from the digital core 110, and the low-side driver 122 is configured to generate a low-side PM drive signal (PWM_drive_LS) based on a low-side PM control signal (PWM_out_LS) output from the digital core 110. Figure 1 In the example of FIG. 1 , the logic circuit 112 is configured to monitor the PM control signals (e.g., PMW_in_HS and PWM_in_LS) at the pins 132 and 134, and detect one or more signal loss in the high-side PM signal or the low-side PM signal based on the monitoring of the PM control signals (e.g., PMW_in_HS and PWM_in_LS) at the pins 132 and 134. In other words, the PM control signals monitored in the bridge driver circuit 102 include input signals from the processor to the digital core 110. Therefore, the fault generated by the logic 112 can pinpoint a signal transmission problem that may come from some device before the digital logic 110, such as a problem with the external processor, a problem with the pins 132 and 134, or a problem with the external leads connecting the pins 132 and 134 to the external processor.

[0031] Figure 2 is a block diagram of a bridge driver circuit 202 configured to control a power switch 242 of an external half-bridge circuit 204 , the power switch 244 . Figure 2 In some respects Figure 1Very similar.Power switch 242 and power switch 244 are arranged in half-bridge configuration.High side power switch 242 can be coupled to the first power supply side (e.g., power supply voltage), and low side power switch 244 can be coupled to the second power supply side (e.g., ground).The switch node 245 between high side power switch 242 and low side power switch 244 can correspond to the control node of another device.For example, switch node 245 can be connected to multi-phase motor and external half-bridge circuit 104 can be configured to control the phase of multi-phase motor.

[0032] The bridge driver circuit 202 includes a high-side driver 220 configured to drive the gate of the high-side power switch 242 based on the high-side pulse PM signal, and the bridge driver circuit 202 also includes a low-side driver 222 configured to drive the gate of the low-side power switch 244 based on the low-side PM signal. The high-side PM signal and the low-side PM signal are generally configured to turn on and off the high-side power switch 242 and the low-side power switch 244 in a complementary manner. In other words, in the complementary manner of operation, the low-side power switch 244 is controlled to be turned on when the high-side power switch 242 is controlled to be turned off, and the high-side power switch 242 is controlled to be turned on when the low-side power switch 244 is controlled to be turned off.

[0033] and Figure 1 Similar to the example shown in, Figure 2 The bridge driver circuit 202 includes a digital core 210, which may include a digital interface with an external processor (not shown in FIG. Figure 2 ). The external processor can be connected to the bridge driver circuit 202 via input pins 232 and 234 to the digital core 210. The high-side driver 220 and the low-side driver 222 can be connected to the digital core via pins 236 and 238. (Not shown in FIG. Figure 2 The ) output pins in can connect the high-side driver 220 to the high-side power switch 242, and can connect the low-side driver 222 to the low-side power switch 244.

[0034] The high-side driver 220 and the low-side driver 222 can be configured to generate PM drive signals (e.g., PWM_drive_HS and PWM_drive_LS) based on the PM control signals (e.g., PWM_out_HS and PWM_out_LS). The high-side driver 220 and the low-side driver 222 can include, for example, an amplifier, a DC / DC power converter, a regulator, and / or one or more power switches, which can generate PM drive signals at voltage levels required to control the high-side power switch 242 and the low-side power switch 244.

[0035] like Figure 1 and Figure 2In the example shown in , the PM signal generally indicates any signal in the PWM signal. Therefore, the PM signal can take different forms (e.g., different levels or amplitudes) as the signal propagates through the bridge driver circuit 202. In general, however, the PM signal typically includes a square wave that defines a high level (on) and a low level (off). For example, the PM signal may include PWM_in_HS and PWM_in_LS, PWM_out_HS and PWM_out_LS, or PWM_drive_HS and PWM_drive_LS. The present disclosure describes monitoring the PM signal to detect unexpected absences, and monitoring different types of PM signals can have different benefits.

[0036] exist Figure 2 In the example shown in, bridge driver circuit 202 includes logic circuit 212, and logic circuit 212 is configured to monitor high-side PM signal and low-side PM signal. In this example, the monitored signal corresponds to the signal PMW_out_HS and PWM_out_LS output by digital core 210 at input pin 236, input pin 238. Logic circuit 212 is configured to detect one or more signal missing in high-side PM signal or low-side PM signal and generate fault signal (for example, return to external processor or to another controller) in response to detecting one or more signal missing. For example, logic circuit 212 can be configured to transmit fault signal to processor.

[0037] In addition, a single missing PM signal in the high side or low side may indicate a circuit problem or a signal transmission problem. However, generating a fault in response to a single missing PM signal may also cause a false alarm or abnormal abnormality. Therefore, in order to reduce possible false alarms, the logic circuit 212 includes a counter 214, which is configured to count consecutive missing in the high side PM signal or the low side PM signal, and the logic circuit 212 can generate a fault signal in response to the count value of the counter 214 reaching a count threshold. In this way, the counter 214 operates as a filtering mechanism, which requires a continuous signal missing (although expected) PM signal before the logic circuit 212 generates a fault signal. The count threshold can be, for example, greater than 1 and less than 8. For motor control applications, a count threshold of 3 is generally sufficient for quickly identifying problems while also limiting false alarms.

[0038] The high-side driver 220 is configured to generate a high-side PM drive signal (PWM_drive_HS) based on the high-side PM control signal (PWM_out_HS) output from the digital core 210, and the low-side driver 222 is configured to generate a low-side PM drive signal (PWM_drive_LS) based on the low-side PM control signal (PWM_out_LS) output from the digital core 210. Figure 1 The difference is that in Figure 2 In the example of , the logic circuit 212 is configured to monitor different PM control signals (e.g., PMW_out_HS and PWM_out_LS) at pins 236 and 238, and detect one or more signal absences in the high-side PM signal or the low-side PM signal based on the monitored PM control signals (e.g., PMW_out_HS and PWM_out_LS). In other words, the PM control signals monitored in the bridge driver circuit 202 include output signals from the digital core 210. Therefore, the fault generated by the logic 212 can generally indicate a signal transmission problem from the digital core 210, a problem with the external processor, a problem with pins 232 and 234, a problem with pins 236 and 238, or a problem with the external leads connecting pins 232 and 234 to the external processor. Therefore, compared to Figure 1 For example, Figure 2 The example shown in may identify more potential errors, but may be slightly less precise in identifying the cause of the errors.

[0039] You can also Figure 1 Examples and Figure 2 The examples of can be combined to help pinpoint the location of any errors. For example, if both logic circuit 112 and logic circuit 212 are used within bridge driver circuit 102 or bridge driver circuit 202, a fault identified by logic circuit 212 but not by logic circuit 112 would indicate a problem with digital core 110, digital core 210, and a fault identified by both logic circuit 212 and logic circuit 112 would likely indicate a problem with an external processor, a problem with pins 132, pin 232, pin 134, pin 234, or a problem with the external leads connecting pins 132, pin 232, pin 134, pin 234 to an external processor.

[0040] Figure 3 is another block diagram of an example bridge driver circuit 302 configured to control a power switch 342 , the power switch 344 of an external half-bridge circuit 304 . Figure 3 In several aspects Figure 1 and Figure 2 The power switch 342 and the power switch 344 are arranged in a half-bridge configuration. The high-side power switch 342 can be coupled to a first power supply side (e.g., a power supply voltage), and the low-side power switch 344 can be coupled to a second power supply side (e.g., ground). Of course, different power supplies can also be used in Figure 1 , Figure 2 ,or Figure 3 In the example of , the high side or low side (e.g., non-grounded or floating reference voltage). Figure 1 and Figure 2 ,exist Figure 3 , the switch node 345 is located between the high-side power switch 342 and the low-side power switch 344 and may correspond to a control node of another device. For example, the switch node 345 may be connected to a multi-phase motor and the external half-bridge circuit 304 may be configured to control the phases of the multi-phase motor.

[0041] As in the other examples, Figure 3 , the bridge driver circuit 302 includes a high-side driver 320 configured to drive the gate of the high-side power switch 342 based on the high-side pulse PM signal, and the bridge driver circuit 302 also includes a low-side driver 322 configured to drive the gate of the low-side power switch 344 based on the low-side PM signal. The high-side PM signal and the low-side PM signal are generally configured to turn on and off the high-side power switch 342 and the low-side power switch 344 in a complementary manner. In other words, in the complementary operation, the low-side power switch 344 is controlled to be turned on when the high-side power switch 342 is controlled to be turned off, and the high-side power switch 342 is controlled to be turned on when the low-side power switch 344 is controlled to be turned off.

[0042] and Figure 1 and Figure 2 Similar to the example shown in, Figure 3 The bridge driver circuit 302 includes a digital core 310, which may include a digital interface with an external processor (not shown in FIG. Figure 3 ). The external processor can be connected to the bridge driver circuit 302 via input pins 332, 334 leading to the digital core 310. The high-side driver 320 and the low-side driver 322 can be connected to the digital core via pins 336, 338. Output pins 352, 353 (i.e., the output of the bridge driver circuit 302) can connect the high-side driver 320 to the high-side power switch 342, and can connect the low-side driver 322 to the low-side power switch 344.

[0043] The high-side driver 320 and the low-side driver 322 can be configured to generate PM drive signals (e.g., PWM_drive_HS and PWM_drive_LS) based on the PM control signals (e.g., PWM_out_HS and PWM_out_LS). The high-side driver 320 and the low-side driver 322 can include, for example, an amplifier, a DC / DC power converter, a regulator, and / or one or more power switches, which can generate PM drive signals at voltage levels required to control the high-side power switch 342 and the low-side power switch 344.

[0044] and Figure 1 and Figure 2 Same as the example shown in Figure 3, the PM signal generally indicates any signal in the PWM signal. Therefore, the PM signal can take different forms (e.g., different levels or amplitudes) as the signal propagates through the bridge driver circuit 302. In general, however, the PM signal typically includes a square wave that defines a high level (on) and a low level (off). For example, the PM signal may include PWM_in_HS and PWM_in_LS, PWM_out_HS and PWM_out_LS, or PWM_drive_HS and PWM_drive_LS. The present disclosure describes monitoring the PM signal to detect unexpected absences, and monitoring different types of PM signals may have different benefits.

[0045] exist Figure 3 In the example shown in, bridge driver circuit 302 includes logic circuit 312, and logic circuit 312 is configured to monitor high-side PM signal and low-side PM signal. In this example, bridge driver circuit 302 also includes level shifter circuit 360, and level shifter circuit 360 is configured to generate the level shift version of PWM_drive_HS and PWM_drive_LS, which can include the feedback signal with the amplitude lower than PM drive signal. In this case, the monitored signal corresponds to PMW_FB_HS and PWM_FB_LS, and PMW_FB_HS and PWM_FB_LS are the level shift version of high-side PM signal and the level shift version of low-side PM signal. Same as other examples, logic circuit 312 is configured to detect one or more signal missing in high-side PM signal or low-side PM signal and generate fault signal (for example, return to external processor or another controller) in response to detecting one or more signal missing. For example, logic circuit 312 can be configured to transmit fault signal to processor.

[0046] As with the other examples, Figure 3 In the example shown in , a single missing PM signal in the high side or low side may indicate a circuit problem or a signal transmission problem. However, generating a fault in response to a single missing PM signal may also cause a false alarm or abnormal failure. Therefore, in order to reduce possible false alarms, the logic circuit 312 includes a counter 314, which is configured to count consecutive signal absences in the high-side PM signal or the low-side PM signal, and the logic circuit 312 can generate a fault signal in response to the count value of the counter 314 reaching a count threshold. In this way, the counter 314 operates as a filtering mechanism, which requires a continuous signal missing (although expected) PM signal before the logic circuit 312 generates a fault signal. The count threshold can, for example, be greater than 1 and less than 8. In addition, as indicated above, for motor control applications, a count threshold of 3 is generally sufficient for quickly identifying problems while also limiting false alarms.

[0047] The high-side driver 320 is configured to generate a high-side PM drive signal (PWM_drive_HS) based on the high-side PM control signal (PWM_out_HS) output from the digital core 310, and the low-side driver 322 is configured to generate a low-side PM drive signal (PWM_drive_LS) based on the low-side PM control signal (PWM_out_LS) output from the digital core 310. Figure 1 and Figure 2 The difference is that in Figure 3 In the example of , the logic circuit 312 is configured to monitor different PM control signals at pins 352 and 354 (e.g., level-shifted versions of the PM drive signals shown as PMW_FB_HS and PWM_FB_LS), and detect one or more signal absences in the high-side PM signal or the low-side PM signal based on monitoring the level-shifted PM control signals at pins 352 and 354 (e.g., PMW_FB_HS and PWM_FB_LS). In other words, the PM control signal monitored in the bridge driver circuit 302 is a level-shifted version of the drive signal sent from the bridge driver circuit 302 to the external half-bridge 304. Therefore, the fault generated by the logic 312 can indicate a problem from the driver 320 and the driver 322, a problem with the output pin 352 and the output pin 354, a problem with the digital core 310, a problem with the external processor, a problem with the pin 332 and the pin 334, a problem with the pin 336 and the pin 338, or a problem with the external leads connecting the pins 332 and the pin 334 to the external processor. Therefore, compared to Figure 1 and Figure 2 For example, Figure 3 The example shown in may identify more potential errors, but may be slightly less precise in identifying the cause of the errors.

[0048] You can also Figure 1 , Figure 2 ,and Figure 3 Examples of the invention can be combined to help pinpoint the location of any errors. For example, if logic circuit 112, logic circuit 212, and logic circuit 312 are all used within bridge driver circuit 102, bridge driver circuit 202, bridge driver circuit 302, a fault identified by one logic circuit but not by another logic circuit can help pinpoint the location of the problem within bridge driver circuit 102, bridge driver circuit 202, bridge driver circuit 302, while a fault identified by all of logic circuits 112, logic circuit 212, and logic circuit 312 (if used in combination) will indicate a possible problem external to bridge driver circuit 102, bridge driver circuit 202, bridge driver circuit 302.

[0049] Figure 4 is a circuit diagram showing three half-bridges (e.g., three half-bridge circuits) arranged to control the operation of motor 420. Power switch 404A and power switch 406A define a first half-bridge circuit, power switch 404B and power switch 406B define a second half-bridge circuit, and power switch 404C and power switch 406C define a third half-bridge circuit. Figure 4 Each half-bridge circuit shown in Figure 1-Figure 3 The half-bridge circuits 104, 204, 304 are similar, and Figure 4 Each half-bridge circuit shown in FIG. 1 can be composed of Figure 1-Figure 3 The external half-bridge driver circuit 102, 202 or 302 is similar to the half-bridge driver circuit control. Figure 3 Each power switch shown in FIG. 1 uses a separate bridge driver circuit (similar to bridge driver circuits 102 , 202 , 302 ).

[0050] Therefore, the present disclosure contemplates configurations for controlling Figure 4 4 , wherein the plurality of half-bridge circuits are configured to control a multi-phase motor 420. In this case, for each half-bridge circuit in the plurality of half-bridge circuits, the corresponding bridge driver circuit 102, 202, 302 includes a corresponding logic circuit 112, 212, 312, and the corresponding logic circuit is configured to detect one or more signal absences in the high-side PM signal or the low-side PM signal for the corresponding half-bridge in the plurality of half-bridges and generate a fault signal in response to detecting the one or more signal absences. The counter 114, 214, 314 can improve fault detection, wherein the corresponding logic circuit 112, 212, 312 defines a count threshold at which consecutive signal absences in the expected PM signal indicate a fault.

[0051] Generally speaking, circuits or systems for driving motors often use half-bridge circuits. A half-bridge circuit may include two MOSFETs driven by a bridge driver circuit. Bridge driver ICs used in brushless DC (BLDC) motor control applications typically have six PWM control inputs (two for each half-bridge) that are externally controlled by a processor (e.g., a microcontroller).

[0052] In a circuit or system used in a safety-critical environment, the MOSFET control capability of the circuit may need to be checked for normal operation. A microcontroller can control a PWM input (e.g., which may include a turn-on request and a turn-off request). It rotates the motor and controls the motor. The control signal of a half-bridge is usually set alternately to "high" and "low".

[0053] In the event that the PWM control input is not properly propagated through the bridge driver circuit (e.g., due to a break pin event, missing bond wire, internal IC single point failure, or other issue), the motor control scheme may be strongly affected (e.g., resulting in reduced or even loss of motor torque), while no error would be reported if the circuit interpreted the event as an expected microcontroller request.

[0054] The circuits and techniques described herein may provide a technical solution for detecting and reporting PWM control schemes that fail to properly alternate high-side and low-side drivers in each PWM cycle.

[0055] In some BLDC motor control systems, the processor or microcontroller can be responsible for detecting accidental disconnection situations by means of rationality checks on the motor current and phase feedback functions. With this approach, however, the problem can only be detected by external safety measures, which means increased complexity and limitations at the system level, since it is difficult to assess in real time an unexpected motor torque reduction associated with a fault in the PWM signal propagation path. Therefore, a disadvantage of this solution is that it cannot be applied to the reliability of any BLDC motor control system. If a single current detection is used for all three motor phases, no rationality check can be performed, since there is no redundancy at the microcontroller level as a detection mechanism for an accidental disconnection event due to a loss of the PWM control signal.

[0056] The proposed technical solution described in this article can monitor the PWM control scheme for each half-bridge driver circuit. In the BLDC motor control circuit and system, it is expected that each half-bridge circuit receives such a PWM control pattern that ensures the alternation of the high-side and low-side MOSFET turn-on phases in each PWM cycle.

[0057] The bridge driver circuit described herein can implement digital logic that strictly checks for the presence of alternation on the two (e.g., high-side and low-side) pins of the PWM control of each half-bridge. In the event that multiple turn-on requests are detected for one MOSFET in a half-bridge without any complementary turn-on request, an error can be reported via an SPI register or, if the device error pin is accessible to a microcontroller, via that pin.

[0058] The various advantages of this program may include:

[0059] Continuous monitoring of PWM correct function during operation, no self-test or rationality check required;

[0060] The digital logic used to detect the presence of PWM alternation does not limit the motor control scheme in any way; and

[0061] This solution provides sufficient flexibility at the system level to adjust the number of consecutive PWM turn-on detections on one MOSFET in the absence of a complementary turn-on request.

[0062] Thus, the described circuit provides a simple and effective mechanism to detect and report a stuck disconnect condition at a PWM input pin.By having the monitoring implemented in the bridge driver circuit already, it is also possible to reduce the external processing load that would otherwise be required in the case of an external rationality check.

[0063] Figure 5 is a timing diagram illustrating PM signals associated with controlling the high-side power switch and the low-side power switch of an external half-bridge circuit. Figure 5 The PM signals shown in FIG. 1 are labeled PWM HS (for the high-side transistor) and PWM LS (for the low-side transistor). PWM HS and PWM LS may correspond to Figure 1-Figure 3 Any PWM signal discussed in . Figure 5 Conventional operation of the PM signal is generally shown, whereby PWM HS and PWM LS define alternating and complementary on and off states.

[0064] Figure 6 is a timing diagram showing the PM signal and the signal loss on the high-side switch. Figure 6 The PM signal is Figure 5 Similar to, but in Figure 6 The PM signal is missing at positions 601, 602, and 603. The logic circuits 112, 212, 312 may be configured to monitor Figure 6 1, 214, 314 and detect any absence of the expected PM signal and count the absence. For example, the counter 114, 214, 314 can count the absence of the PM signal at positions 601, 602, and 603, for example, increasing the count value to 1, 2, 3 as shown at positions 601, 602, and 603, respectively. The logic circuit 112, 212, 312 can react to the count value reaching a threshold value (e.g., counter=3 at position 603). When the counter 114, 214, 314 reaches the threshold value (e.g., counter=3), the logic circuit 112, 212, 312 can send a fault back to the control processor, which can take corrective action, such as disabling the bridge driver 102, 202, 302, or operating the bridge driver 102, 202, 302 in a safe mode. The safe mode for motor control can include a lower power mode than used in normal operation, and can facilitate so-called "limp home" operation of the electric vehicle. The electric vehicle has reduced torque and horsepower in the "limp home" mode compared to the electric vehicle's normal operating mode.

[0065] Figure 7 In many ways Figure 6 Similar timing diagram. Figure 6 shows the missing (and desired) PM signal on the high side, while Figure 7 The missing (and desired) PM signal on the low side is shown. The logic circuits 112, 212, 312 may be configured to monitor Figure 7 The PM signal shown in FIG. 1 and any absence of the expected PM signal is detected and counted. Figure 7 Coincidentally, the counter 114, 214, 314 may count the absence of the PM signal at positions 701, 702, and 703, e.g., increasing the count value to 1, 2, 3 as shown at positions 701, 702, and 703, respectively. The logic circuit 712, 712, 712 may react to the count value reaching a threshold, e.g., counter=3 at position 703. When the counter 114, 214, 314 reaches the threshold (e.g., counter=3), the logic circuit 112, 212, 312 may send a fault back to the control processor, which may take corrective action, such as disabling the bridge driver 102, 202, 302, or operating the bridge driver 102, 202, 302 in a safe mode. Again, the safe mode for motor control may include a lower power mode than used under normal operation and may facilitate so-called "limp home" operation of the electric vehicle. The electric vehicle has reduced torque and horsepower in the "limp home" mode compared to the electric vehicle's normal operating mode.

[0066] Figure 5-Figure 7 Generally, a high logic level means a request to turn on the corresponding MOSFET. Figure 5 The PWM control scheme for the half-bridge MOSFET is correctly applied in . In contrast, the PWM control signal can be forced on the low side (LS) or high side (HS), thus Figure 6 and Figure 7 The specific MOSFET in the PWM input is stuck in the off state, which means there is a problem.

[0067] With the proposed implementation described in this article, digital logic can be used for each half-bridge (for monitoring the PWM_HS, PWM_LS pin pair), where the following control scheme is applied to the synchronized internal PWM signals:

[0068] - A PWM low-to-high transition (whether HS or LS) enables the state machine in the logic 112 , 212 , 312 .

[0069] - For the next PWM low-high transition:

[0070] - If on complementary PWM input, restart the state machine

[0071] - If on the same PWM input as the previous conversion, start error counter 114, 214, 314

[0072] - PWM low-high transition detection on complementary PWM input resets error counters 114, 214, 314

[0073] -If the error count reaches a configured value or consecutive PWM on-requests on the same MOSFET, a PWM stuck at the complementary PWM input is reported (e.g., reported to processor 801) and the system responds (e.g., such as by reporting an error, disconnecting the corresponding half-bridge, modifying system operation to operate in a safe state, or possibly disconnecting all MOSFETs).

[0074] Figure 8 804A is a system diagram consistent with one or more examples of the present disclosure. A processor 801 generates a PM control signal and delivers the PM control signal to bridge driver circuits 802A, 802B, 802C. The bridge driver circuit generates a PM drive signal based on the PM control signal and drives three different half-bridge circuits 804A, 804B, 804C to control three phases of a brushless DC (BLDC) motor 806. The BLDC motor 806 can correspond to any BLDC motor application, and the motor of an electric vehicle is only one example application.

[0075] The bridge driver circuits 802A, 802B, 802C may each correspond to the bridge driver circuits 102, 202, or 302. If a fault is detected by the logic circuits 112, 212, 312 for any of the bridge driver circuits 802A, 802B, 802C, the corresponding bridge driver circuit may send a fault signal back to the processor 801, and the processor may take appropriate action to ensure safe operation of the system, such as by disabling the system, disabling the corresponding bridge driver circuit that issued the fault, or perhaps by implementing different "safe" and "low power" operating modes for some or all of the bridge driver circuits 802A, 802B, 802C.

[0076] Fig. 9 and Fig.10 is a flow chart illustrating a technique according to the present disclosure. Fig. 9 It may also be viewed as a state diagram illustrating a control scheme executed by a bridge driver circuit consistent with the present disclosure.

[0077] exist Fig. 9In the example shown in FIG. 1 , after starting the bridge driver circuit 102, 202, 302 (902), the logic circuit 112, 212, 312 can determine whether the half-bridge circuit 104, 204, 304 is enabled to allow PWM control (904). If so (the yes branch of 904), the logic circuit 112, 212, 312 can wait to detect a PWM_HS or PWM_LS turn-on request (906). Fig. 9 , the PWM_HS or PWM-LS on request may correspond to any of the PM signals described herein. Once a PWM_on request is detected (the YES branch of 908), the logic circuit 112, 212, 312 may then wait for the next PWM_on request (910). If the next on request is from a different PWM input, e.g., a different high side or low side (the NO branch of 912), the counter 114, 214, 314 is reset (914). However, if the next on request is from the same PWM input (the YES branch of 912), the counter 114, 214, 314 is incremented. As long as the counter 114, 214, 314 has not reached its limit or threshold (the NO branch of 918), the process continues. If the counter 114, 214, 314 reaches its limit or threshold (the YES branch of 918), this means that a specific (e.g., predefined) number of consecutive PM signals is missing (also expected). In this case, the logic circuit 112, 212, 312 may report the lack of PMW operation (920), for example, by sending a fault signal back to the processor 801.

[0078] Fig.10 is another flow chart consistent with the present disclosure. Fig.10 As shown in , the bridge driver circuit 102, 202, 302 drives the high-side transistor 142, 242, 342 (1001) and the low-side transistor 144, 244, 344 (1002) in a complementary manner. When doing so, the logic circuit 112, 212, 312 monitors the PM signal (1003) to check for missing or missing signals. If there is no missing PM signal (the no branch of 1004), the counter 114, 214, 314 is reset (1005). However, once the missing PM signal is detected on the high side or the low side, the logic circuit 112, 212, 312 increments the count value (1006). As long as the counter 114, 214, 314 has not reached its count threshold, conventional control continues (the "no" branch of 1007). Once the counter 114, 214, 314 reaches its count threshold ("yes" branch of 1007), which indicates a predefined number of consecutive missing PM signals on the high side or low side, the logic circuit 112, 212, 312 can send a fault signal (1008) back to the processor 801. Fig. 9and Fig.10 In concert, the logic circuit 112 , 212 , 312 maintains a count value indicating consecutive signal absences in the high-side PM signal or the low-side PM signal and generates a fault signal in response to the count value reaching a count threshold.

[0079] The circuits and techniques described herein can be part of a safety mechanism configured to ensure safe operation of a motor and other circuits attached to the motor. The described techniques can improve fault detection in motor control systems. In fact, these techniques can significantly reduce package failure rates in circuit and system-level safety analysis.

[0080] By using the internal PWM monitoring state machine for each half-bridge:

[0081] - The bridge driver circuit may be able to detect package faults (open pins or missing bond wires) or system faults (fault events on PCB traces or microcontroller IOs) that cannot be detected or distinguished by general external safety mechanisms (sanity checks) at the microcontroller or processor level;

[0082] - A microcontroller or processor can offload this more reliable detection, potentially eliminating or reducing the need for system-level sanity checks;

[0083] - Missing or stuck PWM scenarios can be clearly identified at the system level through direct monitoring mechanisms rather than cycle rationality checks or drain-source monitoring of MOSFETs or indirect measurements of motor phase pins (phase feedback monitoring) which imply disruption of the motor’s expected operation;

[0084] - PWM monitoring can be performed in every PWM cycle, thus defining a continuous checking and monitoring scheme.

[0085] The techniques described in the present disclosure may be implemented, at least in part, in circuitry, hardware, software, firmware, or any combination thereof. For example, various aspects of the described techniques may be implemented in one or more logic elements, a processor including one or more microprocessors, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or any other equivalent integrated or discrete logic circuitry, and any combination of these components. The term "processor" or "processing circuitry" may generally refer to any of the foregoing logic circuitry, alone or in combination with other logic circuitry, or any other equivalent circuitry. A control unit including hardware may also perform one or more techniques of the present disclosure.

[0086] The hardware, software, and firmware may be implemented within the same device or within separate devices to support the various operations and functions described in this disclosure. In addition, any described units, modules, or components may be implemented together or separately as separate but cooperatively operating logic devices. The description of modules or units with different functions is intended to highlight different functional aspects and does not necessarily mean that such modules or units must be implemented by independent hardware or software components. On the contrary, the functions associated with one or more modules or units may be performed by separate hardware or software components, or components integrated in common or separate hardware or software components.

[0087] One or more aspects of the present disclosure may also be performed in software, in which case those aspects of the techniques described in the present disclosure may also be implemented or encoded in a computer-readable medium, such as a computer-readable storage medium containing instructions. For example, when the instructions are executed, the instructions embedded or encoded in the computer-readable storage medium may cause a programmable processor or other processor to perform the method. The computer-readable storage medium may include a random access memory (RAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, or other computer-readable medium.

[0088] The following clauses may describe one or more aspects of the present disclosure.

[0089] Item 1 - A driver circuit configured to control a high-side power switch and a low-side power switch arranged in a half-bridge configuration, the driver circuit comprising: a high-side driver configured to drive a gate of the high-side power switch based on a high-side PM signal; a low-side driver configured to drive a gate of the low-side power switch based on the low-side PM signal; and a logic circuit configured to monitor the high-side PM signal and the low-side PM signal, wherein the high-side PM signal and the low-side PM signal are configured to turn on and off the high-side power switch and the low-side power switch in a complementary manner, and wherein the logic circuit is configured to detect one or more signal absences in the high-side PM signal or the low-side PM signal and generate a fault signal in response to detecting the one or more signal absences.

[0090] Clause 2—The driver circuit of clause 1, wherein the logic circuit is configured to communicate the fault signal to the processor.

[0091] Clause 3 - A driver circuit according to clause 1 or clause 2, wherein the high-side driver is configured to generate a high-side PM drive signal based on a high-side PM control signal output from a digital core, wherein the low-side driver is configured to generate a low-side PM drive signal based on a low-side PM control signal output from the digital core, and the logic circuit is configured to: monitor the PM control signal and detect one or more signal absences in the high-side PM signal or the low-side PM signal based on the monitored PM control signal.

[0092] Clause 4—The driver circuit of Clause 3, wherein the PM control signal comprises an input signal from the processor to the digital core.

[0093] Clause 5—The driver circuit of Clause 3, wherein the PM control signal comprises a high-side PM control signal output from the digital core to the high-side driver and a low-side PM control signal output from the digital core to the low-side driver.

[0094] Clause 6 - A driver circuit according to clause 1 or clause 2, further comprising a level shifter circuit, wherein the high-side driver is configured to generate a high-side PM drive signal based on a high-side PM control signal output from the digital core, wherein the low-side driver is configured to generate a low-side PM drive signal based on a low-side PM control signal output from the digital core, wherein the level shifter circuit is configured to generate a level-shifted version of the high-side PM drive signal and a level-shifted version of the low-side PM drive signal, and wherein the logic circuit is configured to: monitor the level-shifted version of the high-side PM drive signal and the level-shifted version of the low-side PM drive signal, and detect one or more signal absences in the high-side PM signal or the low-side PM signal based on monitoring the level-shifted version of the high-side PM drive signal and the level-shifted version of the low-side PM drive signal.

[0095] Clause 7 - A driver circuit as described in any of Clauses 1 - Clause 6, wherein the logic circuit includes a counter configured to count consecutive signal absences in the high-side PM signal or the low-side PM signal, and the logic circuit generates a fault signal in response to a count value of the counter reaching a count threshold.

[0096] Clause 8—The driver circuit of Clause 7, wherein the count threshold is greater than one and less than eight.

[0097] Clause 9—The driver circuit of clause 8, wherein the count threshold is three.

[0098] Clause 10 - A driver circuit as described in any of Clauses 1 - Clause 9, further comprising a plurality of high-side drivers and a plurality of low-side drivers configured to control a plurality of half-bridges.

[0099] Clause 11—The driver circuit of clause 10, wherein the plurality of half-bridges are configured to control a multi-phase motor.

[0100] Clause 12 - A driver circuit according to clause 10 or clause 11, wherein for each half-bridge of the plurality of half-bridges, the driver circuit includes a corresponding logic circuit configured to detect one or more signal absences in the high-side PM signal or the low-side PM signal for the corresponding half-bridge of the plurality of half-bridges and generate a fault signal in response to detecting the one or more signal absences.

[0101] Item 13 - A method of controlling a high-side power switch and a low-side power switch arranged in a half-bridge configuration, the method comprising: driving a gate of the high-side power switch based on a high-side PM signal; driving a gate of the low-side power switch based on a low-side PM signal; and monitoring the high-side PM signal and the low-side PM signal, wherein the high-side PM signal and the low-side PM signal are configured to turn on and off the high-side power switch and the low-side power switch in a complementary manner, and wherein the monitoring comprises: detecting one or more signal absences in the high-side PM signal or the low-side PM signal; and generating a fault signal in response to detecting one or more signal absences.

[0102] Clause 14—The method of clause 13, further comprising: transmitting a fault signal to a processor.

[0103] Clause 15 - A method according to clause 13 or clause 14, wherein the high-side driver is configured to generate a high-side PM drive signal based on a high-side PM control signal output from a digital core, wherein the low-side driver is configured to generate a low-side PM drive signal based on a low-side PM control signal output from the digital core, and wherein monitoring the high-side PM signal and the low-side PM signal includes: monitoring the PM control signal and detecting one or more signal absences in the high-side PM signal or the low-side PM signal based on monitoring the PM control signal.

[0104] Clause 16 - A method according to clause 13 or clause 14, wherein the high-side driver is configured to generate a high-side PM drive signal based on a high-side PM control signal output from a digital core, wherein the low-side driver is configured to generate a low-side PM drive signal based on a low-side PM control signal output from the digital core, wherein the level shifter circuit is configured to generate a level-shifted version of the high-side PM drive signal and a level-shifted version of the low-side PM drive signal, and wherein monitoring the high-side PM signal and the low-side PM signal includes: monitoring the level-shifted version of the high-side PM drive signal and the level-shifted version of the low-side PM drive signal, and detecting one or more signal absences in the high-side PM signal or the low-side PM signal based on monitoring the level-shifted version of the high-side PM drive signal and the level-shifted version of the low-side PM drive signal.

[0105] Clause 17 - The method of any of Clauses 13 - 16, further comprising: maintaining a count value indicating a continuous signal absence in the high-side PM signal or the low-side PM signal; and generating a fault signal in response to the count value reaching a count threshold.

[0106] Clause 18—The method of Clause 17, wherein the count threshold is greater than one and less than six.

[0107] Clause 19 - A method as defined in any of Clauses 13 - 18, wherein the method comprises controlling a plurality of high-side drivers and a plurality of low-side drivers configured to control a plurality of half-bridges, wherein the plurality of half-bridges are configured to control a multi-phase motor.

[0108] Clause 20—The method of clause 19, further comprising: for each half-bridge of the plurality of half-bridges, detecting one or more signal absences in the high-side PM signal or the low-side PM signal for a corresponding half-bridge of the plurality of half-bridges and generating a fault signal in response to detecting the one or more signal absences.

[0109] Item 21 - A system comprising: a three-phase motor; a plurality of half-bridge circuits, each comprising a high-side power switch and a low-side power switch arranged in a half-bridge configuration, wherein each half-bridge circuit controls a corresponding phase of the three-phase motor; for each half-bridge circuit of the plurality of half-bridge circuits, a corresponding driver circuit is configured to control the high-side power switch and the low-side power switch; and a processor configured to generate a control signal for each corresponding driver circuit in the corresponding driver circuits, wherein: each corresponding driver circuit in the corresponding driver circuits comprises: a logic circuit configured to monitor a high-side pulse modulation (PM) signal and a low-side PM signal, wherein the high-side PM signal and the low-side PM signal are configured to turn on and off the high-side power switch and the low-side power switch in a complementary manner, and wherein the logic circuit is configured to detect one or more signal absences in the high-side PM signal or the low-side PM signal and generate a fault signal in response to detecting the one or more signal absences.

[0110] Clause 22 – A system according to clause 21, wherein for each respective one of the respective driver circuits: the high-side driver is configured to generate a high-side PM drive signal based on a high-side PM control signal output from a digital core connected to the processor, the low-side driver is configured to generate a low-side PM drive signal based on a low-side PM control signal output from a digital core connected to the processor, and the logic circuit is configured to monitor the PM control signal and detect one or more signal absences in the high-side PM signal or the low-side PM signal based on monitoring the PM control signal.

[0111] Clause 23 – A system according to clause 21, wherein each of the respective driver circuits includes a level shifter circuit, wherein for each of the respective driver circuits: the high-side driver is configured to generate a high-side PM drive signal based on a high-side PM control signal output from a digital core connected to the processor, the low-side driver is configured to generate a low-side PM drive signal based on a low-side PM control signal output from a digital core connected to the processor, the level shifter circuit is configured to generate a level-shifted version of the high-side PM drive signal and a level-shifted version of the low-side PM drive signal, and the logic circuit is configured to: monitor the level-shifted version of the high-side PM drive signal and the level-shifted version of the low-side PM drive signal, and detect one or more signal absences in the high-side PM signal or the low-side PM signal based on monitoring the level-shifted version of the high-side PM drive signal and the level-shifted version of the low-side PM drive signal.

[0112] Various features and aspects have been described in this disclosure. These and other features and aspects are within the scope of the following claims.

Claims

1. A driver circuit, the driver circuit being configured to control a high-side power switch and a low-side power switch arranged in a half-bridge configuration, the driver circuit comprising: a high-side driver configured to drive a gate of the high-side power switch based on a high-side pulse modulated PM signal; a low-side driver configured to drive a gate of the low-side power switch based on a low-side PM signal; as well as a logic circuit configured to monitor the high-side PM signal and the low-side PM signal, wherein the high-side PM signal and the low-side PM signal are configured to switch on and off the high-side power switch and the low-side power switch in a complementary manner, and The logic circuit is configured to detect a signal absence of one or more of the high-side PM signal or the low-side PM signal, and generate a fault signal in response to detecting the signal absence of one or more of the high-side PM signal or the low-side PM signal. 2 . The driver circuit of claim 1 , wherein the logic circuit is configured to communicate the fault signal to a processor.

3. The driver circuit according to claim 1, wherein the high-side driver is configured to generate a high-side PM driving signal based on a high-side PM control signal output from the digital core, wherein the low-side driver is configured to generate a low-side PM driving signal based on a low-side PM control signal output from the digital core, and The logic circuit is configured to monitor a PM control signal and detect the one or more signal absences in the high-side PM signal or the low-side PM signal based on monitoring the PM control signal. 4 . The driver circuit of claim 3 , wherein the PM control signal comprises an input signal from a processor to the digital core. 5 . The driver circuit of claim 3 , wherein the PM control signal comprises the high-side PM control signal output from the digital core to the high-side driver and the low-side PM control signal output from the digital core to the low-side driver.

6. The driver circuit according to claim 1, further comprising a level shifter circuit, wherein the high-side driver is configured to generate a high-side PM driving signal based on a high-side PM control signal output from the digital core, wherein the low-side driver is configured to generate a low-side PM driving signal based on a low-side PM control signal output from the digital core, wherein the level shifter circuit is configured to generate a level-shifted version of the high-side PM drive signal and a level-shifted version of the low-side PM drive signal, and The logic circuit is configured to monitor the level-shifted version of the high-side PM drive signal and the level-shifted version of the low-side PM drive signal, and detect one or more signal absences in the high-side PM signal or the low-side PM signal based on monitoring the level-shifted version of the high-side PM drive signal and the level-shifted version of the low-side PM drive signal.

7. The driver circuit of claim 1 , wherein the logic circuit comprises a counter configured to count consecutive signal absences in the high-side PM signal or the low-side PM signal, and the logic circuit generates the fault signal in response to a count value of the counter reaching a count threshold. The driver circuit of claim 7 , wherein the count threshold is greater than 1 and less than 8. 9 . The driver circuit of claim 8 , wherein the count threshold is 3. 10 . The driver circuit of claim 1 , further comprising a plurality of high-side drivers and a plurality of low-side drivers configured to control a plurality of half-bridges.

11. The driver circuit of claim 10, wherein the plurality of half-bridges are configured to control a multi-phase motor.

12. The driver circuit of claim 11 , wherein for each half-bridge of the plurality of half-bridges, the driver circuit comprises a corresponding logic circuit, the corresponding logic circuit being configured to: detect one or more signal absences in the high-side PM signal or the low-side PM signal for a corresponding half-bridge of the plurality of half-bridges, and generate the fault signal in response to detecting the one or more signal absences.

13. A method of controlling a high-side power switch and a low-side power switch arranged in a half-bridge configuration, the method comprising: Driving the gate of the high-side power switch based on the high-side pulse modulated PM signal; driving a gate of the low-side power switch based on a low-side PM signal; as well as monitoring the high-side PM signal and the low-side PM signal, wherein the high-side PM signal and the low-side PM signal are configured to switch on and off the high-side power switch and the low-side power switch in a complementary manner, and Monitoring includes: detecting one or more signal absences in the high-side PM signal or the low-side PM signal; as well as A fault signal is generated in response to detecting the absence of the one or more signals.

14. The method according to claim 13, further comprising: The fault signal is transmitted to a processor.

15. The method according to claim 13, wherein the high-side driver is configured to generate a high-side PM driving signal based on a high-side PM control signal output from the digital core, wherein the low-side driver is configured to generate a low-side PM driving signal based on a low-side PM control signal output from the digital core, and Wherein monitoring the high-side PM signal and the low-side PM signal comprises: monitoring a PM control signal; and detecting the one or more signal absences in the high-side PM signal or the low-side PM signal based on monitoring the PM control signal.

16. The method according to claim 13, wherein the high-side driver is configured to generate a high-side PM driving signal based on a high-side PM control signal output from the digital core, wherein the low-side driver is configured to generate a low-side PM driving signal based on a low-side PM control signal output from the digital core, wherein the level shifter circuit is configured to generate a level-shifted version of the high-side PM drive signal and a level-shifted version of the low-side PM drive signal, and Wherein monitoring the high-side PM signal and the low-side PM signal comprises: The level-shifted version of the high-side PM drive signal and the level-shifted version of the low-side PM drive signal are monitored, and one or more signal absences in the high-side PM signal or the low-side PM signal are detected based on monitoring the level-shifted version of the high-side PM drive signal and the level-shifted version of the low-side PM drive signal.

17. The method according to claim 13, further comprising: maintaining a count value indicating consecutive signal absences in the high-side PM signal or the low-side PM signal; as well as The fault signal is generated in response to the count value reaching a count threshold. The method of claim 17 , wherein the count threshold is greater than 1 and less than 6.

19. The method of claim 13, wherein the method comprises controlling a plurality of high-side drivers and a plurality of low-side drivers configured to control a plurality of half-bridges configured to control a multi-phase motor.

20. The method according to claim 19, further comprising: For each of the plurality of half-bridges, one or more signal absences in the high-side PM signal or the low-side PM signal are detected for a corresponding half-bridge in the plurality of half-bridges, and the fault signal is generated in response to detecting the one or more signal absences.

21. A system comprising: Three-phase motor; a plurality of half-bridge circuits including high-side power switches and low-side power switches arranged in a half-bridge configuration, wherein each of said half-bridge circuits controls a respective phase of said three-phase motor; For each half-bridge circuit of the plurality of half-bridge circuits, a corresponding driver circuit is configured to control the high-side power switch and the low-side power switch; as well as a processor configured to generate a control signal for each of the respective driver circuits, wherein: Each of the respective driver circuits comprises: A logic circuit configured to monitor the high-side pulse modulated PM signal and the low-side PM signal, wherein the high-side PM signal and the low-side PM signal are configured to switch on and off the high-side power switch and the low-side power switch in a complementary manner, and Wherein the logic circuit is configured to detect one or more signal absences in the high-side PM signal or the low-side PM signal and generate a fault signal in response to detecting the one or more signal absences.

22. The system of claim 21 , wherein for each of the respective driver circuits: The high-side driver is configured to generate a high-side PM drive signal based on a high-side PM control signal output from a digital core connected to the processor, The low-side driver is configured to generate a low-side PM drive signal based on a low-side PM control signal output from the digital core connected to the processor, and The logic circuit is configured to monitor a PM control signal and detect the one or more signal absences in the high-side PM signal or the low-side PM signal based on monitoring the PM control signal.

23. The system of claim 21 , wherein each of the respective driver circuits comprises a level shifter circuit, wherein for each of the respective driver circuits: The high-side driver is configured to generate a high-side PM drive signal based on a high-side PM control signal output from a digital core connected to the processor, a low-side driver configured to generate a low-side PM drive signal based on a low-side PM control signal output from the digital core connected to the processor, The level shifter circuit is configured to generate a level-shifted version of the high-side PM drive signal and a level-shifted version of the low-side PM drive signal, and The logic circuit is configured to monitor the level-shifted version of the high-side PM drive signal and the level-shifted version of the low-side PM drive signal, and detect one or more signal absences in the high-side PM signal or the low-side PM signal based on monitoring the level-shifted version of the high-side PM drive signal and the level-shifted version of the low-side PM drive signal.

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