Multi-core oscillator

Abstract

The invention discloses a multi-core oscillator. The multi-core oscillator comprises N oscillation cores, N first inductors, N second inductors and N third inductors, every two adjacent oscillation cores are directly synchronized through the coupling relationship between the second inductor and the third inductor; the middle point where each second inductor and each third inductor are connected is connected with a first power supply through a first resistor, so that every two non-adjacent oscillation cores are directly synchronized through the out-of-phase relation between the two ends of the second inductor and the two ends of the third inductor; and the middle point of each first inductor is connected with a second power supply through a second resistor, so that every two adjacent oscillation cores are directly synchronized through the out-of-phase relationship between the two ends of the first inductor. According to the embodiment of the invention, the problem of phase noise loss caused by frequency mismatching between the oscillator cores is relieved, and the quality factor is improved. The oscillator can be widely applied to the technical field of oscillators.

Description

Technical Field

[0001] The present invention relates to the technical field of oscillators, in particular to a multi-core oscillator. Background Art

[0002] The use of advanced modulation schemes in the 60 GHz band requires the local oscillator to have extremely low phase noise. In addition, a high FoM is critical to minimize the power consumption of the local oscillator and improve the overall system efficiency. Due to the small area of ​​the LC resonant cavity at such high frequencies, coupling multiple oscillators to reduce phase noise becomes a viable solution. In related technologies, a compact area is achieved by laying out and placing multi-core oscillators. However, the frequency mismatch between the oscillator cores will cause phase noise loss and reduce the quality factor (Figure-of-Merit, FoM). Summary of the invention

[0003] The purpose of the present invention is to solve one of the technical problems existing in the prior art to at least a certain extent.

[0004] Therefore, an object of the present invention is to provide a multi-core oscillator with low phase noise.

[0005] In order to achieve the above technical objectives, the technical solutions adopted by the embodiments of the present invention include the following aspects:

[0006] On the one hand, an embodiment of the present invention provides a multi-core oscillator, comprising: N oscillation cores, N first inductors, N second inductors and N third inductors; wherein N is an even number greater than or equal to 4; the N oscillation cores are arranged in a ring; the first drain terminal of each oscillation core is connected to the second drain terminal of an adjacent oscillation core through the first inductor; the second gate terminal of each oscillation core is connected to the first gate terminal of a non-adjacent oscillation core through the second inductor and the third inductor; every two adjacent oscillation cores are directly synchronized through the coupling relationship between the second inductor and the third inductor; the middle point where each second inductor and each third inductor are connected is connected to a first power supply through a first resistor, so that every two non-adjacent oscillation cores are directly synchronized through the out-of-phase relationship between the second inductor and the third inductor; the middle point of each first inductor is connected to a second power supply through a second resistor, so that every two adjacent oscillation cores are directly synchronized through the out-of-phase relationship between the two ends of the first inductor. The embodiment of the present application uses the coupling relationship between inductors and the setting of the second resistor to provide a topology of a multi-core oscillator through three synchronization paths, which is beneficial for alleviating the phase noise loss problem caused by frequency mismatch between oscillator cores and improving the quality factor.

[0007] In addition, the multi-core oscillator according to the above embodiment of the present invention may also have the following additional technical features:

[0008] Furthermore, in the multi-core oscillator of the embodiment of the present invention, each oscillation core includes: a first NMOS transistor, a second NMOS transistor and a switch capacitor;

[0009] The first drain terminal of the oscillation core is connected to the second drain terminal of the oscillation core through the switching capacitor; the first gate terminal of the oscillation core is connected to the gate of the first NMOS tube, and the second gate terminal of the oscillation core is connected to the gate of the second NMOS tube; the first drain terminal of the oscillation core is connected to the drain of the first NMOS tube, and the second drain terminal of the oscillation core is connected to the drain of the second NMOS tube; the source of the first NMOS tube and the source of the second NMOS tube are both grounded.

[0010] Further, in an embodiment of the present invention, a value corresponding to the coupling coefficient between the first inductor and the second inductor is a first value, a value corresponding to the coupling coefficient between the first inductor and the third inductor is a second value, and the first value and the second value are different.

[0011] Further, in an embodiment of the present invention, the second inductor and the third inductor have different Q values.

[0012] Further, in an embodiment of the present invention, the resistance of the second resistor is 1 to 50 ohms.

[0013] Further, in an embodiment of the present invention, the second inductor is implemented by a coil and a metal layer, or the third inductor is implemented by a coil and a metal layer.

[0014] Furthermore, in one embodiment of the present invention, the multi-core oscillator includes a plurality of oscillator group structures, each oscillator group structure includes N oscillator cores; and the plurality of oscillator group structures are arranged in a ring shape.

[0015] The two adjacent oscillator cores in each two adjacent oscillator group structures are connected, the first drain terminals of the two adjacent oscillator cores are interconnected, and the second drain terminals of the two adjacent oscillator cores are interconnected, so that the adjacent oscillator group structures are directly synchronized.

[0016] Further, in one embodiment of the present invention, the first oscillator group structure and the second oscillator group structure, the first oscillator group structure and the second oscillator group structure are any two different oscillator group structures;

[0017] The first oscillator group structure includes a first oscillator core, and the second oscillator group structure includes a second oscillator core; the first drain terminal of the first oscillator core is connected to the first drain terminal of the second oscillator core, and the second drain terminal of the first oscillator core is connected to the second drain terminal of the second oscillator core; so that all oscillator group structures are directly synchronized.

[0018] Furthermore, in one embodiment of the present invention, the first drain terminals of two adjacent oscillation cores are interconnected through a metal wire.

[0019] On the other hand, an embodiment of the present invention provides a satellite communication system, comprising the multi-core oscillator as described above.

[0020] The multi-core oscillator provided by the embodiment of the present invention includes: N oscillation cores, N first inductors, N second inductors and N third inductors; wherein N is an even number greater than or equal to 4; the N oscillation cores are arranged in a ring; the first drain terminal of each oscillation core is connected to the second drain terminal of an adjacent oscillation core through the first inductor; the second gate terminal of each oscillation core is connected to the first gate terminal of a non-adjacent oscillation core through the second inductor and the third inductor; every two adjacent oscillation cores are directly synchronized through the coupling relationship between the second inductor and the third inductor; the middle point where each second inductor and each third inductor are connected is connected to the first power supply through a first resistor, so that every two non-adjacent oscillation cores are directly synchronized through the out-of-phase relationship between the second inductor and the third inductor; the middle point of each first inductor is connected to the second power supply through a second resistor, so that every two adjacent oscillation cores are directly synchronized through the out-of-phase relationship between the two ends of the first inductor. The embodiment of the present application uses the coupling relationship between inductors and the setting of the second resistor to provide a topology of a multi-core oscillator through three synchronization paths, which is beneficial for alleviating the phase noise loss problem caused by frequency mismatch between oscillator cores and improving the quality factor. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the embodiments of the present invention or the drawings of related technical solutions in the prior art are introduced below. It should be understood that the drawings introduced below are only for the convenience of clearly describing some embodiments of the technical solutions of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0022] Figure 1 A schematic diagram of the structure of a multi-core oscillator provided for related technology;

[0023] Figure 2A schematic structural diagram of an embodiment of a multi-core oscillator provided by the present invention;

[0024] Figure 3 A comparison diagram of phase noise loss simulation results of the related art solution and the multi-core oscillator proposed in this application when there is a frequency mismatch;

[0025] Figure 4 A schematic diagram of the topological structure of an embodiment of a multi-core oscillator of a 4-core group provided by the present invention;

[0026] Figure 5 for Figure 4 A schematic diagram of one embodiment of an oscillator core in the illustrated embodiment;

[0027] Figure 6 A schematic diagram of simulation results of drain and gate voltages of a multi-core oscillator in related technology;

[0028] Figure 7 A schematic diagram of the simulation results of the drain and gate voltages of the multi-core oscillator proposed in this application;

[0029] Figure 8 A schematic diagram of the topological structure of an embodiment of the oscillator group structure proposed in this application;

[0030] Fig. 9 An equivalent schematic diagram of an embodiment of a multi-core oscillator proposed in this application;

[0031] Fig.10 A schematic diagram of electromagnetic simulation results of the inductance of the multi-core oscillator proposed in this application;

[0032] Fig.11 A physical diagram of an embodiment of a chip based on a multi-core oscillator proposed in this application;

[0033] Fig.12 The phase noise curve of the multi-core oscillator proposed in this application at a frequency of 65.11 GHz;

[0034] Fig.13 The phase noise curve of the multi-core oscillator proposed in this application at a frequency of 54.59 GHz;

[0035] Fig.14 The phase noise curve of the multi-core oscillator proposed in this application within the full frequency range;

[0036] Fig.15 This is the FoM curve of the multi-core oscillator proposed in this application within the full frequency range;

[0037] Fig.16 Phase noise and FoM at 10 MHz offset TA comparison chart with the related art oscillator in the 60 GHz frequency band;

[0038] Fig.17 A comparison chart with other related-art multi-core oscillators and frequency generators operating between 20 and 100 GHz. DETAILED DESCRIPTION

[0039] The embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be construed as limitations on the present invention. In the description of the present application, it should be noted that if the terms "upper", "lower", etc. indicate an orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or are the orientation or positional relationship in which the application product is usually placed when used, it is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be construed as a limitation on the present application.

[0040] In addition, the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0041] In the description of this application, it should also be noted that, unless otherwise clearly specified and limited, the terms "disposed" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection, it can be a direct connection, it can be an indirect connection through an intermediate medium, and it can be the internal communication of two elements. For those skilled in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0042] Advanced modulation schemes used in the 60 GHz band require local oscillators with extremely low phase noise. In addition, a high FoM is critical to minimize the power consumption of the local oscillator and improve the overall system efficiency. Due to the small area of ​​the LC resonant cavity at such high frequencies, coupling multiple oscillators to reduce phase noise becomes a feasible solution. In some embodiments, reference Figure 1 As shown in Figure 1, a 60 GHz 16-core oscillator is proposed to achieve low phase noise. Figure 1 The layout shown is placed to achieve a compact area. However, the frequency mismatch between the oscillator cores will degrade the phase noise and FoM, especially for two cores with a long synchronization path. For example, core #1 and #2, there are 7 oscillator cores in the synchronization path between them. The frequency mismatch between core #1 and #2 needs to be eliminated through a very long link, which will cause severe phase noise or FoM loss.

[0043] It is understandable that the phase noise or FoM loss can be effectively reduced by directly synchronizing non-adjacent cores. To this end, the present application proposes a 60 GHz 16-core oscillator with a multi-path synchronization topology, such as Figure 2 As shown. The proposed topology can reduce the phase noise loss caused by the frequency mismatch between the oscillator cores while still maintaining a compact area. Simulations show that the proposed multipath synchronization topology can reduce the phase noise loss to only 0.1 dB when the frequency mismatch between cores #1 and #2 is 3%; while the embodiment of the above-mentioned related art has a phase noise loss of 6.6 dB under a 3% frequency mismatch. The simulation results refer to Figure 3 shown. Figure 1 and Figure 2 The designs of the middle topology all use NMOS cross-coupled pairs as negative resistance units.

[0044] Specifically, the oscillator proposed in the embodiment of the present application is manufactured using a 65-nanometer CMOS process, and achieves a low phase noise of -131.4 dBc / Hz, a high FoM of 190.9 dBc / Hz, and a high FoMT of 195.8 dBc / Hz at a 10-MHz offset of 65.11 GHz. The average phase noise and FoM changes at a 10-MHz offset measured on 5 chips are only 0.5 and 0.4 dB, respectively. This result verifies that the proposed multipath synchronization topology has a small phase noise and FoM loss.

[0045] The following describes in detail a multi-core oscillator according to an embodiment of the present invention. The multi-core oscillator provided by an embodiment of the present application includes:

[0046] N oscillating cores, N first inductors, N second inductors and N third inductors; wherein N is an even number greater than or equal to 4; the N oscillating cores are arranged in a ring;

[0047] The first drain terminal of each oscillating core is connected to the second drain terminal of an adjacent oscillating core through the first inductor; the second gate terminal of each oscillating core is connected to the first gate terminal of a non-adjacent oscillating core through the second inductor and the third inductor;

[0048] Every two adjacent oscillation cores are directly synchronized through the coupling relationship between the second inductor and the third inductor; the middle point where each of the second inductor and each of the third inductors are connected is connected to the first power supply through a first resistor, so that every two non-adjacent oscillation cores are directly synchronized through the out-of-phase relationship between the second inductor and the third inductor;

[0049] The middle point of each of the first inductors is connected to the second power supply via a second resistor, so that every two adjacent oscillation cores are directly synchronized through the out-of-phase relationship between the two ends of the first inductor.

[0050] Reference Figure 4 As shown, taking a quad-core group as an example, the multi-core oscillator provided by the present application is introduced, with a total of 4 oscillation cores, 4 first inductors, and arranged at Figure 4 4 second inductors, and 4 third inductors. The second inductors and the third inductors are set at Figure 4 The blue dotted line in the G ) or the position outlined by the red dotted line (L G2 ) at the position. The present application does not limit the specific positions of the second inductor and the third inductor. N is an even number greater than or equal to 4. In some embodiments, N is 4 n . Reference Figure 5 The schematic diagram of the oscillator core shown in the figure shows that each oscillator core includes four ports, namely V GNX 、V GPX 、V DPX 、V DNX Among them, G indicates that the port is connected to the gate of the field effect tube in the oscillator core. Similarly, the specific drain or gate port of the field effect tube connected to N and P, for the 4-core group, X can be 1 / 2 / 3 / 4. Therefore, V DPX That is, the first drain terminal in the embodiment of the present application, V DNX That is, the second drain terminal in the embodiment of the present application, V GPX That is, the first gate terminal in the embodiment of the present application, V GNX That is, the second gate terminal in the embodiment of the present application. For any oscillator core, the upper left port is V DNX , the upper right port is V DPX , the lower left port is V GPX , the lower right port is V GNX The embodiment of the present application provides three synchronization paths. Each two adjacent oscillation cores are directly synchronized through the coupling relationship between the second inductor and the third inductor, that is, path 2; each intermediate point where the second inductor and each third inductor are connected is connected through a first resistor R C Connect the first power supply VB , so that each two non-adjacent oscillation cores are directly synchronized through the out-of-phase relationship between the second inductor and the third inductor; that is, path 1. In addition, the middle point of each first inductor is connected through a second resistor R S Connect the second power supply V DD , so that every two adjacent oscillating cores are directly synchronized through the out-of-phase relationship between the two ends of the first inductor, that is, path 3. It can be understood that the embodiment of the present application includes N first resistors and N second resistors, so that path 1 and path 3 are formed between every two oscillating cores. In some embodiments, path 3 can be formed by adding a second resistor R at the center of the first inductor at the drain. S to achieve.

[0051] Optionally, in the multi-core oscillator in the embodiment of the present invention, each oscillation core includes: a first NMOS transistor, a second NMOS transistor and a switch capacitor;

[0052] The first drain terminal of the oscillation core is connected to the second drain terminal of the oscillation core through the switching capacitor; the first gate terminal of the oscillation core is connected to the gate of the first NMOS tube, and the second gate terminal of the oscillation core is connected to the gate of the second NMOS tube; the first drain terminal of the oscillation core is connected to the drain of the first NMOS tube, and the second drain terminal of the oscillation core is connected to the drain of the second NMOS tube; the source of the first NMOS tube and the source of the second NMOS tube are both grounded.

[0053] It is understandable that when the frequency increases to the 60 GHz band, the Q value of the switched capacitor array will drop significantly, resulting in deterioration of phase noise and FoM performance. In order to alleviate this problem, in each oscillator core of the present application, only the drain switched capacitor array ( Figure 5 ). By removing the low-Q switched capacitor array from the gate, the Q of the transformer-based resonant cavity can be improved, which is beneficial for improving phase noise and FoM performance.

[0054] Optionally, in the multi-core oscillator in the embodiment of the present invention, the value corresponding to the coupling coefficient of the first inductor and the second inductor is a first value, the value corresponding to the coupling coefficient of the first inductor and the third inductor is a second value, and the first value and the second value are different.

[0055] Optionally, in the multi-core oscillator in the embodiment of the present invention, the second inductor and the third inductor have different Q values.

[0056] Optionally, in the multi-core oscillator in the embodiment of the present invention, the resistance of the second resistor is 1 to 50 ohms.

[0057] In some possible implementations, the second resistor R S If the resistance of is large enough, the out-of-phase relationship between the two ends of the drain inductor can be ensured, thereby directly synchronizing two adjacent cores. In some embodiments, the second resistor can be selected to be 10 ohms.

[0058] Optionally, in the multi-core oscillator in the embodiment of the present invention, the second inductor is implemented by a coil and a metal layer, or the third inductor is implemented by a coil and a metal layer.

[0059] In some possible implementations, the gate electrode L G2 The partial inductance of is realized by using the metal layer M8. Therefore, the two gate inductors LG and LG2 (ie, the second inductor and the third inductor) not only have different Q values, but also have different coupling coefficients with the drain inductor (ie, the first inductor).

[0060] Optionally, the multi-core oscillator in the embodiment of the present invention includes a plurality of oscillator group structures, each oscillator group structure includes N oscillation cores; the plurality of oscillator group structures are arranged in a ring shape;

[0061] The two adjacent oscillator cores in each two adjacent oscillator group structures are connected, the first drain terminals of the two adjacent oscillator cores are interconnected, and the second drain terminals of the two adjacent oscillator cores are interconnected, so that the adjacent oscillator group structures are directly synchronized.

[0062] In some possible implementations, the multi-core oscillator in the embodiment of the present application may be composed of multiple core groups, each core group being the oscillator group structure in the embodiment of the present application. In some embodiments, the oscillator group structure in the embodiment of the present application may be Figure 4 The oscillator shown in FIG. 1 is composed of four oscillator cores to form an oscillator group structure. Then, multiple oscillator group structures are arranged in a ring in sequence to form Figure 8 Another form of multi-core oscillator is shown. Figure 8 For example, a multi-core oscillator is formed by a topological structure of 4 oscillator groups (the multi-core oscillator has a total of 16 oscillator cores). The two adjacent oscillator cores in each two adjacent oscillator group structures are connected, the first drain terminals of the two adjacent oscillator cores are interconnected, and the second drain terminals of the two adjacent oscillator cores are interconnected. Even the in-phase drains of the two oscillator cores in the adjacent groups are connected to form path 4. It can be understood that Figure 4 and Figure 8 The multi-core oscillator shown is an exemplary example, and the embodiment of the present application does not limit the number of oscillator cores of the multi-core oscillator and the number of groups of oscillator group structures. In some embodiments, the multi-core oscillator can be divided into 4 groups of oscillator group structures, each group of oscillator group structures includes 4 n Oscillator cores, the multi-core oscillator includes a total of 4n+1 An oscillating core.

[0063] Optionally, the multi-core oscillator in the embodiment of the present invention includes: a first oscillator group structure and a second oscillator group structure, wherein the first oscillator group structure and the second oscillator group structure are any two different oscillator group structures;

[0064] The first oscillator group structure includes a first oscillator core, and the second oscillator group structure includes a second oscillator core; the first drain terminal of the first oscillator core is connected to the first drain terminal of the second oscillator core, and the second drain terminal of the first oscillator core is connected to the second drain terminal of the second oscillator core; so that all oscillator group structures are directly synchronized.

[0065] In some possible implementations, the first oscillator group structure and the second oscillator group structure are any two different oscillator group structures. Figure 8 A multi-core oscillator is shown in FIG. 1 . The multi-core oscillator in this example includes a total of 4 oscillator group structures. Figure 8 For example, the first oscillator group structure and the second oscillator group structure in the embodiment of the present application are used to characterize four oscillator group structures. For the four oscillator group structures, the first drain terminal of any oscillation core in each oscillator group structure is connected to the first drain terminal of any oscillation core in other oscillator group structures, and the second drain terminal of any oscillation core in each oscillator group structure is connected to the second drain terminal of any oscillation core in other oscillator group structures, so that all oscillator group structures are directly synchronized. That is, the first oscillation core in the embodiment of the present application is any oscillation core of the first oscillator group structure, and the second oscillation core is any oscillation core of the second oscillator group structure. Refer to Figure 8 As shown, all oscillator group structures are directly synchronized to form path 5.

[0066] Optionally, in the multi-core oscillator in the embodiment of the present invention, the first drain terminals of two adjacent oscillation cores are interconnected by a metal wire.

[0067] The multi-core oscillator provided in the embodiment of the present application is described in detail below:

[0068] First, the three-path synchronous quad-core group (ie, oscillator group structure) proposed in the embodiment of the present application is introduced.

[0069] For simplicity, we divide the 16 oscillator cores into 4 groups (4 cores in each group). Figure 2 As shown, the four cores within each dotted line form a group. First, we introduce the proposed three-path synchronized quad-core oscillator design in each group.

[0070] When the frequency increases to the 60 GHz band, the Q value of the switched capacitor array (i.e., switched capacitor) in the oscillator core will drop significantly, causing the phase noise and FoM performance to deteriorate. To alleviate this problem, only the drain switched capacitor array ( Figure 5 ). By removing the low-Q switched capacitor array from the gate, the Q of the transformer-based resonant cavity can be improved, which is beneficial for improving phase noise and FoM performance.

[0071] Figure 4 The topology of a group with four oscillator cores is given. With the first resistor R in the center of the gate inductance C , non-adjacent cores (e.g. cores #1 and #3) can be directly synchronized via path 1. In addition, thanks to the strong coupling between the gate inductors (the second inductor and the third inductor), adjacent cores (e.g. cores #1 and #2) can be directly synchronized via path 2. Therefore, for a 25 GHz oscillator, directly synchronizing all four cores can effectively reduce the phase noise loss caused by the frequency mismatch between the cores. However, when the frequency increases to the 60 GHz band, the original two paths are not sufficient to suppress the phase noise loss. Figure 4 As shown, the second inductor or the third inductor L at the gate G2 The partial inductance of is realized by using metal layer M8. Therefore, the two gate inductors L G and L G2 Not only is the Q value different, but the coupling coefficient with the drain inductance is also different. It can be understood that L G2 The inductance of the gate is much larger than the inductance of the underlying metal, so the mismatch caused is negligible at 25 GHz. However, since the gate inductance used around 60 GHz is much smaller and the length of the underlying metal does not decrease with frequency, the mismatch caused around 60 GHz becomes non-negligible. Figure 6 As shown, even without intentionally introducing a frequency mismatch, there is a large variation in the voltage amplitude at the drain and gate between adjacent cores (eg, cores #1 and #2).

[0072] To alleviate this problem, we propose a three-path synchronous quad-core topology by introducing a new path ( Figure 4 Path 3) in the figure can be used to further synchronize adjacent cores. Similar to path 1, if the second resistor R S If the second resistor R is large enough, the out-of-phase relationship between the two ends of the drain inductance can be ensured, thereby directly synchronizing the two adjacent cores. S should not be too large, since the DC current will flow through the second resistor R S , resulting in the second resistor R S The voltage across the two ends drops and increases power consumption. In this design, the second resistor R SThe second resistor R is 10 ohms to minimize S The simulation results ( Figure 7 ) shows that the voltage amplitude variation between adjacent cores can be significantly reduced. Simulation results show that the proposed topology can reduce the phase noise loss by 0.5 dB when a 2.5% frequency mismatch is introduced between adjacent cores.

[0073] Figure 8 The proposed 16-core oscillator with the above four groups is shown. Here, we introduce two new paths to synchronize the four groups. First, in order to directly synchronize adjacent groups, in path 4, the in-phase drains of the two oscillator cores in adjacent groups (e.g., groups #1 and #2) are connected by a thin metal wire. In addition, in path 5, the in-phase drains of the central four oscillator cores are also connected by a thin metal wire to directly synchronize the four groups. Therefore, all four groups are directly synchronized, which is beneficial to reduce the phase noise loss caused by the frequency mismatch between the cores. Unlike the first three paths, the voltages at both ends of path 4 or 5 are in phase. Based on the above-proposed technology, the degradation of phase noise and FoM performance caused by frequency mismatch can be kept at a small level. By adopting the five synchronization paths described above, the four groups and the four oscillator cores within each group can be directly synchronized.

[0074] The specific simulation process is as follows:

[0075] The schematic diagram of the proposed quad-core group can be equivalent to a dual-core oscillator, as shown in Fig. 9 The dimensions of the cross-coupled transistors in each oscillator are chosen to be 17 microns wide and 60 nanometers long, respectively, to provide negative resistance to maintain oscillation. To tune the frequency, the adjustable capacitor C D It is implemented using a 4-bit binary switched capacitor array.

[0076] Figure 4 The layout of the quad-core oscillator is shown. Based on the electromagnetic simulation results ( Fig.10 , electromagnetic simulation results of inductance and Q value), the inductance of the transformer is the first inductance L D =60.8 phenry, the second inductor L G =46.9 phenry, the third inductor L G2 =47.2 picohenry, and the corresponding quality factors are Q LD =37.7, Q LG =33.2, Q LG2 =28.8 (at 60 GHz). The coupling coefficient is k1=0.594 (i.e., the first inductor L in the embodiment of the present application) D and the second inductor L G The first value corresponding to the coupling coefficient between them), k1=0.59 (that is, the first inductor L in the embodiment of the present application D and the third inductor LG2 The second value of the coupling coefficient between the two) and k2 (the second inductance L G and the third inductor L G2 =0.68 (at 60 GHz). Electromagnetic simulation results confirm that due to the presence of the lower metal layer, the second inductor L G and the third inductor L G2 are not the same, which will inevitably introduce frequency mismatch. Of course, in the above example, the second inductor is L G and the third inductor is L G2 In some other embodiments, the third inductor may be L G , the second inductor can be L G2 .

[0077] Choose a small resistor R of 20 ohms C , to effectively synchronize non-adjacent cores in path 1. With path 3 (the second resistor R S =10 ohms) and path 2 (k2 = 0.68), the proposed three-path synchronization topology can effectively synchronize the quad-core group, so when Figure 2 A 3% frequency mismatch between cores #1 and #2 results in only a 0.1 dB phase noise penalty at a 10 MHz offset.

[0078] The metal traces used to synchronize the four groups in paths 4 and 5 are optimized to be as close as possible. In addition, metal layers M9 and M8 are used to implement the traces to reduce parasitic resistance. Electromagnetic simulation results show that the metal traces in path 4 behave as an inductance of 102.5 picohenry cascaded with a resistance of 1.91 ohms. In path 5, the metal traces between any two groups behave as an inductance of 115.8 picohenry cascaded with a resistance of 2.01 ohms. In the post-simulation, all metal traces in these two paths are taken into account. Simulation results show that all metal traces together cause a 0.2 dB phase noise reduction at a 10 MHz offset.

[0079] In this design, the DC power supply structure needs to be carefully optimized, especially Figure 8 To ensure good DC bias, the drain port V DD and gate port V B The decoupling capacitors are placed in the center of these four cores. Metal layers M9 and AP are used to provide V DD and V B DC bias is applied to minimize voltage drops on metal traces.

[0080] As with the multi-core oscillator in the related art, the total area of ​​the four groups in this structure is about five times that of one group. The compact area is conducive to expansion to more oscillator cores to achieve lower phase noise. For example, if we regard the proposed 16-core oscillator as a new group and use paths 4 and 5 to connect four such new groups as Figure 8 By synchronizing them together, we can achieve a 64-core oscillator with multipath synchronization. The phase noise can be further reduced by 6 dB, but at the cost of a 5x increase in chip area.

[0081] For the measurement / simulation results, the proposed multi-way synchronized 16-core oscillator is fabricated in 65 nm CMOS process. Fig.11 A micrograph of the chip is shown, with a core area of ​​0.22 square millimeters. The proposed oscillator consumes 47.85 to 67 milliwatts of power at a supply voltage of 0.55 volts. Fig.12 and Fig.13 As shown, the oscillator achieves phase noise of -131.36dBc / Hz and -130.96dBc / Hz at the highest frequency of 65.11 GHz and the lowest frequency of 54.59 GHz, respectively. Fig.14 and Fig.15 The phase noise and FoM measured over the frequency tuning range are plotted. The phase noise at 10 MHz offset varies from -131.4 to -130.3 dBc / Hz, and the corresponding FoM varies from 190.9 to 187.5 dBc / Hz. The corresponding FoM at 17.6% of the frequency tuning range is T The variation range is from 195.8 to 192.4 dBc / Hz. Thanks to the multipath synchronization topology, the average variation of phase noise and FoM at 10 MHz offset in the 5 measurement chips is only 0.5 and 0.4 dB, respectively. This result verifies that the proposed design has small phase noise and FoM loss.

[0082] Based on the measurement results of the proposed oscillator, this work is compared with the state-of-the-art oscillators around 60 GHz. Compared with other 2-core and 4-core oscillators, this work achieves lower phase noise at 10 MHz offset. Compared with the 16-core oscillator in the related art, although the phase noise at 10 MHz offset is 1 dB higher when normalized to 60 GHz, the power consumption is reduced by 59-62 mW and the tuning range is 6.5% larger, so FoM T Compared to recently published fundamental oscillators above 50 GHz or frequency generators using harmonic extraction techniques, Fig.16 It is shown that the design has good phase noise and FoM T Achieved excellent performance in all aspects. Fig.17shows that the design achieves the highest FoM at 10 MHz offset compared to state-of-the-art multicore oscillators operating between 20 and 100 GHz T .

[0083] This paper introduces a 60 GHz multipath synchronized 16-core oscillator. By introducing more synchronization paths between the oscillator cores, the phase noise and FoM loss caused by the frequency mismatch between the oscillator cores can be effectively suppressed. The oscillator implemented in 65nm CMOS process achieves low phase noise of -131.4dBc / Hz, peak FoM of 190.9dBc / Hz and peak FoM of 195.8dBc / Hz at 10MHz offset from 65.11 GHz carrier, respectively. T .

[0084] This paper reports a 60 GHz oscillator that synchronizes 16 cores to reduce phase noise. The proposed multipath synchronization technique introduces more synchronization paths for any oscillator core in the array, which helps to keep the phase noise penalty caused by the frequency mismatch between oscillator cores low when the number of oscillator cores increases. Specifically, our 16-core oscillator is implemented by synchronizing 4 identical groups, each of which is implemented by a quad-core oscillator. The quad-core oscillator in each group is a topology with three synchronization paths, which helps to suppress the frequency mismatch between oscillator cores caused by the asymmetry of the transformer layout when the oscillation frequency increases. Fabricated in a 65 nm CMOS process, the 54.6 to 65.1 GHz oscillator achieves a low phase noise of -131.4 dBc / Hz at 65.11 GHz offset by 10 MHz, while achieving high FoM of 190.9 dBc / Hz and 195.8 dBc / Hz, respectively. T .

[0085] The multi-core oscillator provided in the embodiment of the present application includes: N oscillation cores, N first inductors, N second inductors and N third inductors; wherein N is an even number greater than or equal to 4; the N oscillation cores are arranged in a ring; the first drain terminal of each oscillation core is connected to the second drain terminal of an adjacent oscillation core through the first inductor; the second gate terminal of each oscillation core is connected to the first gate terminal of a non-adjacent oscillation core through the second inductor and the third inductor; every two adjacent oscillation cores are directly synchronized through the coupling relationship between the second inductor and the third inductor; the middle point where each second inductor and each third inductor are connected is connected to the first power supply through a first resistor, so that every two non-adjacent oscillation cores are directly synchronized through the out-of-phase relationship between the second inductor and the third inductor; the middle point of each first inductor is connected to the second power supply through a second resistor, so that every two adjacent oscillation cores are directly synchronized through the out-of-phase relationship between the two ends of the first inductor. The embodiment of the present application uses the coupling relationship between inductors and the setting of the second resistor to provide a topology of a multi-core oscillator through three synchronization paths, which is beneficial for alleviating the phase noise loss problem caused by frequency mismatch between oscillator cores and improving the quality factor.

[0086] It can be understood that the multi-core oscillator provided in the embodiment of the present application can be used in a variety of devices / products. In the communication field, it can be used for 5G communication, satellite communication, wireless local area network, etc.; in the radar field, it can be used for vehicles, security, etc.; it can also be used in the measurement field, medical field, etc., and the present application does not limit the specific application field.

[0087] On the other hand, an embodiment of the present invention provides a satellite communication system, comprising the multi-core oscillator as described above.

[0088] Similarly, the contents of the above-mentioned multi-core oscillator embodiment are applicable to the present satellite communication system embodiment. The functions specifically implemented by the present satellite communication system embodiment are the same as those of the above-mentioned multi-core oscillator embodiment, and the beneficial effects achieved are also the same as those achieved by the above-mentioned multi-core oscillator embodiment.

[0089] In some selectable embodiments, the function / operation mentioned in the block diagram may not occur in the order mentioned in the operation diagram. For example, depending on the function / operation involved, the two boxes shown in succession can actually be executed substantially simultaneously or the boxes can sometimes be executed in reverse order. In addition, the embodiment presented and described in the flow chart of the present invention is provided by way of example, for the purpose of providing a more comprehensive understanding of technology. The disclosed method is not limited to the operation and logic flow presented herein. Selectable embodiments are expected, wherein the order of various operations is changed and the sub-operation of a part for which is described as a larger operation is performed independently.

[0090] In addition, although the present invention is described in the context of functional modules, it should be understood that, unless otherwise specified, one or more of the functions and / or features can be integrated into a single physical device and / or software module, or one or more functions and / or features can be implemented in a separate physical device or software module. It is also understood that a detailed discussion of the actual implementation of each module is unnecessary for understanding the present invention. More specifically, in view of the properties, functions and internal relationships of the various functional modules in the device disclosed herein, the actual implementation of the module will be understood within the conventional skills of the engineer. Therefore, those skilled in the art can implement the present invention set forth in the claims without excessive experimentation using ordinary techniques. It is also understood that the specific concepts disclosed are merely illustrative and are not intended to limit the scope of the present invention, which is determined by the full scope of the appended claims and their equivalents.

[0091] The logic and / or steps represented in the flowchart or otherwise described herein, for example, may be considered as an ordered list of executable programs for implementing the logical functions, and may be embodied in any computer-readable medium for use by a program execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch and execute a program from a program execution system, device or apparatus), or in conjunction with such program execution systems, devices or apparatuses. For purposes of this specification, a "computer-readable medium" may be any device that can contain, store, communicate, propagate or transmit a program for use by a program execution system, device or apparatus, or in conjunction with such program execution systems, devices or apparatuses.

[0092] More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or more wires (electronic device), a portable computer disk case (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be a paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, deciphering or, if necessary, processing in another suitable manner, and then stored in a computer memory.

[0093] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable program execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0094] In the above description of this specification, the description with reference to the terms "one embodiment / example", "another embodiment / example" or "certain embodiments / examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0095] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

[0096] The above is a specific description of the preferred implementation of the present invention, but the present invention is not limited to the embodiments. Those skilled in the art may make various equivalent modifications or substitutions without violating the spirit of the present invention. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present invention.

Claims

1. A multi-core oscillator, characterized in that: include: N oscillating cores, N first inductors, N second inductors and N third inductors; wherein N is an even number greater than or equal to 4; the N oscillating cores are arranged in a ring; The first drain terminal of each oscillating core is connected to the second drain terminal of an adjacent oscillating core through the first inductor; the second gate terminal of each oscillating core is connected to the first gate terminal of a non-adjacent oscillating core through the second inductor and the third inductor; Every two adjacent oscillation cores are directly synchronized through the coupling relationship between the second inductor and the third inductor; the middle point where each of the second inductor and each of the third inductors are connected is connected to the first power supply through a first resistor, so that every two non-adjacent oscillation cores are directly synchronized through the out-of-phase relationship between the second inductor and the third inductor; The middle point of each of the first inductors is connected to the second power supply via a second resistor, so that every two adjacent oscillation cores are directly synchronized through the out-of-phase relationship between the two ends of the first inductor.

2. The multi-core oscillator according to claim 1, characterized in that: Each oscillator core includes: a first NMOS transistor, a second NMOS transistor and a switch capacitor; The first drain terminal of the oscillation core is connected to the second drain terminal of the oscillation core through the switching capacitor; the first gate terminal of the oscillation core is connected to the gate of the first NMOS tube, and the second gate terminal of the oscillation core is connected to the gate of the second NMOS tube; the first drain terminal of the oscillation core is connected to the drain of the first NMOS tube, and the second drain terminal of the oscillation core is connected to the drain of the second NMOS tube; the source of the first NMOS tube and the source of the second NMOS tube are both grounded.

3. The multi-core oscillator according to claim 1, characterized in that: A value corresponding to the coupling coefficient between the first inductor and the second inductor is a first value, a value corresponding to the coupling coefficient between the first inductor and the third inductor is a second value, and the first value and the second value are different.

4. The multi-core oscillator according to claim 1, characterized in that: The second inductor and the third inductor have different Q values.

5. The multi-core oscillator according to claim 1, characterized in that: The resistance of the second resistor is 1 to 50 ohms.

6. The multi-core oscillator according to claim 1, characterized in that: The second inductor is realized by a coil and a metal layer, or the third inductor is realized by a coil and a metal layer.

7. The multi-core oscillator according to claim 1, characterized in that: The multi-core oscillator includes a plurality of oscillator group structures, each oscillator group structure includes N oscillation cores; the plurality of oscillator group structures are arranged in a ring shape; The two adjacent oscillator cores in each two adjacent oscillator group structures are connected, the first drain terminals of the two adjacent oscillator cores are interconnected, and the second drain terminals of the two adjacent oscillator cores are interconnected, so that the adjacent oscillator group structures are directly synchronized.

8. The multi-core oscillator according to claim 7, characterized in that: include: A first oscillator group structure and a second oscillator group structure, wherein the first oscillator group structure and the second oscillator group structure are any two different oscillator group structures; The first oscillator group structure includes a first oscillator core, and the second oscillator group structure includes a second oscillator core; The first drain terminal of the first oscillator core is connected to the first drain terminal of the second oscillator core, and the second drain terminal of the first oscillator core is connected to the second drain terminal of the second oscillator core, so that all oscillator group structures are directly synchronized.

9. The multi-core oscillator according to claim 7, characterized in that: The first drain terminals of the two oscillator cores are interconnected through a metal line.

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