Duty ratio adjusting circuit, delay phase-locked loop circuit and memory

Abstract

The invention discloses a duty ratio adjusting circuit, a delay phase-locked loop circuit and a memory, a duty ratio adjusting link in the duty ratio adjusting circuit receives an input clock signal and adjusts the duty ratio of the input clock signal to generate an output clock signal; the duty ratio detection circuit is coupled with the duty ratio adjustment link, and generates a corresponding first detection signal based on the detected duty ratio of the output clock signal; the initial state confirmation circuit is coupled with the duty ratio adjustment link and is used for detecting the duty ratio of the output clock signal in the initial state of the duty ratio adjustment link and generating a corresponding second detection signal based on the duty ratio of the output clock signal; the adjusting circuit is coupled with the duty ratio detection circuit and the initial state confirmation circuit, and is used for generating corresponding control signals based on the first detection signal and the second detection signal, and generating control codes based on the control signals, so that the duty ratio adjusting link adjusts the duty ratio of the input clock signal to generate the output clock signal.

Description

Technical Field

[0001] The present application relates to the technical field of duty cycle regulation, and in particular to a duty cycle adjustment circuit, a delay locked loop circuit and a memory. Background Art

[0002] Double Data Rate (DDR) synchronous random access memory (SDRAM) is the mainstream of random access memory and is a typical semiconductor memory. DDR type memory is designed to synchronously input or output data at the rising and falling edges of the clock signal. Therefore, the duty cycle of the clock signal needs to be accurately maintained at 50%. For this reason, the chip usually uses a duty cycle adjustment circuit to adjust the duty cycle of the clock signal, narrowing the clock signal with a duty cycle higher than 50%, and widening the clock signal with a duty cycle lower than 50%. However, in the duty cycle adjustment circuit in the prior art, the normal operation of the duty cycle adjustment circuit depends on establishing an accurate initial state, and most of the prior art ignores this problem. If the initial state is inaccurate, the duty cycle adjustment circuit not only cannot achieve the adjustment of the duty cycle, but also loses the clock signal, resulting in data transmission distortion. Summary of the invention

[0003] In order to solve the above problems, the present application provides a duty cycle adjustment circuit, a delay locked loop circuit and a memory to ensure the normal operation of the duty cycle adjustment link, avoid serious deviation of the duty cycle of the output clock signal and ensure the accuracy of data signal transmission.

[0004] In order to solve the above technical problems, a technical solution adopted in the present application is: providing a duty cycle adjustment circuit, which includes a duty cycle adjustment link, a duty cycle detection circuit, an initial state confirmation circuit and an adjustment circuit, the duty cycle adjustment link receives an input clock signal, and adjusts the duty cycle of the input clock signal to generate an output clock signal; the duty cycle detection circuit is coupled to the duty cycle adjustment link, and generates a corresponding first detection signal based on the detected duty cycle of the output clock signal; the initial state confirmation circuit is coupled to the duty cycle adjustment link, and is used to detect the duty cycle of the output clock signal in the initial state of the duty cycle adjustment link, and generate a corresponding second detection signal based on the duty cycle of the output clock signal; the adjustment circuit is coupled to the duty cycle detection circuit and the initial state confirmation circuit, and is used to generate a corresponding control signal based on the first detection signal and the second detection signal, and generate a control code based on the control signal, so that the duty cycle adjustment link adjusts the duty cycle of the input clock signal to generate an output clock signal.

[0005] Among them, the initial state confirmation circuit includes an inverter chain and a buffer unit, the inverter chain includes multiple inverter units connected in series, the input end of the inverter chain receives the output clock signal, the output end of the inverter chain is connected to the input end of the buffer unit, and the output end of the buffer unit is coupled to the adjustment circuit; wherein the inverter chain generates a corresponding output voltage based on the output clock signal; the buffer unit is used to shape the output voltage to obtain a second detection signal.

[0006] Among them, the input end of the inverter unit at the head end of the inverter chain serves as the input end of the inverter chain to receive the output clock signal, the input end of each non-head end inverter unit is connected to the output end of the previous inverter unit, and the output end of the inverter unit at the end of the inverter chain serves as the output end of the inverter chain and is connected to the input end of the buffer unit.

[0007] Each inverter unit includes a first transistor, a second transistor and a capacitor; the control end of the first transistor is connected to the control end of the second transistor; and a first node between the control end of the first transistor and the control end of the second transistor serves as an input end of the inverter unit, a first channel end of the first transistor receives a reference voltage, a second channel end of the first transistor is connected to the first channel end of the second transistor, a second channel end of the second transistor is grounded, and a second node between the second channel end of the first transistor and the first channel end of the second transistor serves as an output end of the inverter unit; a first end of the capacitor is connected to the second node, and a second end of the capacitor is grounded.

[0008] Among them, the first transistor is a PMOS tube, and the second transistor is an NMOS tube. When the input signal at the input end of the inverter unit is at a high level, the second transistor is turned on and the capacitor performs a discharge operation; when the input signal at the input end of the inverter unit is at a low level, the first transistor is turned on and the capacitor performs a charging operation.

[0009] In which, in response to the duty cycle of the output clock signal being less than 0.5, the voltage at the output end of each inverter unit is less than the voltage at the input end of the inverter unit; the output voltage generated by the inverter chain approaches zero, and the second detection signal is shaped into a low-level signal; in response to the duty cycle of the output clock signal being greater than 0.5, the voltage at the output end of each inverter unit is greater than the voltage at the input end of the inverter unit, the output voltage generated by the inverter chain approaches the reference voltage, and the second detection signal is shaped into a high-level signal.

[0010] Among them, the duty cycle adjustment circuit also includes: a logic circuit, the logic circuit is coupled to the duty cycle detection circuit, the initial state confirmation circuit and the adjustment circuit, the logic circuit is used to perform logic operations based on the first detection signal and the second detection signal to obtain a logic control signal, and send the logic control signal to the adjustment circuit; wherein, in response to being in the initial state of the duty cycle adjustment link, the logic control signal of the logic circuit is consistent with the level of the second detection signal; in response to not being in the initial state of the duty cycle adjustment link, the logic control signal of the logic circuit is consistent with the level of the first detection signal.

[0011] The logic circuit is any combination of a D flip-flop, a logic AND gate, a logic OR gate and a logic NOT gate.

[0012] To solve the above technical problems, another technical solution adopted in the present application is: to provide a delay phase-locked loop circuit, which includes the above-mentioned duty cycle adjustment circuit and control logic module, the control logic module is connected to the initial state confirmation circuit, in response to the duty cycle adjustment link being in the initial state, the control logic module converts the enable signal of the initial state confirmation circuit to a valid state; in response to the duty cycle adjustment link not being in the initial state, the control logic module converts the enable signal of the initial state confirmation circuit to an invalid state.

[0013] In order to solve the above technical problem, another technical solution adopted in the present application is: providing a memory, which includes the above-mentioned delay locked loop circuit.

[0014] Different from the prior art, the duty cycle adjustment circuit of the present application includes a duty cycle adjustment link, a duty cycle detection circuit, an initial state confirmation circuit and an adjustment circuit. The duty cycle adjustment link receives an input clock signal and adjusts the duty cycle of the input clock signal to generate an output clock signal; the duty cycle detection circuit is coupled to the duty cycle adjustment link and generates a corresponding first detection signal based on the detected duty cycle of the output clock signal; the initial state confirmation circuit is coupled to the duty cycle adjustment link and is used to detect the duty cycle of the output clock signal in the initial state of the duty cycle adjustment link and generate a corresponding second detection signal based on the duty cycle of the output clock signal; the adjustment circuit is coupled to the duty cycle detection circuit and the initial state confirmation circuit and is used to generate a corresponding control signal based on the first detection signal and the second detection signal, and generate a control code based on the control signal, so that the duty cycle adjustment link adjusts the duty cycle of the input clock signal to generate an output clock signal. In the above manner, the duty cycle adjustment circuit of the present application can perform preliminary duty cycle detection on the output clock signal through the initial state confirmation circuit to determine the initial state of the duty cycle adjustment link, ensure that the duty cycle adjustment link can operate normally, avoid the uncertain state X of the duty cycle detection circuit when the duty cycle deviates seriously, ensure the correct transmission of data, and ensure the accuracy of data signal transmission. That is to say, for an output clock signal with a duty cycle seriously deviating from 50%, when the clock link reaches the duty cycle detection circuit through a long routing, the clock may be lost, resulting in failure of the entire loop. The initial state confirmation circuit of the present application can detect a wider range of duty cycles, can detect an output clock signal with a duty cycle seriously deviating from 50%, and determine the correct loop state, so that the entire loop of the duty cycle adjustment circuit can normally adjust the clock signal duty cycle to about 50%, and ensure the normal operation of the duty cycle detection circuit and the entire loop. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. Among them:

[0016] Figure 1 is a schematic diagram of a first embodiment of a duty cycle adjustment circuit provided by the present application;

[0017] Figure 2 is a structural schematic diagram of an embodiment of a duty cycle detection circuit;

[0018] Figure 3 It is a structural schematic diagram of an embodiment of a duty cycle adjustment circuit in the prior art;

[0019] Figure 4 It is a circuit structure diagram of an embodiment of an initial state confirmation circuit provided by the present application;

[0020] Figure 5 It is a schematic diagram of the circuit structure of an inverter unit 1 implemented in the present application;

[0021] Figure 6 It is a schematic diagram of the working principle of an inverter unit according to an embodiment of the present application;

[0022] Figure 7 is a schematic diagram of a second embodiment of a duty cycle adjustment circuit provided by the present application;

[0023] Figure 8 It is a structural schematic diagram of an embodiment of a delay phase-locked loop circuit provided by the present application;

[0024] Fig. 9 It is a schematic diagram of the structure of a memory embodiment of the present application. DETAILED DESCRIPTION

[0025] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It will be understood that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for ease of description, only some but not all structures related to the present application are shown in the drawings. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application.

[0026] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0027] Double Data Rate (DDR) synchronous random access memory (SDRAM) is the mainstream of random access memory and is a typical semiconductor memory. DDR type memory is designed to synchronously input or output data at the rising and falling edges of the clock signal. Therefore, the duty cycle of the clock signal needs to be accurately maintained at 50%. For this reason, the chip usually uses a duty cycle adjustment circuit to adjust the duty cycle of the clock signal, narrowing the clock signal with a duty cycle higher than 50%, and widening the clock signal with a duty cycle lower than 50%. However, in the duty cycle adjustment circuit in the prior art, the normal operation of the duty cycle adjustment circuit depends on establishing an accurate initial state, and most of the prior art ignores this problem. If the initial state is inaccurate, the duty cycle adjustment circuit not only cannot achieve the adjustment of the duty cycle, but also loses the clock signal, resulting in data transmission distortion.

[0028] In order to solve the above problems, the present application first proposes a duty cycle adjustment circuit. Figure 1 , Figure 1 Schematic diagram of the first embodiment of the duty cycle adjustment circuit provided by the present application. Figure 1 As shown, the duty cycle adjustment circuit 100 of this embodiment includes a duty cycle adjustment link 10 , a duty cycle detection circuit 20 , an initial state confirmation circuit 30 and an adjustment circuit 40 .

[0029] Among them, the duty cycle adjustment link 10 receives the input clock signal CLKIN, and adjusts the duty cycle of the input clock signal CLKIN to generate the output clock signal CLKOUT; the duty cycle detection circuit 20 is coupled to the duty cycle adjustment link 10, and generates a corresponding first detection signal based on the detected duty cycle of the output clock signal CLKOUT; the initial state confirmation circuit 30 is coupled to the duty cycle adjustment link 10, and is used to detect the duty cycle of the output clock signal CLKOUT in the initial state of the duty cycle adjustment link 10, and generate a corresponding second detection signal based on the duty cycle of the output clock signal CLKOUT; the adjustment circuit 40 is coupled to the duty cycle detection circuit 20 and the initial state confirmation circuit 30, and is used to generate a corresponding control signal based on the first detection signal and the second detection signal, and generate a control code based on the control signal, so that the duty cycle adjustment link 10 adjusts the duty cycle of the input clock signal CLKIN to generate the output clock signal CLKOUT.

[0030] In this embodiment, the duty cycle detection circuit 20 is used to detect the duty cycle of the clock signal CLKOUT output by the duty cycle adjustment link 10. In response to the duty cycle of the output clock signal CLKOUT being greater than 50%, the first detection signal is a logic signal 1. In response to the duty cycle of the output clock signal CLKOUT being less than 50%, the first detection signal is a logic signal 0.

[0031] For example, see Figure 2 , Figure 2 FIG. 1 is a schematic diagram of the structure of an embodiment of a duty cycle detection circuit. Figure 2 As shown, the duty cycle detection circuit 20 includes a single-end to dual-end circuit 21, a level detection circuit 22 and a comparator 23, and is composed of the single-end to dual-end circuit 21, the level detection circuit 22 and the comparator 23 connected in sequence. The input of the duty cycle detection circuit 20 is the output clock signal CLKOUT, and the output clock signal CLKOUT is converted into a first differential clock signal LDCCR and a second differential clock signal LDCCF by the single-end to dual-end circuit 21. The first differential clock signal LDCCR and the second differential clock signal LDCCF are detected by the level detection circuit 22 to detect the high level and low level duration, and generate a first voltage analog signal LCMPR and a second voltage analog signal LCMPF representing the effective time of the high level and the low level, and send the two to the comparator 23 for comparison, so as to generate a first detection signal representing whether the duty cycle is greater than 50%. In other embodiments, the duty cycle detection circuit 20 can also be in other forms, which are not limited here.

[0032] In this embodiment, the adjustment circuit 40 may further include a state machine, for example, a finite state machine (FSM). When the state machine receives the control signal generated by the first detection signal of the duty cycle detection circuit 20 and the second detection signal of the initial state confirmation circuit 30, it generates a corresponding control code Code based on the control signal. <n:1>The duty cycle adjustment link 10 further includes a bias voltage generation module, which can receive a corresponding control code Code <n:1>Generate a corresponding bias voltage to act on the duty cycle adjustment link 10 to adjust the slope of the rising edge or falling edge of the intermediate clock signal generated by the intermediate node, thereby adjusting the duty cycle of the output clock signal CLKOUT. In other embodiments, the adjustment circuit 40 can also be a controller or other forms, and the controller can receive the control signal generated by the first detection signal of the duty cycle detection circuit 20 and the second detection signal of the initial state confirmation circuit 30, and obtain the corresponding control code based on the control signal through the logic operation in the controller to control the offset delay time of the rising edge and falling edge of the duty cycle adjustment link 10 to adjust the duty cycle of the output clock signal CLKOUT. In other embodiments, the bias voltage generation module can also be set in the adjustment circuit 40. In this embodiment, the bias voltage generation module in the adjustment circuit 40 outputs the bias voltage to the duty cycle adjustment link 10 to adjust the slope of the rising edge or falling edge of the intermediate clock signal generated by the intermediate node, thereby adjusting the duty cycle of the output clock signal CLKOUT.

[0033] Also, see Figure 3 , Figure 3 FIG. 1 is a schematic diagram of a structure of an embodiment of a duty cycle adjustment circuit in the prior art. Figure 3 As shown, in the prior art, the initial state of the duty cycle regulation link 10 is not confirmed during the operation of the duty cycle regulation link 10, and the first detection signal output by the duty cycle detection circuit 20 is an unknown X state, which causes the duty cycle of the clock signal output by the duty cycle regulation link 10 to deviate seriously. For example, the duty cycle of the input clock signal CLKIN of the duty cycle adjustment link 10 is already greater than 50%. Under normal circumstances, the duty cycle adjustment link 10 should be adjusted in the direction of narrowing the duty cycle. However, since the first detection signal output in the first cycle of the duty cycle detection circuit 20 is unknown, if the first detection signal output in the first cycle controls the adjustment circuit 40 to increase the duty cycle of the output clock signal CLKOUT output by the duty cycle adjustment link 10, it will cause the duty cycle adjustment link 10 to be incorrectly adjusted, so that the duty cycle of the output clock signal CLKOUT is much greater than 50%, and the duty cycle seriously deviates from the clock signal of 50%. When the duty cycle adjustment link 10 reaches the duty cycle detection circuit 20 through a long wiring, the clock signal is easily lost, causing the entire loop to fail and unable to perform normal data transmission.

[0034] Therefore, in this embodiment, in order to determine the initial state of the duty cycle adjustment link 10, ensure that the duty cycle adjustment link 10 can operate normally and avoid serious deviation of the duty cycle, such as Figure 1 As shown, it is necessary to add an initial state confirmation circuit 30 in the duty cycle adjustment circuit 100. The initial state confirmation circuit 30 detects the duty cycle of the output clock signal CLKOUT in the initial state of the duty cycle adjustment link 10, and generates a corresponding second detection signal based on the duty cycle of the output clock signal CLKOUT. Here, the initial state of the duty cycle adjustment link 10 is the state before the first cycle when the duty cycle detection circuit 20 outputs the first detection signal. During this period, the initial state confirmation circuit 30 needs to detect the duty cycle of the output clock signal CLKOUT to obtain the second detection signal to determine the duty cycle adjustment of the duty cycle adjustment link 10.

[0035] Different from the prior art, the duty cycle adjustment circuit 100 of the present application includes a duty cycle adjustment link 10, a duty cycle detection circuit 20, an initial state confirmation circuit 30 and an adjustment circuit 40. The duty cycle adjustment link 10 receives an input clock signal CLKIN and adjusts the duty cycle of the input clock signal CLKIN to generate an output clock signal CLKOUT; the duty cycle detection circuit 20 is coupled to the duty cycle adjustment link 10 and generates a corresponding first detection signal based on the detected duty cycle of the output clock signal CLKOUT; the initial state confirmation circuit 30 is coupled to the duty cycle adjustment link 10 and generates a corresponding first detection signal based on the detected duty cycle of the output clock signal CLKOUT; The first detection signal is coupled to the duty cycle detection circuit 20 and the initial state confirmation circuit 30, and is used to detect the duty cycle of the output clock signal CLKOUT in the initial state of the duty cycle adjustment link 10, and generate a corresponding second detection signal based on the duty cycle of the output clock signal CLKOUT; the adjustment circuit 40 is coupled to the duty cycle detection circuit 20 and the initial state confirmation circuit 30, and is used to generate a corresponding control signal based on the first detection signal and the second detection signal, and generate a control code based on the control signal, so that the duty cycle adjustment link 10 adjusts the duty cycle of the input clock signal CLKIN to generate the output clock signal CLKOUT. In the above manner, the duty cycle adjustment circuit 100 of the present application can perform a preliminary duty cycle detection on the output clock signal CLKOUT through the initial state confirmation circuit 30 to determine the initial state of the duty cycle adjustment link 10, ensure that the duty cycle adjustment link 10 can operate normally, avoid the uncertain state X of the duty cycle detection circuit 20 when the duty cycle deviates seriously, ensure the correct transmission of data, and ensure the accuracy of data signal transmission. That is to say, for the output clock signal CLKOUT whose duty cycle seriously deviates from 50%, when the clock link reaches the duty cycle detection circuit 20 through a long wiring, clock loss may occur, causing the entire loop to fail. The initial state confirmation circuit 30 of the present application can detect a wider range of duty cycles, and can detect the output clock signal CLKOUT whose duty cycle seriously deviates from 50%, and determine the correct loop state, so that the entire loop of the duty cycle adjustment circuit 100 can normally adjust the clock signal duty cycle to about 50%, and ensure the normal operation of the duty cycle detection circuit 20 and the entire loop.

[0036] Optionally, based on the above embodiment, please refer to Figure 4 , Figure 4 1 is a schematic diagram of the circuit structure of an embodiment of the initial state confirmation circuit provided by the present application. Figure 4 As shown, the initial state confirmation circuit 30 of this embodiment includes an inverter chain 31 and a buffer unit 32, the inverter chain 31 includes a plurality of inverter units 311 connected in series, the input end of the inverter chain 31 receives the output clock signal CLKOUT, the output end of the inverter chain 31 is connected to the input end of the buffer unit 32, and the output end of the buffer unit 32 is coupled to the adjustment circuit 40; wherein the inverter chain 31 generates a corresponding output voltage based on the output clock signal CLKOUT; the buffer unit 32 is used to shape the output voltage to obtain a second detection signal.

[0037] In this embodiment, the following can be used: Figure 4 The inverter chain 31 shown filters the high-frequency output clock signal CLKOUT to obtain an output voltage, and shapes the output voltage through a buffer to obtain a second detection signal, wherein the second detection signal can also be represented by a logic signal 0 or 1 to indicate that the duty cycle is greater than or less than 50%; if the duty cycle of the output clock signal CLKOUT is greater than 50%, the second detection signal is a logic signal 1, and if the duty cycle of the output clock signal CLKOUT is less than 50%, the second detection signal is a logic signal 0.

[0038] In addition, in this embodiment, the number of inverter units 311 in the inverter chain 31 can be set to 3-4. In other embodiments, the number of inverter units 311 can also be set based on actual conditions, which is not limited here.

[0039] Optional, such as Figure 4 As shown, in this embodiment, the input end of the inverter unit 311 at the head end of the inverter chain 31 serves as the input end of the inverter chain 31 to receive the output clock signal CLKOUT, the input end of each non-head end inverter unit 311 is connected to the output end of the previous inverter unit 311, and the output end of the inverter unit 311 at the end of the inverter chain 31 serves as the output end of the inverter chain 31 and is connected to the input end of the buffer unit 32.

[0040] Optionally, see Figure 5 , Figure 5 1 is a schematic diagram of the circuit structure of an inverter unit 1 provided in the present application. Figure 5 As shown, in the present embodiment, each inverter unit 311 includes a first transistor M1, a second transistor M2 and a capacitor C; the control end of the first transistor M1 is connected to the control end of the second transistor M2; and a first node P between the control end of the first transistor M1 and the control end of the second transistor M2 serves as an input end of the inverter unit 311, a first channel end of the first transistor M1 receives a reference voltage, a second channel end of the first transistor M1 is connected to a first channel end of the second transistor M2, a second channel end of the second transistor M2 is grounded, and a second node Q between the second channel end of the first transistor M1 and the first channel end of the second transistor M2 serves as an output end of the inverter unit 311; a first end of the capacitor C is connected to a second node Q, and a second end of the capacitor C is grounded.

[0041] Optionally, based on Figure 5 In this embodiment, the first transistor M1 is a PMOS tube, the second transistor M2 is an NMOS tube, and in response to the input signal at the input end of the inverter unit 311 being a high level, the second transistor M2 is turned on, and the capacitor C performs a discharge operation; in response to the input signal at the input end of the inverter unit 311 being a low level, the first transistor M1 is turned on, and the capacitor C performs a charging operation.

[0042] In this embodiment, please refer to Figure 6 , Figure 6 Schematic diagram of the working principle of an inverter unit according to an embodiment of the present application. Assume that the duty cycle of the output clock signal CLKOUT is a, that is, within a period T of the output clock signal CLKOUT, the high level time is aT, and the low level time is (1-a)T. Figure 6 As shown in (a), when the input signal at the input end of the inverter unit 311 is at a high level, the second transistor M2 is turned on, and the capacitor C performs a discharge operation, that is, the charge on the upper plate of the capacitor C flows to the ground end, and the conduction current at this time is I; Figure 6 As shown in (b), when the input signal at the input end of the inverter unit 311 is at a low level, the first transistor M1 is turned on, and the capacitor C performs a charging operation, that is, the reference voltage power supply injects charge into the upper plate of the capacitor C.

[0043] Optionally, based on Figure 2 and Figure 3 In the embodiment, in this embodiment, in response to the duty cycle of the output clock signal CLKOUT being less than 0.5, the voltage at the output end of each inverter unit 311 is less than the voltage at the input end of the inverter unit 311; the output voltage generated by the inverter chain 31 approaches zero, and the second detection signal is shaped into a low level signal; in response to the duty cycle of the output clock signal CLKOUT being greater than 0.5, the voltage at the output end of each inverter unit 311 is greater than the voltage at the input end of the inverter unit 311, the output voltage generated by the inverter chain 31 approaches the reference voltage, and the second detection signal is shaped into a high level signal.

[0044] Assume that the first transistor M1 and the second transistor M2 are completely matched, and the conduction current at this time is also I. Assume that the voltage at the input end of the inverter unit 311 is V 0 , after passing through an inverter unit 311, the voltage V at the output end of the inverter unit 311 out =V 0 -aIT / C+(1-a)IT / C=V 0 +(1-2a)IT / C, where a is the duty cycle, I is the on-current, T is the period of the input clock signal CLKIN, and C is the capacitance. After the output clock signal CLKOUT passes through the inverter chain 31, if the duty cycle a of the output clock signal CLKOUT is greater than 50%, the output voltage output by the inverter chain 31 can approach 0, and the second detection signal after being shaped by the buffer is a low-level signal. If the duty cycle a of the output clock signal CLKOUT is less than 50%, the output voltage output by the inverter chain 31 can approach the reference voltage, and the second detection signal after being shaped by the buffer is a high-level signal.

[0045] Based on the above embodiment, the initial state confirmation circuit 30 can be understood as a simple duty cycle detection circuit 20. The initial state confirmation circuit 30 and the duty cycle detection circuit 20 can both realize duty cycle detection at the same time. The initial state confirmation circuit 30 assists the duty cycle detection circuit 20 to complete the establishment of the initial state of the duty cycle adjustment link 10. Figure 2 The duty cycle detection circuit 20 shown, although the detection accuracy of the initial state confirmation circuit 30 of this embodiment is not as good as that of the duty cycle detection circuit 20, the circuit structure of the initial state confirmation circuit 30 is simple, easy to implement, and small in area, which is sufficient to complete the detection of the initial state of the duty cycle adjustment link 10. For the output clock signal CLKOUT whose duty cycle seriously deviates from 50%, when the duty cycle adjustment link 10 reaches the duty cycle detection circuit 20 through the long wiring, the clock signal may be lost, resulting in failure of the entire loop operation, while the initial state confirmation circuit 30 can detect a wider range of duty cycles, and can detect the output clock signal CLKOUT whose duty cycle seriously deviates from 50%, helping the duty cycle adjustment circuit 100 to determine the correct loop state, so that the duty cycle adjustment circuit 100 can normally adjust the clock signal duty cycle to about 50%, and ensure the normal operation of the duty cycle adjustment circuit 100. In addition, in the present application, the duty cycle range detected by the initial state confirmation circuit 30 is wider than that of the duty cycle detection circuit 20, and even the duty cycle of the output clock signal CLKOUT can be detected in the range of 90%.

[0046] Optionally, see Figure 7 , Figure 7 is a schematic diagram of a second embodiment of a duty cycle adjustment circuit provided by the present application. Figure 7 As shown, in this embodiment, the duty cycle adjustment circuit 100 also includes a logic circuit 50, which is coupled to the duty cycle detection circuit 20, the initial state confirmation circuit 30 and the adjustment circuit 40. The logic circuit 50 is used to perform a logic operation based on the first detection signal and the second detection signal to obtain a logic control signal, and send the logic control signal to the adjustment circuit 40; wherein, in response to being in the initial state of the duty cycle adjustment link 10, the logic control signal of the logic circuit 50 is consistent with the level of the second detection signal; in response to not being in the initial state of the duty cycle adjustment link 10, the logic control signal of the logic circuit 50 is consistent with the level of the first detection signal.

[0047] In this embodiment, if the duty cycle adjustment link 10 is in the initial state, the logic control signal received by the adjustment circuit 40 is mainly based on the initial state confirmation circuit 30, that is, when the duty cycle adjustment link 10 is in the initial state, the logic control signal of the logic circuit 50 is consistent with the level of the second detection signal output by the initial state confirmation circuit 30; if the duty cycle adjustment link 10 is not in the initial state, that is, after the initial state, the logic control signal received by the adjustment circuit 40 is mainly based on the duty cycle detection circuit 20, and at this time, the logic control signal of the logic circuit 50 is consistent with the level of the first detection signal output by the duty cycle detection circuit 20.

[0048] Optionally, based on the above embodiment, the logic circuit 50 of this embodiment is any combination of a D flip-flop, a logic AND gate, a logic OR gate and a logic NOT gate, and only needs to satisfy the functions of the above logic circuit 50, which is not limited here.

[0049] Optionally, the present application further proposes a delay phase-locked loop circuit, see Figure 8 , Figure 8 is a schematic diagram of the structure of an embodiment of a delay phase-locked loop circuit provided by the present application, such as Figure 8 As shown, the delay locked loop circuit 200 of this embodiment includes the duty cycle adjustment circuit 100 of any one of the above embodiments and a control logic module 210 .

[0050] Among them, the control logic module 210 is connected to the initial state confirmation circuit 30. In response to the duty cycle adjustment link 10 being in the initial state, the control logic module 210 converts the enable signal of the initial state confirmation circuit 30 to a valid state; in response to the duty cycle adjustment link 10 not being in the initial state, the control logic module 210 converts the enable signal of the initial state confirmation circuit 30 to an invalid state.

[0051] That is, in this embodiment, the control logic module 210 can be used to make the initial state confirmation circuit 30 work only in the initial state of the duty cycle adjustment link 10; specifically, when the duty cycle adjustment link 10 is enabled, the control logic module 210 converts the enable signal of the initial state confirmation circuit 30 to a valid state, and after the duty cycle adjustment link 10 is established, the control logic module 210 will send a reset signal to convert the enable signal of the initial state confirmation circuit 30 to an invalid state. In the above manner, the control logic module 210 can be used to make the initial state confirmation circuit 30 work only in the initial state of the duty cycle adjustment link 10, which basically does not affect the power consumption of the overall circuit.

[0052] Optionally, the present application further proposes a memory, see Fig. 9 , Fig. 9 Schematic diagram of the structure of a memory device according to an embodiment of the present invention. Fig. 9 As shown, the memory 300 of this embodiment includes the delay locked loop circuit 200 of the above embodiment.

[0053] In this embodiment, the memory 300 may be a random access memory DRAM, a static random access memory SRAM or a pseudo static random access memory (Pseudo SRAM, PSRAM), which is not limited here.

[0054] The above description is only an implementation method of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made according to the description and drawings of the present application, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A duty cycle adjustment circuit, characterized in that: include: A duty cycle adjustment link receives an input clock signal and adjusts the duty cycle of the input clock signal to generate an output clock signal; a duty cycle detection circuit, coupled to the duty cycle adjustment link, and generating a corresponding first detection signal based on the detected duty cycle of the output clock signal; an initial state confirmation circuit, coupled to the duty cycle adjustment link, for detecting the duty cycle of the output clock signal in an initial state of the duty cycle adjustment link, and generating a corresponding second detection signal based on the duty cycle of the output clock signal; An adjustment circuit is coupled to the duty cycle detection circuit and the initial state confirmation circuit, and is used to generate a corresponding control signal based on the first detection signal and the second detection signal, and to generate a control code based on the control signal, so that the duty cycle adjustment link adjusts the duty cycle of the input clock signal to generate the output clock signal.

2. The duty cycle adjustment circuit according to claim 1, characterized in that: The initial state confirmation circuit includes an inverter chain and a buffer unit, the inverter chain includes a plurality of inverter units connected in series, an input end of the inverter chain receives the output clock signal, an output end of the inverter chain is connected to an input end of the buffer unit, and an output end of the buffer unit is coupled to the adjustment circuit; The inverter chain generates a corresponding output voltage based on the output clock signal; and the buffer unit is used to shape the output voltage to obtain the second detection signal.

3. The duty cycle adjustment circuit according to claim 2, characterized in that: The input end of the inverter unit at the head end of the inverter chain serves as the input end of the inverter chain to receive the output clock signal, the input end of each non-head end of the inverter unit is connected to the output end of the inverter unit at the previous level, and the output end of the inverter unit at the end of the inverter chain serves as the output end of the inverter chain and is connected to the input end of the buffer unit.

4. The duty cycle adjustment circuit according to claim 2, characterized in that: Each of the inverter units includes a first transistor, a second transistor and a capacitor; The control end of the first transistor is connected to the control end of the second transistor; and a first node between the control end of the first transistor and the control end of the second transistor serves as an input end of the inverter unit, a first path end of the first transistor receives a reference voltage, a second path end of the first transistor is connected to the first path end of the second transistor, a second path end of the second transistor is grounded, and a second node between the second path end of the first transistor and the first path end of the second transistor serves as an output end of the inverter unit; a first end of the capacitor is connected to the second node, and a second end of the capacitor is grounded.

5. The duty cycle adjustment circuit according to claim 4, characterized in that: The first transistor is a PMOS tube, and the second transistor is an NMOS tube. In response to the input signal of the input end of the inverter unit being at a high level, the second transistor is turned on, and the capacitor performs a discharge operation; in response to the input signal of the input end of the inverter unit being at a low level, the first transistor is turned on, and the capacitor performs a charging operation.

6. The duty cycle adjustment circuit according to claim 3, characterized in that: In response to the duty cycle of the output clock signal being less than 0.5, the voltage at the output end of each inverter unit is less than the voltage at the input end of the inverter unit; the output voltage generated by the inverter chain approaches zero, and the second detection signal is shaped into a low level signal; In response to the duty cycle of the output clock signal being greater than 0.5, the voltage at the output end of each inverter unit is greater than the voltage at the input end of the inverter unit, the output voltage generated by the inverter chain approaches the reference voltage, and the second detection signal is shaped into a high level signal.

7. The duty cycle adjustment circuit according to claim 1, characterized in that: Also includes: a logic circuit, the logic circuit being coupled to the duty cycle detection circuit, the initial state confirmation circuit, and the adjustment circuit, the logic circuit being configured to perform a logic operation based on the first detection signal and the second detection signal to obtain a logic control signal, and send the logic control signal to the adjustment circuit; Wherein, in response to being in the initial state of the duty cycle adjustment link, the logic control signal of the logic circuit is consistent with the level of the second detection signal; In response to not being in the initial state of the duty cycle adjustment link, the logic control signal of the logic circuit is consistent with the level of the first detection signal.

8. The duty cycle adjustment circuit according to claim 7, characterized in that: The logic circuit is any combination of a D flip-flop, a logic AND gate, a logic OR gate and a logic NOT gate.

9. A delay locked loop circuit, characterized in that: It includes the duty cycle adjustment circuit and control logic module as described in any one of claims 1 to 8, wherein the control logic module is connected to the initial state confirmation circuit, and in response to the duty cycle adjustment link being in the initial state, the control logic module converts the enable signal of the initial state confirmation circuit to a valid state; in response to the duty cycle adjustment link not being in the initial state, the control logic module converts the enable signal of the initial state confirmation circuit to an invalid state.

10. A memory, characterized in that: The delay locked loop circuit comprises the delay locked loop circuit as claimed in claim 9.

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