Three-state input port circuit and chip, display panel and display device comprising same

Abstract

The invention discloses a three-state input port circuit, a chip comprising the same, a display panel and display equipment. According to the embodiment of the invention, the three-state input port circuit comprises a receiving end, wherein the receiving end is used for receiving an input signal; the first end of the first branch is connected with the receiving end, and the second end of the first branch is connected to the first output end; the first end of the second branch is connected with the receiving end, and the second end of the second branch is connected to the second output end; the bias voltage source is connected with the first branch circuit so as to control current flowing through the first branch circuit; the bias voltage source is connected with the second branch circuit to control current flowing through the second branch circuit, and when the input signals received by the receiving end are different, the first output end and the second output end output different output combinations. According to the tri-state input port circuit, the chip comprising the tri-state input port circuit, the display panel and the display equipment, the tri-state input port circuit can adapt to application scenes with large power voltage changes.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a three-state input port circuit and a chip, a display panel and a display device comprising the same. Background Art

[0002] The input signals of electronic circuits include three basic logic states: high level, low level and high impedance. Signals with these three logic states are referred to as tri-state signals. When designing a circuit, a detection circuit is usually used to identify the state of the input, and then the system is configured accordingly according to different input states.

[0003] In the prior art, the existing three-state input port circuit structure is relatively complex, consumes a lot of power, and is difficult to adapt to a wide range of power supply voltage changes. The traditional three-state input port circuit may also have detection errors when there is high noise or unstable power supply voltage, and has poor anti-interference ability.

[0004] Therefore, it is hoped that there will be a new three-state input port circuit that can overcome the above problems. Summary of the invention

[0005] In view of the above problems, an object of the present invention is to provide a three-state input port circuit and a chip, a display panel and a display device comprising the same, and in particular, a three-state input port circuit architecture, so as to adapt to application scenarios with large changes in power supply voltage.

[0006] According to one aspect of the present invention, there is provided a three-state input port circuit, comprising:

[0007] A receiving end, the receiving end receiving an input signal;

[0008] A first branch, wherein a first end of the first branch is connected to the receiving end, and a second end of the first branch is connected to a first output end;

[0009] a second branch, a first end of the second branch being connected to the receiving end, and a second end of the second branch being connected to a second output end; and

[0010] a bias voltage source, the bias voltage source being connected to the first branch to control the current flowing through the first branch; the bias voltage source being connected to the second branch to control the current flowing through the second branch,

[0011] When the input signals received by the receiving end are different, the first output end and the second output end output different output combinations.

[0012] Optionally, the tri-state input port circuit further includes:

[0013] A filtering unit is connected to the receiving end to filter the input end and / or power supply noise.

[0014] Optionally, the tri-state input port circuit further includes a first transistor, a second transistor, a third transistor and a fourth transistor;

[0015] The first end of the first transistor is connected to the receiving end, the second end of the first transistor is connected to the first end of the third transistor, and the third end of the first transistor is connected to the bias voltage source;

[0016] The first end of the second transistor is connected to the second end of the fourth transistor, the second end of the second transistor is connected to the receiving end, and the third end of the second transistor is connected to the bias voltage source;

[0017] The third terminal of the third transistor is connected to the first terminal of the third transistor;

[0018] The first terminal of the fourth transistor is grounded, the third terminal of the fourth transistor is connected to the second terminal of the fourth transistor,

[0019] Wherein, the first transistor is a PMOS transistor, the first end of the first transistor is a drain, the second end of the first transistor is a source, and the third end of the first transistor is a gate;

[0020] The second transistor is an NMOS transistor, the first end of the second transistor is a source, the second end of the second transistor is a drain, and the third end of the second transistor is a gate;

[0021] The third transistor is a PMOS transistor, the first end of the third transistor is a drain, the second end of the third transistor is a source, and the third end of the third transistor is a gate;

[0022] The fourth transistor is an NMOS transistor, the first end of the fourth transistor is a source, the second end of the fourth transistor is a drain, and the third end of the fourth transistor is a gate.

[0023] Optionally, the tri-state input port circuit further includes a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor;

[0024] A first terminal of the fifth transistor is connected to the first output terminal, and a third terminal of the fifth transistor is connected to the second terminal of the first transistor;

[0025] A first terminal of the sixth transistor is grounded, and a second terminal of the sixth transistor is connected to the first output terminal;

[0026] The first terminal of the seventh transistor is connected to the second output terminal;

[0027] A first terminal of the eighth transistor is grounded, a second terminal of the eighth transistor is connected to the second output terminal, and a third terminal of the eighth transistor is connected to the first terminal of the second transistor;

[0028] The fifth transistor is a PMOS transistor, the first end of the fifth transistor is a drain, the second end of the fifth transistor is a source, and the third end of the fifth transistor is a gate;

[0029] The sixth transistor is an NMOS transistor, the first end of the sixth transistor is a source, the second end of the sixth transistor is a drain, and the third end of the sixth transistor is a gate;

[0030] The seventh transistor is a PMOS transistor, the first end of the seventh transistor is a drain, the second end of the seventh transistor is a source, and the third end of the seventh transistor is a gate;

[0031] The eighth transistor is an NMOS transistor, the first end of the eighth transistor is a source, the second end of the eighth transistor is a drain, and the third end of the eighth transistor is a gate.

[0032] Optionally, the tri-state input port circuit further includes a first resistor and a first capacitor;

[0033] The first end of the first resistor is connected to the receiving end; the second end of the first resistor is connected to the first end of the first capacitor, the third end of the sixth transistor and the third end of the seventh transistor respectively;

[0034] The second terminal of the first capacitor is grounded.

[0035] Optionally, the tri-state input port circuit further includes:

[0036] A second resistor, wherein a first end of the second resistor is connected to the receiving end, and a second end of the second resistor is respectively connected to a first end of the first resistor, a first end of the first transistor, and a second end of the second transistor.

[0037] Optionally, the bias voltage source comprises a cascode amplifier.

[0038] Optionally, the common-source common-gate amplifier includes a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor and a thirteenth transistor;

[0039] The first terminal of the ninth transistor is connected to the second terminal of the tenth transistor, the second terminal of the ninth transistor is connected to the first bias node, and the third terminal of the ninth transistor is connected to the first bias node;

[0040] A first terminal of the tenth transistor is grounded, a second terminal of the tenth transistor is connected to a third terminal of the tenth transistor, and a third terminal of the tenth transistor is connected to a third terminal of the thirteenth transistor;

[0041] The first terminal of the eleventh transistor is connected to the second terminal of the twelfth transistor, and the third terminal of the eleventh transistor is connected to the first terminal of the eleventh transistor;

[0042] The first terminal of the twelfth transistor is connected to the second bias node, and the third terminal of the twelfth transistor is connected to the second bias node;

[0043] A first terminal of the thirteenth transistor is grounded, and a second terminal of the thirteenth transistor is connected to the second bias node.

[0044] The ninth transistor is an NMOS transistor, the first end of the ninth transistor is a source, the second end of the ninth transistor is a drain, and the third end of the ninth transistor is a gate;

[0045] The tenth transistor is an NMOS transistor, the first end of the tenth transistor is a source, the second end of the tenth transistor is a drain, and the third end of the tenth transistor is a gate;

[0046] The eleventh transistor is a PMOS transistor, the first end of the eleventh transistor is a drain, the second end of the eleventh transistor is a source, and the third end of the eleventh transistor is a gate;

[0047] The twelfth transistor is a PMOS transistor, the first end of the twelfth transistor is a drain, the second end of the twelfth transistor is a source, and the third end of the twelfth transistor is a gate;

[0048] The thirteenth transistor is an NMOS transistor, a first end of the thirteenth transistor is a source, a second end of the thirteenth transistor is a drain, and a third end of the thirteenth transistor is a gate.

[0049] Optionally, the tri-state input port circuit further comprises a first transistor and a second transistor;

[0050] The first terminal of the first transistor is connected to the receiving terminal, and the third terminal of the first transistor is connected to the second bias node;

[0051] The second terminal of the second transistor is connected to the receiving end, and the third terminal of the second transistor is connected to the first bias node.

[0052] According to another aspect of the present invention, a chip is provided, which includes any one of the three-state input port circuits described above.

[0053] According to another aspect of the present invention, a display panel is provided, comprising any one of the three-state input port circuits described above.

[0054] According to another aspect of the present invention, a display device is provided, comprising a display panel and any one of the tri-state input port circuits described above.

[0055] The present invention provides a three-state input port circuit and a chip, a display panel and a display device including the same, wherein the first branch and the second branch are respectively connected to the receiving end, and the bias voltage source is respectively connected to the first branch and the second branch to control the current flowing through each branch. When the input signals received by the receiving end are different, the output ends corresponding to the first branch and the second branch output different output combinations, thereby realizing the input of the three-state signal; and the setting of the bias voltage source can adapt to application scenarios with large changes in the power supply voltage.

[0056] Furthermore, the setting of the bias voltage source effectively reduces the operating current of the port, reduces power consumption, and improves anti-interference capability.

[0057] Furthermore, the filtering unit is connected to the receiving end to perform filtering, and can filter out noise interference.

[0058] Furthermore, the circuit of the present application includes a common-source common-gate amplifier, in which the MOS tube is connected in series between the power supply and the ground, and the current increases exponentially with the power supply.

[0059] Furthermore, the circuit structure of the present application is simple and the power consumption is low. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0061] Figure 1 A schematic structural diagram of a tri-state input port circuit according to an embodiment of the present invention is shown;

[0062] Figure 2 A schematic structural diagram of a bias voltage source according to an embodiment of the present invention is shown;

[0063] Figure 3 A current-voltage schematic diagram is shown when the tri-state input port circuit according to an embodiment of the present invention is in operation. DETAILED DESCRIPTION

[0064] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, identical elements are represented by identical or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown in the drawings.

[0065] The specific implementation of the present invention is further described in detail below in conjunction with the accompanying drawings and examples. Many specific details of the present invention, such as the structure, materials, dimensions, processing technology and techniques of the components are described below to provide a clearer understanding of the present invention. However, as those skilled in the art will appreciate, the present invention may be implemented without following these specific details.

[0066] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean that it is directly on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Moreover, if the component is turned over, the layer or a region will be "below" or "beneath" another layer or another region.

[0067] According to one aspect of the present invention, a three-state input port circuit is provided. The three-state input port circuit includes a receiving end, a first branch, a second branch and a bias voltage source.

[0068] Specifically, the receiving end receives an input signal, and the input signal includes at least one of a high level, a low level, and a high impedance state (NC, floating state).

[0069] The first end of the first branch is connected to the receiving end, and the second end of the first branch is connected to the first output end.

[0070] The first end of the second branch is connected to the receiving end, and the second end of the second branch is connected to the second output end.

[0071] The bias voltage source is connected to the first branch to control the current flowing through the first branch. The bias voltage source is connected to the second branch to control the current flowing through the second branch.

[0072] When the input signals received by the receiving end are different, the first output end and the second output end output different output combinations.

[0073] In an optional embodiment of the present invention, a first transistor is provided on the first branch, and a bias voltage source is connected to a control terminal of the first transistor to control a current flowing through the first transistor (first branch). A second transistor is provided on the second branch, and a bias voltage source is connected to a control terminal of the second transistor to control a current flowing through the second transistor (second branch). The first transistor and the second transistor are, for example, MOS transistors, and their control terminals are gates.

[0074] In an optional embodiment of the present invention, the tri-state input port circuit further includes a filtering unit. The filtering unit is connected to the receiving end to filter the input end and / or power supply noise, for example, to filter the input signal. Optionally, the filtering unit includes a resistor (R) and a capacitor (C), and the filtering unit performs RC filtering to filter out noise interference.

[0075] Figure 1 FIG. 2 shows a schematic diagram of a three-state input port circuit according to an embodiment of the present invention. Figure 1 As shown, in a specific embodiment of the present invention, the tri-state input port circuit includes first to thirteenth transistors, a first resistor, a second resistor, a first capacitor and a bias voltage source. The first to thirteenth transistors are MOS (Metal-Oxide-SemiconductorField-Effect Transistor). For the convenience of description, Figure 1 For each transistor in the transistor, the port located at the top is called the second end, the port located at the bottom is called the first end, and the port located on the side of the first end and the second end is called the third end.

[0076] Specifically, the first end of the first transistor (MOS1) is connected to the receiving end 10. The second end of the first transistor (MOS1) is connected to the first end of the third transistor (MOS3). The third end of the first transistor (MOS1) is connected to a bias voltage source (the structure of the bias voltage source is not shown in the figure, and VBPB represents the bias voltage connected to the first transistor). Optionally, the first transistor (MOS1) is a PMOS tube (P-type MOS tube), the first end of the first transistor (MOS1) is a drain, the second end of the first transistor (MOS1) is a source, and the third end of the first transistor (MOS1) is a gate.

[0077] The first end of the second transistor (MOS2) is connected to the second end of the fourth transistor (MOS4). The second end of the second transistor (MOS2) is connected to the receiving end 10. The third end of the second transistor (MOS2) is connected to a bias voltage source (the structure of the bias voltage source is not shown in the figure, and VBNB represents the bias voltage connected to the second transistor). Optionally, the second transistor (MOS2) is an NMOS tube (N-type MOS tube), the first end of the second transistor (MOS2) is a source, the second end of the second transistor (MOS2) is a drain, and the third end of the second transistor (MOS2) is a gate.

[0078] The third end of the third transistor (MOS3) is connected to the first end of the third transistor (MOS3). Optionally, the second end of the third transistor (MOS3) is connected to the sky or to other devices. Optionally, the third transistor (MOS3) is a PMOS tube (P-type MOS tube). The first end of the third transistor (MOS3) is a drain, the second end of the third transistor (MOS3) is a source, and the third end of the third transistor (MOS3) is a gate.

[0079] The first end of the fourth transistor (MOS4) is grounded. The third end of the fourth transistor (MOS4) is connected to the second end of the fourth transistor (MOS4). Optionally, the fourth transistor (MOS4) is an NMOS tube (N-type MOS tube). The first end of the fourth transistor (MOS4) is a source, the second end of the fourth transistor (MOS4) is a drain, and the third end of the fourth transistor (MOS4) is a gate.

[0080] The first end of the fifth transistor (MOS5) is connected to the first output terminal 21. The third end of the fifth transistor (MOS5) is connected to the second end of the first transistor (MOS1). Optionally, the second end of the fifth transistor (MOS5) is connected to the sky or to other devices. Optionally, the fifth transistor (MOS5) is a PMOS tube (P-type MOS tube). The first end of the fifth transistor (MOS5) is a drain, the second end of the fifth transistor (MOS5) is a source, and the third end of the fifth transistor (MOS5) is a gate.

[0081] The first end of the sixth transistor (MOS6) is grounded, and the second end of the sixth transistor (MOS6) is connected to the first output terminal 21. Optionally, the sixth transistor is an NMOS tube (N-type MOS tube), the first end of the sixth transistor (MOS6) is the source, the second end of the sixth transistor (MOS6) is the drain, and the third end of the sixth transistor (MOS6) is the gate.

[0082] The first end of the seventh transistor (MOS7) is connected to the second output terminal 22. Optionally, the second end of the seventh transistor (MOS7) is connected to the sky or to other devices. Optionally, the seventh transistor (MOS7) is a PMOS tube (P-type MOS tube). The first end of the seventh transistor (MOS7) is a drain, the second end of the seventh transistor (MOS7) is a source, and the third end of the seventh transistor (MOS7) is a gate.

[0083] The first end of the eighth transistor (MOS8) is grounded, the second end of the eighth transistor (MOS8) is connected to the second output end 22, and the third end of the eighth transistor (MOS8) is connected to the first end of the second transistor (MOS2). Optionally, the eighth transistor (MOS8) is an NMOS tube (N-type MOS tube). The first end of the eighth transistor (MOS8) is a source, the second end of the eighth transistor (MOS8) is a drain, and the third end of the eighth transistor (MOS8) is a gate.

[0084] In an optional embodiment of the present invention, the tri-state input port circuit further includes a first resistor R1 and a first capacitor C1. The first end of the first resistor R1 is connected to the receiving end 10. The second end of the first resistor R1 is respectively connected to the first end of the first capacitor C1, the third end of the sixth transistor (MOS6) and the third end of the seventh transistor (MOS7). The second end of the first capacitor C1 is grounded. Optionally, the tri-state input port circuit further includes a second resistor R2. The first end of the second resistor R2 is connected to the receiving end 10, and the second end of the second resistor R2 is respectively connected to the first end of the first resistor R1, the first end of the first transistor (MOS1) and the second end of the second transistor (MOS2).

[0085] In an optional embodiment of the present invention, the first end of the first branch is connected to the receiving end 10, and the second end of the first branch is connected to the first output end 21. At least one of the first transistor (MOS1), the third transistor (MOS3), the fifth transistor (MOS5) and the sixth transistor (MOS6) is arranged on the first branch. The first end of the second branch is connected to the receiving end 10, and the second end of the second branch is connected to the second output end 22. At least one of the second transistor (MOS2), the fourth transistor (MOS4), the seventh transistor (MOS7) and the eighth transistor (MOS8) is arranged on the second branch. The receiving end 10 receives an input signal, and the input signal includes a high level (the receiving end 10 is connected to the power supply), a low level (the receiving end 10 is grounded) and a high impedance state (the receiving end 10 is suspended). Three different input signals correspond to the output of three different control code words, that is, the first output end 21 and the second output end 22 output different combinations.

[0086] Figure 2 FIG. 2 shows a schematic diagram of the structure of a bias current source according to an embodiment of the present invention. Figure 2 As shown, the bias current source according to an embodiment of the present invention includes a common-source common-gate amplifier (cascode structure). The common-source common-gate amplifier, for example, includes cascaded transistors, one of which is used as an input stage and the other is used as an output stage. The transistor of the input stage is responsible for providing high input impedance and low noise, and the transistor of the output stage is responsible for providing high output impedance and gain. Further, the common-source common-gate amplifier includes a ninth transistor (MOS9), a tenth transistor (MOS10), an eleventh transistor (MOS11), a twelfth transistor (MOS12) and a thirteenth transistor (MOS13).

[0087] Specifically, the first end of the ninth transistor (MOS9) is connected to the second end of the tenth transistor (MOS10), the second end of the ninth transistor (MOS9) is connected to the first bias node, and the third end of the ninth transistor (MOS9) is connected to the first bias node. The first bias node is, for example, VBNB as shown in the figure. The first bias node VBNB in ​​the bias current source is connected to Figure 1 The third end of the second transistor (MOS2) shown. Optionally, the second end / first bias node VBNB of the ninth transistor (MOS9) is connected to the sky or other devices. Optionally, the ninth transistor (MOS9) is an NMOS tube (N-type MOS tube). The first end of the ninth transistor (MOS9) is the source, the second end of the ninth transistor (MOS9) is the drain, and the third end of the ninth transistor (MOS9) is the gate.

[0088] The first end of the tenth transistor (MOS10) is grounded, the second end of the tenth transistor (MOS10) is connected to the third end of the tenth transistor (MOS10), and the third end of the tenth transistor (MOS10) is connected to the third end of the thirteenth transistor (MOS13). Optionally, the tenth transistor (MOS10) is an NMOS tube (N-type MOS). The first end of the tenth transistor (MOS10) is a source, the second end of the tenth transistor (MOS10) is a drain, and the third end of the tenth transistor (MOS10) is a gate.

[0089] The first end of the eleventh transistor (MOS11) is connected to the second end of the twelfth transistor (MOS12), and the third end of the eleventh transistor (MOS11) is connected to the first end of the eleventh transistor (MOS11). Optionally, the second end of the eleventh transistor (MOS11) is connected to the sky or to other devices. Optionally, the eleventh transistor (MOS11) is a PMOS tube (P-type MOS tube). The first end of the eleventh transistor (MOS11) is a drain, the second end of the eleventh transistor (MOS11) is a source, and the third end of the eleventh transistor (MOS11) is a gate.

[0090] The first terminal of the twelfth transistor (MOS12) is connected to the second bias node, and the third terminal of the twelfth transistor (MOS12) is connected to the second bias node. The second bias node is, for example, VBPB as shown in the figure. The second bias node VBPB in the bias current source is connected to Figure 1 The third end of the first transistor (MOS1) shown. Optionally, the twelfth transistor (MOS12) is a PMOS tube (P-type MOS tube). The first end of the twelfth transistor (MOS12) is a drain, the second end of the twelfth transistor (MOS12) is a source, and the third end of the twelfth transistor (MOS12) is a gate.

[0091] The first end of the thirteenth transistor (MOS13) is grounded, and the second end of the thirteenth transistor (MOS13) is connected to the second bias node. Optionally, the thirteenth transistor (MOS13) is an NMOS tube (N-type MOS tube). The first end of the thirteenth transistor (MOS13) is a source, the second end of the thirteenth transistor (MOS13) is a drain, and the third end of the thirteenth transistor (MOS13) is a gate.

[0092] Optionally, the tri-state input port circuit further includes a first transistor (MOS1) and a second transistor (MOS2). The first end of the first transistor (MOS1) is connected to the receiving end 10, and the third end of the first transistor (MOS1) is connected to the second bias node. The second end of the second transistor (MOS2) is connected to the receiving end 10, and the third end of the second transistor (MOS2) is connected to the first bias node.

[0093] The tri-state input port circuit according to the embodiment of the present invention adopts a common-source common-gate amplifier, two diode-connected MOS are connected in series between the power supply / ground, and the current increases exponentially with the power supply.

[0094] Figure 3 FIG. 2 shows a current-voltage schematic diagram of a three-state input port circuit according to an embodiment of the present invention when the circuit is operating. Figures 1 to 3 As shown, when the power supply voltage changes from 2.5V to 3.3V, the current (I1) flowing through the first transistor (MOS1) and the second transistor (MOS2) changes from 0.8μA to 5μA; when the power supply voltage is above 3.3V, the current (I1) flowing through the first transistor (MOS1) and the second transistor (MOS2) changes less around 5μA. For most tri-state input port circuits in the prior art, when the power supply voltage changes from 2.5V to 6V, the current (I0) flowing through the part corresponding to the first transistor and the second transistor of the present application changes from 0.5μA to more than 10μA. In contrast, the solution of the present application can effectively reduce the working current of the port.

[0095] According to another aspect of the present invention, a chip is provided. The chip includes the tri-state input port circuit as described above. Optionally, the receiving end of the tri-state input port circuit is connected to the pin of the chip. The chip according to the embodiment of the present invention can realize the detection and use of tri-state input.

[0096] According to another aspect of the present invention, a display panel is provided. The display panel includes the tri-state input port circuit as described above. The display panel may be a liquid crystal display panel, an organic light emitting diode (OLED) panel, an electronic ink panel, etc.

[0097] According to another aspect of the present invention, a display device is provided. The display device includes a display panel and the tri-state input port circuit as described above. The display device can be used for a television, a computer, a smart phone, etc. Optionally, the display device is at least one selected from a sub-millimeter diode light-emitting display device, a micron diode light-emitting display device, and a quantum dot diode light-emitting display device. The display device is, for example, a complete display including a display panel, a housing, a bracket, a circuit board, etc. The display device may include one or more display panels, and other necessary components (such as a power adapter, an interface port, a control button, etc.).

[0098] The tri-state input port circuit implemented according to the present invention and the chip, display panel and display device including the same can adapt to application scenarios with a large range of power supply voltage changes, and effectively reduce the port operating current, optimize power consumption and anti-interference capabilities. The tri-state input port circuit according to the embodiment of the present invention also has the characteristics of simple structure and low power consumption.

[0099] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0100] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A three-state input port circuit, comprising: A receiving end, the receiving end receiving an input signal; A first branch, wherein a first end of the first branch is connected to the receiving end, and a second end of the first branch is connected to a first output end; A second branch, a first end of the second branch is connected to the receiving end, and a second end of the second branch is connected to a second output end; as well as a bias voltage source, the bias voltage source being connected to the first branch to control a current flowing through the first branch; The bias voltage source is connected to the second branch to control the current flowing through the second branch, When the input signals received by the receiving end are different, the first output end and the second output end output different output combinations.

2. The tri-state input port circuit according to claim 1, wherein: The tri-state input port circuit also includes: A filtering unit is connected to the receiving end to filter the input end and / or power supply noise.

3. The tri-state input port circuit according to claim 1, wherein: The tri-state input port circuit further includes a first transistor, a second transistor, a third transistor and a fourth transistor; The first end of the first transistor is connected to the receiving end, the second end of the first transistor is connected to the first end of the third transistor, and the third end of the first transistor is connected to the bias voltage source; The first end of the second transistor is connected to the second end of the fourth transistor, the second end of the second transistor is connected to the receiving end, and the third end of the second transistor is connected to the bias voltage source; The third terminal of the third transistor is connected to the first terminal of the third transistor; The first terminal of the fourth transistor is grounded, the third terminal of the fourth transistor is connected to the second terminal of the fourth transistor, Wherein, the first transistor is a PMOS transistor, the first end of the first transistor is a drain, the second end of the first transistor is a source, and the third end of the first transistor is a gate; The second transistor is an NMOS transistor, the first end of the second transistor is a source, the second end of the second transistor is a drain, and the third end of the second transistor is a gate; The third transistor is a PMOS transistor, the first end of the third transistor is a drain, the second end of the third transistor is a source, and the third end of the third transistor is a gate; The fourth transistor is an NMOS transistor, the first end of the fourth transistor is a source, the second end of the fourth transistor is a drain, and the third end of the fourth transistor is a gate.

4. The tri-state input port circuit according to claim 3, wherein: The tri-state input port circuit further includes a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor; A first terminal of the fifth transistor is connected to the first output terminal, and a third terminal of the fifth transistor is connected to the second terminal of the first transistor; A first terminal of the sixth transistor is grounded, and a second terminal of the sixth transistor is connected to the first output terminal; The first terminal of the seventh transistor is connected to the second output terminal; A first terminal of the eighth transistor is grounded, a second terminal of the eighth transistor is connected to the second output terminal, and a third terminal of the eighth transistor is connected to the first terminal of the second transistor; The fifth transistor is a PMOS transistor, the first end of the fifth transistor is a drain, the second end of the fifth transistor is a source, and the third end of the fifth transistor is a gate; The sixth transistor is an NMOS transistor, the first end of the sixth transistor is a source, the second end of the sixth transistor is a drain, and the third end of the sixth transistor is a gate; The seventh transistor is a PMOS transistor, the first end of the seventh transistor is a drain, the second end of the seventh transistor is a source, and the third end of the seventh transistor is a gate; The eighth transistor is an NMOS transistor, the first end of the eighth transistor is a source, the second end of the eighth transistor is a drain, and the third end of the eighth transistor is a gate.

5. The tri-state input port circuit according to claim 4, wherein: The tri-state input port circuit further includes a first resistor and a first capacitor; The first end of the first resistor is connected to the receiving end; the second end of the first resistor is connected to the first end of the first capacitor, the third end of the sixth transistor and the third end of the seventh transistor respectively; The second terminal of the first capacitor is grounded.

6. The tri-state input port circuit according to claim 5, wherein: The tri-state input port circuit also includes: A second resistor, wherein a first end of the second resistor is connected to the receiving end, and a second end of the second resistor is respectively connected to a first end of the first resistor, a first end of the first transistor, and a second end of the second transistor.

7. The tri-state input port circuit according to claim 1, wherein: The bias voltage source includes a cascode amplifier.

8. The tri-state input port circuit according to claim 7, wherein: The cascode amplifier includes a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor and a thirteenth transistor; The first terminal of the ninth transistor is connected to the second terminal of the tenth transistor, the second terminal of the ninth transistor is connected to the first bias node, and the third terminal of the ninth transistor is connected to the first bias node; A first terminal of the tenth transistor is grounded, a second terminal of the tenth transistor is connected to a third terminal of the tenth transistor, and a third terminal of the tenth transistor is connected to a third terminal of the thirteenth transistor; The first terminal of the eleventh transistor is connected to the second terminal of the twelfth transistor, and the third terminal of the eleventh transistor is connected to the first terminal of the eleventh transistor; The first terminal of the twelfth transistor is connected to the second bias node, and the third terminal of the twelfth transistor is connected to the second bias node; A first terminal of the thirteenth transistor is grounded, and a second terminal of the thirteenth transistor is connected to the second bias node. The ninth transistor is an NMOS transistor, the first end of the ninth transistor is a source, the second end of the ninth transistor is a drain, and the third end of the ninth transistor is a gate; The tenth transistor is an NMOS transistor, the first end of the tenth transistor is a source, the second end of the tenth transistor is a drain, and the third end of the tenth transistor is a gate; The eleventh transistor is a PMOS transistor, the first end of the eleventh transistor is a drain, the second end of the eleventh transistor is a source, and the third end of the eleventh transistor is a gate; The twelfth transistor is a PMOS transistor, the first end of the twelfth transistor is a drain, the second end of the twelfth transistor is a source, and the third end of the twelfth transistor is a gate; The thirteenth transistor is an NMOS transistor, a first end of the thirteenth transistor is a source, a second end of the thirteenth transistor is a drain, and a third end of the thirteenth transistor is a gate.

9. The tri-state input port circuit according to claim 8, wherein: The tri-state input port circuit also includes a first transistor and a second transistor; The first terminal of the first transistor is connected to the receiving terminal, and the third terminal of the first transistor is connected to the second bias node; The second terminal of the second transistor is connected to the receiving end, and the third terminal of the second transistor is connected to the first bias node.

10. A chip, comprising: A three-state input port circuit as claimed in any one of claims 1 to 9.

11. A display panel, comprising: A three-state input port circuit as claimed in any one of claims 1 to 9.

12. A display device comprising: Display panel; as well as A three-state input port circuit as claimed in any one of claims 1 to 9.

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