A DMX and return-to-zero code synchronous output method and device

Abstract

The present invention discloses a method and device for synchronously outputting DMX and return-to-zero codes. The method includes: starting from when the first frame sequence generation pulse signal is received, according to the frame sequences of the several combined frames, reading several DMX data in one of the combined frames each time a new frame sequence generation pulse signal is received; starting from when the second frame sequence generation pulse signal is received, according to the frame sequences of the several combined frames, reading several return-to-zero code data in one of the combined frames each time a new frame sequence generation pulse signal is received. By adopting the present invention, the combined frames are processed according to the frame sequence generation pulse signal sent periodically, ensuring the synchronous output of two signals of DMX and return-to-zero codes.

Description

Technical Field

[0001] The present invention relates to the technical field of audio control, and particularly to a method and device for synchronously outputting DMX and return-to-zero codes. Background Art

[0002] In the existing technology, when it is necessary to simultaneously output DMX signals and return-to-zero code signals, due to the different characteristics of these two types of signals, the signal output may be asynchronous, resulting in the control devices (such as lighting and audio systems) being unable to respond correctly. In addition, if the received data frames do not arrive in the correct order, the output signals will be incorrect or chaotic. In the final waveform output process, the DMX signal and the return-to-zero code signal have different coding rules and transmission formats. Without appropriate conversion, the two signals of DMX and return-to-zero code cannot be correctly synchronously expressed. Summary of the Invention

[0003] An embodiment of the present invention provides a method and device for synchronously outputting DMX and return-to-zero codes, which processes a combined frame according to a pulse signal generated based on the frame sequence sent periodically to ensure the synchronous output of the two signals of DMX and return-to-zero code.

[0004] To achieve the above object, a first aspect of the embodiments of the present application provides a method for synchronously outputting DMX and return-to-zero codes, including:

[0005] Continuously obtaining a plurality of combined frames sent according to a preset period; the combined frame includes a frame sequence, a plurality of DMX data paths, and a plurality of return-to-zero code data paths;

[0006] Starting from generating a pulse signal when receiving the first frame sequence, according to the frame sequence of the plurality of combined frames, when a new pulse signal is generated each time a new frame sequence is received, reading a plurality of DMX data paths in one of the combined frames; sequentially reading the plurality of DMX data paths of the plurality of combined frames, and continuously generating a DMX output waveform;

[0007] Starting from generating a pulse signal when receiving the second frame sequence, according to the frame sequence of the plurality of combined frames, when a new pulse signal is generated each time a new frame sequence is received, reading a plurality of return-to-zero code data paths in one of the combined frames; sequentially reading the plurality of return-to-zero code data paths of the plurality of combined frames, and continuously generating a return-to-zero code output waveform;

[0008] Starting from the generation moment of the DMX output waveform, outputting the DMX output waveform at the corresponding port; starting from the generation moment of the return-to-zero code output waveform, outputting the return-to-zero code output waveform at the corresponding port.

[0009] In a possible implementation of the first aspect, starting from when the pulse signal is generated upon receiving the second frame sequence, according to the frame sequences of the plurality of combined frames, when a new frame sequence generates a pulse signal each time, several return-to-zero code data in one of the combined frames are read, specifically including:

[0010] Starting from when the pulse signal is generated upon receiving the second frame sequence, the plurality of combined frames are sorted in ascending order of frame sequence;

[0011] According to the sorting result and the preset return-to-zero code parameter duration, when a new frame sequence generates a pulse signal each time, several return-to-zero code data in one of the combined frames are read.

[0012] In a possible implementation of the first aspect, when a new frame sequence generates a pulse signal each time and several return-to-zero code data in one of the combined frames are read, specifically including:

[0013] According to the T0H parameter duration, T0L parameter duration, T1H parameter duration, and T1L parameter duration, several return-to-zero code data in one of the combined frames are converted into a return-to-zero code output sub-waveform.

[0014] In a possible implementation of the first aspect, according to the T0H parameter duration, T0L parameter duration, T1H parameter duration, and T1L parameter duration, converting several return-to-zero code data in one of the combined frames into a return-to-zero code output sub-waveform specifically includes:

[0015] Set a first timer, a second timer, and a third timer with consistent interruption periods and staggered trigger time points;

[0016] Make the difference between the trigger time point of the second timer and the trigger time point of the first timer be the T0H parameter duration;

[0017] Make the difference between the trigger time point of the third timer and the trigger time point of the first timer be the T1H parameter duration;

[0018] At the trigger time point of the first timer, the trigger time point of the second timer, and the trigger time point of the third timer, read the level values of several return-to-zero code data in one of the combined frames;

[0019] Obtain the return-to-zero code output sub-waveform according to all the level values.

[0020] In a possible implementation of the first aspect, obtaining the return-to-zero code output sub-waveform according to all the level values specifically includes:

[0021] If three consecutive level values are 110, convert them to 1;

[0022] If three consecutive level values are 100, convert them to 0.

[0023] In a possible implementation of the first aspect, starting from the generation of a pulse signal when receiving the first frame sequence, according to the frame sequences of the plurality of combined frames, when a new frame sequence generates a pulse signal each time, read a plurality of DMX data in one of the combined frames, specifically including:

[0024] Starting from the generation of a pulse signal when receiving the first frame sequence, sort the plurality of combined frames in ascending order of frame sequence;

[0025] According to the sorting result and preset DMX parameters, when a new frame sequence generates a pulse signal each time, read a plurality of DMX data in one of the combined frames.

[0026] In a possible implementation of the first aspect, the step of, according to the sorting result and preset DMX parameters, when a new frame sequence generates a pulse signal each time, read a plurality of DMX data in one of the combined frames, specifically includes:

[0027] According to the baud rate, start bit, and stop bit, convert a plurality of DMX data in one of the combined frames into a DMX output sub-waveform.

[0028] In a possible implementation of the first aspect, the step of, according to the baud rate, start bit, and stop bit, convert a plurality of DMX data in one of the combined frames into a DMX output sub-waveform, specifically includes:

[0029] Set a fourth timer with an interruption period being the reciprocal of the baud rate;

[0030] Convert a plurality of DMX data in one of the combined frames into a binary bit stream;

[0031] Insert a start bit in front of the binary bit stream and insert a stop bit behind the binary bit stream;

[0032] Each time the fourth timer interrupts, push the binary bit stream bit by bit to obtain a DMX output sub-waveform.

[0033] In a possible implementation of the first aspect, the step of, insert a start bit in front of the binary bit stream and insert a stop bit behind the binary bit stream, specifically includes:

[0034] Insert a start bit 0 in front of the binary bit stream and insert a stop bit 11 behind the binary bit stream.

[0035] A second aspect of the embodiments of the present application provides a DMX and return-to-zero code synchronous output device, including:

[0036] A frame rate control module, for periodically outputting a frame sequence generation pulse signal;

[0037] A receiving module, for continuously acquiring a plurality of combined frames sent according to a preset period; the combined frames include a frame sequence, a plurality of DMX data channels, and a plurality of return-to-zero code data channels;

[0038] A DMX module, for starting from the moment when the first frame sequence generation pulse signal is received, according to the frame sequences of the plurality of combined frames, reading a plurality of DMX data channels in one of the combined frames each time a new frame sequence generation pulse signal is received; sequentially reading the plurality of DMX data channels of the plurality of combined frames, and continuously generating a DMX output waveform;

[0039] A return-to-zero code module, for starting from the moment when the second frame sequence generation pulse signal is received, according to the frame sequences of the plurality of combined frames, reading a plurality of return-to-zero code data channels in one of the combined frames each time a new frame sequence generation pulse signal is received; sequentially reading the plurality of return-to-zero code data channels of the plurality of combined frames, and continuously generating a return-to-zero code output waveform;

[0040] An output module, for starting from the generation moment of the DMX output waveform, outputting the DMX output waveform at a corresponding port; starting from the generation moment of the return-to-zero code output waveform, outputting the return-to-zero code output waveform at a corresponding port.

[0041] Compared with the prior art, for a DMX and return-to-zero code synchronous output method and device provided by an embodiment of the present invention, the DMX output waveform is generated starting from the first frame sequence pulse signal, while the return-to-zero code output waveform is generated starting from the second frame sequence pulse, so that the relative time relationship between the two signals can be effectively adjusted, and the influence of delay can be reduced. The unified frame sequence controls the processing order of the combined frames and the reading of the DMX data and return-to-zero code data, ensuring the synchronous output of the two signals; according to the arrangement of the processing time by the frame sequence pulse signal, it also ensures the synchronous output of the DMX signal and the return-to-zero code signal, improving the consistency and accuracy of the signal output, reducing the risk of signal interference, and improving the overall efficiency of the system. This is very important for application scenarios that require precise control of lighting, audio, and other stage equipment. Description of the Drawings

[0042] Figure 1 is a schematic flowchart of a DMX and return-to-zero code synchronous output method provided by an embodiment of the present invention;

[0043] Figure 2 is a schematic diagram of the process of generating a frame sequence provided by an embodiment of the present invention;

[0044] Figure 3FIG. 0 is a schematic diagram of the process of converting data of return-to-zero code in a combined frame into a return-to-zero code waveform provided by an embodiment of the present invention;

[0045] Figure 4 FIG. 4 is a schematic diagram of the process of converting DMX data in a combined frame into a DMX waveform provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0046] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0047] To solve the above problems, please refer to Figure 1 , an embodiment of the present invention provides a method for synchronously outputting DMX and return-to-zero code, including:

[0048] S10. Continuously obtain a plurality of combined frames sent according to a preset period; the combined frames include a frame sequence, a plurality of paths of DMX data, and a plurality of paths of return-to-zero code data. Among them, the generation process of the frame sequence can be referred to Figure 2 .

[0049] S11. Starting from the moment when the first frame sequence generation pulse signal is received, according to the frame sequence of the plurality of combined frames, read a plurality of paths of DMX data in one of the combined frames each time a new frame sequence generation pulse signal is received; sequentially read the plurality of paths of DMX data in the plurality of combined frames, and continuously generate a DMX output waveform.

[0050] S12. Starting from the moment when the second frame sequence generation pulse signal is received, according to the frame sequence of the plurality of combined frames, read a plurality of paths of return-to-zero code data in one of the combined frames each time a new frame sequence generation pulse signal is received; sequentially read the plurality of paths of return-to-zero code data in the plurality of combined frames, and continuously generate a return-to-zero code output waveform.

[0051] S13. Starting from the generation moment of the DMX output waveform, output the DMX output waveform at the corresponding port; starting from the generation moment of the return-to-zero code output waveform, output the return-to-zero code output waveform at the corresponding port.

[0052] The above process can be used to realize the synchronous output of DMX (Digital Multiplex) signals and return-to-zero code (RZ, Return-to-Zero) signals:

[0053] S10 Continuously receive an external data stream, which contains a certain number of combined frames. Each combined frame contains necessary information, such as frame sequence, DMX data, and return-to-zero code data. This step is to ensure that the input data stream of the system is continuous and sent at a predetermined time interval, which is very important for real-time control.

[0054] It should be noted that in Figure 2 the shown combined frame, channels 1 - 6 are for DMX data output, and channels 7 - 8 are for return-to-zero code data output. This combined frame can be pre-produced by software and output in the bin file format.

[0055] Starting from the pulse signal generated by the first received frame sequence, S11 begins to parse the DMX data in each combined frame and convert it into a DMX output waveform. DMX data is usually used to control stage lights, special effects equipment, etc. By generating the DMX output waveform, it can be ensured that these devices work in a predetermined manner.

[0056] Starting from the pulse signal generated by the second received frame sequence, S12 begins to parse the return-to-zero code data in each combined frame and convert it into a return-to-zero code output waveform. The return-to-zero code is a special coding method that returns to the zero level at the end of each signal bit. This coding method helps to reduce the cumulative error in signal transmission. The return-to-zero code output waveform can be used to control certain devices that require return-to-zero code signals.

[0057] After generating the DMX and return-to-zero code output waveforms, S13 outputs these two signals on the corresponding ports. Outputting these two signals enables external devices to receive and perform corresponding actions according to the received signals.

[0058] The above solution can ensure that the DMX signal and the return-to-zero code signal can be correctly parsed and synchronously output. This is very important in many occasions. For example, in a stage lighting control system, precise time synchronization can ensure the perfect coordination of lighting effects and other special effects devices. In addition, the use of the return-to-zero code helps to reduce interference and errors in the signal transmission process, thereby improving the reliability and stability of the overall system.

[0059] Exemplarily, starting from the pulse signal generated by the second received frame sequence, according to the frame sequences of the several combined frames, when a new pulse signal is generated for each received frame sequence, reading the several channels of return-to-zero code data in one of the combined frames specifically includes:

[0060] Starting from the pulse signal generated by the second received frame sequence, sorting the several combined frames in ascending order of the frame sequence.

[0061] Read several pieces of return-to-zero code data in one of the combined frames each time a pulse signal is generated upon receiving a new frame sequence, according to the sorting result and the preset return-to-zero code parameter duration.

[0062] The processing of the return-to-zero code data starts from the second frame sequence (i.e., the second group of data). The first frame sequence is usually used to address the delay problem of synchronous output, while the actual processing of the return-to-zero code data starts from the second frame sequence. By setting the data processing to start from the second frame sequence, it can ensure the stable operation of the system, avoid the influence caused by the instability during the initialization stage, and also ensure the synchronous output with other misaligned DMX data.

[0063] Sort all the received combined frames in ascending order according to their frame sequences. This can ensure that the system processes the data in the correct order. This is to ensure that the output of the return-to-zero code data is in chronological order, which is crucial for maintaining the accuracy and consistency of the data.

[0064] Each time a pulse signal is generated upon receiving a new frame sequence, read the return-to-zero code data in the next combined frame according to the sorted combined frame sequence and the preset return-to-zero code parameter duration. This can ensure that the return-to-zero code data is read and processed in the correct time sequence, thus ensuring the accuracy of the output.

[0065] In this way, the system can efficiently and accurately process the return-to-zero code data, ensure that the output waveform meets the expectations, and thus achieve a good control effect.

[0066] Exemplarily, the step of reading several pieces of return-to-zero code data in one of the combined frames each time a pulse signal is generated upon receiving a new frame sequence specifically includes:

[0067] Convert several pieces of return-to-zero code data in one of the combined frames into a return-to-zero code output sub-waveform according to the T0H parameter duration, T0L parameter duration, T1H parameter duration, and T1L parameter duration.

[0068] Please refer to Figure 3 Exemplarily, the step of converting several pieces of return-to-zero code data in one of the combined frames into a return-to-zero code sub-waveform according to the T0H parameter duration, T0L parameter duration, T1H parameter duration, and T1L parameter duration specifically includes:

[0069] Set a first timer, a second timer, and a third timer with consistent interruption periods and staggered trigger time points.

[0070] Make the difference between the trigger time point of the second timer and the trigger time point of the first timer be the T0H parameter duration.

[0071] Make the difference between the trigger time point of the third timer and the trigger time point of the first timer be the duration of the T1H parameter.

[0072] At the trigger time point of the first timer, the trigger time point of the second timer, and the trigger time point of the third timer, read the level values of several channels of return-to-zero code data in a combined frame.

[0073] Obtain the return-to-zero code output sub-waveform based on all the level values.

[0074] The following uses a specific example to illustrate the conversion process:

[0075] A) As Figure 3 shown, define three timers (the first timer, the second timer, and the third timer), whose interruption periods are the same, but the trigger time points are staggered. The time by which the second timer timer2 lags behind the first timer timer1 is T0H, and the time by which the third timer timer3 lags behind timer1 is T1H.

[0076] B) Data conversion. For example, to send three bits of data 101, first convert it into nine bits of data 110100110. 1 corresponds to 110, and 0 corresponds to 100.

[0077] C) At the interruption moment of timer1, push the first bit data "1" of 110 to the GPIO interface. Then at the interruption moment of timer2, push the second bit data "1" of 110 to the GPIO interface. At the interruption moment of timer3, push the third bit data "0" of 110 to the GPIO interface.

[0078] D) Through the above process, 0 and 1 can be converted into a return-to-zero code waveform and sent out. For more data, just loop the above process because all data is composed of 0 and 1.

[0079] Exemplarily, the obtaining of the return-to-zero code output sub-waveform based on all the level values specifically includes:

[0080] If three consecutive level values are 110, convert them to 1;

[0081] If three consecutive level values are 100, convert them to 0.

[0082] Exemplarily, the reading of several channels of DMX data in a combined frame each time a new pulse signal is generated according to the frame sequence of the several combined frames starting from the generation of the pulse signal for the first frame sequence specifically includes:

[0083] Starting from the generation of the pulse signal for the first frame sequence, sort the several combined frames in ascending order of the frame sequence;

[0084] According to the sorting result and the preset DMX parameters, read several DMX data in one of the combined frames each time a new frame sequence generation pulse signal is received.

[0085] Starting from the generation of the pulse signal for the first frame sequence, this means that the processing of DMX data starts from the reception of the first frame sequence (i.e., the first set of data). This is the starting point of the entire processing flow. By setting the data processing to start from the first frame sequence, it can be ensured that the system can immediately start processing the received data, thus achieving a fast response. More importantly, processing the DMX data in sequence according to the frame sequence and starting the processing of the DMX data according to the pulse signal generated by the frame sequence can maintain the same processing principle as the return-to-zero code data that is also processed in sequence according to the frame sequence and starts the processing according to the pulse signal generated by the frame sequence, effectively controlling the synchronization of the output waveform. That is, by triggering the reading of new data through the pulse signal, precise synchronization with other system components can be achieved.

[0086] In this way, the system can efficiently and accurately process the DMX data, ensure that the output waveform meets the expectations, and thus achieve a good control effect.

[0087] Exemplarily, the step of reading several DMX data in one of the combined frames each time a new frame sequence generation pulse signal is received according to the sorting result and the preset DMX parameters specifically includes:

[0088] Convert several DMX data in one of the combined frames into a DMX output sub-waveform according to the baud rate, start bit, and stop bit.

[0089] Exemplarily, the step of converting several DMX data in one of the combined frames into a DMX output sub-waveform according to the baud rate, start bit, and stop bit specifically includes:

[0090] Set a fourth timer with an interrupt period of the reciprocal of the baud rate;

[0091] Convert several DMX data in one of the combined frames into a binary bit stream;

[0092] Insert a start bit in front of the binary bit stream and a stop bit behind the binary bit stream.

[0093] Each time the fourth timer interrupts, push the binary bit stream bit by bit to obtain a DMX output sub-waveform.

[0094] In DMX data, there are generally parameter configurations: break duration, mab duration, baud rate (usually 250000 bps, or 500000 bps or others according to chip parameter configurations), 1 start bit, 2 stop bits, and 8 data bits.

[0095] The following uses a specific example to illustrate the conversion process:

[0096] A) First, obtain the data to be output, byte by byte. For example, it is necessary to send 0xA2 (hexadecimal).

[0097] B) Convert 0xA2 into a binary bit stream, obtaining b’10100010.

[0098] C) DMX data requires a start bit (0) and two stop bits (1). Therefore, insert them into the original data, obtaining b’01010001011.

[0099] D) Configure timer4 (the fourth timer) with a fixed interrupt period of 1 / baud rate. However, each time an interrupt occurs, push the data obtained in step C bit by bit to the GPIO interface, and a DMX waveform can be generated.

[0100] Exemplarily, inserting a start bit in front of the binary bit stream and inserting stop bits behind the binary bit stream specifically includes:

[0101] Insert a start bit 0 in front of the binary bit stream and insert stop bits 11 behind the binary bit stream.

[0102] Compared with the prior art, a DMX and return-to-zero code synchronous output method provided by an embodiment of the present invention generates a DMX output waveform starting from the first frame sequence pulse signal, while the return-to-zero code output waveform starts from the second frame sequence pulse. In this way, the relative time relationship between the two signals can be effectively adjusted, reducing the influence of delay. The unified frame sequence controls the processing order of the combined frames, and the reading of DMX data and return-to-zero code data ensures the synchronous output of the two signals; according to the arrangement of the processing time by the frame sequence pulse signal, it also ensures the synchronous output of the DMX signal and the return-to-zero code signal, improving the consistency and accuracy of signal output, reducing the risk of signal interference, and improving the overall efficiency of the system. This is very important for application scenarios that require precise control of lights, sound, and other stage equipment.

[0103] An embodiment of the present application provides a DMX and return-to-zero code synchronous output device, including: a frame rate control module, a receiving module, a DMX module, a return-to-zero code module, and an output module.

[0104] The frame rate control module is used to periodically output a frame sequence generation pulse signal.

[0105] A receiving module, configured to continuously obtain a plurality of combined frames sent at a preset period; the combined frames include a frame sequence number, a plurality of paths of DMX data, and a plurality of paths of return-to-zero code data.

[0106] A DMX module, configured to start generating a pulse signal from the moment when the first frame sequence number is received, and according to the frame sequence numbers of the plurality of combined frames, read the plurality of paths of DMX data in one of the combined frames each time a new frame sequence number generates a pulse signal; sequentially read the plurality of paths of DMX data in the plurality of combined frames, and continuously generate a DMX output waveform.

[0107] A return-to-zero code module, configured to start generating a pulse signal from the moment when the second frame sequence number is received, and according to the frame sequence numbers of the plurality of combined frames, read the plurality of paths of return-to-zero code data in one of the combined frames each time a new frame sequence number generates a pulse signal; sequentially read the plurality of paths of return-to-zero code data in the plurality of combined frames, and continuously generate a return-to-zero code output waveform.

[0108] An output module, configured to output the DMX output waveform at a corresponding port starting from the generation moment of the DMX output waveform; and output the return-to-zero code output waveform at a corresponding port starting from the generation moment of the return-to-zero code output waveform.

[0109] The DMX and return-to-zero code synchronous output device can be applied to a controller system. After the controller is powered on, the frame rate control module starts to work, and the internal timer of the single-chip microcomputer of the system outputs a frame sequence number generation pulse signal regularly according to the set frame rate.

[0110] The DMX module generates a pulse signal according to the frame sequence number of the frame rate control unit, and the processed frame sequence number starts to increment by 1 from the frame sequence number f1; the return-to-zero code module generates a pulse signal according to the frame sequence number of the frame rate control unit, and when the second frame sequence number generation pulse signal arrives, the processed frame sequence number f1 starts to increment by 1.

[0111] The DMX module and the return-to-zero code module read the content with the frame sequence number f1 when processing the frame sequence number f1, and read the content with the frame sequence number fn when processing the frame sequence number fn according to different frame sequence numbers, and organize them into DMX data and return-to-zero code data and send them out. The organized data format is described in the above embodiments.

[0112] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working process of the above-described system can refer to the corresponding process in the foregoing method embodiments, and will not be elaborated herein.

[0113] Compared with the prior art, a DMX and return-to-zero code synchronous output device provided by an embodiment of the present invention generates a DMX output waveform starting from the first frame sequence pulse signal, while the return-to-zero code output waveform starts from the second frame sequence pulse. In this way, the relative time relationship between the two signals can be effectively adjusted to reduce the influence of delay. The unified frame sequence controls the processing order of the combined frames, and the reading of DMX data and return-to-zero code data ensures the synchronous output of the two signals; according to the arrangement of the processing time by the frame sequence pulse signal, it also ensures the synchronous output of the DMX signal and the return-to-zero code signal, improves the consistency and accuracy of signal output, reduces the risk of signal interference, and improves the overall efficiency of the system. This is very important for application scenarios that require precise control of lighting, sound, and other stage equipment.

[0114] An embodiment of the present application provides a computer-readable storage medium, which includes a stored computer program. When the computer program runs, it controls the device where the computer-readable storage medium is located to execute a DMX and return-to-zero code synchronous output method as described above.

[0115] The computer device can be a computing device such as a smart phone, a tablet computer, a desktop computer, and a cloud server. The computer device may include but is not limited to a processor and a memory. Those skilled in the art can understand that the figure is only an example of the computer device and does not constitute a limitation on the computer device. It may include more or fewer components than shown, or combine certain components, or different components. For example, it may also include input / output devices, network access devices, etc.

[0116] The so-called processor may be a central processing unit (CPU), and the processor may also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0117] In some embodiments, the memory may be an internal storage unit of the computer device, such as the hard disk or memory of the computer device. In other embodiments, the memory may also be an external storage device of the computer device, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) card, a Flash Card, etc. equipped on the computer device. Further, the memory may also include both the internal storage unit and the external storage device of the computer device. The memory is used to store an operating system, application programs, a BootLoader, data, and other programs, such as the program code of the computer program. The memory may also be used to temporarily store data that has been output or is to be output.

[0118] An embodiment of the present application provides a computer program product. When the computer program product runs on a computer device, it enables the computer device to implement the steps in each of the above method embodiments when executed.

[0119] In several embodiments provided in the present application, it can be understood that each block in the flowchart or block diagram may represent a module, a program segment, or a part of code, and the module, program segment, or part of code includes one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in an order different from that marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved.

[0120] If the function is implemented in the form of a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for enabling a computer device to execute all or part of the steps of the methods described in various embodiments of the present application. The foregoing storage medium includes: various media such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disc that can store program code.

[0121] The above are the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements are also regarded as the protection scope of the present invention.

Claims

1. A method for synchronously outputting DMX and return-to-zero codes, characterized in that, Including: Continuously obtaining a plurality of combined frames sent according to a preset period; the combined frames include a frame sequence number, a plurality of channels of DMX data, and a plurality of channels of return-to-zero code data; Starting from the moment when a pulse signal is generated by receiving the first frame sequence number, according to the frame sequence numbers of the plurality of combined frames, when a pulse signal is generated by receiving a new frame sequence number each time, read a plurality of channels of DMX data in one of the combined frames; sequentially read the plurality of channels of DMX data in the plurality of combined frames, and continuously generate a DMX output waveform; Starting from the moment when a pulse signal is generated by receiving the second frame sequence number, according to the frame sequence numbers of the plurality of combined frames, when a pulse signal is generated by receiving a new frame sequence number each time, read a plurality of channels of return-to-zero code data in one of the combined frames; Sequentially read the plurality of channels of return-to-zero code data in the plurality of combined frames, and continuously generate a return-to-zero code output waveform; Starting from the generation moment of the DMX output waveform, output the DMX output waveform at the corresponding port; starting from the generation moment of the return-to-zero code output waveform, output the return-to-zero code output waveform at the corresponding port; The step of starting from the moment when a pulse signal is generated by receiving the second frame sequence number, according to the frame sequence numbers of the plurality of combined frames, when a pulse signal is generated by receiving a new frame sequence number each time, read a plurality of channels of return-to-zero code data in one of the combined frames specifically includes: Starting from the moment when a pulse signal is generated by receiving the second frame sequence number, sort the plurality of combined frames in ascending order of the frame sequence number; According to the sorting result and the preset return-to-zero code parameter duration, when a pulse signal is generated by receiving a new frame sequence number each time, read a plurality of channels of return-to-zero code data in one of the combined frames; The step of starting from the moment when a pulse signal is generated by receiving the first frame sequence number, according to the frame sequence numbers of the plurality of combined frames, when a pulse signal is generated by receiving a new frame sequence number each time, read a plurality of channels of DMX data in one of the combined frames specifically includes: Starting from the moment when a pulse signal is generated by receiving the first frame sequence number, sort the plurality of combined frames in ascending order of the frame sequence number; According to the sorting result and the preset DMX parameters, when a pulse signal is generated by receiving a new frame sequence number each time, read a plurality of channels of DMX data in one of the combined frames.

2. The method for synchronously outputting DMX and return-to-zero codes as described in claim 1, wherein, The step of when a pulse signal is generated by receiving a new frame sequence number each time, read a plurality of channels of return-to-zero code data in one of the combined frames specifically includes: According to the T0H parameter duration, T0L parameter duration, T1H parameter duration, and T1L parameter duration, convert a plurality of channels of return-to-zero code data in one of the combined frames into a return-to-zero code output sub-waveform.

3. The method for synchronously outputting DMX and return-to-zero codes according to claim 2, characterized in that, The step of according to the T0H parameter duration, T0L parameter duration, T1H parameter duration, and T1L parameter duration, convert a plurality of channels of return-to-zero code data in one of the combined frames into a return-to-zero code output sub-waveform specifically includes: Set a first timer, a second timer, and a third timer with consistent interruption periods and staggered trigger time points; Make the difference between the trigger time point of the second timer and the trigger time point of the first timer be the T0H parameter duration; Make the difference between the trigger time point of the third timer and the trigger time point of the first timer be the T1H parameter duration; At the trigger time points of the first timer, the second timer, and the third timer, read the level values of several channels of return-to-zero code data in one of the combined frames; Obtain the return-to-zero code output sub-waveform based on all the level values.

4. The method for synchronously outputting DMX and return-to-zero codes according to claim 3, wherein, The obtaining of the return-to-zero code output sub-waveform based on all the level values specifically includes: If three consecutive level values are 110, convert them to 1; If three consecutive level values are 100, convert them to 0.

5. The method for synchronously outputting DMX and return-to-zero codes according to claim 1, wherein The reading of several channels of DMX data in one of the combined frames each time a new frame sequence generates a pulse signal according to the sorting result and preset DMX parameters specifically includes: Convert several channels of DMX data in one of the combined frames into a DMX output sub-waveform according to the baud rate, start bit, and stop bit.

6. The method for synchronously outputting DMX and return-to-zero codes as described in claim 5, wherein The converting of several channels of DMX data in one of the combined frames into a DMX output sub-waveform according to the baud rate, start bit, and stop bit specifically includes: Set a fourth timer with an interrupt period of the reciprocal of the baud rate; Convert several channels of DMX data in one of the combined frames into a binary bit stream; Insert a start bit in front of the binary bit stream and insert a stop bit behind the binary bit stream; Each time the fourth timer interrupts, push the binary bit stream bit by bit to obtain the DMX output sub-waveform.

7. The method for synchronously outputting DMX and return-to-zero code according to claim 6, wherein, The inserting of a start bit in front of the binary bit stream and inserting a stop bit behind the binary bit stream specifically includes: Insert a start bit 0 in front of the binary bit stream and insert a stop bit 11 behind the binary bit stream.

8. A DMX and return-to-zero code synchronous output device, characterized in that, Includes: A frame rate control module for periodically outputting a frame sequence generation pulse signal; A receiving module for continuously obtaining several combined frames sent according to a preset period; the combined frame includes a frame sequence, several channels of DMX data, and several channels of return-to-zero code data; A DMX module for starting from receiving the first frame sequence generation pulse signal, according to the frame sequences of the several combined frames, reading several channels of DMX data in one of the combined frames each time a new frame sequence generates a pulse signal; sequentially reading several channels of DMX data of the several combined frames and continuously generating a DMX output waveform; A return-to-zero code module for starting from receiving the second frame sequence generation pulse signal, according to the frame sequences of the several combined frames, reading several channels of return-to-zero code data in one of the combined frames each time a new frame sequence generates a pulse signal; Sequentially reading several channels of return-to-zero code data of the several combined frames and continuously generating a return-to-zero code output waveform; An output module for starting from the generation moment of the DMX output waveform, outputting the DMX output waveform at the corresponding port; starting from the generation moment of the return-to-zero code output waveform, outputting the return-to-zero code output waveform at the corresponding port; The return-to-zero code module starting from receiving the second frame sequence generation pulse signal, according to the frame sequences of the several combined frames, reading several channels of return-to-zero code data in one of the combined frames each time a new frame sequence generates a pulse signal specifically includes: Starting from the generation of a pulse signal when the second frame sequence is received, the return-to-zero code module sorts the several combined frames in ascending order of the frame sequence; According to the sorting result and the preset return-to-zero code parameter duration, several return-to-zero code data in one of the combined frames are read each time a new frame sequence generation pulse signal is received; Starting from the generation of a pulse signal when the first frame sequence is received, the DMX module reads several DMX data in one of the combined frames each time a new frame sequence generation pulse signal is received according to the frame sequence of the several combined frames. Specifically, it includes: Starting from the generation of a pulse signal when the first frame sequence is received, the DMX module sorts the several combined frames in ascending order of the frame sequence; According to the sorting result and the preset DMX parameters, several DMX data in one of the combined frames are read each time a new frame sequence generation pulse signal is received.

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