Data clock multiplexing receiving circuit, analog front-end processing module and receiver

Abstract

The invention discloses a data clock multiplexing receiving circuit, an analog front-end processing module and a receiver. Comprising an input module, a differential clock signal input switch module, a data signal input switch module, a multipath selection module, an analog front-end processing module, a differential clock signal output switch module, a data signal output switch module, a first output module and a second output module. The input module is connected with the analog front-end processing module through the differential clock signal input switch module; the analog front-end processing module is connected with the first output module through the differential clock signal output switch module; the input module is connected with the multi-path selection module through the data signal input switch module; the multi-path selection module is connected with the analog front-end processing module; and the analog front-end processing module is connected with the second output module through the data signal output switch module, so that differential clock signals or data signals are received, and the universality and compatibility of a clock path and a data path of the receiving circuit are improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of integrated circuits, and in particular to a data clock multiplexing receiving circuit, an analog front-end processing module and a receiver. Background Art

[0002] In modern electronic systems, the speed and efficiency of data transmission have a crucial impact on the overall performance. With the advancement of technology and the increase in application demand, especially in the fields of high-performance computing, data centers and communication systems, the demand for bandwidth is growing. The model of driving the continuous growth of computing power by miniaturizing circuit size has become very inefficient, and the integration of chiplet technology can further break through the computing power limit of the chip, reduce the complexity of chip design, and form a feature-rich chip.

[0003] However, there are many chip interconnection standards, such as UCIe, Bow, etc., and many high-speed interface protocols, such as DDR5, HBI3, PCIE4, etc. At present, in the electrical physical layer architecture defined by various interface protocols, the clock and data paths of the receiving circuit cannot be universal, resulting in low configurability, versatility and compatibility of the receiving circuit. Summary of the invention

[0004] The present invention provides a data clock multiplexing receiving circuit, an analog front-end processing module and a receiver, so that the receiving circuit can receive both differential clock signals and data signals, thereby improving the versatility and compatibility of the clock path and data path of the receiving circuit.

[0005] In a first aspect, an embodiment of the present invention provides a data clock multiplexing receiving circuit, comprising: an input module, a differential clock signal input switch module, a data signal input switch module, a multi-way selection module, an analog front-end processing module, a differential clock signal output switch module, a data signal output switch module, a first output module, and a second output module;

[0006] The input module is connected to the analog front-end processing module through the differential clock signal input switch module; the differential clock signal input switch module is used to conduct the path when the differential clock signal is input to the input module; the analog front-end processing module is used to amplify the differential clock signal and output a logic level signal according to the amplified differential clock signal;

[0007] The analog front-end processing module is connected to the first output module through the differential clock signal output switch module; the differential clock signal output switch module is used to conduct the path when the differential clock signal is input to the input module; the first output module is used to output a clock signal of a preset phase according to the logic level signal;

[0008] The input module is connected to the multi-way selection module through the data signal input switch module; the multi-way selection module is connected to the analog front-end processing module; the data signal input switch module is used to conduct the path when the input module inputs the data signal; the multi-way selection module is used to select the data signal of the input module connected to the analog front-end processing module, and the analog front-end processing module is used to amplify and output the data signal after high-frequency compensation;

[0009] The analog front-end processing module is connected to the second output module through the data signal output switch module; the data signal output switch module is used to turn on the path when the input module inputs a data signal; the second output module is used to output a data signal of a preset rate according to the amplified data signal.

[0010] Optionally, the analog front-end processing module includes: a continuous-time linear equalizer unit and a variable gain operational amplifier unit;

[0011] The differential clock signal input switch module is connected to the input end of the variable gain operational amplifier unit; the variable gain operational amplifier unit is used to amplify the differential clock signal when the input module inputs the differential clock signal, and output a logic level signal according to the amplified differential clock signal;

[0012] The output end of the multi-way selection module is connected to the input end of the continuous time linear equalizer unit, and the output end of the continuous time linear equalizer unit is connected to the input end of the variable gain operational amplifier unit. The continuous time linear equalizer unit is used to perform high frequency compensation on the data signal, and the variable gain operational amplifier unit is also used to amplify the compensated data signal when the input module inputs the data signal.

[0013] Optionally, the variable gain operational amplifier unit includes: a first operational amplifier unit, a second operational amplifier unit and a switch unit; the first operational amplifier unit is connected to the second operational amplifier unit through the switch unit; the switch unit is used to turn on the path when the input module inputs the differential clock signal;

[0014] Wherein, the first operational amplifier unit includes: a first transistor, a second transistor, a first variable load resistor, a second variable load resistor, a first current source and a second current source; the input end of the variable gain operational amplifier unit includes a first end and a second end;

[0015] The control electrode of the first transistor serves as the first end, the first electrode of the first transistor is connected to the first end of the first variable load resistor, and the second end of the first variable load resistor is connected to the system power supply; the second electrode of the first transistor is connected to the first end of the first current source, and the second end of the first current source is grounded;

[0016] The control electrode of the second transistor serves as the second end, the first electrode of the second transistor is connected to the first end of the second variable load resistor, and the second end of the second variable load resistor is connected to the system power supply; the second electrode of the second transistor is connected to the first end of the second current source, and the second end of the second current source is grounded;

[0017] The second operational amplifier unit includes: a third transistor, a fourth transistor, a third current source and a fourth current source;

[0018] The control electrode of the third transistor is connected to the first electrode of the first transistor through the switch unit; the first electrode of the third transistor is connected to the system power supply; the second electrode of the third transistor is connected to the first end of the third current source; the second end of the third current source is grounded;

[0019] The control electrode of the fourth transistor is connected to the first electrode of the second transistor through the switch unit; the first electrode of the fourth transistor is connected to the system power supply; the second electrode of the fourth transistor is connected to the first end of the fourth current source; and the second end of the fourth current source is grounded.

[0020] Optionally, the continuous time linear equalizer unit comprises: a third variable load resistor, a fourth variable load resistor, a source degeneration resistor, a source degeneration capacitor, a fifth transistor, a sixth transistor, a fifth current source and a sixth current source;

[0021] The control electrode of the fifth transistor and the control electrode of the sixth transistor serve as the input end of the continuous time linear equalizer unit, the first electrode of the fifth transistor is connected to the first end of the third variable load resistor, and the second end of the third variable load resistor is connected to the system power supply; the second electrode of the fifth transistor is connected to the first end of the fifth current source, and the second end of the fifth current source is grounded;

[0022] The first electrode of the sixth transistor is connected to the first end of the fourth variable load resistor, and the second end of the fourth variable load resistor is connected to the system power supply; the second electrode of the sixth transistor is connected to the first end of the sixth current source, and the second end of the sixth current source is grounded;

[0023] The second electrode of the fifth transistor is connected to the second electrode of the sixth transistor through the source degeneration capacitor; the second electrode of the fifth transistor is connected to the second electrode of the sixth transistor through the source degeneration resistor.

[0024] Optionally, the data clock multiplexing receiving circuit further includes a delay chain module;

[0025] The analog front-end processing module is connected to the delay chain module, and the delay chain module is respectively connected to the differential clock signal output switch module and the data signal output switch module; the delay chain module is used to de-skew the logic level signal or align the phase of the amplified data signal.

[0026] Optionally, the data clock multiplexing receiving circuit further includes: an electrostatic protection module, an attenuator module and an impedance matching module; the input module is connected to the electrostatic protection module, the electrostatic protection module is connected to the attenuator module, the attenuator module is connected to the impedance matching module, and the impedance matching module is respectively connected to the differential clock signal input switch module and the data signal input switch module;

[0027] The electrostatic protection module is used to provide circuit protection for the signal input by the input module; the attenuator module is used to attenuate the low-frequency part of the signal input by the input module and compensate for the high-frequency part; the impedance matching module is used to adjust the impedance of the signal input by the input module and the signal output by the analog front-end processing module to reduce the reflection coefficient.

[0028] Optionally, the electrostatic protection module includes: a first clamping diode, a second clamping diode

[0029] A port of the input module is connected to the cathode of the first clamping diode, and the anode of the first clamping diode is connected to the system power supply; the anode of the second clamping diode is connected to the cathode of the first clamping diode, and the cathode of the second clamping diode is grounded;

[0030] The attenuator module includes: a first voltage-dividing resistor, a first capacitor, a second voltage-dividing resistor and a second capacitor;

[0031] The output end of the electrostatic protection module is connected to the first end of the first voltage-dividing resistor, the second end of the first voltage-dividing resistor is connected to the first end of the second voltage-dividing resistor, and the second end of the second voltage-dividing resistor is grounded; the first capacitor is connected in parallel with the first voltage-dividing resistor; and the second capacitor is connected in parallel with the second voltage-dividing resistor.

[0032] Optionally, the data clock multiplexing receiving circuit further includes a Schmitt trigger output module, the Schmitt trigger output module is connected to the input module, and the Schmitt trigger output module is used to provide a bypass output mode.

[0033] In a second aspect, an embodiment of the present invention provides an analog front-end processing module, comprising: a continuous time linear equalizer unit and a variable gain operational amplifier unit; the output end of the continuous time linear equalizer unit is connected to the input end of the variable gain operational amplifier unit;

[0034] The input end of the continuous time linear equalizer unit is used to receive a data signal, the continuous time linear equalizer unit is used to perform high frequency compensation on the data signal, and the variable gain operational amplifier unit is used to amplify the compensated data signal;

[0035] The input end of the variable gain operational amplifier unit is also used to receive a differential clock signal; the variable gain operational amplifier unit is also used to amplify the differential clock signal when receiving the input differential clock signal, and output a logic level signal according to the amplified differential clock signal.

[0036] In a third aspect, an embodiment of the present invention provides a receiver, comprising a receiving circuit for data clock multiplexing as described in any embodiment of the present invention.

[0037] The data clock multiplexing receiving circuit provided by the embodiment of the present invention can select the data channel entering the analog front-end processing module by using the differential clock signal input switch module and the data signal input switch module to realize the switching between the data and receiving clock modes. When the input module receives the differential clock signal, the differential clock signal input switch module is in the on state, the differential clock signal is input to the analog front-end processing module, the differential clock signal is gain-amplified through the analog front-end processing module, the differential clock signal is converted from a current mode signal to a logic level signal, the differential clock signal output switch module is in the on state, and the clock signal of the preset phase is output through the first output module. When the input module inputs the data signal, the data signal input switch module is in the on state, the data signal is input to the analog front-end processing module, the data signal is gain-amplified, the data signal output switch module is in the on state, and the low-rate parallel data signal is output through the second output module, so that the receiving circuit can receive both the differential clock signal and the data signal, thereby improving the versatility and compatibility of the clock path and the data path of the receiving circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 A schematic diagram of the structure of a data clock multiplexing receiving circuit provided by an embodiment of the present invention;

[0039] Figure 2 A schematic structural diagram of another data clock multiplexing receiving circuit provided in an embodiment of the present invention;

[0040] Figure 3 A schematic diagram of the structure of a variable gain operational amplifier unit provided by an embodiment of the present invention;

[0041] Figure 4 A schematic diagram of the structure of a continuous time linear equalizer unit provided by an embodiment of the present invention;

[0042] Figure 5 A schematic diagram of the structure of a delay chain module provided by an embodiment of the present invention;

[0043] Figure 6 A schematic diagram of the structure of a delay unit provided by an embodiment of the present invention;

[0044] Figure 7 A schematic diagram of the structure of an electrostatic protection module provided by an embodiment of the present invention;

[0045] Figure 8 A schematic structural diagram of an attenuator module provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0047] Figure 1 A schematic diagram of a data clock multiplexing receiving circuit provided by an embodiment of the present invention is shown in FIG. Figure 1 , including: an input module 110, a differential clock signal input switch module 120, a data signal input switch module 130, a multi-way selection module 140, an analog front-end processing module 150, a differential clock signal output switch module 160, a data signal output switch module 170, a first output module 180 and a second output module 190;

[0048] The input module 110 is connected to the analog front-end processing module 150 through the differential clock signal input switch module 120; the differential clock signal input switch module 120 is used to conduct the path when the input module 110 inputs the differential clock signal; the analog front-end processing module 150 is used to amplify the differential clock signal and output a logic level signal according to the amplified differential clock signal;

[0049] The analog front-end processing module 150 is connected to the first output module 180 through the differential clock signal output switch module 160; the differential clock signal output switch module 160 is used to conduct the path when the input module 110 inputs the differential clock signal; the first output module 180 is used to output a clock signal of a preset phase according to the logic level signal;

[0050] The input module 110 is connected to the multi-channel selection module 140 through the data signal input switch module 130; the multi-channel selection module 140 is connected to the analog front-end processing module 150; the data signal input switch module 130 is used to conduct the path when the input module 110 inputs the data signal; the multi-channel selection module 140 is used to select the data signal of the input module 110 to be connected to the analog front-end processing module 150, and the analog front-end processing module 150 is used to perform high-frequency compensation on the data signal and then amplify and output it;

[0051] The analog front-end processing module 150 is connected to the second output module 190 through the data signal output switch module 170; the data signal output switch module 170 is used to turn on the path when the input module 110 inputs the data signal; the second output module 190 is used to output a data signal of a preset rate according to the amplified data signal.

[0052] Specifically, in commonly used interface standards such as UCIe, BoW, hbi and chiplet interface standards, differential clocks are usually used. Therefore, the input module 110 can adopt a differential line structure, and the input module 110 includes a first input port VIO_PAD+ and a second input port VIO_PAD-. The first input port VIO_PAD+ and the second input port VIO_PAD- are connected to the analog front-end processing module 150 through the differential clock signal input switch module 120 and the data signal input switch module 130, respectively. Among them, when the differential clock signal is input, the differential clock signal input switch module 120 is in the on state, and the differential clock signal can be input to the analog front-end processing module 150; when the data signal is input, the data signal input switch module 130 is in the on state, and the data signal can be input to the analog front-end processing module 150 through the multi-way selection module 140. Exemplarily, the multiplexer module 140 may adopt a multiplexer, which is a combinational logic circuit with multiple inputs and a single output, and can select one output from n inputs to a common output terminal according to different channel selection control signals. In an embodiment of the present invention, the multiplexer takes two inputs and one output as an example. The multiplexer module 140 can select the data signal at any one end of the first input port VIO_PAD+ and the second input port VIO_PAD-, thereby realizing the input selection of the single-ended data signal.

[0053] When a differential clock signal is input, the differential clock signal output switch module 160 is in an on state, and the first output module 180 can output a clock signal of a preset phase by converting the signal output by the analog front-end processing module 150. Exemplarily, the first output module 180 can use a two-stage injection locked ring oscillator (ILRO) to obtain a four-phase clock signal output.

[0054] When a data signal is input, the data signal output switch module 170 is in a conducting state. The second output module 190 can sample and deserialize the signal output by the analog front-end processing module 150, that is, convert the high-speed serial data signal into a low-speed parallel data signal. Exemplarily, the second output module 190 can use a high-speed sampler.

[0055] The data clock multiplexing receiving circuit provided in the embodiment of the present invention can select the data channel entering the analog front-end processing module 150 by using the differential clock signal input switch module 120 and the data signal input switch module 130 to realize the switching between the two modes of receiving data signals and receiving clock signals. When the differential clock signal is input to the first input port VIO_PAD+ and the second input port VIO_PAD- of the input module 110, the differential clock signal input switch module 120 is in the on state, and the differential clock signal is input to the analog front-end processing module 150. The differential clock signal is gain amplified by the analog front-end processing module 150, and the differential clock signal is converted from a current mode signal to a logic level signal. The differential clock signal output switch module 160 is in the on state, and a clock signal of a preset phase is output through the first output module 180. When data signals are input to the first input port VIO_PAD+ and the second input port VIO_PAD- of the input module 110, the data signal input switch module 130 is in the on state, and the data signal is input to the analog front-end processing module 150, and the data signal is gain amplified. The data signal output switch module 170 is in the on state, and a low-rate parallel data signal is output through the second output module 190, so that the receiving circuit can receive both differential clock signals and data signals, thereby improving the versatility and compatibility of the clock path and data path of the receiving circuit.

[0056] Based on the above embodiment, optionally, Figure 2 A schematic diagram of a receiving circuit for data clock multiplexing according to an embodiment of the present invention is shown in FIG. Figure 2 , the analog front-end processing module 150 includes: a continuous time linear equalizer unit 151 and a variable gain operational amplifier unit 152;

[0057] The differential clock signal input switch module 120 is connected to the input end of the variable gain operational amplifier unit 152; the variable gain operational amplifier unit 152 is used to amplify the differential clock signal when the input module 110 inputs the differential clock signal, and output a logic level signal according to the amplified differential clock signal;

[0058] The output end of the multi-way selection module 140 is connected to the input end of the continuous time linear equalizer unit 151, and the output end of the continuous time linear equalizer unit 151 is connected to the input end of the variable gain operational amplifier unit 152. The continuous time linear equalizer unit 151 is used to perform high frequency compensation on the data signal, and the variable gain operational amplifier unit 152 is also used to amplify the compensated data signal when the input module 110 inputs the data signal.

[0059] Specifically, the output end of the differential clock signal input switch module 120 is connected to the input end of the variable gain operational amplifier unit 152. Therefore, when the differential clock signal input switch module 120 is in the on state, the differential clock signal directly enters the variable gain operational amplifier unit 152, and the differential clock signal is amplified by the variable gain operational amplifier unit 152, and the differential clock signal is converted from a current mode signal to a logic level signal output.

[0060] The output end of the data signal input switch module 130 is connected to the continuous time linear equalizer unit 151 through the multi-way selection module 140. When the data signal input switch module 130 is in the on state, the data signal enters the continuous time linear equalizer unit 151 through the multi-way selection module 140, and the continuous time linear equalizer unit 151 is used to compensate the high frequency part of the data signal. Exemplarily, the continuous time linear equalizer unit 151 can adopt a continuous time linear equalizer (CTLE), and the continuous time linear equalizer can be used as a high-pass filter to compensate for the limited channel band. The continuous time linear equalizer can be connected to a digital to analog converter (DAC), and the DAC can provide a reference voltage VREF through digital coding. Exemplarily, the continuous time linear equalizer in the embodiment of the present invention can be implemented in an active manner. After the data signal is compensated by the continuous time linear equalizer unit 151, it can enter the variable gain operational amplifier unit 152, and be amplified by the variable gain operational amplifier unit 152 and then output.

[0061] Exemplarily, the variable gain operational amplifier unit 152 may include two stages of operational amplifier units. When processing the differential clock signal, the first stage operational amplifier unit performs gain amplification, and the second stage operational amplifier unit converts the differential clock signal from a current mode signal to a logic level signal output. When processing the data signal, the gain amplification may be performed only by the first stage operational amplifier unit. Exemplarily, the variable gain operational amplifier unit 152 may use a variable gain operational amplifier (VGA), and the VGA may change the amplification factor of the signal as needed.

[0062] Based on the above embodiment, optionally, Figure 3 A schematic diagram of a variable gain operational amplifier unit provided in an embodiment of the present invention is shown in FIG. Figure 3 The variable gain operational amplifier unit 152 includes: a first operational amplifier unit, a second operational amplifier unit and a switch unit S1; the first operational amplifier unit is connected to the second operational amplifier unit through the switch unit S1; the switch unit S1 is used to turn on the path when the input module 110 inputs a differential clock signal;

[0063] The first operational amplifier unit includes: a first transistor M1, a second transistor M1', a first variable load resistor RD, a second variable load resistor RD', a first current source ISS1 and a second current source ISS1'; the input end of the variable gain operational amplifier unit 152 includes a first end VIN and a second end VIN';

[0064] The control electrode of the first transistor M1 serves as the first terminal VIN, the first electrode of the first transistor M1 is connected to the first terminal of the first variable load resistor RD, and the second terminal of the first variable load resistor RD is connected to the system power supply VDD; the second electrode of the first transistor M1 is connected to the first terminal of the first current source ISS1, and the second terminal of the first current source ISS1 is grounded;

[0065] The control electrode of the second transistor M1' serves as the second terminal VIN', the first electrode of the second transistor M1' is connected to the first terminal of the second variable load resistor RD', and the second terminal of the second variable load resistor RD' is connected to the system power supply VDD; the second electrode of the second transistor M1' is connected to the first terminal of the second current source ISS1', and the second terminal of the second current source ISS1' is grounded;

[0066] The second operational amplifier unit includes: a third transistor M2, a fourth transistor M2', a third current source ISS2 and a fourth current source ISS2';

[0067] The control electrode of the third transistor M2 is connected to the first electrode of the first transistor M1 through the switch unit S1; the first electrode of the third transistor M2 is connected to the system power supply VDD; the second electrode of the third transistor M2 is connected to the first end of the third current source ISS2; the second end of the third current source ISS2 is grounded;

[0068] The control electrode of the fourth transistor M2' is connected to the first electrode of the second transistor M1' through the switch unit S1; the first electrode of the fourth transistor M2' is connected to the system power supply VDD; the second electrode of the fourth transistor M2' is connected to the first end of the fourth current source ISS2'; the second end of the fourth current source ISS2' is grounded.

[0069] Combination Figure 2 Exemplarily, the first transistor M1 and the second transistor M1' are both NMOS transistors, then the control electrode of the first transistor M1 is the gate, the first electrode of the first transistor M1 is the drain, and the second electrode of the first transistor M1 is the source; the control electrode of the second transistor M1' is the gate, the first electrode of the second transistor M1' is the drain, and the second electrode of the second transistor M1' is the source.

[0070] Exemplarily, the third transistor M2 and the fourth transistor M2' are both PMOS transistors, then the control electrode of the third transistor M2 is the gate, the first electrode of the third transistor M2 is the source, and the second electrode of the third transistor M2 is the drain; the control electrode of the fourth transistor M2' is the gate, the first electrode of the fourth transistor M2' is the source, and the second electrode of the fourth transistor M2' is the drain.

[0071] When the input module 110 inputs a data signal, the data signal is subjected to high-frequency compensation by the continuous-time linear equalizer unit 151 and then outputs a differential signal, which is input to the first operational amplifier unit through the first terminal VIN and / or the second terminal VIN'. At this time, the switch unit S1 is in the cut-off state, and the first operational amplifier unit is a common source amplifier, which converts the gate input signal of the first transistor M1 and the second transistor M1' into the output signal of the drain of the first transistor M1 and the second transistor M1'. The current changes, and the first variable load resistor RD and the second variable load resistor RD' are used as loads to generate a voltage signal output. The first variable load resistor RD and the second variable load resistor RD' provide gain for the common source operational amplifier, wherein the gain can be expressed as the product of the transconductance of the transistor and the variable load resistor. Therefore, by adjusting the resistance value of the first variable load resistor RD and the second variable load resistor RD', the gain of the operational amplifier can be adjusted. The first current source ISS1 and the second current source ISS1' can adjust relevant parameters through the external bias voltage BIAS, so that the first transistor M1 and the second transistor M1' can operate in the saturation region, thereby amplifying the input signal of the first terminal VIN and / or the second terminal VIN', wherein the drain of the first transistor M1 and / or the second transistor M1' serves as the output terminal VOUT of the first operational amplifier unit, and the amplified signal is output from the output terminal VOUT.

[0072] When the differential clock signal is input, the switch unit S1 is in the on state, combined with Figure 2 , the differential clock signal is input to the first operational amplifier unit through the first terminal VIN and the second terminal VIN'. The amplification process of the differential clock signal by the first operational amplifier unit is the same as the amplification process when the data signal is input. After the differential clock signal is amplified by the first operational amplifier unit, it will enter the third transistor M2 and the fourth transistor M2' of the second operational amplifier unit through the switch unit S1. The load of the second operational amplifier unit is the third current source ISS2 and the fourth current source ISS2'. The clock signal output by the output terminals Vout and Vout' of the second operational amplifier unit is determined by the state of the differential clock signal at the time of input. For example, if the original differential clock signal is low level, the output clock signal is low level. If the original differential clock signal is high level, the output clock signal is high level. In other words, the differential clock signal is converted from a current mode signal (CML signal) to a logic level signal (CMOS signal).

[0073] Optional, Figure 4 A schematic diagram of the structure of a continuous time linear equalizer unit provided by an embodiment of the present invention, see Figure 4, the continuous time linear equalizer unit 151 includes: a third variable load resistor RL, a fourth variable load resistor RL', a source degeneration resistor RS, a source degeneration capacitor CS, a fifth transistor M3, a sixth transistor M3', a fifth current source ISS and a sixth current source ISS';

[0074] The control electrode of the fifth transistor M3 and the control electrode of the sixth transistor M3' serve as the input terminal VIN1 of the continuous time linear equalizer unit 151, the first electrode of the fifth transistor M3 is connected to the first end of the third variable load resistor RL, and the second end of the third variable load resistor RL is connected to the system power supply VDD; the second electrode of the fifth transistor M3 is connected to the first end of the fifth current source ISS, and the second end of the fifth current source ISS is grounded;

[0075] A first electrode of the sixth transistor M3' is connected to a first end of a fourth variable load resistor RL', and a second end of the fourth variable load resistor RL' is connected to a system power supply VDD; a second electrode of the sixth transistor M3' is connected to a first end of a sixth current source ISS', and a second end of the sixth current source ISS' is grounded;

[0076] The second electrode of the fifth transistor M3 is connected to the second electrode of the sixth transistor M3 ′ via the source degeneration capacitor CS; the second electrode of the fifth transistor M3 is connected to the second electrode of the sixth transistor M3 ′ via the source degeneration resistor RS.

[0077] Exemplarily, the fifth transistor M3 and the sixth transistor M3' are both NMOS transistors, then the control electrode of the fifth transistor M3 is the gate, the first electrode of the fifth transistor M3 is the drain, and the second electrode of the fifth transistor M3 is the source; the control electrode of the sixth transistor M3' is the gate, the first electrode of the sixth transistor M3' is the drain, and the second electrode of the sixth transistor M3' is the source, and the drains of the fifth transistor M3 and the sixth transistor M3' serve as the output terminal VOUT1 of the continuous time linear equalizer unit 151. The continuous time linear equalizer unit 151 is used as a high-pass filter to compensate for the high-frequency part of the data signal, and a low-pass feedback network is formed by the source degeneration resistor RS and the source degeneration capacitor CS of the source of the fifth transistor M3 and the sixth transistor M3'. The source degeneration resistor RS and the source degeneration capacitor CS serve as the source negative feedback part of the differential common source circuit, so that the transmission function of the circuit has one more zero point, so as to have a high-pass characteristic.

[0078] Combination Figure 4 , the transmission equation of the continuous-time linear equalizer unit 151 can be expressed as:

[0079]

[0080] Among them, g m1,EQU is the equivalent transconductance, Z L is the output impedance, gm1 is the transconductance of the fifth transistor M3 and the sixth transistor M3'; CL is the load capacitance, RL is the load resistance, RS is the source degeneration resistance, and CS is the source degeneration capacitance.

[0081] in:

[0082]

[0083] The load resistor RL, the source degeneration capacitor CS, and the source degeneration resistor RS can be adjustable components, and the zero-pole frequency of the continuous time linear equalizer can be adjusted in time according to the amplitude-frequency characteristic curve of the channel. It should be noted that the load capacitor CL can be provided by the next stage of the circuit, which is not shown in the figure.

[0084] The fifth current source ISS and the sixth current source ISS' can be connected to a digital to analog converter (DAC), and the DAC can change the reference voltage through digital coding, and the output voltage can provide a bias voltage to the fifth current source ISS and the sixth current source ISS' to ensure that the continuous time linear equalizer unit 151 has a correct bias, so that the fifth transistor M3 and the sixth transistor M3' work in the saturation region. Among them, the tunable parts such as the digital coding of the DAC, the load resistor RL, the source degeneration capacitor CS, and the source degeneration resistor RS can be implemented by a separate finite state machine (FSM).

[0085] Based on the above embodiment, optionally, continue to refer to Figure 2 The data clock multiplexing receiving circuit also includes a delay chain module 210, the analog front-end processing module 150 is connected to the delay chain module 210, and the delay chain module 210 is respectively connected to the differential clock signal output switch module 160 and the data signal output switch module 170; the delay chain module 210 is used to de-skew the logic level signal output by the analog front-end processing module 150 when the input module 110 inputs a differential clock signal, or to align the phase of the amplified data signal output by the analog front-end processing module 150 when the input module 110 inputs a data signal.

[0086] Specifically, Figure 5 A schematic diagram of a delay chain module provided by an embodiment of the present invention is shown in FIG. Figure 5 The delay chain module 210 may include a plurality of delay cells cell0-celln connected in series. The delay time may be adjusted by changing the supply voltage of the delay cells. Through multi-stage adjustment, the data signal may be delayed and aligned, and the clock signal may be de-skewed. For example, Figure 6 A schematic diagram of a delay unit provided by an embodiment of the present invention is shown in FIG. Figure 6 , by connecting two inverters in series, the output end of the first inverter V1 is connected to the first end of the resistor R, the second end of the resistor R is connected to the input end of the second inverter V2, the second end of the resistor R is connected to the first electrode of the capacitor C, and the second electrode of the capacitor C is grounded. Among them, the first inverter V1 or the second inverter V2 is connected to the variable voltage Vtrl, and by controlling the variable voltage, the charging time of the delay capacitor C can be controlled, thereby controlling the delay time of the circuit.

[0087] Continue to see Figure 2 The data clock multiplexing receiving circuit also includes: an electrostatic protection module 220, an attenuator module 230 and an impedance matching module 240; the input module 110 is connected to the electrostatic protection module 220, the electrostatic protection module 220 is connected to the attenuator module 230, and the attenuator module 230 is connected to the impedance matching module 240; the impedance matching module 240 is respectively connected to the differential clock signal input switch module 120 and the data signal input switch module 130.

[0088] The electrostatic protection module 220 is used to provide circuit protection for the signal input by the input module 110; the attenuator module 230 is used to attenuate the low-frequency part of the signal input by the input module 110 and compensate for the high-frequency part; the impedance matching module 240 is used to adjust the impedance of the signal input by the input module 110 and the signal output by the analog front-end processing module 150 to reduce the reflection coefficient.

[0089] For example, Figure 7 A schematic diagram of the structure of an electrostatic protection module provided by an embodiment of the present invention is shown in FIG. Figure 7 , the electrostatic protection module 220 includes: a first clamping diode D1 and a second clamping diode D2;

[0090] One port of the input module 110 is connected to the cathode of the first clamping diode D1, and the anode of the first clamping diode D1 is connected to the system power supply VDD; the anode of the second clamping diode D2 is connected to the cathode of the first clamping diode D1, and the cathode of the second clamping diode D2 is grounded. The node between the cathode of the first clamping diode D1 and the anode of the second clamping diode D2 serves as an output terminal Vout1 of the electrostatic protection module 220.

[0091] Specifically, the first input port VIO_PAD+ and the second input port VIO_PAD- are respectively connected to an electrostatic protection module 220. When the input voltage of the first input port VIO_PAD+ and the second input port VIO_PAD- is at a normal level, the first clamping diode D1 and the second clamping diode D2 are in a high resistance state. When the input voltage of the first input port VIO_PAD+ and the second input port VIO_PAD- is too high, the first clamping diode D1 and the second clamping diode D2 suddenly change from a high resistance state to a low resistance state, discharge the instantaneous overcurrent caused by the abnormal overvoltage to the ground, quickly absorb most of the energy, and clamp the abnormal overvoltage at a lower level, thereby realizing the protection function of the subsequent circuit.

[0092] Figure 8 A schematic diagram of the structure of an attenuator module provided by an embodiment of the present invention is shown in FIG. Figure 8 , the attenuator module 230 includes: a first voltage-dividing resistor R1, a first capacitor C1, a second voltage-dividing resistor R2 and a second capacitor C2;

[0093] The output end Vout1 of the electrostatic protection module 220 is connected to the first end of the first voltage-dividing resistor R1, the second end of the first voltage-dividing resistor R1 is connected to the first end of the second voltage-dividing resistor R2, and the second end of the second voltage-dividing resistor R2 is grounded; the first capacitor C1 is connected in parallel with the first voltage-dividing resistor R1; the second capacitor C2 is connected in parallel with the second voltage-dividing resistor R2.

[0094] Specifically, the output terminal Vout1 of the electrostatic protection module 220 is connected to the first end of the first voltage-dividing resistor R1, wherein the first end of the first voltage-dividing resistor R1 can be used as the input terminal Vin1 of the attenuator module 230, and the node between the second end of the first voltage-dividing resistor R1 and the first end of the second voltage-dividing resistor R2 can be used as the output terminal Vout2 of the attenuator module 230. The attenuator module 230 uses a passive continuous time linear equalizer, which can attenuate the low-frequency part of the signal and compensate for the high-frequency part. The low-frequency gain is determined by the resistor ratio, and the high-frequency gain is determined by the capacitor ratio.

[0095] Combination Figure 8 , the transmission equation of the attenuator module 230 is:

[0096]

[0097] Among them, the zero frequency is:

[0098]

[0099] The pole frequency is:

[0100]

[0101] The DC gain is:

[0102]

[0103] The second voltage-dividing resistor R2 and the second capacitor C2 are adjustable components, so that the pole frequency can be adjusted.

[0104] See also Figure 2 The data clock multiplexing receiving circuit also includes: a Schmitt trigger output module 250, the Schmitt trigger output module 250 is connected to the input module 120, and the Schmitt trigger output module 250 is used to provide a bypass output mode.

[0105] Specifically, the Schmitt trigger output module 250 includes two Schmitt triggers, which are connected to the outputs of the first input port VIO_PAD+ and the second input port VIO_PAD-, and the Schmitt trigger output module 250 is in bypass output mode (bypass mode), and the signal of the input module 110 can be directly output to the outside through the Schmitt trigger output module 250. In bypass mode, the anti-interference ability and waveform conversion function of the Schmitt trigger are utilized. The Schmitt trigger can be used as a noise filter to help reduce the noise in the signal, thereby ensuring stable transmission of the signal.

[0106] The embodiment of the present invention also provides an analog front-end processing module, combined with Figure 2 The analog front-end processing module includes: a continuous time linear equalizer unit 151 and a variable gain operational amplifier unit 152; the output end of the continuous time linear equalizer unit 151 is connected to the input end of the variable gain operational amplifier unit 152;

[0107] The input end of the continuous time linear equalizer unit 151 is used to receive a data signal, the continuous time linear equalizer unit 151 is used to perform high frequency compensation on the data signal, and the variable gain operational amplifier unit 152 is used to amplify the compensated data signal;

[0108] The input end of the variable gain operational amplifier unit 152 is also used to receive a differential clock signal; the variable gain operational amplifier unit 152 is also used to amplify the differential clock signal when receiving the input differential clock signal, and output a logic level signal according to the amplified differential clock signal.

[0109] Specifically, the output end of the differential clock signal input switch module 120 is connected to the input end of the variable gain operational amplifier unit 152. Therefore, when the differential clock signal input switch module 120 is in the on state, the differential clock signal directly enters the variable gain operational amplifier unit 152, and the differential clock signal is amplified by the variable gain operational amplifier unit 152, and the differential clock signal is converted from a current mode signal to a logic level signal output.

[0110] The output end of the data signal input switch module 130 is connected to the continuous time linear equalizer unit 151 through the multi-way selection module 140. When the data signal input switch module 130 is in the on state, the data signal enters the continuous time linear equalizer unit 151 through the multi-way selection module 140, and the continuous time linear equalizer unit 151 is used to compensate for the high frequency part of the data signal. Exemplarily, the continuous time linear equalizer unit 151 can use CTLE, and the continuous time linear equalizer can be used as a high-pass filter to compensate for the limited channel band. The continuous time linear equalizer can be connected to a DAC, and the DAC can provide a reference voltage VREF through digital coding. Exemplarily, the continuous time linear equalizer in the embodiment of the present invention can be implemented in an active manner. After the data signal is compensated by the continuous time linear equalizer unit 151, it can enter the variable gain operational amplifier unit 152, and be amplified by the variable gain operational amplifier unit 152 and then output.

[0111] Exemplarily, the variable gain operational amplifier unit 152 may include two stages of operational amplifier units. When processing the differential clock signal, gain amplification is performed by the operational amplifier unit of the first stage, and the differential clock signal is converted from a current mode signal to a logic level signal output by the operational amplifier unit of the second stage. When processing the data signal, gain amplification can be performed only by the operational amplifier unit of the first stage. Exemplarily, the variable gain operational amplifier unit 152 may adopt a variable gain operational amplifier (Variable Gain Amplifier, VGA), and the VGA can change the amplification factor of the signal as needed. Among them, the related structures of the continuous time linear equalizer unit 151 and the variable gain operational amplifier unit 152 can be referred to 3 and Figure 4 , I will not go into details here.

[0112] An embodiment of the present invention further provides a receiver for receiving or sending a data signal or a clock signal. Since it includes the data clock multiplexing receiving circuit of any embodiment of the present invention, it has the same beneficial effects and will not be elaborated here.

[0113] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data clock multiplexing receiving circuit, characterized in that: include: Input module, differential clock signal input switch module, data signal input switch module, multi-way selection module, analog front-end processing module, differential clock signal output switch module, data signal output switch module, first output module and second output module; The input module is connected to the analog front-end processing module through the differential clock signal input switch module; the differential clock signal input switch module is used to conduct the path when the differential clock signal is input to the input module; The analog front-end processing module is used to amplify the differential clock signal and output a logic level signal according to the amplified differential clock signal; The analog front-end processing module is connected to the first output module through the differential clock signal output switch module; the differential clock signal output switch module is used to conduct the path when the differential clock signal is input to the input module; The first output module is used to output a clock signal of a preset phase according to the logic level signal; The input module is connected to the multi-way selection module through the data signal input switch module; the multi-way selection module is connected to the analog front-end processing module; the data signal input switch module is used to conduct the path when the input module inputs a data signal; The multi-channel selection module is used to select the data signal of the input module to be connected to the analog front-end processing module, and the analog front-end processing module is used to perform high-frequency compensation on the data signal and then amplify and output it; The analog front-end processing module is connected to the second output module through the data signal output switch module; the data signal output switch module is used to turn on the path when the input module inputs a data signal; the second output module is used to output a data signal of a preset rate according to the amplified data signal.

2. The data clock multiplexing receiving circuit according to claim 1, characterized in that: The analog front-end processing module includes: a continuous-time linear equalizer unit and a variable gain operational amplifier unit; The differential clock signal input switch module is connected to the input end of the variable gain operational amplifier unit; the variable gain operational amplifier unit is used to amplify the differential clock signal when the input module inputs the differential clock signal, and output a logic level signal according to the amplified differential clock signal; The output end of the multi-way selection module is connected to the input end of the continuous time linear equalizer unit, and the output end of the continuous time linear equalizer unit is connected to the input end of the variable gain operational amplifier unit. The continuous time linear equalizer unit is used to perform high frequency compensation on the data signal, and the variable gain operational amplifier unit is also used to amplify the compensated data signal when the input module inputs the data signal.

3. The data clock multiplexing receiving circuit according to claim 2, characterized in that: The variable gain operational amplifier unit comprises: a first operational amplifier unit, a second operational amplifier unit and a switch unit; the first operational amplifier unit is connected to the second operational amplifier unit through the switch unit; the switch unit is used to conduct the path when the input module inputs the differential clock signal; Wherein, the first operational amplifier unit includes: a first transistor, a second transistor, a first variable load resistor, a second variable load resistor, a first current source and a second current source; the input end of the variable gain operational amplifier unit includes a first end and a second end; The control electrode of the first transistor serves as the first end, the first electrode of the first transistor is connected to the first end of the first variable load resistor, and the second end of the first variable load resistor is connected to the system power supply; the second electrode of the first transistor is connected to the first end of the first current source, and the second end of the first current source is grounded; The control electrode of the second transistor serves as the second end, the first electrode of the second transistor is connected to the first end of the second variable load resistor, and the second end of the second variable load resistor is connected to the system power supply; the second electrode of the second transistor is connected to the first end of the second current source, and the second end of the second current source is grounded; The second operational amplifier unit includes: a third transistor, a fourth transistor, a third current source and a fourth current source; The control electrode of the third transistor is connected to the first electrode of the first transistor through the switch unit; the first electrode of the third transistor is connected to the system power supply; the second electrode of the third transistor is connected to the first end of the third current source; the second end of the third current source is grounded; The control electrode of the fourth transistor is connected to the first electrode of the second transistor through the switch unit; the first electrode of the fourth transistor is connected to the system power supply; the second electrode of the fourth transistor is connected to the first end of the fourth current source; and the second end of the fourth current source is grounded.

4. The data clock multiplexing receiving circuit according to claim 3, characterized in that: The continuous time linear equalizer unit comprises: a third variable load resistor, a fourth variable load resistor, a source degeneration resistor, a source degeneration capacitor, a fifth transistor, a sixth transistor, a fifth current source and a sixth current source; The control electrode of the fifth transistor and the control electrode of the sixth transistor serve as the input end of the continuous time linear equalizer unit, the first electrode of the fifth transistor is connected to the first end of the third variable load resistor, and the second end of the third variable load resistor is connected to the system power supply; the second electrode of the fifth transistor is connected to the first end of the fifth current source, and the second end of the fifth current source is grounded; The first electrode of the sixth transistor is connected to the first end of the fourth variable load resistor, and the second end of the fourth variable load resistor is connected to the system power supply; the second electrode of the sixth transistor is connected to the first end of the sixth current source, and the second end of the sixth current source is grounded; The second electrode of the fifth transistor is connected to the second electrode of the sixth transistor through the source degeneration capacitor; the second electrode of the fifth transistor is connected to the second electrode of the sixth transistor through the source degeneration resistor.

5. The data clock multiplexing receiving circuit according to any one of claims 1 to 4, characterized in that: Also included is a delay chain module; The analog front-end processing module is connected to the delay chain module, and the delay chain module is respectively connected to the differential clock signal output switch module and the data signal output switch module; the delay chain module is used to de-skew the logic level signal or align the phase of the amplified data signal.

6. The data clock multiplexing receiving circuit according to claim 5, characterized in that: Also includes: Electrostatic protection module, attenuator module and impedance matching module; The input module is connected to the electrostatic protection module, the electrostatic protection module is connected to the attenuator module, the attenuator module is connected to the impedance matching module, and the impedance matching module is respectively connected to the differential clock signal input switch module and the data signal input switch module; The electrostatic protection module is used to provide circuit protection for the signal input by the input module; the attenuator module is used to attenuate the low-frequency part of the signal input by the input module and compensate for the high-frequency part; the impedance matching module is used to adjust the impedance of the signal input by the input module and the signal output by the analog front-end processing module to reduce the reflection coefficient.

7. The data clock multiplexing receiving circuit according to claim 6, characterized in that: The electrostatic protection module includes: a first clamping diode, a second clamping diode A port of the input module is connected to the cathode of the first clamping diode, and the anode of the first clamping diode is connected to the system power supply; the anode of the second clamping diode is connected to the cathode of the first clamping diode, and the cathode of the second clamping diode is grounded; The attenuator module includes: a first voltage-dividing resistor, a first capacitor, a second voltage-dividing resistor and a second capacitor; The output end of the electrostatic protection module is connected to the first end of the first voltage-dividing resistor, the second end of the first voltage-dividing resistor is connected to the first end of the second voltage-dividing resistor, and the second end of the second voltage-dividing resistor is grounded; the first capacitor is connected in parallel with the first voltage-dividing resistor; and the second capacitor is connected in parallel with the second voltage-dividing resistor.

8. The data clock multiplexing receiving circuit according to claim 6, characterized in that: It also includes a Schmitt trigger output module, which is connected to the input module and is used to provide a bypass output mode.

9. An analog front-end processing module, characterized in that: include: a continuous-time linear equalizer unit and a variable-gain operational amplifier unit; The output end of the continuous time linear equalizer unit is connected to the input end of the variable gain operational amplifier unit; The input end of the continuous time linear equalizer unit is used to receive a data signal, the continuous time linear equalizer unit is used to perform high frequency compensation on the data signal, and the variable gain operational amplifier unit is used to amplify the compensated data signal; The input end of the variable gain operational amplifier unit is also used to receive a differential clock signal; the variable gain operational amplifier unit is also used to amplify the differential clock signal when receiving the input differential clock signal, and output a logic level signal according to the amplified differential clock signal.

10. A receiver, characterized in that: A receiving circuit comprising the data clock multiplexing as described in any one of claims 1-8.

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