A low resource overhead MSK timing error estimation method

Abstract

The application discloses a low-resource consumption MSK timing error estimation method, comprising the following steps: S1, a sending end inserts a repeated training sequence; S2, a receiving end performs 2bit differential demodulation on the training sequence, and normalizes the demodulation result; S3, a timing error measurement value is calculated through the normalized sequence, then the timing error measurement value is grouped, the mean value is calculated after the grouping, and the size of each group mean value is compared; S4, the offset direction of timing synchronization is determined through the comparison, then the timing synchronization error is calculated according to the timing error measurement value. The application estimates the timing error by means of the result of 2bit differential demodulation, the method can complete the timing error estimation within the duration of the training sequence, and the required time is far less than the locking time of the traditional closed-loop estimation method. Meanwhile, the calculation amount of the method is only L times of addition, 1 time of multiplication and 1 time of phase calculation, compared with the traditional open-loop estimation method which needs at least 2L times of addition, 4L times of multiplication and 1 time of phase calculation, the calculation complexity is very low, and in the hardware implementation, the timing error estimation module can reuse the demodulation module, without extra hardware resource consumption.

Description

Technical Field

[0001] The present invention relates to the field of wireless communications, and in particular to a low-resource-overhead MSK timing error estimation method. Background Art

[0002] Minimum shift keying (MSK) is a special form of binary frequency shift keying modulation. It features phase continuity, high bandwidth utilization, and minimal out-of-band radiation, making it widely used in digital communication systems. Timing synchronization, also known as clock synchronization, requires optimal sampling time. Advances or lags in timing will affect data recovery at the receiver, necessitating timing error estimation and compensation.

[0003] Commonly used timing synchronization algorithms in the prior art are mainly divided into closed-loop estimation methods and open-loop estimation methods. Closed-loop estimation methods, represented by the early-late gate phase-locked loop method, continuously adjust the local code phase through a feedback loop to gradually converge the timing error. However, this method often has a long lock time and is not suitable for burst signals, limiting its application scenarios. Open-loop estimation methods, represented by the MCM algorithm, are based on the autocorrelation of training sequences. The transmitter inserts a training sequence specified by both the transmitter and receiver into the pilot signal. Upon receiving the signal, the receiver uses the locally stored training sequence to correlate with the received pilot sequence, and estimates the timing synchronization error based on the correlation result. In hardware implementation, this method typically requires large-bit-width complex multiplication and addition operations to ensure error estimation accuracy. This consumes a large amount of hardware storage and wiring resources, increasing hardware resource overhead. Summary of the Invention

[0004] Aiming at the problems of the existing MSK timing error estimation algorithm, such as long locking time, large computational complexity, and high resource occupation, the present invention combines timing synchronization with demodulation and proposes a low-resource-overhead MSK signal timing error estimation method by multiplexing the demodulation module.

[0005] To achieve the above objectives, the present invention adopts the following technical solutions:

[0006] A low-resource-overhead MSK timing error estimation method comprises the following steps:

[0007] S1, the transmitter inserts a repeated training sequence;

[0008] S2. The receiving end performs 2-bit differential demodulation on the training sequence and normalizes the demodulation result.

[0009] S3. Calculate the timing error metric value using the normalized sequence, then group it, calculate the average value after grouping, and compare the average values ​​of each group;

[0010] S4. Determine the offset direction of the timing synchronization by comparing the sizes, and then calculate the timing synchronization error according to the timing error metric value.

[0011] As a preferred embodiment of the above solution, in step S1, the transmitting end inserts a pilot sequence p of length L before the data segment, where p is composed of M segments of repeated pilot sequences, and each pilot segment is {1,1,1,0,0,0}.

[0012] As a preferred embodiment of the above solution, step S2 includes:

[0013] S21, the receiving end completes frame detection and carrier synchronization by capturing, and performs 2-bit differential demodulation on the pilot sequence. The demodulation result is u k ,k=1,2,…,L;

[0014] S22, for sequence u k Normalize to get sequence v k , where the sequence v k The maximum absolute value is 1.

[0015] As a preferred embodiment of the above solution, step S3 includes:

[0016] S31. Calculate the timing error metric d using the following formula (1): k ,k=1,2,…,L:

[0017]

[0018] S32, error metric d k Draw once every 3 times and get d1 k , d2 k , d3 k , k=1,2,…L / 3, and calculate the sequence d1 respectively by the following formulas (2)-(4) k , d2 k , d3 k The mean of , the calculation results are d1, d2, d3:

[0019]

[0020] Among them, d1 k =d 3i-2 ,i=1,2,…L / 3,d2 k =d 3i-1 ,i=1,2,…L / 3,d3 k =d 3i ,i=1,2,…L / 3.

[0021] As a preferred embodiment of the above solution, in step S4, the timing error τ is calculated using the sequence d1, d2, and d3 according to the following formula (5):

[0022]

[0023] If the sum of sequence d1 is greater than or equal to the sum of sequence d2, the timing error is calculated using sequences d1 and d3. If the sum of sequence d1 is less than the sum of sequence d2, the timing error is calculated using sequences d2 and d3, where T is the duration of a single symbol.

[0024] Due to the above structure, the present invention has the following beneficial effects:

[0025] The present invention uses the results of 2-bit differential demodulation to perform timing error estimation. This method can complete timing error estimation within the duration of the training sequence, requiring significantly less time than the lock-in time of traditional closed-loop estimation methods. Furthermore, this method requires only L additions, 1 multiplication, and 1 phase calculation, compared to traditional open-loop estimation methods, which require at least 2L additions, 4L multiplications, and 1 phase calculation. This method significantly reduces computational complexity. Furthermore, in hardware implementation, the timing error estimation module can reuse the demodulation module, eliminating the need for redundant hardware resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments.

[0027] Figure 1 is a flow chart of the method of the present invention;

[0028] Figure 2 A flow chart of signal processing performed by a receiving end of the present invention;

[0029] Figure 3 Flowchart for calculating timing error of the present invention. DETAILED DESCRIPTION

[0030] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0031] like Figure 1 As shown, this embodiment provides a low-resource-overhead MSK timing error estimation method, including the following steps:

[0032] S1. The transmitter inserts a repeated training sequence: The transmitter inserts a pilot sequence p of length L before the data segment. p consists of M segments of repeated pilot sequences, and each pilot segment is {1,1,1,0,0,0}.

[0033] S2. The receiving end performs 2-bit differential demodulation on the training sequence and normalizes the demodulation result:

[0034] S21, the receiving end completes frame detection and carrier synchronization by capturing, and performs 2-bit differential demodulation on the pilot sequence. The demodulation result is u k ,k=1,2,…,L;

[0035] S22, for sequence u k Normalize to get sequence v k , where the sequence v k The maximum absolute value is 1;

[0036] S3. Calculate the timing error metric using the normalized sequence, then group it, calculate the mean after grouping, and compare the mean values ​​of each group:

[0037] S31. Calculate the timing error metric d using the following formula (1): k ,k=1,2,…,L:

[0038]

[0039] S32, error metric d k Draw once every 3 times and get d1 k , d2 k , d3 k , k=1,2,…L / 3, and calculate the sequence d1 respectively by the following formulas (2)-(4) k , d2 k , d3 k The mean of , the calculation results are d1, d2, d3:

[0040]

[0041] Among them, d1 k =d 3i-2 ,i=1,2,…L / 3,d2 k =d 3i-1 ,i=1,2,…L / 3,d3 k =d 3i ,i=1,2,…L / 3;

[0042] S4. Determine the offset direction of the timing synchronization by comparing the sizes, and then calculate the timing synchronization error based on the timing error metric:

[0043] The timing error τ is calculated from the sequence d1, d2, d3 according to the following formula (5):

[0044]

[0045] If the sum of sequence d1 is greater than or equal to the sum of sequence d2, the timing error is calculated using sequences d1 and d3. If the sum of sequence d1 is less than the sum of sequence d2, the timing error is calculated using sequences d2 and d3, where T is the duration of a single symbol.

[0046] The present invention is further illustrated below by introducing specific numerical values:

[0047] The transmitter inserts a pilot sequence p of length 60, which consists of 10 repeated pilot sequences of {1, 1, 1, 0, 0, 0}.

[0048] The receiving end completes frame detection and carrier synchronization by capturing and performs 2-bit differential demodulation on the pilot sequence. The demodulation result is u k ,k=1,2,…,60;

[0049] For sequence u k Perform row normalization to obtain the sequence v k ,

[0050]

[0051] Normalized sequence v k The maximum absolute value is 1;

[0052] Define the timing error metric as d k ,k=1,2,…,60, and the calculation formula is as follows:

[0053]

[0054] The error metric d k Draw once every 3 times and get d1 k , d2 k , d3 k ,k=1,2,…20, where d1 k =d 3i-2 ,i=1,2,…20,d2 k =d 3i-1 ,i=1,2,…20,d3 k =d 3i ,i=1,2,…20;

[0055] Calculate sequence d1 separately k , d2 k , d3 k The average value of d1, d2, d3

[0056]

[0057]

[0058] Compare the magnitudes of d1 and d2. If d1 ≥ d2, it indicates that the sampling point at this time has shifted forward compared to the optimal sampling point, and the offset τ is If d1 < d2, it indicates that the sampling point at this time has shifted backward compared to the optimal sampling point, and the offset τ is where T is the duration of a single symbol.

[0059] Taking real simulation data as an example, when the sampling point of the sequence shifts backward by 1 / 4T, through the calculation of this algorithm, it can be obtained that d1 = 0.0359, d2 = 0.1871, d3 = 0.4345. At this time, d1 < d2, indicating that the sampling point has shifted backward, and the offset Compared with the actual timing synchronization offset, the error is only 0.0076T.

[0060] The present invention estimates the timing error by means of the result of 2-bit differential demodulation. This method can complete the timing error estimation within the duration of the training sequence, and the required time is much less than the locking time of the traditional closed-loop estimation method. At the same time, the computational complexity of this method is only L additions, 1 multiplication and 1 phase calculation. Compared with the traditional open-loop estimation method, which requires at least 2L additions, 4L multiplications and 1 phase calculation, its computational complexity is very low. At the same time, in the hardware implementation, the timing error estimation module can reuse the demodulation module without additional hardware resource overhead.

[0061] The above are only the preferred embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A low-resource-overhead MSK timing error estimation method, characterized by: The following steps are involved: S1, the transmitter inserts a repeated training sequence; S2. The receiving end performs 2-bit differential demodulation on the training sequence and normalizes the demodulation result. S3. Calculate the timing error metric value using the normalized sequence, then group it, calculate the average value after grouping, and compare the average values ​​of each group; S4. Determine the offset direction of the timing synchronization by comparing the sizes, and then calculate the timing synchronization error based on the timing error metric value; In step S1, the transmitter inserts a pilot sequence p of length L before the data segment. p consists of M segments of repeated pilot sequences, and each pilot segment is {1,1,1,0,0,0}. Step S2 includes: S21, the receiving end completes frame detection and carrier synchronization by capturing, and performs 2-bit differential demodulation on the pilot sequence. The demodulation result is u k ,k=1,2,…,L; S22, for sequence u k Normalize to get sequence v k , where the sequence v k The maximum absolute value is 1; Step S3 includes: S31. Calculate the timing error metric d using the following formula (1): k ,k=1,2,…,L: S32, error metric d k Draw once every 3 times and get d1 k , d2 k , d3 k , k=1,2,…L / 3, and calculate the sequence d1 respectively by the following formulas (2)-(4) k , d2 k , d3 k The mean of , the calculation results are d1, d2, d3: Among them, d1 k =d 3i-2 ,i=1,2,…L / 3,d2 k =d 3i-1 ,i=1,2,…L / 3,d3 k =d 3i ,i=1,2,…L / 3; In step S4, the timing error τ is calculated using the sequence d1, d2, and d3 according to the following formula (5): If the sum of sequence d1 is greater than or equal to the sum of sequence d2, the timing error is calculated using sequences d1 and d3. If the sum of sequence d1 is less than the sum of sequence d2, the timing error is calculated using sequences d2 and d3, where T is the duration of a single symbol.

Images