Semiconductor device, power module, conversion circuit, vehicle and device manufacturing method

Abstract

The present invention discloses a semiconductor device, a power module, a conversion circuit, a vehicle and a method for preparing the device, wherein the semiconductor device comprises: a semiconductor body, the semiconductor body comprises a substrate, an epitaxial layer, a well region, a first region and a second region, the semiconductor body is provided with a gate trench and a source trench, both of which extend from the first surface to the epitaxial layer; the second region is provided on the side of the source trench away from or close to the gate trench; the first region and the epitaxial layer are of the first doping type, the well region and the second region are of the second doping type; the gate structure is located in the gate trench; the source structure is located in the source trench; the drain is located on the side of the substrate away from the epitaxial layer. The semiconductor device provided by the present invention reduces the reverse conduction voltage drop of the semiconductor device, increases the leakage speed of the semiconductor device when it is reversely connected, and improves the performance stability and safety of the semiconductor device.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor technology, and in particular, to a semiconductor device, a power module, a conversion circuit, a vehicle, and a method for manufacturing the device. Background Art

[0002] Silicon carbide trench devices have the advantages of high current density and small cell pitch, and are widely used. In existing trench devices, there is a PN junction parasitic diode between the source and the drain, which is often used as a freewheeling diode. However, when the source is connected to a positive voltage, its reverse conduction voltage drop is too large, affecting the stability and reliability of the device. Summary of the invention

[0003] The present invention provides a semiconductor device, a power module, a conversion circuit, a vehicle and a method for preparing the device, which can reduce the reverse conduction voltage drop of the semiconductor device, increase the leakage speed of the semiconductor device when it is reversely connected, and improve the performance stability and safety of the semiconductor device.

[0004] In a first aspect, an embodiment of the present invention provides a semiconductor device, including:

[0005] A semiconductor body, comprising a substrate, an epitaxial layer, a well region, a first region, and a second region, wherein the epitaxial layer is located on one side of the substrate, the well region is arranged on a side of the epitaxial layer away from the substrate, and the first region is arranged on a side of the well region away from the substrate; a surface of the first region away from the substrate is used as a first surface, and a gate trench and a source trench are respectively arranged on the first surface, and the gate trench and the source trench both extend from the first surface into the epitaxial layer; the second region is arranged on a side of the source trench away from or close to the gate trench; the first region and the epitaxial layer are of a first doping type, and the well region and the second region are of a second doping type;

[0006] A gate structure, located in the gate trench;

[0007] A source structure, located in the source trench;

[0008] The drain is located on a side of the substrate away from the epitaxial layer.

[0009] Optionally, the second region is arranged on a side of the source trench away from the gate trench, the second region extends from the first surface to the epitaxial layer, and the orthographic projection of the second region at the bottom of the source trench at least covers a portion of the bottom of the source trench.

[0010] Optionally, the semiconductor body further includes:

[0011] A first buried layer is arranged in the epitaxial layer on a side of the source trench close to the gate trench, wherein an orthographic projection of the first buried layer on a side wall of the source trench close to the gate trench does not overlap with an orthographic projection of the well region and the first region on a side wall of the source trench close to the gate trench.

[0012] Optionally, the second region is arranged on a side of the source trench close to the gate trench, and the second region extends from the first surface to the epitaxial layer; the orthographic projection of the second region at the bottom of the source trench at least covers a portion of the bottom of the source trench.

[0013] Optionally, the semiconductor body further includes:

[0014] A second buried layer is arranged in the epitaxial layer on the side of the source trench away from the gate trench, wherein the orthographic projection of the second buried layer on the side wall of the source trench away from the gate trench does not overlap with the orthographic projection of the well region and the first region on the side wall of the source trench away from the gate trench.

[0015] Optionally, the source structure includes a first insulating layer and a trench source;

[0016] The first insulating layer is arranged on the inner wall and the bottom of the source trench;

[0017] The trench source is disposed in the source trench on one side of the first insulating layer; wherein the length of the trench source in the extension direction of the source trench is greater than the depth of the source trench.

[0018] Optionally, the semiconductor device further includes:

[0019] A second insulating layer is disposed on a side of the first surface away from the gate structure; an orthographic projection of the second insulating layer on the first surface covers the gate structure;

[0020] The ohmic contact metal layer is located on a side of the second insulating layer away from the gate structure, and the ohmic contact metal layer is electrically connected to the first region; the metal material of the ohmic contact metal layer includes titanium.

[0021] In a second aspect, an embodiment of the present invention provides a power module, comprising a substrate and at least one semiconductor device according to any embodiment of the present invention, wherein the substrate is used to carry the semiconductor device.

[0022] In a third aspect, an embodiment of the present invention provides a power conversion circuit, wherein the power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction;

[0023] The power conversion circuit includes a circuit board and at least one semiconductor device according to any embodiment of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0024] In a fourth aspect, an embodiment of the present invention provides a vehicle, comprising a load and the power conversion circuit described in any embodiment of the present invention, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0025] In a fifth aspect, an embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising:

[0026] A semiconductor body is provided, the semiconductor body comprising a substrate, an epitaxial layer, a well region, a first region, and a second region, the epitaxial layer being located on one side of the substrate, the well region being arranged on a side of the epitaxial layer away from the substrate, and the first region being arranged on a side of the well region away from the substrate; a surface of the first region on a side away from the substrate is used as a first surface, a gate trench and a source trench are respectively arranged on the first surface, and the gate trench and the source trench both extend from the first surface into the epitaxial layer; the second region is arranged on a side of the source trench away from or close to the gate trench; the first region and the epitaxial layer are of a first doping type, and the well region and the second region are of a second doping type;

[0027] forming a gate structure in the gate trench;

[0028] forming a source structure in the source trench;

[0029] A drain is formed on a side of the substrate away from the epitaxial layer.

[0030] Optionally, when the second region is arranged on a side of the source trench away from the gate trench, the second region extends from the first surface to the epitaxial layer, and the orthographic projection of the second region at the bottom of the source trench at least covers a portion of the bottom of the source trench.

[0031] Optionally, the semiconductor body further includes a first buried layer;

[0032] The preparation method further comprises:

[0033] The first buried layer is formed in the epitaxial layer on a side of the source trench close to the gate trench, wherein an orthographic projection of the first buried layer on a side wall of the source trench close to the gate trench does not overlap with an orthographic projection of the well region and the first region on a side wall of the source trench close to the gate trench.

[0034] Optionally, when the second region is arranged on a side of the source trench close to the gate trench, the second region extends from the first surface into the epitaxial layer; and the orthographic projection of the second region at the bottom of the source trench at least covers a portion of the bottom of the source trench.

[0035] Optionally, the semiconductor body further includes a second buried layer;

[0036] The preparation method further comprises:

[0037] The second buried layer is formed in the epitaxial layer on the side of the source trench away from the gate trench, wherein the orthographic projection of the second buried layer on the side wall of the source trench away from the gate trench does not overlap with the orthographic projection of the well region and the first region on the side wall of the source trench away from the gate trench.

[0038] Optionally, forming a source structure in the source trench includes:

[0039] forming a first insulating layer on the inner wall and bottom of the source trench;

[0040] A trench source is formed in the source trench on one side of the first insulating layer, wherein a length of the trench source in an extending direction of the source trench is greater than a depth of the source trench.

[0041] Optionally, the semiconductor device further comprises: an ohmic contact metal layer and a second insulating layer;

[0042] The preparation method further comprises:

[0043] forming a second insulating layer on a side of the first surface away from the gate structure; an orthographic projection of the second insulating layer on the first surface covers the gate structure;

[0044] The ohmic contact metal layer is formed on a side of the second insulating layer away from the gate structure, and the ohmic contact metal layer is electrically connected to the first region; the metal material of the ohmic contact metal layer includes titanium.

[0045] The semiconductor device provided by the technical solution provided in the embodiment of the present invention includes: a semiconductor body, the semiconductor body includes a substrate, an epitaxial layer, a well region, a first region and a second region, the epitaxial layer is located on one side of the substrate, the well region is arranged on the side of the epitaxial layer away from the substrate, and the first region is arranged on the side of the well region away from the substrate; the surface of the first region away from the substrate is used as the first surface, and the first surface is respectively provided with a gate trench and a source trench, and the gate trench and the source trench both extend from the first surface to the epitaxial layer; the second region is arranged on the side of the source trench away from or close to the gate trench; the gate structure is located in the gate trench; the source structure is located in the source trench; the drain is located on the side of the substrate away from the epitaxial layer. The first region and the epitaxial layer are of the first doping type, and the well region and the second region are of the second doping type; due to the different doping types of the second region and the epitaxial layer, a PN junction parasitic diode can be formed between the second region and the epitaxial layer, which is used as a freewheeling diode. Furthermore, a PNP or NPN type transistor is formed between the epitaxial layer, the well region and the first region on one side of the source trench close to the gate trench, and is used as a freewheeling transistor. Therefore, when the source level is connected to a positive voltage, the freewheeling diode can be turned on, and the source structure serves as the control electrode of the freewheeling transistor, and the freewheeling transistor can also be turned on. By integrating the freewheeling diode and the freewheeling transistor, the reverse-connected freewheeling path of the semiconductor device is increased, the reverse conduction voltage drop of the semiconductor device is reduced, the leakage speed of the semiconductor device when reversely connected is increased, and the performance stability and safety of the semiconductor device are improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 A schematic diagram of the structure of a semiconductor device provided by an embodiment of the present invention;

[0047] Figure 2 A schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0048] Figure 3 A schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0049] Figure 4 A schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0050] Figure 5 is a flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention;

[0051] Figure 6 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention;

[0052] Figures 7 to 13Schematic diagram of the intermediate structure of the preparation process provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0053] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0054] Figure 1 A schematic diagram of a semiconductor device according to an embodiment of the present invention is shown in FIG. Figure 1 ,include:

[0055] A semiconductor body 100, the semiconductor body 100 includes a substrate 10, an epitaxial layer 20, a well region 30, a first region 40 and a second region 50, the epitaxial layer 20 is located on one side of the substrate 10, the well region 30 is arranged on the side of the epitaxial layer 20 away from the substrate 10, and the first region 40 is arranged on the side of the well region 30 away from the substrate 10; the surface of the first region 40 away from the substrate 10 is used as a first surface, and the first surface is respectively provided with a gate trench 70 and a source trench 60, and the gate trench 70 and the source trench 60 both extend from the first surface to the epitaxial layer 20; the second region 50 is arranged on the side of the source trench 60 away from or close to the gate trench 70; the first region 40 and the epitaxial layer 20 are of the first doping type, and the well region 30 and the second region 50 are of the second doping type;

[0056] A gate structure, located in the gate trench 70;

[0057] A source structure, located in the source trench 60;

[0058] The drain 110 is located on a side of the substrate 10 away from the epitaxial layer 20 .

[0059] Specifically, the material of the substrate 10 and the material of the epitaxial layer 20 may be the same or different. Exemplarily, the materials of the substrate 10 and the epitaxial layer 20 may include silicon or silicon carbide. The semiconductor device in the embodiment of the present invention may be a silicon carbide trench metal oxide semiconductor field effect transistor (Metal Oxide Semiconductor Field Effect Transistor, MOSFET). The first doping type in the embodiment of the present invention may be N-type doping, and the second doping type may be P-type doping, or the first doping type may be P-type doping, and the second doping type may be N-type doping. P+ and N+ shown in the accompanying drawings indicate that the ion doping concentration in the region is high, and P- and N- indicate that the ion doping concentration in the region is low. Among them, the N-type doping ions may be P (phosphorus) or N (nitrogen) ions, and the P-type doping ions may be Al (aluminum) ions or B (boron) ions. Exemplarily, the embodiment of the present invention takes the first doping type as N-type doping and the second doping type as P-type doping as an example. When the semiconductor device is an N-type device, the substrate 10 is N+ type doped, for example, it can be an N+ silicon carbide substrate 10; the epitaxial layer 20 is N- type doped, for example, it can be an N- silicon carbide epitaxial layer 20; when the semiconductor device is a P-type device, the substrate 10 is P+ type doped and the epitaxial layer 20 is P- type doped.

[0060] An epitaxial layer 20 is formed on one side of the substrate 10, a well region 30 is arranged on the side of the epitaxial layer 20 away from the substrate 10, and a first region 40 is arranged on the side of the well region 30 away from the substrate 10. The well region 30 is of the second doping type, and the first region 40 is of the first doping type. The well region 30 and the first region 40 are used to form a conductive channel of the semiconductor device, and the well region 30 and the first region 40 can be formed by epitaxial growth, ion implantation, or vapor deposition.

[0061] A gate trench 70 and a source trench 60 are formed on the first surface by an etching process, wherein the gate trench 70 and the source trench 60 can be formed by simultaneous etching in the same preparation process. In some other embodiments, the gate trench 70 and the source trench 60 are set to different depths, so the gate trench 70 and the source trench 60 need to be etched step by step in different preparation processes. For example, the depth of the source trench 60 can be 1.2-2.5 μm, and the depth of the gate trench 70 can be 0.7-1.2 μm. By selecting the appropriate source trench 60 depth and gate trench 70 depth, the on-resistance is optimized while ensuring the device performance and the breakdown voltage of the semiconductor device is improved, so that the device can work stably at a higher voltage. The gate trench 70 and the source trench 60 pass through the first region 40 and the well region 30, and extend from the first surface to the epitaxial layer 20. The source trench 60 is located on one side of the gate trench 70, and the source trench 60 can be an annular trench, which is set to a structure surrounding the gate trench 70. The source trench 60 may also be an independent trench, and a plurality of source trenches 60 are distributed on both sides of the gate trench 70. For example, Figure 1 Source trenches 60 are arranged on both sides of the middle gate trench 70. The two source trenches 60 can be arranged symmetrically or asymmetrically. A second region 50 is formed on one side of the source trench 60 away from the gate trench 70 by ion implantation.

[0062] The gate structure is arranged in the gate trench 70, and the source structure is arranged in the source trench 60. Exemplarily, the gate structure may include a first insulating layer 71 and a trench gate 72, the first insulating layer 71 is arranged on the inner wall and the bottom of the gate trench 70, the first insulating layer 71 may be a gate oxide layer, the gate oxide layer may be a high dielectric constant (K) material, the trench gate 72 may be a polysilicon layer, the gate structure is arranged in the gate trench 70, the well regions 30 on both sides of the gate structure may form a vertical conductive channel, the junction field-effect transistor (JFET) region may be eliminated, and the on-resistance of the semiconductor device may be lower.

[0063] The source structure may include a first insulating layer 71 and a trench source 62, wherein the first insulating layer 71 is arranged on the inner wall and the bottom of the source trench 60, and the trench source 62 may be a polysilicon layer, and the first insulating layer 71 in the source structure may be the same as the first insulating layer 71 in the gate structure. Therefore, during preparation, the first insulating layer 71 in the source structure and the first insulating layer 71 in the gate structure may be formed simultaneously. The source structure is arranged in the source trench 60, and the second region 50 is arranged on the side of the source trench 60 away from the gate trench 70, that is, the second region 50 is arranged on the side of the source structure away from the gate structure, and the doping type of the second region 50 is the same as the doping type of the well region 30, therefore, a depletion region may be formed between the second region 50 and the epitaxial layer 20, which may play a role in shielding the electric field of the gate structure, thereby improving the problem of gate oxide layer breakdown and ensuring the reliability of device operation. Furthermore, since the second region 50 and the epitaxial layer 20 have different doping types, a PN junction parasitic diode can be formed between the second region 50 and the epitaxial layer 20, which is used as a freewheeling diode 102. Furthermore, since the second region 50 is not provided on the side of the source trench 60 close to the gate trench 70, a PNP or NPN type transistor is formed between the epitaxial layer 20, the well region 30 and the first region 40 on the side of the source trench 60 close to the gate trench 70, which is used as a freewheeling transistor 101. Therefore, the freewheeling diode 102 and the freewheeling transistor 101 are respectively integrated on both sides of the source trench, the source metal layer 120 is electrically connected to the source structure, and the source metal layer 120 serves as the source of the semiconductor device. When the source is connected to a positive voltage, the freewheeling diode 102 can be turned on. When the source is connected to a positive voltage, the source structure serves as the control electrode of the freewheeling transistor 101, and the freewheeling transistor 101 can also be turned on. By integrating the freewheeling diode 102 and the freewheeling transistor 101, the freewheeling path of the semiconductor device when reversely connected is increased, the reverse conduction voltage drop of the semiconductor device is reduced, the leakage speed of the semiconductor device when reversely connected is increased, and the performance stability and safety of the semiconductor device are improved.

[0064] In some embodiments, the second region 50 may also be disposed on a side of the source trench 60 close to the gate trench 70. Figure 2 A schematic diagram of a semiconductor device according to an embodiment of the present invention is shown in FIG. Figure 2, the doping type of the second region 50 is the same as the doping type of the well region 30. Similarly, the second region 50 can also play a role in shielding the electric field of the gate structure. On the side of the source trench 60 close to the gate trench 70, a freewheeling diode 102 is formed between the second region 50 and the epitaxial layer 20. On the side of the source trench 60 away from the gate trench 70, a PNP or NPN type freewheeling triode 101 is formed between the epitaxial layer 20, the well region 30 and the first region 40. It can also play a role in increasing the reverse connection freewheeling path of the semiconductor device, reducing the reverse conduction voltage drop of the semiconductor device, and increasing the leakage speed of the semiconductor device when it is reversely connected.

[0065] The semiconductor device provided by the technical solution provided in the embodiment of the present invention includes: a semiconductor body 100, the semiconductor body 100 includes a substrate 10, an epitaxial layer 20, a well region 30, a first region 40 and a second region 50, the epitaxial layer 20 is located on one side of the substrate 10, the well region 30 is arranged on the side of the epitaxial layer 20 away from the substrate 10, and the first region 40 is arranged on the side of the well region 30 away from the substrate 10; the surface of the first region 40 away from the substrate 10 is used as the first surface, and the first surface is respectively provided with a gate trench 70 and a source trench 60, and the gate trench 70 and the source trench 60 both extend from the first surface to the epitaxial layer 20; the second region 50 is arranged on the side of the source trench 60 away from or close to the gate trench 70; the gate structure is located in the gate trench 70; the source structure is located in the source trench 60; the drain 110 is located on the side of the substrate 10 away from the epitaxial layer 20. The first region 40 and the epitaxial layer 20 are of the first doping type, and the well region 30 and the second region 50 are of the second doping type; due to the different doping types of the second region 50 and the epitaxial layer 20, a PN junction parasitic diode can be formed between the second region 50 and the epitaxial layer 20, which is used as a freewheeling diode 102. Further, since the second region 50 is not provided on the side of the source trench 60 close to the gate trench 70, a PNP or NPN type transistor is formed between the epitaxial layer 20, the well region 30 and the first region 40, which is used as a freewheeling transistor 101. Therefore, when the source level is connected to a positive voltage, the freewheeling diode 102 can be turned on, and the source structure serves as the control electrode of the freewheeling transistor 101, and the freewheeling transistor 101 can also be turned on. By integrating the freewheeling diode 102 and the freewheeling transistor 101, the freewheeling path of the semiconductor device in reverse connection is increased, the reverse conduction voltage drop of the semiconductor device is reduced, the leakage speed of the semiconductor device when reversely connected is increased, and the performance stability and safety of the semiconductor device are improved.

[0066] In some embodiments, the second region 50 is disposed on a side of the source trench 60 away from the gate trench 70 , and the second region 50 extends from the first surface into the epitaxial layer 20 , and the orthographic projection of the second region 50 at the bottom of the source trench 60 at least covers a portion of the bottom of the source trench 60 .

[0067] Continue to see Figure 1 Specifically, the second region 50 can be formed on one side of the source trench 60 by ion implantation, so that the second region 50 is distributed on the side of the source trench 60 away from the gate trench 70. In the embodiment of the present invention, the second region 50 is distributed on the side of the source trench 60 away from the gate trench 70, and a PN junction parasitic diode can be formed between the second region 50 and the epitaxial layer 20, which is used as a freewheeling diode 102. Among them, the positive projection of the second region 50 at the bottom of the source trench 60 at least covers part of the bottom of the source trench 60, that is, the second region 50 can at least partially cover the bottom of the source trench 60, or completely cover the bottom of the source trench 60, thereby increasing the contact area between the second region 50 and the epitaxial layer 20, thereby increasing the depletion region between the second region 50 and the epitaxial layer 20, and further improving the electric field to the shielding gate structure.

[0068] Figure 3 A schematic diagram of a semiconductor device according to an embodiment of the present invention is shown in FIG. Figure 3 The semiconductor body 100 also includes: a first buried layer 80, which is arranged in the epitaxial layer 20 on the side of the source trench 60 close to the gate trench 70, wherein the orthographic projection of the first buried layer 80 on the side wall of the source trench 60 close to the gate trench 70 does not overlap with the orthographic projection of the well region 30 and the first region 40 on the side wall of the source trench 60 close to the gate trench 70.

[0069] Specifically, with Figure 1 The difference between the semiconductor device shown in the figure is that a first buried layer 80 is arranged in the epitaxial layer 20 on the side of the source trench 60 close to the gate trench 70, and the first buried layer 80 can be formed by ion implantation, and the first buried layer 80 has the same doping type as the second region 50. Exemplarily, when forming the epitaxial layer 20, the first buried layer 80 can be formed by ion implantation, and the source trench 60 is formed according to the position of the first buried layer 80, so that the first buried layer 80 is distributed on the side of the source trench 60 close to the gate trench 70. The first buried layer 80 can also be coated on the bottom of the source trench 60, so as to be arranged adjacent to the second region 50 at the bottom of the source trench 60, and further improve the function of shielding the electric field of the gate structure. Among them, the first buried layer 80 can extend along the side wall of the source trench 60 in the direction pointing to the first region 40, but the first buried layer 80 does not contact the first region 40 and the well region 30, so as to avoid blocking the channel of the freewheeling triode 101.

[0070] In some embodiments, the second region 50 is disposed on one side of the source trench 60 close to the gate trench 70 , and the second region 50 extends from the first surface into the epitaxial layer 20 ; the orthographic projection of the second region 50 at the bottom of the source trench 60 at least covers a portion of the bottom of the source trench 60 .

[0071] Continue to see Figure 2 Specifically, the second region 50 can be formed on one side of the source trench 60 by ion implantation, so that the second region 50 is distributed on the side of the source trench 60 close to the gate trench 70. In the embodiment of the present invention, the second region 50 is distributed on the side of the source trench 60 close to the gate trench 70, and a PN junction parasitic diode can be formed between the second region 50 and the epitaxial layer 20, which is used as a freewheeling diode 102. Among them, the positive projection of the second region 50 at the bottom of the source trench 60 at least covers part of the bottom of the source trench 60, that is, the second region 50 can at least partially cover the bottom of the source trench 60, or completely cover the bottom of the source trench 60, thereby increasing the contact area between the second region 50 and the epitaxial layer 20, thereby increasing the depletion region between the second region 50 and the epitaxial layer 20, and the second region 50 is close to the side of the gate trench 70, which can further improve the electric field to the shielding gate structure.

[0072] Figure 4 A schematic diagram of a semiconductor device according to an embodiment of the present invention is shown in FIG. Figure 4 , specifically, with Figure 2 The difference between the semiconductor device shown in is that a second buried layer 90 is provided in the epitaxial layer 20 on the side of the source trench 60 away from the gate trench 70, and the second buried layer 90 can be formed by ion implantation, and the second buried layer 90 has the same doping type as the second region 50. Exemplarily, when forming the epitaxial layer 20, the second buried layer 90 can be formed by ion implantation, and the source trench 60 is formed according to the position of the second buried layer 90, so that the second buried layer 90 is distributed on the side of the source trench 60 close to the gate trench 70. The second buried layer 90 can also be coated on the bottom of the source trench 60, so as to be arranged adjacent to the second region 50 at the bottom of the source trench 60, and further improve the function of shielding the electric field of the gate structure. Among them, the first buried layer 80 can extend along the side wall of the source trench 60 in the direction pointing to the first region 40, but the first buried layer 80 does not contact the first region 40 and the well region 30, so as to avoid blocking the channel of the freewheeling triode 101.

[0073] Based on the above embodiments, optionally, the source structure includes a first insulating layer 71 and a trench source 62; the first insulating layer 71 is arranged on the inner wall and bottom of the source trench 60; the trench source 62 is arranged in the source trench 60 on one side of the first insulating layer 71; wherein the length of the trench source 62 in the extension direction of the source trench 60 is greater than the depth of the source trench 60.

[0074] Specifically, the first insulating layer 71 is arranged on the inner wall and the bottom of the source trench 60, the trench source 62 can be a polysilicon layer, and the first insulating layer 71 in the source structure is the same as the first insulating layer 71 in the gate structure. Therefore, during preparation, the first insulating layer 71 in the source structure and the first insulating layer 71 in the gate structure can be formed at the same time, and then the polysilicon layer is deposited, and then the entire polysilicon layer is etched back so that 200-500nm of the polysilicon layer on the first surface remains, and then the polysilicon layer in the source trench 60 is protected by a photoresist, and then the etch back is continued to fill the gate trench 70 with a polysilicon layer, and the deposition height of the polysilicon layer in the source trench 60 is greater than the depth of the source trench 60. That is to say, the polysilicon layer exceeds the plane where the first surface is located to form a protruding portion. Therefore, when the source metal layer 120 is formed on the first surface, the protruding portion will be inside the source metal layer 120, thereby increasing the contact area between the polysilicon layer and the source metal layer 120, which is beneficial to improving the voltage sensitivity of the control electrode of the freewheeling transistor 101 and controlling the conduction process of the freewheeling transistor 101. Exemplarily, the protruding portion can be cylindrical, trapezoidal pillar, conical or other regular or irregular shapes, as long as it can increase the contact area between the polysilicon layer and the source metal layer 120.

[0075] Combination Figure 1-Figure 4 , the semiconductor device further includes: a second insulating layer 130, disposed on a side of the first surface away from the gate structure; an orthographic projection of the second insulating layer 130 on the first surface covers the gate structure;

[0076] The ohmic contact metal layer 140 is located on a side of the second insulating layer 130 away from the gate structure. The ohmic contact metal layer 140 is electrically connected to the first region 40 . The metal material of the ohmic contact metal layer 140 includes titanium.

[0077] Specifically, a second insulating layer 130 is formed on the surface of the first region 40 away from the substrate 10. The second insulating layer 130 may be an interlayer dielectric layer (ILD). The second insulating layer 130 may cover the surface of the gate structure. An ohmic contact metal layer 140 is provided on the side of the second insulating layer 130 away from the gate structure. A source metal layer 120 is formed on the surface of the ohmic contact metal layer 140 away from the substrate 10. The second insulating layer 130 isolates the gate structure and the source metal layer 120. The ohmic contact metal layer 140 is electrically connected to the trench source 62. When the ohmic contact metal layer 140 contacts the trench source 62, the resistance of the contact surface is very small, so that the current-voltage relationship is linear and no obvious additional impedance is generated. Good ohmic contact can significantly reduce the contact resistance between the source and the trench source 62, thereby improving the conductive efficiency of the device. The ohmic contact metal of the ohmic contact metal layer 140 can be nickel (Ni), but Ni easily reacts with the polysilicon layer, resulting in reduced reliability of the device. Therefore, the ohmic contact metal can be titanium (Ti). For example, when Ti is used as the ohmic contact metal, the ohmic contact metal layer 140 will not react with the polysilicon layer, and the ohmic contact metal layer 140 has a contact connection with the first region 40. When the first region 40 is of N+ doping type, titanium and the first region 40 can obtain a lower contact resistance, thereby reducing the reverse conduction voltage drop of the freewheeling transistor 101.

[0078] An embodiment of the present invention provides a power module based on the above embodiment, including a substrate and a semiconductor device according to any embodiment of the present invention, wherein the substrate is used to carry the semiconductor device.

[0079] The power module provided by the technical solution of the embodiment of the present invention has the same beneficial effects as the semiconductor device of any embodiment of the present invention.

[0080] An embodiment of the present invention provides a power conversion circuit based on the above embodiments, and the power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one semiconductor device as in any embodiment of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0081] The power conversion circuit provided by the technical solution of the embodiment of the present invention has the same beneficial effects as the semiconductor device of any embodiment of the present invention.

[0082] An embodiment of the present invention provides a vehicle based on the above embodiment, including a load and a power conversion circuit as in any embodiment of the present invention, the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0083] An embodiment of the present invention provides a method for preparing a semiconductor device based on the above embodiment. Figure 5 is a flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention, with reference to Figure 5 , the preparation method comprises:

[0084] S110, providing a semiconductor body 100, the semiconductor body 100 comprising a substrate 10, an epitaxial layer 20, a well region 30, a first region 40 and a second region 50, the epitaxial layer 20 is located on one side of the substrate 10, the well region 30 is arranged on a side of the epitaxial layer 20 away from the substrate 10, and the first region 40 is arranged on a side of the well region 30 away from the substrate 10; a surface of the first region 40 away from the substrate 10 is used as a first surface, and a gate trench 70 and a source trench 60 are respectively arranged on the first surface, and the gate trench 70 and the source trench 60 both extend from the first surface to the epitaxial layer 20; the second region 50 is arranged on a side of the source trench 60 away from or close to the gate trench 70; the first region 40 and the epitaxial layer 20 are of the first doping type, and the well region 30 and the second region 50 are of the second doping type;

[0085] The material of the substrate 10 and the material of the epitaxial layer 20 may be the same or different. For example, the materials of the substrate 10 and the epitaxial layer 20 may include silicon or silicon carbide. The semiconductor device in the embodiment of the present invention may be a silicon carbide trench metal oxide semiconductor field effect transistor (MOSFET). The first doping type in the embodiment of the present invention may be N-type doping, and the second doping type may be P-type doping, or the first doping type may be P-type doping, and the second doping type may be N-type doping. P+ and N+ shown in the accompanying drawings indicate that the ion doping concentration in the region is high, and P- and N- indicate that the ion doping concentration in the region is low. The N-type doping ions may be P (phosphorus) or N (nitrogen) ions, and the P-type doping ions may be Al (aluminum) ions or B (boron) ions. Exemplarily, the embodiment of the present invention takes the first doping type as N-type doping and the second doping type as P-type doping as an example. When the semiconductor device is an N-type device, the substrate 10 is N+ type doped, for example, it can be an N+ silicon carbide substrate 10; the epitaxial layer 20 is N- type doped, for example, it can be an N- silicon carbide epitaxial layer 20; when the semiconductor device is a P-type device, the substrate 10 is P+ type doped and the epitaxial layer 20 is P- type doped.

[0086] Specifically, an epitaxial layer 20 is formed on one side of the substrate 10, a well region 30 is arranged on the side of the epitaxial layer 20 away from the substrate 10, and a first region 40 is arranged on the side of the well region 30 away from the substrate 10. The well region 30 is of the second doping type, and the first region 40 is of the first doping type. The well region 30 and the first region 40 are used to form a conductive channel of a semiconductor device, and the well region 30 and the first region 40 can be formed by epitaxial growth, ion implantation, or vapor deposition. The surface of the first region 40 away from the substrate 10 is used as the first surface, and a gate trench 70 and a source trench 60 are formed on the first surface by an etching process, wherein the gate trench 70 and the source trench 60 can be formed by simultaneous etching in the same preparation process. Exemplarily, in some embodiments, the gate trench 70 and the source trench 60 have different depths, so the gate trench 70 and the source trench 60 are formed by etching in steps during different preparation processes. For example, the depth of the source trench 60 can be 1.2-2.5 μm, and the depth of the gate trench 70 can be 0.7-1.2 μm. By selecting the appropriate depth of the source trench 60 and the depth of the gate trench 70, the on-resistance is optimized while ensuring the performance of the device and the breakdown voltage of the semiconductor device is improved, so that the device can work stably at a higher voltage. The gate trench 70 and the source trench 60 pass through the first region 40 and the well region 30, and extend from the first surface to the epitaxial layer 20. The source trench 60 is located on one side of the gate trench 70, and the source trench 60 can be an annular trench, which is arranged to be a structure surrounding the gate trench 70. The source trench 60 may also be an independent trench, and a plurality of source trenches 60 are distributed on both sides of the gate trench 70. For example, in the figure, source trenches 60 are arranged on both sides of the gate trench 70, and the two source trenches 60 may be arranged symmetrically or asymmetrically. The second region 50 is formed on one side of the source trench 60 away from the gate trench 70 by ion implantation.

[0087] Optional, see Figure 1 In the case where the second region 50 is disposed on a side of the source trench 60 away from the gate trench 70, the second region 50 extends from the first surface to the epitaxial layer 20, and the orthographic projection of the second region 50 at the bottom of the source trench 60 at least covers a portion of the bottom of the source trench 60. In other words, the second region 50 may at least partially cover the bottom of the source trench 60, or may completely cover the bottom of the source trench 60, thereby increasing the contact area between the second region 50 and the epitaxial layer 20, thereby increasing the depletion region between the second region 50 and the epitaxial layer 20, and further improving the electric field to shield the gate structure.

[0088] See also Figure 2, the second region 50 can also be arranged on the side of the source trench 60 close to the gate trench 70. Optionally, in the case where the second region 50 is arranged on the side of the source trench 60 close to the gate trench 70, the second region 50 extends from the first surface to the epitaxial layer 20; the orthographic projection of the second region 50 at the bottom of the source trench 60 at least covers part of the bottom of the source trench 60. In other words, the second region 50 can at least partially cover the bottom of the source trench 60, or completely cover the bottom of the source trench 60, thereby increasing the contact area between the second region 50 and the epitaxial layer 20, thereby increasing the depletion region between the second region 50 and the epitaxial layer 20, and the second region 50 close to the side of the gate trench 70 can further improve the electric field to shield the gate structure.

[0089] S120, forming a gate structure in the gate trench;

[0090] Specifically, a gate structure is disposed in the gate trench 70, and a source structure is disposed in the source trench 60. Exemplarily, the gate structure may include a first insulating layer 71 and a trench gate 72, wherein the first insulating layer 71 is disposed on the inner wall and the bottom of the gate trench 70, the first insulating layer 71 may be a gate oxide layer, the gate oxide layer may be a high dielectric constant (K) material, the trench gate 72 may be a polysilicon layer, the gate structure is disposed in the gate trench 70, the well regions 30 on both sides of the gate structure may form a vertical conductive channel, the junction field-effect transistor (JFET) region may be eliminated, and the on-resistance of the semiconductor device may be lower.

[0091] S130, forming a source structure in the source trench;

[0092] Specifically, the source structure may include a first insulating layer 71 and a trench source 62, wherein the first insulating layer 71 is disposed on the inner wall and bottom of the source trench 60, the trench source 62 may be a polysilicon layer, the source structure is disposed in the source trench 60, and the second region 50 is disposed on the side of the source trench 60 away from the gate trench 70, that is, the second region 50 is disposed on the side of the source structure away from the gate structure, and the doping type of the second region 50 is the same as the doping type of the well region 30, therefore, a depletion region may be formed between the second region 50 and the epitaxial layer 20, which may play a role in shielding the electric field of the gate structure, thereby improving the problem of gate oxide layer breakdown and ensuring the reliability of the device operation. Furthermore, since the second region 50 and the epitaxial layer 20 have different doping types, a PN junction parasitic diode may be formed between the second region 50 and the epitaxial layer 20, which is used as a freewheeling diode 102. Furthermore, since the second region 50 is not provided on the side of the source trench 60 close to the gate trench 70, a PNP or NPN type transistor is formed between the epitaxial layer 20, the well region 30 and the first region 40 on the side of the source trench 60 close to the gate trench 70, which is used as a freewheeling transistor 101. Therefore, a freewheeling diode and a freewheeling transistor 101 are respectively integrated on both sides of the source trench, and the source metal layer 120 covers the first surface, wherein the source metal layer 120 is electrically connected to the source structure, and when the source is connected to a positive voltage, the freewheeling diode 102 can be turned on. When the source is connected to a positive voltage, the source structure serves as the control electrode of the freewheeling transistor 101, and the freewheeling transistor 101 can also be turned on. By integrating the freewheeling diode 102 and the freewheeling transistor 101, the freewheeling path of the semiconductor device is increased, the reverse conduction voltage drop of the semiconductor device is reduced, the leakage speed of the semiconductor device when reversely connected is increased, and the performance stability and safety of the semiconductor device are improved.

[0093] See also Figure 2 , the second region 50 can also be arranged on the side of the source trench 60 close to the gate trench 70, and the doping type of the second region 50 is the same as the doping type of the well region 30. Similarly, the second region 50 can also play a role in shielding the electric field of the gate structure. On the side of the source trench 60 close to the gate trench 70, a freewheeling diode 102 is formed between the second region 50 and the epitaxial layer 20. On the side of the source trench 60 away from the gate trench 70, a PNP or NPN type freewheeling triode 101 is formed between the epitaxial layer 20, the well region 30 and the first region 40. It can also play a role in increasing the reverse connection freewheeling path of the semiconductor device, reducing the reverse conduction voltage drop of the semiconductor device, and increasing the leakage speed of the semiconductor device when it is reversely connected.

[0094] S140, forming a drain on a side of the substrate away from the epitaxial layer.

[0095] Specifically, the drain electrode 110 may be formed on the side of the substrate 10 away from the epitaxial layer 20 by sputtering or the like, wherein the surface of the substrate 10 away from the epitaxial layer 20 is first thinned, and then the drain electrode 110 is formed by sputtering or the like. The drain electrode 110 is a metal conductive layer, and illustratively, the metal conductive layer may be titanium (Ti), nickel (Ni) or silver (Ag).

[0096] The method for preparing a semiconductor device provided by the technical solution provided in the embodiment of the present invention includes: providing a semiconductor body 100, the semiconductor body 100 includes a substrate 10, an epitaxial layer 20, a well region 30, a first region 40 and a second region 50, the epitaxial layer 20 is located on one side of the substrate 10, the well region 30 is arranged on the side of the epitaxial layer 20 away from the substrate 10, and the first region 40 is arranged on the side of the well region 30 away from the substrate 10; the surface of the first region 40 away from the substrate 10 is used as the first surface, and the first surface is respectively provided with a gate trench 70 and a source trench 60, and the gate trench 70 and the source trench 60 both extend from the first surface to the epitaxial layer 20; the second region 50 is arranged on the side of the source trench 60 away from or close to the gate trench 70; a gate structure is formed in the gate trench 70; a source structure is formed in the source trench 60; and a drain 110 is formed on the side of the substrate 10 away from the epitaxial layer 20. The first region 40 and the epitaxial layer 20 are of the first doping type, and the well region 30 and the second region 50 are of the second doping type; due to the different doping types of the second region 50 and the epitaxial layer 20, a PN junction parasitic diode can be formed between the second region 50 and the epitaxial layer 20, which is used as a freewheeling diode 102. Further, since the second region 50 is not provided on the side of the source trench 60 close to the gate trench 70, a PNP or NPN type transistor is formed between the epitaxial layer 20, the well region 30 and the first region 40, which is used as a freewheeling transistor 101. Therefore, when the source level is connected to a positive voltage, the freewheeling diode 102 can be turned on, and the source structure serves as the control electrode of the freewheeling transistor 101, and the freewheeling transistor 101 can also be turned on. By integrating the freewheeling diode 102 and the freewheeling transistor 101, the freewheeling path of the semiconductor device in reverse connection is increased, the reverse conduction voltage drop of the semiconductor device is reduced, the leakage speed of the semiconductor device when reversely connected is increased, and the performance stability and safety of the semiconductor device are improved.

[0097] Optionally, the semiconductor body 100 further includes a first buried layer 80;

[0098] The preparation method also includes:

[0099] A first buried layer 80 is formed in the epitaxial layer 20 on the side of the source trench 60 close to the gate trench 70 , wherein the orthographic projection of the first buried layer 80 on the side wall of the source trench 60 close to the gate trench 70 does not overlap with the orthographic projection of the well region 30 and the first region 40 on the side wall of the source trench 60 close to the gate trench 70 .

[0100] For details, see Figure 3 , the first buried layer 80 can be formed by ion implantation, and the first buried layer 80 has the same doping type as the second region 50. Exemplarily, when forming the epitaxial layer 20, the first buried layer 80 can be formed by ion implantation, and the source trench 60 is formed according to the position of the first buried layer 80, so that the first buried layer 80 is distributed on the side of the source trench 60 close to the gate trench 70. The first buried layer 80 can also be coated on the bottom of the source trench 60, so as to be arranged adjacent to the second region 50 at the bottom of the source trench 60, further improving the function of shielding the electric field of the gate structure. Among them, the first buried layer 80 can extend along the side wall of the source trench 60 in the direction pointing to the first region 40, but the first buried layer 80 does not contact the first region 40 and the well region 30, so as to avoid blocking the channel of the freewheeling transistor 101.

[0101] Optionally, the semiconductor body 100 further includes a second buried layer 90;

[0102] The preparation method also includes:

[0103] A second buried layer 90 is formed in the epitaxial layer 20 on the side of the source trench 60 away from the gate trench 70 , wherein the orthographic projection of the second buried layer 90 on the side wall of the source trench 60 away from the gate trench 70 does not overlap with the orthographic projection of the well region 30 and the first region 40 on the side wall of the source trench 60 away from the gate trench 70 .

[0104] For details, see Figure 4 , the second buried layer 90 can be formed by ion implantation, and the second buried layer 90 has the same doping type as the second region 50. Exemplarily, when forming the epitaxial layer 20, the second buried layer 90 can be formed by ion implantation, and the source trench 60 is formed according to the position of the second buried layer 90, so that the second buried layer 90 is distributed on the side of the source trench 60 close to the gate trench 70. The second buried layer 90 can also be coated on the bottom of the source trench 60, so as to be arranged adjacent to the second region 50 at the bottom of the source trench 60, further improving the function of shielding the electric field of the gate structure. Among them, the first buried layer 80 can extend along the side wall of the source trench 60 in the direction pointing to the first region 40, but the first buried layer 80 does not contact the first region 40 and the well region 30, so as to avoid blocking the channel of the freewheeling transistor 101.

[0105] Optionally, forming a source structure in the source trench 60 includes:

[0106] forming a first insulating layer 71 on the inner wall and bottom of the source trench 60;

[0107] A trench source 62 is formed in the source trench 60 on one side of the first insulating layer 71 , wherein the length of the trench source 62 in the extending direction of the source trench 60 is greater than the depth of the source trench 60 .

[0108] Specifically, the first insulating layer 71 is arranged on the inner wall and the bottom of the source trench 60, the trench source 62 may be a polysilicon layer, and the first insulating layer 71 in the source structure may be the same as the first insulating layer 71 in the gate structure. Therefore, during preparation, the first insulating layer 71 in the source structure and the first insulating layer 71 in the gate structure may be formed simultaneously, and then the polysilicon layer is deposited, and then the entire polysilicon layer is etched back so that 200-500nm of the polysilicon layer on the first surface remains, and then the polysilicon layer in the source trench 60 is protected by a photoresist, and then the etching is continued to fill the gate trench 70 with a polysilicon layer, and the deposition height of the polysilicon layer in the source trench 60 is greater than the depth of the source trench 60. That is to say, the polysilicon layer exceeds the plane where the first surface is located to form a protruding portion. Therefore, when the source metal layer 120 is formed on the first surface, the protruding portion will be inside the source metal layer 120, thereby increasing the contact area between the polysilicon layer and the source metal layer 120, which is beneficial to improving the voltage sensitivity of the control electrode of the freewheeling transistor 101 and controlling the conduction process of the freewheeling transistor 101. Exemplarily, the protruding portion can be cylindrical, trapezoidal pillar, conical or other regular or irregular shapes, as long as it can increase the contact area between the polysilicon layer and the source metal layer 120.

[0109] Optionally, the semiconductor device further includes: an ohmic contact metal layer 140 and a second insulating layer 130;

[0110] The preparation method also includes:

[0111] A second insulating layer 130 is formed on a side of the first surface away from the gate structure; an orthographic projection of the second insulating layer 130 on the first surface covers the gate structure;

[0112] An ohmic contact metal layer 140 is formed on a side of the second insulating layer 130 away from the gate structure. The ohmic contact metal layer 140 is electrically connected to the first region 40 . The metal material of the ohmic contact metal layer 140 includes titanium.

[0113] Specifically, a second insulating layer 130 is formed on the surface of the first region 40 away from the substrate 10. The second insulating layer 130 may be an interlayer dielectric layer (ILD). The second insulating layer 130 may cover the surface of the gate structure. An ohmic contact metal layer 140 is provided on the side of the second insulating layer 130 away from the gate structure. A source electrode is formed on the surface of the ohmic contact metal layer 140 away from the substrate 10. The second insulating layer 130 isolates the gate structure and the source electrode. The ohmic contact metal layer 140 is electrically connected to the trench source 62. When the ohmic contact metal layer 140 contacts the trench source 62, the resistance of the contact surface is very small, so that the current-voltage relationship is linear and no obvious additional impedance is generated. Good ohmic contact can significantly reduce the contact resistance between the source and the trench source 62, thereby improving the conductive efficiency of the device. The ohmic contact metal of the ohmic contact metal layer 140 can be nickel (Ni), but Ni easily reacts with the polysilicon layer, resulting in reduced reliability of the device. Therefore, the ohmic contact metal can be titanium (Ti). For example, when Ti is used as the ohmic contact metal, the ohmic contact metal layer 140 will not react with the polysilicon layer, and the ohmic contact metal layer 140 has a contact connection with the first region 40. When the first region 40 is of N+ doping type, the contact between titanium and the first region 40 can obtain a lower contact resistance, thereby reducing the reverse conduction voltage drop of the freewheeling transistor 101.

[0114] The embodiment of the present invention is Figure 3 Taking the semiconductor device structure in as an example, a method for preparing a semiconductor device is introduced. Figure 6 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention. Figures 7 to 13 is a schematic diagram of an intermediate structure of a preparation process provided by an embodiment of the present invention, and the preparation method comprises:

[0115] S210, forming a first portion of the epitaxial layer 20 on one side of the substrate 10, and forming a first buried layer 80 in the first portion of the epitaxial layer 20;

[0116] The substrate 10 may be an N+ doped silicon carbide substrate. A first portion of the epitaxial layer 20 is grown on the substrate 10, and then ion implantation is performed at a certain position to form a P+ doped first buried layer 80. The structure of the first buried layer 80 is as follows: Figure 7 shown.

[0117] S220, forming a second portion of the epitaxial layer 20 on a side of the first portion of the epitaxial layer 20 away from the substrate 10, the structure of which is as follows Figure 8 shown.

[0118] S230, forming a well region 30 on a side of the second portion of the epitaxial layer 20 away from the substrate 10; forming a first region 40 on a side of the well region 30 away from the substrate 10;

[0119] The well region 30 and the first region 40 are used to form a conductive channel of the semiconductor device. The well region 30 and the first region 40 can be formed by epitaxial growth, ion implantation or vapor deposition, and the structure thereof is as follows: Fig. 9 shown.

[0120] S240, the surface of the first region 40 away from the substrate 10 is used as the first surface, and a gate trench 70 and a source trench 60 are formed on the first surface, so that the first buried layer 80 is located on a side of the source trench 60 close to the gate trench 70; the gate trench 70 and the source trench 60 both extend from the first surface to the epitaxial layer 20;

[0121] Specifically, the gate trench 70 and the source trench 60 are set to different depths, so the gate trench 70 and the source trench 60 need to be etched step by step in different preparation processes. For example, the depth of the source trench 60 can be 1.2-2.5μm, and the depth of the gate trench 70 can be 0.7-1.2μm. By selecting the appropriate source trench 60 depth and gate trench 70 depth, the on-resistance is optimized and the breakdown voltage of the semiconductor device is improved while ensuring the device performance, so that the device can work stably at a higher voltage. The gate trench 70 and the source trench 60 pass through the first region 40 and the well region 30, and extend from the first surface to the epitaxial layer 20. Its structure is as follows Fig.10 shown.

[0122] S250, forming a second region 50 on a side of the source trench 60 away from the gate trench 70;

[0123] The second region 50 is formed on the side of the source trench 60 away from the gate trench 70 by ion implantation. The first region 40 is of the first doping type, and the well region 30 and the second region 50 are of the second doping type; the structure is as follows Fig.11 shown.

[0124] S260, forming a gate structure in the gate trench 70, and forming a source structure in the source trench 60;

[0125] Specifically, a gate structure is arranged in the gate trench 70, and a source structure is arranged in the source trench 60. The gate structure may include a first insulating layer 71 and a trench gate 72, wherein the first insulating layer 71 is arranged on the inner wall and the bottom of the gate trench 70, and the source structure may include a first insulating layer 71 and a trench source 62, wherein the first insulating layer 71 is arranged on the inner wall and the bottom of the source trench 60. During preparation, the first insulating layer 71 in the source structure and the first insulating layer 71 in the gate structure may be formed simultaneously by a thermal oxidation process, wherein the first insulating layer 71 at the bottom of the gate trench 70 is relatively thick, and the first insulating layer 71 on the sidewall of the gate trench 70 is relatively thin. Then, a polysilicon layer is deposited, and then the entire polysilicon layer is backetched to leave 200-500nm of the polysilicon layer on the first surface. Then, a photoresist is used to protect the polysilicon layer in the source groove 60, and then the backetching is continued to fill the gate groove 70 with the polysilicon layer to form a trench gate 72. The deposition height of the polysilicon layer in the source groove 60 is greater than the depth of the source groove 60. In other words, the polysilicon layer exceeds the plane where the first surface is located to form a protruding portion. Therefore, when the source metal layer 120 is subsequently formed on the first surface, the protruding portion will be inside the source metal layer 120, thereby increasing the contact area between the polysilicon layer and the source metal layer 120, which is beneficial to improving the voltage sensitivity of the control electrode of the freewheeling transistor 101, and controlling the conduction process of the freewheeling transistor 101. Exemplarily, the protruding portion can be cylindrical, trapezoidal, conical or other regular or irregular shapes, as long as it can increase the contact area between the polysilicon layer and the source metal layer 120. Its structure is as follows Fig.12 shown.

[0126] S270, forming a second insulating layer 130 on a side of the first surface away from the gate structure; the orthographic projection of the second insulating layer 130 on the first surface covers the gate structure; and forming an ohmic contact metal layer 140 on a side of the second insulating layer 130 away from the gate structure;

[0127] Specifically, a second insulating layer 130 is prepared, and the second insulating layer 130 covers the surface of the gate structure, exposing the ohmic contact region, and the ohmic contact region includes a portion of the first region, and an ohmic contact metal layer 140 is prepared. The ohmic contact metal layer 140 is electrically connected to the first region 40; the metal material of the ohmic contact metal layer 140 includes titanium. Its structure is as follows Fig.13 shown.

[0128] S280, forming a source metal layer 120, a passivation layer 150, and a drain 110 on the other side of the substrate 10. The structure is as follows Figure 3 shown.

[0129] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor body, comprising a substrate, an epitaxial layer, a well region, a first region, a second region and a buried layer, wherein the epitaxial layer is located on one side of the substrate, the well region is located on a side of the epitaxial layer away from the substrate, and the first region is located on a side of the well region away from the substrate; a surface of the first region on a side away from the substrate is used as a first surface, and a gate trench and a source trench are respectively provided on the first surface, and the gate trench and the source trench both extend from the first surface into the epitaxial layer; The second region is arranged on one side of the source trench away from or close to the gate trench, and the buried layer is arranged on the other side of the source trench; the second region extends from the first surface into the epitaxial layer; The orthographic projection of the buried layer on the sidewall of the source trench does not overlap with the orthographic projection of the well region and the first region on the sidewall of the source trench; the first region and the epitaxial layer are of the first doping type, and the well region and the second region are of the second doping type; A gate structure, located in the gate trench; A source structure, located in the source trench; A source metal layer, located on the first surface and in contact with the source structure; The drain is located on a side of the substrate away from the epitaxial layer.

2. The semiconductor device according to claim 1, wherein: The second region is arranged on a side of the source trench away from the gate trench, and an orthographic projection of the second region on the bottom of the source trench at least covers a portion of the bottom of the source trench.

3. The semiconductor device according to claim 2, characterized in that The buried layer comprises: A first buried layer is arranged in the epitaxial layer on a side of the source trench close to the gate trench, wherein an orthographic projection of the first buried layer on a side wall of the source trench close to the gate trench does not overlap with an orthographic projection of the well region and the first region on a side wall of the source trench close to the gate trench.

4. The semiconductor device according to claim 1, wherein: The second region is arranged on a side of the source trench close to the gate trench; an orthographic projection of the second region at the bottom of the source trench at least covers a portion of the bottom of the source trench.

5. The semiconductor device according to claim 4, characterized in that The buried layer comprises: A second buried layer is arranged in the epitaxial layer on the side of the source trench away from the gate trench, wherein the orthographic projection of the second buried layer on the side wall of the source trench away from the gate trench does not overlap with the orthographic projection of the well region and the first region on the side wall of the source trench away from the gate trench.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that: The source structure includes a first insulating layer and a trench source; The first insulating layer is arranged on the inner wall and the bottom of the source trench; The trench source is disposed in the source trench on one side of the first insulating layer; wherein the length of the trench source in the extension direction of the source trench is greater than the depth of the source trench.

7. The semiconductor device according to claim 6, characterized in that The semiconductor device further comprises: A second insulating layer is disposed on a side of the first surface away from the gate structure; an orthographic projection of the second insulating layer on the first surface covers the gate structure; The ohmic contact metal layer is located on a side of the second insulating layer away from the gate structure, and the ohmic contact metal layer is electrically connected to the first region; the metal material of the ohmic contact metal layer includes titanium.

8. A power module, characterized in that: It comprises a substrate and at least one semiconductor device according to any one of claims 1 to 7, wherein the substrate is used for carrying the semiconductor device.

9. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit comprises a circuit board and at least one semiconductor device according to any one of claims 1 to 7, wherein the semiconductor device is electrically connected to the circuit board.

10. A vehicle, characterized in that: It includes a load and a power conversion circuit as described in claim 9, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

11. A method for preparing a semiconductor device, characterized in that: include: A semiconductor body is provided, the semiconductor body comprising a substrate, an epitaxial layer, a well region, a first region, a second region and a buried layer, the epitaxial layer is located on one side of the substrate, the well region is arranged on a side of the epitaxial layer away from the substrate, and the first region is arranged on a side of the well region away from the substrate; a surface of the first region away from the substrate is used as a first surface, a gate trench and a source trench are respectively arranged on the first surface, and the gate trench and the source trench both extend from the first surface into the epitaxial layer; The second region is arranged on one side of the source trench away from or close to the gate trench, and the buried layer is arranged on the other side of the source trench; the second region extends from the first surface into the epitaxial layer; The orthographic projection of the buried layer on the sidewall of the source trench does not overlap with the orthographic projection of the well region and the first region on the sidewall of the source trench; the first region and the epitaxial layer are of the first doping type, and the well region and the second region are of the second doping type; forming a gate structure in the gate trench; forming a source structure in the source trench; A source metal layer, located on the first surface and in contact with the source structure; A drain is formed on a side of the substrate away from the epitaxial layer.

12. The method for preparing a semiconductor device according to claim 11, characterized in that: In a case where the second region is disposed on a side of the source trench away from the gate trench, an orthographic projection of the second region on the bottom of the source trench at least covers a portion of the bottom of the source trench.

13. The method for preparing a semiconductor device according to claim 12, characterized in that: The buried layer includes a first buried layer; The preparation method further comprises: The first buried layer is formed in the epitaxial layer on a side of the source trench close to the gate trench, wherein an orthographic projection of the first buried layer on a side wall of the source trench close to the gate trench does not overlap with an orthographic projection of the well region and the first region on a side wall of the source trench close to the gate trench.

14. The method for preparing a semiconductor device according to claim 11, characterized in that: In a case where the second region is disposed on a side of the source trench close to the gate trench, an orthographic projection of the second region on the bottom of the source trench at least covers a portion of the bottom of the source trench.

15. The method for preparing a semiconductor device according to claim 14, characterized in that: The buried layer includes a second buried layer; The preparation method further comprises: The second buried layer is formed in the epitaxial layer on the side of the source trench away from the gate trench, wherein the orthographic projection of the second buried layer on the side wall of the source trench away from the gate trench does not overlap with the orthographic projection of the well region and the first region on the side wall of the source trench away from the gate trench.

16. The method for preparing a semiconductor device according to any one of claims 11 to 15, characterized in that: Forming a source structure in the source trench includes: forming a first insulating layer on the inner wall and bottom of the source trench; A trench source is formed in the source trench on one side of the first insulating layer, wherein a length of the trench source in an extending direction of the source trench is greater than a depth of the source trench.

17. The method for preparing a semiconductor device according to claim 16, characterized in that: The semiconductor device further comprises: an ohmic contact metal layer and a second insulating layer; The preparation method further comprises: forming a second insulating layer on a side of the first surface away from the gate structure; an orthographic projection of the second insulating layer on the first surface covers the gate structure; The ohmic contact metal layer is formed on a side of the second insulating layer away from the gate structure, and the ohmic contact metal layer is electrically connected to the first region; the metal material of the ohmic contact metal layer includes titanium.

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