Method for constructing low-energy-consumption memristor

Abstract

The invention discloses a method for constructing a low-energy-consumption memristor, relates to the technical field of memristor construction, and aims to solve the problem of how to reduce the energy consumption of a two-dimensional material memristor. The method comprises the following steps: depositing a single layer of MoS2 on a silicon wafer with a 300nm SiO2 layer by adopting a chemical vapor deposition method; putting the silicon wafer deposited with the single layer of MoS2 into a vacuum annealing furnace for annealing treatment to obtain a two-dimensional MoS2 material; patterning on the new silicon wafer by utilizing a photoetching process, prefabricating a position of a bottom electrode, evaporating an Au bottom electrode at the position of the prefabricating bottom electrode through a high-vacuum thermal evaporation method, and evaporating Cr at the same time; evaporating a Sb2O3 film on the electrode; transferring the prepared two-dimensional MoS2 material to the prepared Sb2O3 thin film through a wet method, and etching by using an electron beam exposure method and an etching machine to etch triangular MoS2 into strips; au is evaporated through a thermal evaporation method to serve as a top electrode, the device is put into a vacuum annealing furnace to be annealed, and finally the memristor is manufactured.

Description

Technical Field

[0001] The present invention relates to the technical field of memristor construction, and in particular to a method for constructing a low-energy memristor. Background Art

[0002] Memristor is a resistor device with memory function. It is considered as a key member of the "fourth" basic electronic component together with resistors, capacitors and inductors. It has the characteristics of simulation and hysteresis. This characteristic enables it to simulate synapses and neurons by imitating the working mechanism of organisms, realize the function of storage and computing, rather than a single imitation of surface features, which helps to achieve brain-like intelligence beyond limited artificial intelligence. The emergence of memristors marks a revolutionary change in data storage and processing technology, and has an impact on advanced computing architectures such as neuromorphic computing and basic scientific research. The variable resistance of memristors is similar to the synaptic plasticity of neural networks, realizing the adaptive regulation function of the connection strength between neurons. Therefore, memristors can be applied to neuromorphic computing systems. As a key component for simulating biological neurons and synapses, their low energy consumption, high density and non-volatility make them the best choice for brain-like computing. Their application in neuromorphic computing can promote the development of brain-like computer systems, thus hopefully overcoming the limitations of the von Neumann architecture.

[0003] Two-dimensional material memristors have been widely studied due to their compatibility with CMOS processes and high stability, but how to reduce the energy consumption of two-dimensional material memristors remains a key challenge. Summary of the invention

[0004] The present invention proposes a method for constructing a low-energy memristor, which comprises the following steps: S1: Depositing a single layer of MoS2 on a silicon wafer with a 300nm SiO2 layer by chemical vapor deposition (CVD); placing the silicon wafer with the deposited single layer of MoS2 in a vacuum annealing furnace for annealing to obtain a two-dimensional MoS2 material; S2: Patterning is performed on the new silicon wafer using a photolithography process to pre-fabricate the position of the bottom electrode, and 30-80 nm Au is evaporated as the bottom electrode at the position of the pre-fabricated bottom electrode by a high vacuum thermal evaporation method, and 5-15 nm Cr is evaporated at the same time to make the bottom electrode more stable; S3: Using high vacuum thermal evaporation method, Sb2O3 is evaporated on the electrode in step S2, and an excess of Sb2O3 is placed in the tungsten boat. 3， The evaporation current is 25-35A, ensuring the evaporation rate is The evaporation thickness is 3nm-7nm to obtain Sb2O3 thin film; S4: transferring the two-dimensional MoS2 material obtained in step S1 to the Sb2O3 film obtained in step S3 by wet method, transferring 1-5 layers, and then etching by electron beam exposure method and etcher to carve the triangular MoS2 into strips; S5: Use thermal evaporation to evaporate 30-90nm Au as the top electrode, put the device into a vacuum annealing furnace at a temperature of 120-200℃ for 1-3h to improve the interface contact and finally make a memristor.

[0005] The present invention is further configured as follows: wherein in step S1, an excess amount of sulfur powder is placed in advance in the tubular furnace used for the chemical vapor deposition method, the temperature of the sulfur powder temperature zone is 150-170°C, and in an atmosphere with an Ar flow rate of 140-180sccm, the tubular furnace is heated from room temperature to 500°C in 1h, and then a 2×2cm silicon wafer is placed, and the temperature is raised to 780-860°C after 35-45min, and O2 is introduced into the tubular furnace, the temperature is kept constant for 30-55min, and then the tubular furnace is cooled to 500°C and then taken out.

[0006] The present invention is further configured as follows: wherein the wet transfer method in step S4 is to first use a coating machine to coat the two-dimensional MoS2 material, spin coat two layers of polymethyl methacrylate (PMMA), heat on a hot plate at 120°C for 1 min, and then cut into a size of 2×2 mm; place the cut two-dimensional MoS2 material into an etching solution for etching, separate the spin-coated PMMA film from the two-dimensional MoS2 material, and use a coverslip to scoop out the PMMA film and repeatedly wash it in deionized water.

[0007] A further configuration of the present invention is that the etching solution is prepared by mixing HF and deionized water in a ratio of 1:3.

[0008] The present invention is further configured as follows: the film is cleaned 4-6 times.

[0009] The present invention is further configured as follows: wherein the etcher in step S4 uses SF6 gas during the etching process, the gas flow rate is 5-15 sccm, the power is 60-80 W, and the etching time is 8-12 s.

[0010] The beneficial effects of the present invention are:

[0011] 1. The present invention realizes the design and construction of MoS2 low-energy memristor by combining Sb2O3 through interface engineering. Controlling the evaporation rate can make the MoS2 / Sb2O3 interface have good contact. The introduction of the high dielectric constant Sb2O3 layer increases the equivalent resistance between electrodes, effectively reducing the working current of the memristor. At the same time, the high dielectric constant material can better optimize the electric field distribution, promote the effective injection and migration of carriers, reduce the energy consumption of MoS2 memristor, and improve energy efficiency. The energy consumption of the MoS2 / Sb2O3 memristor prepared by the present invention is reduced by one order of magnitude compared to when the Sb2O3 layer is not added, reaching the pJ level.

[0012] 2. The introduction of the high dielectric constant layer effectively expands the operating voltage range of the MoS2 memristor. The situation where the device may fail due to breakdown when exceeding 1V has now been extended to 7V, enhancing the stability and applicability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 A schematic diagram of the structure of the prepared memristor is shown.

[0014] Figure 2 A light microscope image of a memristor is shown.

[0015] Figure 3 The IV characteristic curve of 0.5-2V is shown.

[0016] Figure 4 A graph showing the 100 IV cycle characteristics is shown.

[0017] Figure 5 A pulse voltage-current graph of a memristor is shown.

[0018] Figure 6 A pulsed positive voltage-current graph of a memristor is shown.

[0019] Figure 7 A pulsed negative voltage-current graph of a memristor is shown.

[0020] Figure 8 A graph showing the synaptic performance of a memristor at pulse frequencies.

[0021] Fig. 9 A graph showing the synaptic performance of a memristor at pulse frequencies.

[0022] Fig.10 Defect map showing the synaptic performance of the memristor at pulse frequencies.

[0023] Fig.11 The energy consumption curve of the memristor under the conditions of Example 1 is shown.

[0024] Fig.12The IV characteristic curve of 0.5-2.5V is shown.

[0025] Fig.13 The energy consumption curve of the memristor under the conditions of Example 2 is shown.

[0026] Fig.14 The energy consumption curve of the memristor under the conditions of Example 3 is shown.

[0027] Fig.15 The energy consumption curve of the memristor under the conditions of Example 4 is shown.

[0028] Fig.16 The energy consumption curve of the memristor under the conditions of Example 5 is shown.

[0029] Fig.17 The energy consumption curve of the memristor under the conditions of Example 6 is shown. DETAILED DESCRIPTION

[0030] Those skilled in the art can refer to the content of this article and appropriately improve the process parameters. It is particularly important to point out that all similar replacements and modifications are obvious to those skilled in the art, and they are all considered to be included in the present invention. The methods and applications of the present invention have been described through preferred embodiments, and relevant personnel can modify or appropriately change and combine the methods and applications described herein without departing from the content, spirit and scope of the present invention to implement and apply the technology of the present invention.

[0031] The present invention proposes a method for constructing a low-energy memristor, comprising the following steps: S1: Depositing a single layer of MoS2 on a silicon wafer with a 300 nm SiO2 layer by chemical vapor deposition (CVD); placing the silicon wafer with the deposited single layer of MoS2 in a vacuum annealing furnace for annealing to obtain a two-dimensional MoS2 material; S2: Patterning is performed on the new silicon wafer using a photolithography process to pre-fabricate the position of the bottom electrode, and 30-80 nm Au is evaporated as the bottom electrode at the position of the pre-fabricated bottom electrode by a high vacuum thermal evaporation method, and 5-15 nm Cr is evaporated at the same time to make the bottom electrode more stable; S3: Using high vacuum thermal evaporation method, Sb2O3 is evaporated on the electrode in step S2. Excess Sb2O3 is placed in the tungsten boat. The evaporation current is 25-35A, and the evaporation rate is guaranteed to be The evaporation thickness is 3nm-7nm to obtain Sb2O3 thin film; S4: transferring the two-dimensional MoS2 material obtained in step S1 to the Sb2O3 thin film layer obtained in step S3 by wet method, transferring 1-5 layers, and then etching by electron beam exposure method and etcher to carve the triangular MoS2 into strips; S5: Use thermal evaporation to evaporate 30-90nm Au as the top electrode, put the device into a vacuum annealing furnace at a temperature of 120-200℃ for 1-3h to improve the interface contact and finally make a memristor.

[0032] In the step S1, an excess amount of sulfur powder needs to be placed in the tubular furnace used for the chemical vapor deposition method in advance, and the temperature of the sulfur powder is in the temperature zone of 150-170°C. In an atmosphere with an Ar flow rate of 140-180sccm, the tubular furnace is heated from room temperature to 500°C in 1 hour. At this time, a silicon wafer of a size of 2×2cm is placed in the tubular furnace, and the temperature is raised to 780-860°C after 35-45 minutes. O2 is introduced into the tubular furnace and the temperature is kept constant for 30-55 minutes. Then, the silicon wafer is taken out while the tubular furnace is cooled to 500°C.

[0033] The wet transfer method in step S4 is to first use a coating machine to coat the two-dimensional MoS2 material generated in step 1, spin-coat two layers of polymethyl methacrylate (PMMA), heat on a hot plate at 120°C for 1 min, and then cut into 2×2 mm size; place the cut two-dimensional MoS2 into an etching solution for etching, and separate the spin-coated PMMA film from the two-dimensional MoS2 material, use a coverslip to scoop up the film and repeatedly wash it in deionized water for 4-6 times.

[0034] The etching solution is prepared by mixing HF and deionized water in a ratio of 1:3.

[0035] In step S4, the etcher uses SF6 gas during the etching process, with a gas flow rate of 5-15 sccm, a power of 60-80 W, and an etching time of 8-12 s.

[0036] Example 1

[0037] This embodiment uses the above method to construct a low-energy memristor, and the specific steps are as follows: S1: Depositing a single layer of MoS2 on a silicon wafer with a 300 nm SiO2 layer by chemical vapor deposition (CVD); placing the silicon wafer with the deposited single layer of MoS2 in a vacuum annealing furnace for annealing to obtain a two-dimensional MoS2 material; S2: patterning the new silicon wafer by using a photolithography process to pre-fabricate the position of the bottom electrode, and evaporating 10nmCr+60nmAu as the bottom electrode at the position of the pre-fabricated bottom electrode by a high vacuum thermal evaporation method; S3: Using high vacuum thermal evaporation method, Sb2O3 powder is evaporated on the electrode in step S2. Excess Sb2O3 powder is placed in the tungsten boat. The evaporation current is 30A, and the evaporation rate is ensured to be The evaporation thickness is 4 nm; S4: The two-dimensional MoS2 material prepared in step S1 is transferred to the Sb2O3 layer prepared in step S3 by a wet method, and three layers are transferred. Then, the triangular MoS2 is etched into strips by an electron beam exposure method and an etcher; S5: Use thermal evaporation to evaporate 60nm Au as the top electrode, and put the device into a vacuum annealing furnace at a temperature of 150℃ for 2h to improve the interface contact and finally make a memristor.

[0038] The 4200-SCS parameter analysis memristor was used to obtain IV cycle and synaptic performance for testing, refer to Figure 1 This is a schematic diagram of the final memristor structure. Figure 2 This is a light microscope image of a memristor. Figure 3 The IV characteristic curve of 0.5V-2V is shown. Figure 4 Demonstrated high stability over 100 IV cycles. Figure 5 , 6 7 demonstrates the device's pulsed electrical plasticity-dependent synaptic performance. The device remains intact when operating at a voltage higher than 7V, which greatly expands the safe operating voltage compared to the existing 1V device breakdown. Figure 8 , 9 , 10 respectively demonstrate the synaptic performance of the device in pulse frequency-dependent plasticity and pulse number-dependent plasticity. Figure 5 , 6 , 7, 8, 9, and 10 prove that the memristor prepared by the present application has synaptic plasticity, demonstrating its application potential in the synaptic field. Fig.11 The energy consumption of a single pulse with a duration of 50 μs can be calculated to be 5.36×10 -10 J / spike, which is an order of magnitude lower than the nJ level energy consumption when no Sb2O3 dielectric layer is added.

[0039] Example 2

[0040] The only difference between this embodiment and embodiment 1 is that the number of two-dimensional MoS2 layers transferred by the wet method is 2.

[0041] refer to Fig.12 The IV characteristic curve under 0.5-2.5V voltage, Fig.13 This is a single pulse diagram with a pulse duration of 50 μs. Based on this calculation, the energy consumption at this time is 7.8×10 -10 J / spike.

[0042] Example 3

[0043] The only difference between this embodiment and embodiment 1 is that the number of two-dimensional MoS2 layers transferred by the wet method is 1.

[0044] Fig.14 This is a single pulse diagram with a pulse duration of 50 μs. Based on this calculation, the energy consumption at this time is 8.11×10 - 10 J / spike.

[0045] Example 4

[0046] The only difference between this embodiment and embodiment 1 is that the number of two-dimensional MoS2 layers transferred by the wet method is 4.

[0047] Fig.15 This is a single pulse diagram with a pulse duration of 50 μs. Based on this calculation, the energy consumption at this time is 8.46×10 - 10 J / spike.

[0048] Example 5

[0049] The only difference between this embodiment and Embodiment 1 is that the thickness of the evaporated dielectric layer Sb2O3 is 3 nm.

[0050] Fig.16 This is a single pulse diagram with a pulse duration of 50 μs. Based on this calculation, the energy consumption at this time is 8.67×10 - 10 J / spike.

[0051] Example 6

[0052] The only difference between this embodiment and Embodiment 1 is that the thickness of the evaporated dielectric layer Sb2O3 is 5 nm.

[0053] Fig.17 This is a single pulse diagram with a pulse duration of 50 μs. Based on this calculation, the energy consumption at this time is 6.54×10 - 10 J / spike.

[0054] In summary, the present invention realizes the design and construction of MoS2 low-energy memristor by combining Sb2O3 through interface engineering, and controlling the evaporation rate can make the MoS2 / Sb2O3 interface have good contact. The introduction of the high dielectric constant Sb2O3 layer increases the equivalent resistance between the electrodes, effectively reducing the working current of the memristor. At the same time, the high dielectric constant material can better optimize the electric field distribution, promote the effective injection and migration of carriers, reduce the energy consumption of the MoS2 memristor, and improve the energy efficiency. The energy consumption of the MoS2 / Sb2O3 memristor prepared by the present invention is reduced by one order of magnitude compared to when the Sb2O3 layer is not added, reaching the pJ level. The introduction of the high dielectric constant layer effectively expands the operating voltage range of the MoS2 memristor. The situation that may cause device breakdown failure when exceeding 1V is now extended to 7V, enhancing the stability and applicability of the equipment.

[0055] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be within the scope of protection of the present invention.

Claims

1. A method for constructing a low-energy memristor, characterized in that: The following steps are included: S1: Depositing a single layer of MoS2 on a silicon wafer with a 300nm SiO2 layer by chemical vapor deposition (CVD); placing the silicon wafer with the deposited single layer of MoS2 in a vacuum annealing furnace for annealing to obtain a two-dimensional MoS2 material; S2: Patterning is performed on the new silicon wafer using a photolithography process to pre-fabricate the position of the bottom electrode, and 30-80 nm Au is evaporated as the bottom electrode at the position of the pre-fabricated bottom electrode by a high vacuum thermal evaporation method, and 5-15 nm Cr is evaporated at the same time to make the bottom electrode more stable; S3: Using high vacuum thermal evaporation method, Sb2O3 is evaporated on the electrode in step S2, and an excess of Sb2O3 is placed in the tungsten boat. 3， The evaporation current is 25-35A, ensuring the evaporation rate is The evaporation thickness is 3nm-7nm to obtain Sb2O3 thin film; S4: transferring the two-dimensional MoS2 material obtained in step S1 to the Sb2O3 film obtained in step S3 by wet method, transferring 1-5 layers, and then etching by electron beam exposure method and etcher to carve the triangular MoS2 into strips; S5: Use thermal evaporation to evaporate 30-90nm Au as the top electrode, put the device into a vacuum annealing furnace at a temperature of 120-200℃ for 1-3h to improve the interface contact and finally make a memristor.

2. The method for constructing a low-energy memristor according to claim 1, characterized in that: In the step S1, an excess amount of sulfur powder is placed in advance in the tubular furnace used for the chemical vapor deposition method, and the temperature of the sulfur powder temperature zone is 150-170°C. In an atmosphere with an Ar flow rate of 140-180sccm, the tubular furnace is heated from room temperature to 500°C in 1 hour, and then a 2×2cm silicon wafer is placed in it. After 35-45 minutes, the temperature is raised to 780-860°C, and O2 is introduced into the tubular furnace, and the temperature is kept constant for 30-55 minutes. Then, the tubular furnace is cooled to 500°C and then taken out.

3. The method for constructing a low-energy memristor according to claim 1, characterized in that: The wet transfer method in step S4 is to first use a coating machine to coat the two-dimensional MoS2 material, spin-coat two layers of polymethyl methacrylate (PMMA), heat on a hot plate at 120°C for 1 min, and then cut into 2×2 mm size; place the cut two-dimensional MoS2 material into an etching solution for etching, separate the spin-coated PMMA film from the two-dimensional MoS2 material, use a coverslip to scoop out the PMMA film and repeatedly wash it in deionized water.

4. The method for constructing a low-energy memristor according to claim 3, characterized in that: The etching solution is prepared by mixing HF and deionized water in a ratio of 1:

3.

5. The method for constructing a low-energy memristor according to claim 3, characterized in that: The film was washed 4-6 times.

6. The method for constructing a low-energy memristor according to claim 1, characterized in that: The etcher in step S4 uses SF6 gas during the etching process, with a gas flow rate of 5-15 sccm, a power of 60-80 W, and an etching time of 8-12 s.

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