Method for detecting mismatch between parallel power electronic components, power electronic module, computer software, and computer-readable non-transitory recording medium

Abstract

A method for detecting a mismatch between parallel power electronic components (11.1, 11.2) in a power electronic module (1), the method comprising: a. Triggering a measurement period in response to a detection of a common turn-off of the components; b. During said measurement period, measuring a series of emitter voltages VeE of at least one of said elements; c. Extracting data from the measurement, said data comprising a sign and / or magnitude of a local extremum of said emitter voltage VeE during said measurement period; d. At least deducing the presence or absence of a mismatch between the elements from the extracted data.

Description

Technical Field

[0001] The present disclosure relates to the field of power electronic modules. More specifically, the present invention relates to monitoring of assemblies comprising multiple devices / elements connected in parallel. Background Art

[0002] Such power devices are subject to high thermal variations and high thermo-mechanical stresses. Due to the wide diversity of composition and architecture of the different parts / devices constituting the assembly, effects such as crack propagation, wire bond detachment, delamination, metallization reconstruction, etc. can lead to interconnect failures. The failure mechanisms are coupled, with the most common outcome being the detachment of wire bonds. Such failures are difficult to predict and detect before the total failure of the assembly. Furthermore, due to manufacturing or installation mismatches, paralleled devices may age unevenly, resulting in mismatched electro-thermal lifetimes. During the operation and maintenance phases, it is very important to know the health status of each power device in the assembly to perform life extension and selective maintenance / replacement, respectively.

[0003] In-line monitoring of wire bonds can be accomplished by passing a steady-state voltage (denoted V ce ) and compares it to the limit. ce Specific to a single power unit, other parallel units can be shut down. Operating these units one by one allows for evaluation of individual degradation. However, this method requires individual drivers. Steady-state V ce Dependency on temperature and current (including ripple), calibration / correction must be performed. In addition, clamping circuits must be implemented to protect the measurement, imposing a time response that is incompatible with fast switching frequencies and / or extreme duty cycles. Finally, the connection to high voltage imposes high design and safety constraints, making this solution difficult to adopt. Summary of the invention

[0004] The present disclosure improves this situation.

[0005] A method for detecting mismatch between parallel power electronic components in a power electronic module is proposed, the method comprising:

[0006] a. in response to detection of a common shutdown of the elements, triggering a measurement period;

[0007] b. During the measurement period, measuring a series of emitter voltages V of at least one of the elements eE ;

[0008] c. Extracting data from the measurement, the data including the emitter voltage V during the measurement period eE the sign and / or magnitude of the local extrema of ;

[0009] d. Inferring at least the presence or absence of a mismatch between the elements from the extracted data.

[0010] On the other hand, a power electronic module is proposed, which comprises at least two power electronic components connected in parallel and is arranged to implement the method.

[0011] In another aspect, a computer software is provided, the computer software comprising instructions for implementing at least a part of the method defined herein when the software is executed by a processor. In another aspect, a computer-readable non-transitory recording medium is provided, on which software is registered, which, when executed by a processor, implements the method defined herein.

[0012] The following features can be optionally implemented alone or in combination with other features:

[0013] The extracted data includes at least:

[0014] - The two emitter voltages V of the two components eE1 and V eE2 The sign of the local extremum of the sequence of , or

[0015] - The emitter voltage V of a component eE The sign and magnitude of the local extrema of the sequence;

[0016] And, if a mismatch between the elements has been inferred, the method further comprises:

[0017] e. Infer the emitter voltage V from the extracted data eE , or V eE1 and V eE2 , whether the measured component is the most degraded.

[0018] The extraction step from the measured data is performed by analog and logic circuits, making the use of analog-to-digital converters redundant.

[0019] The extracted data also includes the emitter voltage V during the measurement period. eE The magnitude of the local extremum

[0020] And, if a mismatch between the elements has been inferred, the method further comprises:

[0021] f. Inferring a quantification of the mismatch from the extracted data.

[0022] The differential emitter voltage V of a pair of components is measured ee .

[0023] Implemented on a module comprising at least three parallel-connected power electronic components, the measurements are performed in a sequential manner on each pair of components having a common monitoring circuit, a multiplexer being operatively interfaced between said monitoring circuit and said components.

[0024] The method further comprises:

[0025] - An additional external gate resistor is applied during the measurement operation.

[0026] The inference operation also includes identifying the most degraded component of the at least two components and then

[0027] A sequence of operations is repeated at least once, the at least one repetition comprising inferring a turn-off delay d of at least one of the components relative to another component before triggering the measurement period.

[0028] This series of operations is repeated at least once to achieve detection of mismatches throughout the operational life of the module.

[0029] The method further comprises:

[0030] -Generate an alarm signal based on the inferred information. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Other features, details and advantages will be seen in the following detailed description and in the accompanying drawings, in which:

[0032] [ Figure 1 ]

[0033] Figure 1 is a cross-sectional side view of an assembly or module including two parallel-connected semiconductor devices / elements.

[0034] [ Figure 2 ]

[0035] Figure 2 is based on Figure 1 A top view of a component, where "Y" is Figure 1 cutting plane.

[0036] [ Figure 3 ]

[0037] Figure 3 is a graph showing a turn-off delay according to a current flowing through a power element according to an embodiment.

[0038] [ Figure 4 ]

[0039] Figure 4 is a graph showing a turn-off delay according to a threshold voltage of a power element according to an embodiment.

[0040] [ Figure 5]

[0041] Figure 5 is a graph showing current flowing through two parallel power elements during an off period according to an embodiment.

[0042] [ Figure 6 ]

[0043] Figure 6 The architecture of a power module according to an embodiment is shown.

[0044] [ Figure 7 ]

[0045] Figure 7 The architecture of a power module according to an embodiment is shown.

[0046] [ Figure 8 ]

[0047] Figure 8 is a graph showing a waveform of an emitter voltage of two parallel-connected power elements of a module during a turn-off period according to an embodiment.

[0048] [ Fig. 9 ]

[0049] Fig. 9 is a graph showing a superposition of waveforms of emitter voltages of power elements during a turn-off period according to an embodiment.

[0050] [ Fig.10 ]

[0051] Fig.10 is a diagram showing that during the same off period, Fig. 9 A graph showing superimposed waveforms of emitter voltages of power elements connected in parallel.

[0052] [ Fig.11 ]

[0053] Fig.11 Schematically illustrates how a degraded power component may be identified using a circuit according to one embodiment.

[0054] [ Fig.12 ]

[0055] Fig.12 : is a graph showing the maximum value (“peak value”) of the emitter voltage of the degraded power element according to the number n of lead-offs which are counted.

[0056] [ Fig.13 ]

[0057] Fig.13 It shows that according to Figure 6A graph showing the superposition of voltage waveforms between the emitters of two parallel-connected power elements of a module of the architecture.

[0058] [ Fig.14 ]

[0059] Fig.14 It shows that according to Figure 7 A graph showing the superposition of voltage waveforms between the emitters of two parallel-connected power elements of a module of the architecture.

[0060] [ Fig.15 ]

[0061] Fig.15 is a diagram showing a method according to one embodiment Figure 6 A graph showing the minimum value of the voltage between the emitters of two parallel-connected power elements of a module of the architecture.

[0062] [ Fig.16 ]

[0063] Fig.16 is a diagram showing a method according to one embodiment Figure 8 A graph showing the minimum value of the voltage between the emitters of two parallel-connected power elements of a module of the architecture.

[0064] [ Fig.17 ]

[0065] Fig.17 is a diagram showing a method according to one embodiment Figure 6 A graph showing the maximum value of the voltage between the emitters of two parallel-connected power elements of a module of the architecture.

[0066] [ Fig.18 ]

[0067] Fig.18 is a diagram showing a method according to one embodiment Figure 7 A graph showing the maximum value of the voltage between the emitters of two parallel-connected power elements of a module of the architecture.

[0068] [ Fig.19 ]

[0069] Fig.19 is a circuit that applies additional external resistance during off switching according to one embodiment.

[0070] [ Fig. 20 ]

[0071] Fig. 20 is a logic diagram showing how to convert a voltage offset into a delay offset according to one embodiment.

[0072] [ Fig.21 ]

[0073] Fig.21 is a graph showing how an index of degradation of two parallel elements in a module is constructed as a function of time according to one embodiment. DETAILED DESCRIPTION

[0074] See now Figure 1 and Figure 2 . In the following, an assembly or module 1 comprises at least two power electronic components 11 connected in parallel. For example, the power electronic component 11 can be a power semiconductor device, a power submodule or a power converter. Here, the word "component" or "device" is used to designate a sub-part of an electric "module" or an electric "assembly" where one is electrically connected in parallel with respect to the other. The components 11 of the same module 1 can be packaged together or separated from each other.

[0075] Figure 1 It is along Figure 2 An example of a cross-sectional view taken along the line marked "Y" of the module 1 is shown in FIG. In various embodiments, the top view may show individually packaged components. Figure 2 The element marked "Z" in the figure schematically represents the electrical isolation of a configuration in which the elements 11.1 and 11.2 are disconnected from each other, as will be referred to below. Figure 7 The emitter pads (e1 and e2) of the elements 11.1 and 11.2 are separated from each other. The gate drivers (G1 and G2) of the elements 11.1 and 11.2 are separated from each other. In contrast, in a configuration in which the elements 11.1 and 11.2 are connected to each other (which will be referred to below), Figure 6 (Common emitter pad E and common gate driver G) will not exist Figure 2 For simplicity, no external connections to the system are drawn. In another configuration, components 11.1 and 11.2 are based on Figure 1 In the separate mechanical structure described in , element E, gate drivers (G1 and G2), and emitter pads (e1 and e2) have external electrical connections. In other words, the connections of the elements can be determined and made at the system level outside of the device structure.

[0076] Figure 1 and Figure 2 An example of a module 1 is shown, which comprises two elements 11 (in Figure 2 1 and 11.2) and contain a superposition of layers. From bottom to top, Figure 1The module 1 comprises an element 11: an electrically insulating layer 101 (e.g. based on aluminum oxide) and a conductive layer 102 (e.g. of copper). The module 1 also comprises components respectively associated with each element 11 from bottom to top: a solder layer 103, a semiconductor die 104 and a metallization layer 105. The module 1 also comprises an electrically conductive wire bond 2 which ensures an electrical connection between a portion of the conductive layer 102 of the element 11 in the cross-sectional view and the metallization layer 105 (the module 1 comprises at least two power electronic elements 11 connected in parallel).

[0077] Here, each element 11 includes a semiconductor die 104, which is a semiconductor element, such as an insulated gate bipolar transistor (IGBT) or a metal oxide semiconductor field effect transistor (MOSFET). It can be made of silicon, silicon carbide (SiC) and / or gallium nitride (GaN). The element 11 is a power electronic device, which is arranged to operate at a voltage higher than 50V and a current higher than 1A.

[0078] The semiconductor die 104 is metallized at least on one side, here on the top. In other words, the semiconductor die 104 is coated with a metallization 105. For example, the metallization layer is made of an aluminum alloy. The thickness of this metallization 105 is between 1 and 20 micrometers. The free surface is used to fix the wire bonds, for example by thermosonic bonding. During the service life of the module 1, this connection is subject to harsh conditions and some cracks and defects may appear at this specific location.

[0079] <Theory>

[0080] In a module 1 comprising at least two parallel power electronic components 11, the load current is distributed through each parallel element 11 according to its on-state resistance, which depends on the assembly and junction temperature. When a wire bond 2 is detached or any other electrical connection defect occurs, the on-state resistance of the component increases. When one component 11 deteriorates more than the other parallel power component 11, a reduction of the current flowing through this one component, for example 1% to 20%, can be observed. The current reduction is supported by the parallel power component that will conduct more current.

[0081] Furthermore, in the case of thermal degradation (typically resulting in delamination), the temperature across the degraded power element 11 increases, resulting in a decrease in the threshold voltage by up to 0.5V.

[0082] In the following, the component 11 is an IGBT device, but any skilled person can transfer the explanation based on such examples to other power electronic components, such as MOSFET or MISFET semiconductors.

[0083] The applicant has noticed that the turn-off waveform is strongly dependent on the current flowing in element 11. The classical gate drive circuit applies a positive voltage V cc To negative voltage V ee The gate voltage V ge The change with time t can be calculated according to the following formula [Math 1]. The saturated collector current depends on the gate voltage V according to the following formula [Math 2] ge The turn-off delay of a component is d , such as die 104, is driven by current I sw Through, the following formula [Mathematical formula 3] can be used according to the gate resistance R g , input capacitor C ies , transconductance gfe and threshold voltage V th to calculate.

[0084] [Mathematical formula 1]

[0085]

[0086] [Mathematical formula 2]

[0087] I c =gfe·(V ge -V th )

[0088] [Mathematical formula 3]

[0089]

[0090] Figure 3 and Figure 4 They represent the turn-off delay t d According to the shutdown current I toff (Here the current I is subtracted from the off current sw to make the reference zero) and the threshold voltage V th An example of evolution. Figure 3 and Figure 4 The values ​​shown are obtained for a component 11 which, in the example, is an IGBT with reference number "CM100RX-24S1" and has the following nominal properties: V cc =15V; V ee =-5V; R g =72Ω; C ies =21nF; V th =6V and gfe=43A / V.

[0091] Therefore, the components with higher current should start to turn off the current switch before the (degraded) components with lower current. The turn-off of the degraded components through which the reduced current passes can be delayed by a few nanoseconds to 100 nanoseconds. In addition, the components with higher threshold voltage V th The components should have a lower threshold voltage than V th The (degraded) components start to turn off the current switch earlier. th The turn-off of the affected degraded components can be delayed by a few nanoseconds to 40ns.

[0092] The following [Table 1] summarizes the effects of the two degradations of element 11, where R on is the resistance of element 11 in the on state, I c is the current flowing through element 11, T j is the junction temperature, V ce is the steady-state voltage.

[0093] [Table 1]

[0094] Wire Bonding2 Solder layer 103 <![CDATA[↑R on →↓I c →↑t d ]]> <![CDATA[↑T j →↓V th →↑t d ]]> <![CDATA[↑T j →↑V ce →↓I c →↑t d ]]>

[0095] Figure 5 1 shows the current I flowing through the two parallel elements 11.1 and 11.2 (here two IGBTs) of the module 1 when the commutation is turned off when the first element 11.1 is more degraded than the second element 11.2. c As we can see, the switch-off of the degraded element 11.1 is delayed. It temporarily sees its current increase because it alone holds a higher proportion of the total load current.

[0096] A method for detecting mismatch between parallel power electronic components 11 in a power electronic module 1 may include:

[0097] a. In response to detection of a common shutdown of the element 11, triggering a measurement period;

[0098] b. During the measurement period, measuring a series of emitter voltages V of at least one of the components eE ;

[0099] c. Extracting data from the measurement, the data including the emitter voltage V during the measurement period eE the sign and / or magnitude of the local extrema of ;

[0100] d. Inferring from the extracted data at least the presence or absence of a mismatch between the elements.

[0101] Now Figure 6 and Figure 7 Take this as an example for reference. Figure 6corresponds to a configuration in which the two parallel elements 11.1 and 11.2 (IGBTs) have a common gate driver, and Figure 7 The configuration corresponds to the two parallel-connected elements 11.1 and 11.2 (IGBTs) with their respective gate drivers. At the corresponding voltages, a change in the currents I1 and I2 flowing through the elements 11.1 and 11.2, respectively, can be observed.

[0102] exist Figure 6 and Figure 7 In the example, gate driver resistors and Kelvin resistors are not presented. Based on these examples, in various embodiments, each component 11 may include a single die or a combination of dies. The components 11 of the same module 1 may or may not be packaged together. These components may have a common gate driver configuration ( Figure 6 ) or their respective gate drivers ( Figure 7 ). The number of parallel power elements 11 in the module 1 is at least two. For example, in various embodiments, it can be three, four, up to ten or even twenty.

[0103] exist Figure 6 and Figure 7 In the example, the emitter voltages of components 11.1 and 11.2 are V eE1 and V eE2 , respectively, between the emitter pads on the power semiconductor elements 11.1 and 11.2 (respectively L eE1 and L eE2 ) is sensed to the external emitter pad of module 1. This inductor L eE is generated by connecting the power semiconductor element 11 to the rest of the power module 1. The emitter pad on the power semiconductor element 11 can be measured using, for example, a Kelvin emitter provided on the power module 1. In other words, due to the RL behavior, V eE1 and V eE2 The change (curve shape) is a proportional and derivative image of the power semiconductor current. Those skilled in the art will understand that, depending on the structure and component type of each module 1, the corresponding voltage V can be measured at other points in the circuit. eE1 and V eE2 :The above has two IGBTs and a parasitic inductor L eE1 and L eE2 The architecture is just an example, but the solutions disclosed here are not limited to such architecture.

[0104] In some embodiments, the shutdown event can be detected directly from the trigger signal sent by the controller of module 1, or by detecting the emitter voltage V eEIn order to detect the peak value, the measured emitter voltage V eE The value is compared with a predetermined value. For example, if the emitter voltage V eE If the value is outside the nominal range centered around 0V (such as -1V; 1V or -2V; 2V), a peak can be identified.

[0105] Reference now Figure 8 The emitter voltage V of the elements 11.1 and 11.2 is measured (and stored) starting from the instant t corresponding to the common turn-off command signal of said elements 11.1 and 11.2. eE1 and V eE2 In other words, the measurement is synchronized with the common shutdown trigger. Figure 8 The values ​​shown correspond to Figure 7 Measurements performed on the structure shown (two IGBTs with separate gate driver configurations).

[0106] <Mismatch or non-mismatch>

[0107] In some embodiments, if the purpose is only to determine whether there is a mismatch in the module 1 without identifying which component is the most degraded, a single emitter voltage V of a single component 11 is monitored. eE The absolute value of is sufficient, even if the sign is unknown, for example by comparing the absolute value with a threshold value. During the measurement period, an emitter voltage V eE The magnitude of the local extrema of makes it possible to infer whether there is a mismatch between the corresponding element 11 of the module 1 and another element 11. In some embodiments with the same purpose (only determining whether there is a mismatch in the module 1, without needing to identify which element is the most degraded), even if the absolute value itself is unknown, a pair of emitter voltages V of a pair of elements 11.1 and 11.2 is monitored. eE1 and V eE2 The two signs of are sufficient, for example by checking whether the two signals are different. During the measurement period, the two emitter voltages V eE and V eE2 The sign of the local extremum of makes it possible to infer whether there is a mismatch between the corresponding elements 11.1 and 11.2. These two possibilities (single absolute value V eE Compared with the threshold, or two values ​​V eE1 and V eE2 The reason why we can say that the desired data is the magnitude and / or sign of the local extreme value of the emitter voltage of "at least one element" is that we can compare the two signs of each other) eE data with one symbol because the reliability of inferring the presence or absence of a mismatch is low.

[0108] <The most severe degeneration, or not severe>

[0109] In some other embodiments, the purpose is to determine whether there is a mismatch in module 1 and, if there is a mismatch, also determine that the emitter voltage V has been measured and extracted. eE Whether the element 11 is the most degraded, for example, to determine the target intervention. The voltage V eE1 and V eE2 The extreme values ​​(minimum and / or maximum) of V can be used to determine which component 11.1 or 11.2 conducts the large current, since the switching current is proportional to the corresponding V eE1 and V eE2 is inversely proportional to the minimum or maximum value of . Figure 8 In the example, I C,11.1 =89A and I C,11.2 =107A. Fig. 9 and Fig.10 In Figure 1, the measured values ​​of several test cases are superimposed: there are zero, one, two, three, four and five lead-off cases in a component 11. Each curve corresponds to one of these cases. Fig. 9 shows the measured emitter voltage V of element 11.1 eE1 value, Fig.10 shows the measured emitter voltage V of element 11.2 eE2 The following [Table 2] shows an example of measured values ​​(amplitude and sign) of the amplitude (absolute value) above 0.5 V of the two power elements 11.1 and 11.2 in the test case with five types of lead-off.

[0110] [Table 2]

[0111]

[0112]

[0113] As an example, the first value outside a predetermined range (eg, [-0.5V; +0.5V]) is designated as a trigger "peak", marked as "0" on the drawing. The trigger peak can be used to define a time reference, triggering and synchronizing measurement operations.

[0114] In this example, the first peak "I" after the reference peak "O", the emitter voltage V eE1 The extreme value is positive (+3.65V), and the emitter voltage V eE2 The extreme value of is negative (-2.8 V). Therefore, it can be identified that the component 11.1 is the most degraded component among the components 11.1 and 11.2.

[0115] If we measure a single emitter voltage V eE, and if a first peak I corresponding to a shutdown trigger can be identified (for example, in the case of a command / trigger signal issued by the controller of module 1), the emitter voltage V of the first peak I eE The sign of is sufficient to identify whether the corresponding element is the most degraded: if the sign is positive, the element is the most degraded element. If the sign is negative, it is not the most degraded element. This is true even for modules comprising more than two parallel elements. Identifying the first peak I to be considered means avoiding the comparison with the preliminary peak directly generated by the shutdown command signal (corresponding to Fig. 9 and Fig.10 For example, one example of clearly identifying the initial peak O and the first peak I is to directly monitor the trigger / command signal issued by the controller of module 1.

[0116] The value of the extreme value, and in particular the sign, is key to the measurement. To extract this data from the raw measurement signal, an analog-to-digital converter (ADC) may be used. In some embodiments, the extraction of the extreme value from the measurement (identification of the "peak") is performed by analog and logic circuits, making the use of expensive analog-to-digital converters unnecessary.

[0117] Fig.11 An example of analog and logic circuits that can be used is shown. In the example described here, the analog and logic circuits include a first signal conditioning circuit 201, a second signal conditioning circuit 202, and a module 203 including an RS flip-flop and an inverter. In various embodiments, the analog and logic circuits include other functionally equivalent parts.

[0118] Waveform A is the emitter voltage V measured on the most degraded element 11. eE In practice, the relative degradation state of each element 11 is unknown, as it is one of the information we want to determine. For example, if two power elements 11.1 and 11.2 are connected in parallel, and 11.1 is the most degraded, then if the two emitters e1 and e2 of the power elements 11.1 and 11.2 are disconnected, the waveform is V eE1 After being processed by the first signal conditioning circuit 201 and the second signal conditioning circuit 202, logic signals A1 and A2 are output respectively. When the two logic signals are analyzed by the RS flip-flop and the inverter (module 203), a logic signal (q=1) is output, which means that the power element 11.1 is the most degraded.

[0119] Waveform B is the emitter voltage V measured on the most non-degraded element 11. eEFor example, if two power elements 11.1 and 11.2 are connected in parallel, and 11.2 is not the most degraded, then if the two emitters e1 and e2 of the power elements 11.1 and 11.2 are disconnected, the waveform is V e2e1 =V eE2 -V eE1 After being processed by the first signal conditioning circuit 201 and the second signal conditioning circuit 202, logic signals B1 and B2 are output respectively. When the two signals are analyzed by the RS trigger and the inverter (module 203), a logic signal (q=0) is output, which means that the power element 11.2 is not the most degraded.

[0120] Waveform C is the emitter voltage V measured on the most non-degraded element 11. eE For example, if two power elements 11.1 and 11.2 are connected in parallel, and 11.2 is not the most degraded, then if the two emitters e1 and e2 of power elements 11.2 and 11.2 are disconnected, the waveform is V eE2 .

[0121] After being processed by the first signal conditioning circuit 201 and the second signal conditioning circuit 202, logic signals C1 and C2 are output respectively. When the two signals are analyzed by the RS flip-flop and the inverter (module 203), a logic signal (q=0) is output, which means that the power element 11.2 is not the most degraded.

[0122] In summary, the output signals of the sequence analyzers 201, 202, 203 directly answer the logical question: "Is the monitored component the most degraded?"

[0123] <Mismatched Quantization>

[0124] In some embodiments, the degradation mismatch can be quantified. For example, an assembly of a diode, a capacitor, and a resistor, used as a peak detector, can be combined as Fig.11 The circuit shown. Sampling can be performed by an ADC, or the signal can be compared with a predetermined threshold by a comparator, so that the maximum emitter voltage (V eE ) to obtain mismatched quantization. Fig.12 is an example of this quantification to determine the number of lead drops.

[0125] <Kelvin to Kelvin voltage measurement>

[0126] In an embodiment where only the mismatch between the two components 11 of the module 1 is monitored, a differential emitter voltage V may be obtained (measured) across the emitter pads of the components 11.1 and 11.2. eeIn other embodiments, two measurements may be compared: V e1e2 =V eE1 –V eE2 In doing so, only one sensor and conditioning circuit is required (one for each pair of elements 11), and the sensitivity to degradation mismatch is increased. In addition, the partial dependence on temperature and current is reduced. Such an implementation is compatible with two architectures: common or separate gate driver configurations ( Figure 6 and Figure 7 ).

[0127] Fig.13 shows the emitter voltage V during a turn-off event e1e2 , each curve corresponding to a specific number of pin-outs in the component 11 . 1 in the split gate driver configuration. Fig.14 shows the emitter voltage V during a turn-off event e1e2 , each curve corresponding to a specific number of pin-outs in the component 11 . 1 in the common gate driver configuration. Fig.15 The values ​​of the negative extremes (minimum) (peak) of the degradation level imbalance quantified according to the number of shedding (n) in the configuration of the split gate driver are shown, each curve corresponding to a specific current I and temperature T case. Fig.17 shows the emitter voltage V e1e2 The same content as the positive extreme value (maximum value) of . Fig.16 The common gate driver configuration is shown with Fig.15 The same content, Fig.18 In a common gate driver configuration the Fig.16 Same content.

[0128] from Figures 13 to 18 It can be seen that the magnitude of the peak is a function of the degradation level. This is true for both common and individual gate driver configurations. The extracted data includes the measured emitter voltage V eE When the emitter voltage V of a pair of elements 11.1 and 11.2 is measured by a Kelvin emitter sensor, the quantification of the mismatch can be inferred from the extracted data. eE1 and V eE2 This information can be obtained for module 1 including such a sensor when a sequence is performed.

[0129] Using only a single Kelvin emitter sensor for a pair of elements 11 is possible for both configurations: the connected elements (e.g. Figure 6 as shown) and disconnected components (as Figure 7). In addition, it is very convenient because Kelvin emitter sensors can be used in some existing architectures: there is no need to modify these existing architectures to add Kelvin emitter sensors. This sensor is inexpensive compared to other existing sensors.

[0130] <Pair Monitoring>

[0131] In some embodiments, a multiplexer may be provided to connect a single monitoring circuit to the appropriate pair of elements 11, so that even for a large number of power elements 11 in the module 1, the number of monitoring circuits is advantageously limited to a single circuit. The elements 11 are switched two by two, and for each pair, the emitter voltage V e1e2 .

[0132] <Enhanced Sensitivity>

[0133] In some embodiments, the method further comprises:

[0134] - An additional external gate resistor is applied during the measurement operation.

[0135] By artificially increasing the measured gate resistance, the mismatch sensitivity is increased during a single switching time, and the resulting increased losses are limited in time (only during a small measurement period). Fig.19 An example of a circuit that can be used to temporarily apply this increased resistance is shown. Switch M3 is only open during the measurement due to the inverted trigger signal. During the measurement, the total gate resistance is R gext and R gext2 Otherwise, module 1 only has external gate resistor R gext Works in normal mode under the condition of

[0136] <Feedback loops and synchronization>

[0137] In some embodiments, the method is performed a first time to identify the most degraded component, and then the method is repeated at least once using a transformation loop configured to infer a turn-off delay of at least one component relative to other components in order to converge to a time-synchronized first peak I.

[0138] This embodiment with two elements 11.1 and 11.2 is presented in Fig. 20. The turn-off delay of the first element 11.1 is marked with t1 and the turn-off delay of the second element 11.2 is marked with t2. In embodiments with more than two elements, the same approach can be used by applying the same delay t to the turn-off of the element not identified as the "most degraded". The values ​​of the inferred delays t1 and / or t2 can be adjusted step by step until the time synchronization of the first peak I is achieved. In doing so, by reducing the time offset, even before perfect synchronization is achieved, the turn-off losses are at least partially balanced in module 1: the overcurrent in module 1 is reduced and the degradation consequences produced in module 1 are reduced. The absolute difference between the two applied delays (|t1-t2|) can serve as an indicator for the relative degradation between elements 11.1 and 11.2. For example, if Fig. 20 As shown, the absolute difference between the two applied delays (|t1-t2|) can be compared with a predetermined threshold value t th When the threshold value t is exceeded, th When an alarm signal is generated.

[0139] <Cyclic process>

[0140] In some embodiments, the method comprises a series of cycles of operation. In other words, the method described at the beginning is repeated N times, for example over a period of several hours. The measured and / or extracted data are stored to constitute a history of events related to the degradation of the element 11 during an operating period of the module 1 longer than a single off period. Then, or in real time, the data extracted at the current time can be compared with the data extracted previously. If the comparison indicates that there is an evolution, the degradation index of the module 1 can be increased. Once this degradation index reaches a predetermined value (threshold), a warning signal is generated.

[0141] The degradation of module 1 can be observed over the entire service life, even at V eE In the event of any mismatch in the waveforms. In addition, the current degradation level of each element 11 can be identified (not only relative to each other). [Table 3] below shows an example of four measurements taken at intervals of 1000 hours, the voltage of the first peak I is measured and saved in the table.

[0142] [Table 3]

[0143]

[0144] The data extracted and stored in [Table 3] are shown as:

[0145] - From the comparison between measurement 2 and measurement 1, it can be seen that the degradation rate of component 11.2 is faster than that of component 11.1 → the degradation index of component 11.2 can be increased

[0146] - From the comparison between measurement 3 and measurement 2, it can be seen that the degradation rate of component 11.2 is faster than that of component 11.1 → the degradation index of component 11.2 can be increased

[0147] - From the comparison between measurement 4 and measurement 3, it can be seen that the degradation rate of component 11.1 is faster than that of component 11.2 → the degradation index of component 11.1 can be increased.

[0148] In the example described here, the threshold for triggering the alarm / warning signal is pre-set to correspond to the situation where the fifth wire bond is off. The threshold is obtained by testing the prototype. The definition of the threshold can vary and can be modified by those skilled in the art according to the context.

[0149] Fig.21 shows the voltage V between the two emitters of components 11.1 and 11.2 e1e2 Schematic example of the evolution over time and the corresponding degradation indicators.

[0150] <Conclusion>

[0151] Electrical, thermal and degradation differences of parallel power components lead to steady-state current imbalance. This is due to non-uniform resistance, junction temperature produces non-uniform current distribution. Therefore, monitoring this current imbalance is a differential electrical, thermal and damage sensitive parameter. However, it requires monitoring the current of individual power components with relatively high resolution, which is technically complex and expensive.

[0152] Methods based on transient switching waveform monitoring are generally considered expensive, inaccurate, and non-robust due to high-frequency sensor requirements, low sensitivity, and complex dependencies on operating conditions and designs.

[0153] To achieve high current capabilities, one technique consists of paralleling power components (e.g., dies, converters, or subsets of components). This solution is widely adopted given the flexibility and scalability of current power electronics. Among the issues that should be faced with parallelization of power electronics, current distribution caused by non-uniform electro-thermal damage characteristics should be identified during commissioning, use, and maintenance phases.

[0154] The problem solved by the method disclosed above is safe, accurate and low-cost current distribution and degradation monitoring of the electrical and thermal interconnections of individual power elements connected in parallel, as well as the automatic generation of alarm signals. eE Such problems can be solved by identifying the mismatch based on the sign and / or magnitude of the series of peaks (voltage between Kelvin and emitter) during the turn-off switching time.

[0155] <Industrial Applicability>

[0156] The technical solution proposed here can be used to automatically trigger an alarm signal to implement corrective measures, such as repair or functional adjustment of the power module, or even targeted replacement.

[0157] The present disclosure is not limited to the methods, modules and computer programs described herein, which are only examples. The present invention includes every option that a person skilled in the art would think of when reading this document.

[0158] <Reference Signs List>

[0159] -1: System -11: Power electronic components -2: Conductive wire bonds -101: Electrical insulation layer -102: Conductive layer -103: Solder layer -104: Semiconductor die -105: Metallization layer -201: Signal conditioning circuit -202: Signal conditioning circuit -203: RS flip-flop and inverter -O: Trigger peak -I: First peak -II: Second peak -III: Third peak -A: Waveform -B: Waveform -C: Waveform.

Claims

1. A method for detecting mismatch between parallel power electronic components (11) in a power electronic module (1), the method comprising the following steps: a. in response to detection of a common shut-off of the element (11), triggering a measurement period; b. During the measurement period, measuring a series of emitter voltages V of at least one of the components eE ; c. Extracting data from the measurement, the data including the emitter voltage V during the measurement period eE the sign and / or magnitude of the local extrema of ; d. Inferring at least the presence or absence of a mismatch between the elements from the extracted data.

2. The method according to claim 1, wherein: The extracted data at least includes: - The two emitter voltages V of the two components eE1 and V eE2 the sign of the local extremum of the sequence of , or - The emitter voltage V of a component eE The sign and magnitude of the local extrema of the sequence; And, if it has been inferred that there is a mismatch between the elements, the method further comprises the following steps: e. Inferring the emitter voltage V from the extracted data eE , or V eE1 and V eE2 Whether the component being measured is the most degraded.

3. The method according to one of the preceding claims, wherein: The step of extracting from the measurement is performed by analog and logic circuits, making the use of analog-to-digital converters superfluous.

4. The method according to one of the preceding claims, wherein: The extracted data also includes the emitter voltage V during the measurement period eE The amplitude of the local extremum of And, if it has been inferred that there is a mismatch between the elements, the method further comprises the following steps: f. Inferring a quantification of the mismatch from the extracted data.

5. The method according to one of the preceding claims, wherein: Measure the differential emitter voltage V of a pair of components (11.1, 11.2) ee .

6. The method according to one of the preceding claims, implemented on a module (1) comprising at least three power electronic components (11) connected in parallel, wherein: Measurements are performed in a sequential manner for each pair of components (11) having a common monitoring circuit, a multiplexer being operatively interfaced between the monitoring circuit and the components (11).

7. The method according to one of the preceding claims, further comprising the following steps: - An additional external gate resistor is applied during the measurement operation.

8. The method according to one of the preceding claims, wherein: The inferring operation further includes identifying the most degraded element (11) of the at least two elements (11), and then The sequence of operations is repeated at least once, the at least one repetition comprising deducing a delay d of the switching off of at least one of the elements relative to another element before triggering the measurement period.

9. The method according to one of the preceding claims, wherein: The series of operations is repeated at least once to achieve detection of mismatches over the operational life of the module (1).

10. The method according to one of the preceding claims, further comprising the steps of: -Generate an alarm signal based on the inferred information.

11. A power electronic module (1) comprising at least two power electronic components (11) connected in parallel and arranged to implement the method according to one of claims 1 to 10.

12. Computer software comprising instructions for implementing at least part of the method according to one of claims 1 to 10 when the computer software is executed by a processor. 13 . A computer-readable non-transitory recording medium on which software is registered, the software implementing the method according to claim 1 when the software is executed by a processor.

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