Determining mask rule check violations and mask design based on local feature dimensions

Abstract

Methods and systems are described herein for determining mask rule check (MRC) violations associated with mask features based on local feature sizes (LFDs) of the mask features. A detector is placed at a first position of the mask feature and its size is changed until it is in contact with a second position of the mask feature. The size of the detector when it is in contact with the second position is determined as the LFD of the portion of the mask feature. For example, the LFD may be determined as a function of the radius of the circular detector. The MRC violation may be detected by comparing the LFD to an LFD specification in the MRC. For example, when the partial LFD is less than a minimum LFD specified in the MRC or greater than a maximum LFD, an MRC violation may be detected.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Application No. 63 / 389,137, filed on July 14, 2022, and incorporated herein by reference in its entirety. Technical Field

[0003] The description herein relates to a mechanism for determining mask rule checking violations and mask design for a photolithography mask to be used in semiconductor manufacturing. Background Art

[0004] A lithographic projection apparatus may, for example, be used in the manufacture of integrated circuits (ICs). In this case, a patterning device (e.g., a mask) may contain or provide a circuit pattern (a "design layout") corresponding to a separate layer of the IC, and the circuit pattern may be transferred to a target portion (e.g., including one or more dies) on a substrate (e.g., a silicon wafer) that has been coated with a layer of radiation-sensitive material ("resist"), such as by irradiating the target portion through the circuit pattern on the patterning device. Typically, a single substrate contains a plurality of adjacent target portions to which the circuit pattern is transferred successively, one target portion at a time, by the lithographic projection apparatus. In one type of lithographic projection apparatus, the circuit pattern on the entire patterning device is transferred to one target portion at a time; such an apparatus is generally referred to as a stepper. In an alternative apparatus, generally referred to as a stepper-scan apparatus, the projection beam is scanned over the patterning device in a given reference direction (the "scanning" direction) while synchronously moving the substrate parallel or antiparallel to the reference direction. Different portions of the circuit pattern on the patterning device are gradually transferred to one target portion. Typically, since the lithographic projection apparatus has a magnification factor M (typically <1), the speed F at which the substrate is moved will be a factor of M times the speed at which the projection beam scans the patterning apparatus. Further information on the lithographic apparatus described herein can be gleaned, for example, from US 6,046,792, which is incorporated herein by reference.

[0005] Before the circuit pattern is transferred from the patterning device to the substrate, the substrate can undergo various procedures, such as priming, resist coating and soft baking. After exposure, the substrate can undergo other procedures, such as post-exposure baking (PEB), developing, hard baking and measurement / inspection of the transfer circuit pattern. This program array is used as the basis for the individual layers of manufacturing equipment (such as IC). Then, the substrate can undergo various processes, such as etching, ion implantation (doping), metallization, oxidation, chemical mechanical polishing, etc., all of which are intended to complete the individual layers of the device. If several layers are needed in the device, then the entire procedure or its variant is repeated for each layer. Eventually, the device will be present in each target portion on the substrate. Then, these devices are separated from each other by technology (such as cutting or sawing, etc.), so that the individual device can be mounted on the carrier, connected to the pin, etc.

[0006] As mentioned, photolithography is a central step in the fabrication of ICs, where patterns formed on a substrate define the functional elements of the IC, such as microprocessors, memory chips, etc. Similar photolithography techniques are also used in the formation of flat panel displays, microelectromechanical systems (MEMS), and other devices.

[0007] As semiconductor manufacturing processes continue to advance, following a trend generally referred to as "Moore's Law," the size of functional elements continues to decrease, while the number of functional elements (such as transistors) per device has steadily increased for decades. At the current state of the art, the layers of a device are manufactured using a lithographic projection apparatus that projects a design layout onto a substrate using illumination from a deep ultraviolet illumination source, thereby creating individual functional elements with dimensions well below 100 nm (i.e., less than half the wavelength of the radiation from the illumination source (e.g., a 193 nm illumination source)).

[0008] The process of printing features with dimensions smaller than the classical resolution limit of a lithographic projection apparatus is generally referred to as low-k1 lithography, according to the resolution formula CD=k1×λ / NA, where λ is the wavelength of the radiation employed (currently 248nm or 193nm in most cases), NA is the numerical aperture of the projection optics in the lithographic projection apparatus, CD is the "critical dimension" (usually the smallest printed feature size), and k1 is an empirical resolution factor. In general, the smaller the k1, the more difficult it is to reproduce a pattern on a substrate that is similar in shape and size to that planned by the circuit designer in order to achieve specific electrical functionality and performance. In order to overcome these difficulties, complex fine-tuning steps are applied to the lithographic projection apparatus and / or the design layout. For example, these include, but are not limited to, optimization of NA and optical coherence settings, customized illumination schemes, the use of phase-shifted patterning equipment, optical proximity correction (OPC, sometimes also referred to as "optical and process correction") in the design layout, or other methods generally defined as "resolution enhancement technology" (RET). The term "projection optics" as used herein should be broadly interpreted to cover various types of optical systems, including, for example, refractive optics, reflective optics, apertures, and reflective-refractive optics. The term "projection optics" may also include components that operate according to any of these design types to collectively or individually direct, shape, or control a projection beam of radiation. The term "projection optics" may include any optical component in a lithographic projection apparatus, regardless of the location of the optical component in the optical path of the lithographic projection apparatus. Projection optics may include optical components for shaping, conditioning, and / or projecting radiation from a source before the radiation passes through a patterning device and / or optical components for shaping, conditioning, and / or projecting radiation after the radiation passes through a patterning device. Projection optics typically do not include a source and a patterning device. Summary of the invention

[0009] In some embodiments, a non-transitory computer-readable medium having instructions is provided, which, when executed by a computer, causes the computer to perform a method for determining a mask rule check violation associated with a mask feature. The method includes: placing a detector at a location on an edge of the mask feature, wherein the detector is a two-dimensional (2D) geometric structure; changing the size of the detector until the detector contacts a specified point, the specified point being on the edge of the mask feature or on the edge of another mask feature; determining a local feature size based on the size of the detector that causes contact with the specified point; and determining a mask rule check (MRC) violation based on the local feature size.

[0010] In some embodiments, a non-transitory computer-readable medium having instructions is provided, which, when executed by a computer, causes the computer to perform a method for updating a mask design to reduce mask rule check violations associated with mask features. The method includes: obtaining a local feature size associated with a mask feature of the mask design; determining an MRC violation of the mask feature based on the local feature size; and adjusting the mask feature to satisfy the MRC based on the local feature size.

[0011] In some embodiments, a method for determining a mask rule check violation associated with a mask feature is provided. The method includes: placing a detector at a location on an edge of the mask feature, wherein the detector is a two-dimensional (2D) geometric structure; changing the size of the detector until the detector contacts a specified point, the specified point being on the edge of the mask feature or on the edge of another mask feature; determining a local feature size based on the size of the detector that causes contact with the specified point; and determining a mask rule check (MRC) violation based on the local feature size.

[0012] In some embodiments, a device for determining a mask rule check violation associated with a mask feature is provided. The device includes: a memory storing an instruction set; and a processor configured to execute the instruction set to cause the device to perform the following method: placing a detector at a position on an edge of a mask feature, wherein the detector is a two-dimensional (2D) geometric structure; changing the size of the detector until the detector contacts a specified point, the specified point being on the edge of the mask feature or on the edge of another mask feature; determining a local feature size based on the size of the detector that causes contact with the specified point; and determining a mask rule check (MRC) violation based on the local feature size. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a block diagram of various subsystems of a lithography system consistent with various embodiments.

[0014] Figure 2 A flow of a lithography process or patterning simulation method consistent with various embodiments is shown.

[0015] Figure 3 is a block diagram of a system for improving mask design based on local feature dimensions (LFD) of mask features consistent with various embodiments.

[0016] Figure 4 is a flow chart of a method for performing mask rule checking (MRC) consistent with various embodiments.

[0017] Figure 5A and Figure 5B Determination of the LFD of a mask feature consistent with various embodiments is illustrated.

[0018] Fig. 6A and Figure 6B Determination of the LFD of a mask feature consistent with various embodiments is illustrated.

[0019] Figure 7 Detection of MRC violations of LFD-based mask features consistent with various embodiments is illustrated.

[0020] Fig. 8A Determination of a cost function for LFD based on mask features consistent with various embodiments is illustrated.

[0021] Figure 8B A graph depicting an example form of a kernel function consistent with various embodiments is shown.

[0022] Figure 8C Determination of the gradient of a cost function consistent with various embodiments is illustrated.

[0023] Fig. 9 is a flow chart of a method for optimizing mask design based on LFD of mask features consistent with various embodiments.

[0024] Fig.10 is a flow chart illustrating aspects of an example research method for joint optimization / co-optimization consistent with various embodiments.

[0025] Fig.11 An embodiment of a further optimization method consistent with the various embodiments is shown.

[0026] Fig. 12A , Fig. 12B and Fig.13 Example flow diagrams of various optimization processes consistent with various embodiments are shown.

[0027] Fig.14 is a block diagram of an example computer system according to an embodiment of the present disclosure.

[0028] Specify implementation method

[0029] In lithography, in order to print a pattern onto a substrate, a pattern of a patterning device (e.g., a mask) (also commonly referred to as a "design layout" or "design") is projected onto a resist layer provided on a substrate (e.g., a wafer). The pattern may be projected onto one or more dies of the substrate. In some embodiments, the design layout or a portion of the design layout is used to design a mask to be used in semiconductor manufacturing. Generating a mask design includes determining mask features based on a mask optimization simulation, and checking whether the mask features satisfy a mask rule check (MRC). Conventional MRC violation detection processes may use a detector (e.g., a circular, elliptical, or other shaped structure) that slides along the edge of a mask feature to detect an MRC violation of a mask feature to identify an MRC violation. The detector may have a fixed size defined according to an MRC constraint (such as a minimum width or a minimum curvature) during detection. Conventional techniques may have some disadvantages. For example, conventional MRC violation detection processes may not quantify MRC violations. That is, these processes may not indicate the extent of MRC violations in a measurable manner (e.g., expressed in units such as nanometers (nm)). Further, conventional MRC violation detection processes may detect MRC violations based on mask feature sizes being smaller than a minimum feature size, but may not detect MRC violations based on mask feature sizes being larger than a maximum feature size, which may be undesirable in some applications or scenarios.

[0030] A mechanism for improving the detection of MRC violations associated with, for example, mask designs with curved mask features is disclosed herein. The present disclosure provides a detector (e.g., a two-dimensional (2D) geometry) that is not only configured to determine the MRC violations of mask features whose size exceeds a specified size (e.g., the maximum feature size specified in MRC), but also to determine the extent of the MRC violations (e.g., in nm). For example, a detector is placed at a specified position on the edge of a mask feature, and the size of the detector is changed until the detector contacts another position of the mask feature (e.g., one or more positions on the edge) or another mask feature (e.g., an adjacent mask feature). When the detector contacts other positions, the size of the detector represents the local feature size (LFD) of the portion of the mask feature at the position where the detector is placed. In some embodiments, the LFD indicates the size of a portion of a mask feature (e.g., between two specified positions on the edge of a mask feature) or the distance between two mask features. In this way, the LFD of a mask feature can be determined based on the size of the detector (e.g., a function of the radius of a circular detector). When the LFD is outside a specified LFD range (e.g., the LFD is less than the minimum LFD or greater than the maximum LFD), an embodiment can detect an MRC violation. In some embodiments, the degree of MRC violation is determined as the difference between the actual LFD and the minimum or maximum LFD. The measured LFD can also be used to adjust the mask design to minimize or eliminate MRC violations. For example, the cost function indicating the penalty associated with the mask feature that violates MRC can be determined as LFD. The mask features (such as the size or shape of the mask features) can be updated until the cost function is minimized. Therefore, the mask design can be improved based on the information related to LFD determined using the detector. According to the present disclosure, this can therefore improve the semiconductor manufacturing process of the mask designed based on the information related to MRC violations.

[0031] Although reference may be made to the manufacture of ICs in this document, it should be clearly understood that the description herein has many other possible applications. For example, it can be used to manufacture integrated optical systems, guide and detection patterns for magnetic domain memories, liquid crystal display panels, thin film magnetic heads, etc. Those skilled in the art will understand that in the context of such alternative applications, any use of the terms "mask", "wafer" or "die" herein should be considered interchangeable with the more general terms "mask", "substrate" and "target portion", respectively.

[0032] Herein, the terms "radiation" and "beam" are used to cover all types of electromagnetic radiation, including ultraviolet radiation (e.g., wavelengths of 365, 248, 193, 157 or 126 nm) and EUV (extreme ultraviolet radiation, e.g., wavelengths in the range of about 5 to 100 nm).

[0033] As used herein, the terms "optimizing" and "optimization" refer to or mean adjusting a lithographic projection apparatus, a lithographic process, etc., so that the result and / or process of the lithography has a more desired characterization, such as a higher accuracy of the projection of the design layout on the substrate, a larger process window, etc. Therefore, as used herein, the terms "optimizing" and "optimization" refer to or mean a process of identifying one or more values ​​of one or more parameters that provide an improvement (e.g., a local optimum) in at least one relevant indicator compared to an initial set of one or more values ​​for those one or more parameters. "Optimal" and other related terms should be interpreted accordingly. In an embodiment, the optimization step may be applied iteratively to provide further improvements in one or more indicators.

[0034] Further, the lithographic projection apparatus may be of a type having two or more stages (e.g. two or more substrate stages, a substrate stage and a measurement stage, two or more patterning device stages, etc.). In such a "multi-stage" apparatus, a plurality of stages may be used in parallel, or preparatory steps may be performed on one or more stages while one or more other stages are being used for exposure. A dual-stage lithographic projection apparatus is described, for example, in US 5,969,441, which is incorporated herein by reference.

[0035] The patterned device cited above includes or can form one or more design layouts. A CAD (computer-aided design) program can be used to generate the design layout, which is generally referred to as EDA (electronic design automation). Most CAD programs follow a predetermined set of design rules to create a functional design layout / patterned device. These rules are set by processing and design constraints. For example, the design rules define the spatial tolerances between circuit devices (such as gates, capacitors, etc.) or interconnects to ensure that the circuit devices or lines do not interact with each other in an undesirable manner. One or more design rule restrictions can be referred to as "critical dimensions" (CD). The critical dimension of a circuit can be defined as the minimum width of a line or hole or the minimum space between two lines or two holes. Therefore, CD determines the total size and density of the designed circuit. Of course, one of the goals in the preparation of integrated circuits is to faithfully reproduce the original circuit design (via patterned devices) on a substrate.

[0036] The term "mask" or "patterning device" as used herein may be broadly interpreted as referring to a general purpose patterning device that may be used to impart to an incoming radiation beam a patterned cross-section corresponding to the pattern to be created in a target portion of the substrate; in this context, the term "light valve" may also be used. In addition to classical masks (transmissive or reflective; binary, phase-shift, hybrid, etc.), examples of other such patterning devices include:

[0037] Programmable mirror array. An example of such a device is a matrix-addressable surface having a viscoelastic control layer and a reflective surface. The basic principle behind such an apparatus is that (for example) addressed areas of the reflective surface reflect incident radiation as diffracted radiation, while unaddressed areas reflect incident radiation as undiffracted radiation. Using appropriate filters, the undiffracted radiation can be filtered out of the reflected beam, leaving only the diffracted radiation; in this way, the beam is patterned according to the addressing pattern of the matrix-addressable surface. The required matrix addressing can be performed using suitable electronics. For example, more information about such a reflector array can be gleaned, for example, from U.S. Patent Nos. 5,296,891 and 5,523,193, which are incorporated herein by reference.

[0038] Programmable LCD Array An example of such a configuration is given in US Pat. No. 5,229,872, which is incorporated herein by reference.

[0039] As a brief introduction, Figure 1 An exemplary lithographic projection apparatus 10A is illustrated. The main components are a radiation source 12A, which may be a deep ultraviolet excimer laser source or other types of sources, including: an extreme ultraviolet (EUV) source (as discussed above, the lithographic projection apparatus itself does not require a radiation source); illumination optics, which define partial coherence (denoted as Σ) and may include optics 14A, 16Aa, and 16Ab that shape the radiation from source 12A; a patterning device 14A; and transmission optics 16Ac that projects an image of the patterning device pattern onto a substrate plane 22A. An adjustable filter or aperture 20A at a pupil plane of the projection optics may limit the range of beam angles that impinge on the substrate plane 22A, with the maximum possible angle defining the numerical aperture NA of the projection optics = nsin(Θ max ), n is the refractive index of the medium between the last element of the projection optics and the substrate, and θ max Is the maximum angle of the beam leaving the projection optics that can still impinge on the substrate plane 22A. The radiation from the radiation source 12A may not necessarily be a single wavelength. Instead, the radiation may be at a range of different wavelengths. The range of different wavelengths may be characterized by a quantity referred to as "imaging bandwidth", "source bandwidth" or simply "bandwidth", which are used interchangeably herein. A small bandwidth can reduce chromatic aberration and associated focusing errors of downstream components, including optics in the source (e.g., optics 14A, 16Aa, and 16Ab), patterning devices, and projection optics. However, this does not necessarily lead to a rule that bandwidth should never be expanded.

[0040] In the optimization process of the system, the quality factor of the system can be expressed as a cost function. The optimization process is reduced to the process of finding a set of parameters (design variables) of the system to optimize (e.g., minimize or maximize) the cost function. Depending on the goal of the optimization, the cost function can have any suitable form. For example, the cost function can be the weighted root mean square (RMS) of the deviation of certain characteristics (evaluation points) of the system relative to the expected values ​​(e.g., ideal values) of these characteristics; the cost function can also be the maximum value (i.e., the worst deviation) among these deviations. The term "evaluation point" herein should be broadly interpreted as including any characterization of the system. Due to the practicality of the implementation of the system, the design variables of the system can be limited to a limited range and / or interdependent. In the case of a lithographic projection device, constraints are usually associated with physical properties and characteristics of the hardware (such as tunable range and / or patterning equipment manufacturability design rules), and evaluation points can include physical points on the resist image on the substrate and non-physical characteristics (such as dose and focus).

[0041] In a lithographic projection apparatus, a source provides illumination (i.e., radiation) to a patterning device, and projection optics directs and shapes the illumination onto a substrate via the patterning device. The term "projection optics" is broadly defined here as including any optical component that can change the wavefront of a radiation beam. For example, projection optics may include at least some of components 14A, 16Aa, 16Ab, and 16Ac. An aerial image (AI) is a radiation intensity distribution at the substrate level. A resist layer on a substrate is exposed, and an aerial image is transferred to the resist layer as a potential "resist image" (RI) therein. A resist image (RI) may be defined as a spatial distribution of the solubility of a resist in a resist layer. A resist model may be used to calculate a resist image from an aerial image, an example of which may be found in U.S. Patent Application Publication No. US2009-0157360, the disclosure of which is incorporated herein by reference in its entirety. The resist model is only related to the characteristics of the resist layer (e.g., the effects of chemical processes occurring during exposure, PEB, and development). The optical properties of a lithographic projection apparatus, such as the properties of the source, the patterning device and the projection optics, define the aerial image. Since the patterning device used in a lithographic projection apparatus can be changed, it is desirable to separate the optical properties of the patterning device from the optical properties of the rest of the lithographic projection apparatus, including at least the source and the projection optics.

[0042] Figure 2An exemplary flow chart for modeling and / or simulating portions of a patterning process is illustrated in . As will be appreciated, models may represent different patterning processes, and need not include all of the models described below. Source model 200 represents an optical characterization of the illumination of a patterning device (including radiation intensity distribution, bandwidth, and / or phase distribution). Source model 200 may represent an optical characterization of the illumination, which includes, but is not limited to, numerical aperture settings, illumination sigma (σ) settings, and any particular illumination shape (e.g., off-axis radiation shapes, such as toroidal, quadrupole, dipole, etc.), where σ (or sigma) is the outer radial extent of the illuminator.

[0043] The projection optics model 210 represents an optical characterization of the projection optics (including changes in the radiation intensity distribution and / or phase distribution caused by the projection optics). The projection optics model 210 may represent an optical characterization of the projection optics, including aberrations, distortions, one or more refractive indices, one or more physical sizes, one or more physical dimensions, etc.

[0044] The patterning device / design layout model module 220 captures how design features are laid out in a pattern of a patterning device, and may include a representation of detailed physical properties of the patterning device, such as described in U.S. Pat. No. 7,587,704, which is incorporated herein by reference in its entirety. In an embodiment, the patterning device / design layout model module 220 represents an optical characterization of a design layout (e.g., a device design layout corresponding to features of an integrated circuit, memory, electronic device, etc.) (including changes in radiation intensity distribution and / or phase distribution caused by a given design layout), which is a representation of how features are arranged on or formed by a patterning device. Since the patterning device used in a lithographic projection apparatus can be changed, it is desirable to separate the optical properties of the patterning device from the optical properties of the rest of the lithographic projection apparatus, including at least the illumination and projection optics. The purpose of the simulation is typically to accurately predict, for example, edge placement and CD, which can then be compared to the device design. The device design is typically defined as a pre-OPC patterning device layout and will be provided in a standardized digital file format (such as GDSII or OASIS).

[0045] The aerial image 230 can be simulated from the source model 200, the projection optics model 210, and the patterning device / design layout model module 220. The aerial image (AI) is the radiation intensity distribution at the substrate level. The optical characteristics of the lithographic projection apparatus (e.g., the characteristics of the illumination, patterning device, and projection optics) dictate the aerial image.

[0046] The resist layer on the substrate is exposed by the aerial image, and the aerial image is transferred to the resist layer as a potential "resist image" (RI) therein. The resist image (RI) can be defined as the spatial distribution of the solubility of the resist in the resist layer. The resist image 250 can be simulated from the aerial image 230 using the resist model 240. The resist model can be used to calculate the resist image from the aerial image, and its example can be found in the U.S. Patent Application Publication No. US2009-0157360, the disclosure of which is incorporated herein by reference in its entirety. The resist model generally describes the influence of the chemical processes occurring during resist exposure, post-exposure baking (PEB) and development, so as to predict the profile of the resist features formed on the substrate, for example, and is therefore generally only related to such characteristics of the resist layer (e.g., the influence of the chemical processes occurring during exposure, post-exposure baking and development). In an embodiment, the optical properties of the resist layer (e.g., refractive index, film thickness, propagation and polarization effects) can be captured as part of the projection optical device model 210.

[0047] Thus, in general, the connection between the optical model and the resist model is the simulated aerial image intensity within the resist layer, which results from the projection of the radiation onto the substrate, refraction at the resist interface, and multiple reflections in the resist film stack. By absorbing the incident energy, the radiation intensity distribution (aerial image intensity) is transformed into a potential "resist image", which is further modified by diffusion processes and various loading effects. For full-chip applications, efficient simulation methods that are fast enough approximate the actual 3-dimensional intensity distribution in the resist stack by a 2-dimensional aerial (and resist) image.

[0048] In an embodiment, the resist image may be used as an input to the post-pattern transfer process model module 260. The post-pattern transfer process model module 260 defines the performance of one or more post-resist development processes (eg, etching, developing, etc.).

[0049] The simulation of the patterning process can, for example, predict the profile, CD, edge placement (e.g., edge placement error), etc. in the resist and / or etch image. Thus, the purpose of the simulation is, for example, to accurately predict, for example, edge placement of the printed pattern and / or aerial image intensity slope and / or CD, etc. These values ​​can be compared to the intended design to, for example, correct the patterning process, identify locations where defects are predicted to occur, etc. The intended design is typically defined as a pre-OPC design layout, which can be provided in a standardized digital file format (such as GDSII or OASIS) or other file format.

[0050] Thus, the model formulation describes most, if not all, of the physical and chemical processes in the overall process, and each of the model parameters desirably corresponds to a different physical or chemical effect. Thus, the model formulation sets an upper limit on how well the model can be used to simulate the overall manufacturing process.

[0051] The following paragraphs describe determining a local feature size (LFD) of a mask feature, determining an MRC violation based on the LFD, and updating a mask design based on the LFD to eliminate the MRC violation.

[0052] Typically, a mask may have thousands or even millions of mask features, and MRC may be performed on thousands or even millions of mask features. MRC may be performed on each of the mask features. The mask features may be any of a variety of shapes (e.g., curved mask features). In some embodiments, a detector may be used to determine MRC violations. A detector is a geometric structure of any size or shape that is configured to help detect MRC violations for mask features of various shapes. For example, a detector may be a circular detector that is configured to perform MRC on curved mask features of different curvature shapes and sizes (e.g., Figure 5A and 5B In some embodiments, the detector can be configured to detect MRC violations associated with the space between two mask features (e.g., Fig. 6A and 6B These detectors can help determine MRC violations based on LFD as described below.

[0053] Figure 3 is a block diagram of a system 300 for optimizing mask design based on LFD of mask features consistent with various embodiments. Figure 4 4 is a flow chart of a method 400 for performing MRC consistent with various embodiments. In process P402, LFD component 325 obtains mask design 305 having one or more mask features. In some embodiments, mask features (e.g., mask features 505) of mask design 305 are determined from a design layout by simulating a mask optimization process (e.g., SMO, OPC, etc.), thereby generating mask design 305. The design layout may correspond to features to be printed on a semiconductor chip.

[0054] In process P404, LFD component 325 places a detector on the edge or contour of a mask feature. Figure 5AAs illustrated, the LFD component 325 places the detector 510 within the mask feature 505 at a first position 515 on the edge of the mask feature 505. The detector 510 may have certain geometric properties configured to facilitate MRC detection. In some embodiments, the detector 510 is configured to be circular. In some embodiments, the mask feature 505 has a curved shape. In some embodiments, the MRC 335 may include one or more geometric properties associated with the mask feature 505. The geometric properties may include the minimum critical dimension (CD) or LFD of the mask feature that can be manufactured, the minimum curvature of the mask feature that can be manufactured, the minimum space between two features that can be manufactured, or the maximum CD or LFD of the mask feature that can be manufactured. In some embodiments, the LFD is the size or size of the mask feature at a specified point on the edge of the mask feature.

[0055] At process P406, LFD component 325 may change the size of detector 510 until the detector contacts another location of the mask feature. For example, LFD component 325 may increase (or decrease) the size of detector 510 until detector 510 contacts another location, such as second location 520 on the edge of mask feature 505, at which point detector 510 transitions to detector 530. LFD component 325 obtains LFD 310 as a function of the size of detector 530. For example, as Figure 5B As illustrated, LFD component 325 obtains LFD 310 as a function of radius 525 of detector 530. LFD 310 may indicate the size of a portion of mask feature 505 at first location 515. In some embodiments, Figure 5A and 5B The LFD 310 in can be referred to as an internal LFD because LFD 310 indicates the dimensions within the mask feature 505.

[0056] In some embodiments, the LFD component 325 may also determine an external LFD, which indicates the distance between two adjacent mask features, such as Fig. 6A and 6B As shown. For example, the LFD component 325 can place a detector 615 between the first mask feature 605 and the second mask feature 610. The detector 615 can be placed outside the first mask feature 605, at a first position 625 on the edge of the first mask feature 605. The LFD component 325 can change the size of the detector 615 until the detector 615 contacts any position on the edge of the second mask feature 610 (e.g., the second position 620), at which point the detector 615 is transformed into a detector 630. The LFD component 325 can obtain the LFD 310 as a function of the size of the detector 630. For example, the LFD component 325 obtains the LFD 310 as a function of the radius 635 of the detector 630. Figure 6B The LFD 310 in (also referred to as the outer LFD) may indicate a distance between the first mask feature 605 and the second mask feature 610 at the first position 625 .

[0057] At process P408, MRC violates component 350 based on the LFD detection MRC violation of mask features. In some embodiments, determining the occurrence of MRC violation can involve comparing the LFD of mask features with the LFD constraints specified in MRC 335. In some embodiments, when the geometric characteristics of mask features do not meet the constraints specified in MRC, MRC violation can occur. For example, when the LFD 310 of mask feature 505 is less than the minimum LFD or CD specified in MRC 335, MRC violation component 350 can detect MRC violation. In another example, when the LFD 310 of mask feature 505 exceeds the maximum LFD or CD specified in MRC 335, MRC violation component 350 can detect MRC violation. In yet another example, when the LFD 310 associated with first mask feature 605 is less than the minimum LFD or CD specified in MRC 335 or greater than the maximum LFD or CD, MRC violation component 350 can detect MRC violation. Figure 7 Detection of MRC violations of mask features based on LFD consistent with various embodiments is illustrated. In some embodiments, MRC 335 may specify constraints (such as minimum LFD 750 and maximum LFD 755) within which the LFD of the mask feature should be. When the LFD determined using detector 720 at a first position 715 is less than the minimum LFD 750, the MRC violation component 350 may detect an MRC violation of the mask feature 705. In another example, when the LFD of the mask feature 705 determined using detector 710 at a second position 725 exceeds the maximum LFD 755, the MRC violation component 350 may detect an MRC violation of the mask feature 705.

[0058] The MRC violation component 350 may also determine the extent of the MRC violation. In some embodiments, the extent of the MRC violation may be determined as the difference between the LFD of the mask feature corresponding to the position and the minimum or maximum LFD specified in the violated MRC 335. For example, if the LFD of the mask feature 705 at the second position 725 is determined to be 8 nm, and the maximum LFD 755 specified in the MRC is 5 nm, the MRC violation component 350 may determine the extent of the violation as 3 nm (8 nm - 5 nm), i.e., the difference between the LFD of the mask feature 705 at the second position 725 and the maximum LFD 755.

[0059] The MRC violation component 350 can output MRC violation data 315, which includes MRC violation information of the mask feature (such as the location where the violation occurred, the type of violation that occurred (e.g., minimum or maximum LFD violation), the LFD at that location, the degree of violation, etc.). For example, referring to Figure 7 , the MRC violation data 315 may include information such as the position coordinates of the first position 715, the minimum LFD violation as the violation type, 3nm as the LFD at the first position 715, and 2nm as the MRC violation degree of the first MRC violation at the first position 715 (for example, considering that the minimum LFD 750 is 1nm). Similarly, for the second MRC violation at the second position 725, the MRC violation data 315 may include information such as the position coordinates of the second position 725, the maximum LFD violation as the violation type, 8nm as the LFD at the second position 725, and 3nm as the MRC violation degree (for example).

[0060] In some embodiments, MRC violation data 315 (e.g., LFD information) can be used to improve mask design by eliminating (e.g., or minimizing) MRC violations. Mask design component 375 can be configured to use cost function 340 to eliminate MRC violations when adjusting the design (e.g., shape or size) of mask features. For example, cost function 340 can indicate a penalty associated with a mask feature that violates MRC 335. In some embodiments, cost function 340 can be determined as a LFD function of a mask feature.

[0061] Fig. 8A The determination of a cost function for LFD based on mask features consistent with various embodiments is illustrated. Figure 4 As described, the LFD of the mask feature at a specified position can be a function of the radius of the detector placed on the edge at the specified position, and its size is adjusted so that it contacts one or more other positions of the mask feature. For example, the LFD of a portion of the mask feature 805 at position 820 can be determined as the radius 815 of the detector 810 positioned at position 820, so that the detector 810 also contacts one or more other points on the edge of the mask feature 805 and is still within the mask feature 805. That is, if the radius 815 is depicted as r, then the kernel function can be depicted as f(r). The kernel function can take any form. For example, as the difference between the actual LFD and the minimum or maximum LFD increases, the kernel function can grow exponentially. Figure 8BA graph depicting an example form of a kernel function consistent with various embodiments is shown. In graph 800, considering the x-axis as LFD values ​​and the y-axis as kernel function values, a first curve 840 indicates that as the LFD continues to decrease beyond the minimum LFD 750, the kernel function value increases exponentially, and similarly, a second curve 835 indicates that as the LFD continues to increase beyond the maximum LFD 755, the kernel function value increases exponentially. Thus, the kernel function f(r) may take any mathematical form that satisfies the above conditions depicted in graph 800.

[0062] In some embodiments, cost function 340 may be determined as an integral of a kernel function along a contour, curve, or edge of mask feature 805. For example, cost function 340I may be depicted as:

[0063] I=∫f(r)ds...Equation (1A)

[0064] where ds is the length of the edge segment that determines the kernel function.

[0065] In some embodiments, a gradient 342 of the cost function 340 may also be determined. The gradient 432 (i.e., the derivative of the cost function 340) may be used with the cost function 340 to adjust or update the mask feature to eliminate the MRC violation. In some embodiments, given the mask feature, the cost function 340 may determine the possible degree of penalty, and the gradient 342 may determine the manner or degree of change of the cost function 340 (e.g., the penalty) when the mask feature changes in a particular manner (e.g., the shape or size of the mask feature changes). As described below, in some embodiments, the gradient 342 may be determined based on at least one of the cost function, the LFD, or the geometry of the mask feature.

[0066] Figure 8C The determination of the gradient of the cost function consistent with various embodiments is illustrated. The figure shows a portion of a mask feature 805 and a detector 810 for determining the LFD of the mask feature 805 at a position P. The gradient density function g(C) may be determined as follows:

[0067]

[0068] Where κ is the curvature and can be determined as dθ / ds, as illustrated in Example 875; α is the normal direction and the conjugate point The angle between the directions, ds is the segment length, r is the radius or LFD as defined, and f'(r) is the derivative of the kernel function f(r).

[0069] The gradient 342 may be determined as:

[0070]

[0071] where v i is the ith variable, and δl is the mask bias.

[0072] Fig. 9 900 is a flow chart of a method 900 for optimizing a mask design based on LFD of a mask feature consistent with various embodiments. In process P902, LFD component 325 may obtain LFD of a mask feature. For example, LFD component 325 may obtain LFD 310 of mask feature 505, as at least referring to Figure 4 In some embodiments, the LFD is determined as a function of the size of the detector used to determine the LFD (e.g., a function of the radius of the circular detector). For example, the LFD 310 may be determined as Figure 5B A function of radius 525 of the illustrated detector 530. In some embodiments, a mask design may be generated by simulating a mask optimization process (e.g., SMO, OPC, etc.) using the design layout to determine mask features of the mask design. The design layout may correspond to features to be printed on a substrate.

[0073] In process P904, MRC violation component 350 can determine the MRC violation of mask features based on LFD. In some embodiments, when the geometric characteristics of the mask features do not meet the constraints specified in MRC, MRC violation can occur. For example, as described in process P408 of at least reference method 400, when the LFD 310 of mask feature 505 is less than the minimum LFD specified in MRC or greater than the maximum LFD specified in MRC, MRC violation component 350 can detect MRC violation. MRC violation component 350 can output MRC violation data 315, which includes MRC violation information of mask features (such as the position of the mask feature where the violation occurs, the type of violation (such as minimum or maximum LFD violation), LFD at the position, degree of violation, etc.).

[0074] In process P906, mask design component 375 can optimize (e.g., adjust mask features) mask features based on LFD to eliminate or reduce MRC violations, thereby generating an adjusted, updated, or optimized mask design. For example, mask design component 375 can obtain cost function 340 and gradient 342 of cost function 340 based on LFD associated with mask feature 705 (e.g., as at least referenced Figures 8A to 8C), the cost function 340 indicates a penalty associated with a mask feature that violates the MRC, and the mask feature 705 (e.g., the shape, size, or other geometry of the mask feature) is adjusted or updated to reduce the cost function 340 using the gradient 342. The mask design component 375 can then verify the updated mask design using the MRC 335 to determine whether the updated mask feature 705 still violates the MRC 335 (e.g., if the LFD of the updated mask feature violates the LFD specified in the MRC 335). In some embodiments, the mask design component 375 can also verify the imaging parameters of the updated mask design using the imaging constraints 330 to determine whether any of the imaging constraints are violated. Some of the imaging parameters may include image log slope (ILS), edge placement error (EPE), depth of focus (DOF), etc. The imaging parameters can be obtained in various ways, such as from using at least a reference Figure 2 The mask design component 375 may further update the mask features 705. The mask design component 375 may continue to update the mask features 705 until the specified criteria are met. For example, the specified criteria may include a predefined number of iterations for updating the mask features. In another example, the specified criteria may include updating the mask features 705 until the cost function 340 or the gradient 342 is minimized.

[0075] In some embodiments, adjusting, updating, or optimizing a mask design may involve (a) simulating a mask optimization process using a design layout to determine mask features of the mask design; (b) determining, via a detector, portions of the mask features that violate MRC 335 (e.g., as discussed with respect to method 400); and (c) in response to violating MRC 335, modifying corresponding portions of the mask features to satisfy MRC 335; and repeating steps (a) to (c).

[0076] In some embodiments, the above process may be performed on one or more mask features in the mask design that violate MRC 335. After the optimization process is complete, mask design component 375 may output an updated mask design 345 in which the MRC violations are eliminated or minimized.

[0077] In some embodiments, the mask optimization process may involve a mask-only optimization process, a source mask optimization (SMO) process, or an optical proximity correction (OPC) process. Figures 10 to 13 An example mask design process including OPC is discussed. In some embodiments, the OPC process can be adapted to include MRC violation checking using the detectors discussed herein (e.g. Figures 5A to 6B). In some embodiments, a check may be performed after a certain number of iterations, at the end of the OPC process, or at other points in the simulation. After modifying the mask features that violate the MRC 335, the OPC process may be repeated to ensure that the cost function associated with the OPC remains valid or within the desired limits. In this way, the mask features obtained after the OPC simulation process will not only meet the MRC, but also meet the design specifications associated with the cost function.

[0078] Relative to Figures 10 to 13 An example of a mask optimization process including an OPC process is discussed in further detail. In some embodiments, the mask optimization process involves calculating a cost function as a function of parameters associated with the lithography process and the mask. For example, mask features can be represented as design variables, as discussed herein. These design variables will be affected by changes in MRC violations detected based on the detector.

[0079] According to the present disclosure, combinations and sub-combinations of the disclosed elements constitute separate embodiments. For example, a first combination includes obtaining a detector and determining an MRC violation associated with a mask feature. A sub-combination may include a detector based on a specific closed shape and size of the mask feature, wherein an MRC violation occurs when a portion of the mask feature is inside the detector. In another sub-combination, the detector may be circular or non-circular in shape. In another example, the combination includes determining a mask design based on an MRC violation identified by the detector. A detector with a non-circular shape detects width, space, and / or curvature violations.

[0080] As an example, in the photolithography process, the cost function can be expressed as

[0081]

[0082] where (z1, z2, …, z N ) are N design variables or their values. p (z1,z2,…·,z N ) can be the design variables (z1, z2, …, z N ), such as (z1, z2, …, z N ) is the difference between the actual value and the expected value at the evaluation point of the value set of the design variable. p is with f p (z1,z2,…,z N ) is associated with a weight constant. A higher w may be assigned to an evaluation point or pattern that is more critical than other evaluation points or patterns. p Patterns and / or evaluation points that appear in greater numbers may also be assigned higher values ​​of w pExamples of evaluation points may be any physical point or pattern on the substrate, any point on the virtual design layout, or a resist image, or an aerial image, or a combination thereof. CF(z1, z2, ..., z N ) can be a function of the radiation source, a function of the radiation source, or a function of a variable that affects the radiation source. Of course, CF(z1, z2, ..., z N ) is not limited to the form in equation 1. CF(z1, z2, ..., z N ) may be in any other suitable form.

[0083] The cost function may represent any one or more suitable characterizations of the lithographic projection apparatus, the lithographic process, or the substrate (e.g., focus, CD, image shift, image distortion, image rotation, random variation, throughput, local CD variation, process window, or a combination thereof). In one embodiment, the design variables (z1, z2, ..., z N ) include one or more selected from dose, global bias of the patterning device and / or irradiation shape. In one embodiment, the design variables (z1, z2, ..., z N ) includes the bandwidth of the source. Since the resist image generally defines the pattern on the substrate, the cost function may include a function representing one or more characteristics of the resist image. For example, f of such an evaluation point p (z1,z2,…,z N ) can simply be the distance between a point in the resist image and the expected position of that point (i.e., the edge placement error EPE p (z1,z2,…,z N )). Design variables can include any adjustable parameters, such as adjustable parameters of the source (e.g., intensity and shape), patterning equipment, projection optics, dose, focus, etc.

[0084] The lithographic apparatus may include components collectively referred to as "wavefront manipulators", which may be used to adjust the shape of the wavefront and the intensity distribution and / or phase shift of the radiation beam. In an embodiment, the lithographic apparatus may adjust the wavefront and intensity distribution at any position along the optical path of the lithographic projection apparatus, such as before the patterning device, near the pupil plane, near the image plane and / or near the focal plane. The wavefront manipulator may be used to correct or compensate for certain distortions of the wavefront and intensity distribution and / or phase shift caused by, for example, temperature changes in the source, patterning device, lithographic projection apparatus, thermal expansion of components of the lithographic projection apparatus, etc. Adjusting the wavefront and intensity distribution and / or phase shift may change the value of the evaluation point and the cost function. Such changes may be simulated from a model or actually measured.

[0085] Design variables can have constraints, which can be expressed as (z1, z2, …, z N)∈Z, where Z is a set of possible values ​​for the design variables. One possible constraint on the design variables can be imposed by the desired throughput of the lithographic projection apparatus. In the absence of such a constraint imposed by the desired throughput, the optimization can produce an unrealistic set of values ​​for the design variables. For example, if dose is a design variable, in the absence of such a constraint, the optimization can produce dose values ​​that make the throughput economically impossible. However, the usefulness of a constraint should not be interpreted as a necessity. For example, throughput can be affected by pupil fill rate. For some irradiation designs, a low pupil fill rate can discard radiation, resulting in lower throughput. Throughput can also be affected by resist chemistry. Slower resists (e.g., resists that require a higher amount of radiation to be properly exposed) result in lower throughput. In an embodiment, the constraints on the design variables are such that the design variables cannot have values ​​that change any geometric characterization of the patterning device, i.e., the pattern on the patterning device will remain unchanged during optimization.

[0086] Therefore, the optimization process is performed under the constraints (z1, z2, ..., z N )∈Z to find the set of values ​​of one or more design variables that optimize the cost function, for example:

[0087]

[0088] Fig.10A general method of optimization according to an embodiment is shown in . The method includes a step S302 of defining a multivariate cost function for a plurality of design variables. The design variables may include any suitable combination selected from design variables representing one or more characterizations of the illumination (300A) (e.g., pupil fill rate, i.e., the percentage of the illuminated radiation that passes through the pupil or aperture), one or more characterizations of the projection optics (300B), and / or one or more characterizations of the design layout (300C). For example, the design variables may include design variables representing one or more characterizations of the illumination (300A) (e.g., being or including bandwidth) and one or more characterizations of the design layout (300C) (e.g., global bias) but not representing one or more characterizations of the projection optics (300B), which results in optimization of the illumination patterning device (e.g., mask) ("source mask optimization" or SMO). Alternatively, the design variables may include design variables representing one or more characterizations of the illumination (300A) (optionally polarized), the projection optics (300B), and the design layout (300C), which results in an illumination patterning device (e.g., mask)-projection system (e.g., lens) optimization ("source-mask-lens optimization" or SMLO). Alternatively, the design variables may include design variables representing one or more characterizations of the illumination (300A) (e.g., being or including bandwidth), one or more non-geometric characterizations of the patterning device, or one or more characterizations of the projection optics (300B), but not including any geometric characterizations of the patterning device. In step S304, the design variables are adjusted simultaneously so that the cost function moves toward convergence. In an embodiment, not all design variables may be adjusted simultaneously. Each design variable may also be adjusted individually. In step S306, it is determined whether a predefined termination condition is met. The predetermined termination condition may include various possibilities, such as one or more selected from the following: as required by the numerical technique used, the cost function is minimized or maximized, the value of the cost function is equal to a threshold or crosses a threshold, the value of the cost function reaches within a preset error limit, and / or a preset number of iterations is reached. If the conditions in step S306 are met, the method ends. If one or more conditions in step S306 are not met, steps S304 and S306 are iteratively repeated until the desired result is obtained. Optimization does not necessarily result in a single set of values ​​for one or more design variables, as there may be physical limitations caused by factors such as pupil fill factor, resist chemistry, throughput, etc. Optimization may provide multiple sets of values ​​for one or more design variables and associated performance characteristics (e.g., throughput), and allow a user of the lithographic apparatus to pick one or more sets.

[0089] Different subsets of design variables (e.g., a subset that includes characterizations of the illumination, a subset that includes characterizations of the patterning device, and a subset that includes characterizations of the projection optics) can be optimized alternatively (referred to as alternative optimization) or simultaneously (referred to as simultaneous optimization). Thus, two subsets of design variables that are optimized "simultaneously" or "jointly" means that the design variables of the two subsets are allowed to be changed simultaneously. As used herein, two subsets of design variables that are optimized "alternatively" means that the design variables of a first subset, but not a second subset, are allowed to be changed in a first optimization, and then the design variables of the second subset, but not the first subset, are allowed to be changed in a second optimization.

[0090] exist Fig.10 In this case, the optimization of all design variables is performed simultaneously. This process can be called a simultaneous process or a joint optimization process. Alternatively, the optimization of all design variables is performed alternately, such as Fig.11 In this process, in each step, some design variables are fixed while other design variables are optimized to optimize the cost function; then in the next step, a different set of variables is fixed while other items are optimized to minimize or maximize the cost function. These steps are performed alternately until convergence or some termination condition is met. Fig.11 As shown in the non-limiting example flow chart of , a design layout is first obtained (step S402), and then an illumination optimization step is performed in step S404, wherein one or more design variables of the illumination (e.g., bandwidth) are optimized (SO) to minimize or maximize the cost function, while the other design variables are fixed. Then in the next step S406, a projection optics optimization (LO) is performed, wherein the design variables of the projection optics are optimized to minimize or maximize the cost function, while the other design variables are fixed. These two steps are performed alternately until certain termination conditions are met in step S408. One or more various termination conditions (such as the value of the cost function becomes equal to a threshold, the value of the cost function crosses a threshold, the value of the cost function reaches a preset error limit, a preset number of iterations is reached, etc.) can be used. It should be noted that SO-LO alternating optimization is used as an example of an alternating process. As another example, a first illumination-patterning device co-optimization (SMO) or an illumination-patterning device-projection optics co-optimization (SMLO) can be performed without allowing bandwidth changes, followed by a second SO or illumination-projection optics co-optimization (SLO) that allows bandwidth changes. Finally, in step S410, an output of the optimization result is obtained and the process stops.

[0091] As previously discussed, the pattern selection algorithm can be integrated with simultaneous or alternating optimization. For example, when alternating optimization is employed, first the full chip SO can be performed, one or more 'hot spots' and / or 'warm spots' are identified, and then the LO is performed. In view of the present disclosure, many permutations and combinations of sub-optimizations are possible in order to achieve the desired optimization results.

[0092] Fig. 12A An exemplary optimization method is shown in which a cost function is minimized or maximized. In step S502, initial values ​​of one or more design variables including one or more associated tuning ranges, if any, are obtained. In step S504, a multivariate cost function is set. In step S506, the cost function is expanded within a sufficiently small neighborhood around the starting point value of the one or more design variables for the first iteration step (i=0). In step S508, standard multivariate optimization techniques are applied to the cost function. It should be noted that constraints (such as one or more tuning ranges) may be applied to the optimization problem during the optimization process in S508 or at a later stage in the optimization process. Step S520 indicates that each iteration is performed for one or more given test patterns (also referred to as "gauges") of identified evaluation points that have been selected to optimize the lithography process. In step S510, the lithography response is predicted. In step S512, the results of step S510 are compared with the expected or ideal lithography response values ​​obtained in step S522. If the termination condition is met in step S514, that is, the optimization generates a lithographic response value that is close enough to the expected value, then the final value of the design variable is output in step S518. The output step may also include outputting one or more other functions using the final value of the design variable, such as outputting a wavefront aberration adjustment map at the pupil plane (or other plane), an optimized illumination map, and / or an optimized design layout. If the termination condition is not met, then in step S516, the value of one or more design variables is updated using the result of the i-th iteration, and the process returns to step S506. The following is explained in detail. Fig. 12A process.

[0093] In the exemplary optimization process, in addition to f p (z1,z2,…,z N ) is sufficiently smooth (e.g., there is a first-order derivative (n=1, 2, ..., N)), which is generally valid in a lithographic projection apparatus and does not assume or approximate the design variables (z1, z2, ..., z N ) and f p (z1,z2,…,z N). Algorithms such as Gauss-Newton, Levenberg-Marquardt, Broyden-Fletcher-Goldfarb-Shanno, gradient descent, simulated annealing, interior point, and genetic algorithms can be applied to find

[0094] Here, the Gauss-Newton algorithm is used as an example. The Gauss-Newton algorithm is an iterative method suitable for general nonlinear multivariable optimization problems. In the i-th iteration, the design variables (z1, z2, ..., z N ) take (z 1i 、z 2i , …, z Ni ) value, the Gauss-Newton algorithm is in (z 1i 、z 2i , …, z Ni ) is linearized near f p (z1,z2,…,z N ), and then calculates to give CF(z1, z2, ..., z N ) of the minimum value (z 1i 、z 2i , …, z Ni ) near the value (z 1(i+1) 、z 2(i+1) , …, z N(i+1) ). Design variables (z1, z2, …, z N ) takes (z 1(i+1) 、z 2(i+1) , …, z N(i+1) ) value. This iteration continues until convergence (i.e., CF(z1, z2, …, z N ) is no longer reduced further) or reaches a preset number of iterations.

[0095] In particular, in the i-th iteration, in (z 1i 、z 2i , …, z Ni )nearby,

[0096]

[0097] Under the approximation of Equation 3, the cost function becomes:

[0098]

[0099] It is the design variable (z1, z2, ..., z N ). Except for the design variables (z1, z2, …, z N), each term is a constant.

[0100] If the design variables (z1, z2, ..., z N ) is not under any constraints, then (z 1(i+1) 、z 2(i+1) ,…,z N(i+1) ) can be derived by solving N linear equations: Where n=1, 2, ..., N.

[0101] If the design variables (z1, z2, ..., z N ) in the form of J inequality (e.g. (z1, z2, …, z N ) tuning range j = 1, 2, ..., J; and if in K equations (e.g., interdependencies between design variables) Under the constraints of k = 1, 2, ..., K, the optimization process becomes a classic quadratic programming problem, where A nj , B j , C nk , D k is a constant. Additional constraints can be imposed at each iteration. For example, a “damping factor” Δ D To limit (z 1(i+1) 、z 2(i+1) ,…,z N(i+1) ) and (z 1i 、z 2i ,…,z Ni ), so that the approximation to Equation 3 holds. This constraint can be expressed as z ni -Δ D ≤z n ≤z ni +Δ D . (z 1(i+1) 、z 2(i+1) ,…,z N(i+1) ), which can be derived using, for example, the method described by Jorge Nocedal and Stephen J. Wright in Numerical Optimization (2nd Edition) (Cambridge University Press, Berlin Vandenberghe, New York).

[0102] The optimization process is not to minimize f p (z1,z2,…, z N), but rather the magnitude of the maximum deviation (worst defect) between the evaluation points can be minimized to its expected value. In this approach, the cost function can be alternatively expressed as

[0103]

[0104] Among them, CLp Yes p (z1,z2,…,z N ). The cost function represents the worst defect among the evaluation points. The optimization using the cost function minimizes the magnitude of the worst defect. An iterative greedy algorithm can be used for the optimization.

[0105] The cost function of Equation 5 can be approximated as:

[0106]

[0107] Where q is an even positive integer such as at least 4 or at least 10. Equation 6 mimics the behavior of Equation 5 while allowing the optimization to be performed analytically and accelerated using methods such as the deepest descent method, the conjugate gradient method, and the like.

[0108] Minimizing the worst defect size can also be done with f p (z1,z2,…,z N ). In particular, f p (z1,z2,…,z N ) is approximated as shown in Equation 3. Then, the constraint on the worst defect size is written as the inequality E Lp ≤f p (z1,z2,…,z N )≤E Up , where E Lp and E Up Is to specify f p (z1,z2,…,z N ) are two constants for the minimum and maximum allowable deviations. Inserting into equation 3, for p = 1, ... P, these constraints are transformed into,

[0109]

[0110] as well as

[0111]

[0112] Since Equation 3 is usually only valid for (z1, z2, …, z N ) is valid near this location, where the desired constraint E cannot be achieved. Lp ≤f p (z1,z2,…,z N )≤E Up In the case of , this can be determined by any conflicts in the inequalities, and the constant E can be relaxed Lp and E Up , until the constraints are achievable. This optimization process makes (z1, z2, …, z N), the worst defect size around i is minimized. Each step then progressively reduces the worst defect size, and each step is iterated until some termination condition is met. This results in an optimal reduction in the worst defect size.

[0113] Another way to minimize the worst-case defect is to adjust the weight w in each iteration p For example, after the i-th iteration, if the r-th evaluation point is the worst defect, then w can be increased in the (i+1)-th iteration. r , so that the reduction of the defect size at this evaluation point is given higher priority.

[0114] In addition, the cost functions in Equations 4 and 5 can be modified by introducing Lagrange multipliers to achieve a trade-off between optimization on the RMS of defect size and optimization on the worst defect size, i.e.,

[0115]

[0116] Where λ is a preset constant that specifies the tradeoff between optimization over the RMS of defect size and optimization over the worst defect size. In particular, if λ=0, then this becomes Equation 4, and only the RMS of defect size is minimized; while if λ=1, then this becomes Equation 5, and only the worst defect size is minimized; if 0<λ<1, then both are considered in the optimization. This optimization can be solved using a variety of methods. For example, the weights in each iteration can be adjusted, similar to the one described previously. Alternatively, similar to minimizing the worst defect size from inequalities, the inequalities of Equations 6' and 6" can be viewed as constraints on the design variables during the solution of the quadratic programming problem. Then, the bounds on the worst defect size can be incrementally relaxed, or the weights of the worst defect size can be incrementally increased, the cost function values ​​for each achievable worst defect size are calculated, and the design variable values ​​that minimize the total cost function are selected as the initial point for the next step. By doing this iteratively, minimization of this new cost function can be achieved.

[0117] Optimizing the lithography projection apparatus can expand the process window. A larger process window provides greater flexibility for process design and chip design. The process window can be defined as, for example, focus set, dose, aberration, laser bandwidth (e.g., E95 or (λmin to λmax)) and a cost specified for an intensity value, where the resist image is within a certain limit of the design target of the resist image. It should be noted that all methods discussed herein can also be extended to a generalized process window definition, which can be established by different or additional basic parameters than exposure dose and defocus. These may include, but are not limited to, optical settings (such as NA, sigma, aberration, polarization, or optical constants of the resist layer). For example, as described earlier, if the process window (PW) also includes different patterning device pattern biases (mask biases), then the optimization includes minimization of the mask error enhancement factor (MEEF), which is defined as the ratio of the substrate edge placement error (EPE) to the induced patterning device pattern edge bias. In the present disclosure, the process window defined on the focus and dose values ​​is used only as an example.

[0118] The following describes a method for maximizing a process window using, for example, dose and focus as its parameters according to an embodiment. In a first step, starting from the known conditions (f0, ε0) in the process window, where f0 is the nominal focus and ε0 is the nominal dose, one of the cost functions in the vicinity (f0±Δf, ε0±ε) is minimized:

[0119]

[0120] or

[0121]

[0122] or

[0123]

[0124] If the nominal focus f0 and the nominal dose ε0 are allowed to shift, they can be related to the design variables (z1, z2, ..., z N ) joint optimization. In the next step, if (z1, z2, …, z N , f, ε) such that the cost function is within preset limits, then (f0±Δf,ε0±ε) is accepted as part of the process window.

[0125] If focus and dose shifts are not allowed, the design variables (z1, z2, ..., z N In an alternative embodiment, if (z1, z2, ..., z N) such that the cost function is within preset limits, then (f0±Δf,ε0±ε) is accepted as part of the process window.

[0126] The methods described earlier in this disclosure can be used to minimize the corresponding cost functions of Eq. 7, Eq. 7', or Eq. 7". If the design variables represent one or more characteristics of the projection optics (such as Zernike coefficients), then minimizing the cost function of Eq. 7, Eq. 7', or Eq. 7" results in maximizing the process window based on projection optics optimization (i.e., LO). If, in addition to the characteristics of the projection optics, the design variables also represent one or more characteristics of the illumination and patterning devices, then minimizing the cost function of Eq. 7, Eq. 7', or Eq. 7" results in maximizing the process window based on SMLO, such as Fig.10 If the design variables represent one or more characteristics of the source and the patterning device, then minimizing the cost function of Equation 7, Equation 7', or Equation 7" results in maximizing the SMO-based process window. The cost function of Equation 7, Equation 7', or Equation 7" may also include at least one f p (z1,z2,…,z N ) (a function of bandwidth, such as described herein).

[0127] Fig.13 A specific example of how a simultaneous SMLO process can use gradient-based optimization (e.g., a quasi-Newton or Gauss-Newton algorithm) is shown. In step S702, starting values ​​for one or more design variables are identified. The tuning range for each variable can also be identified. In step S704, a cost function is defined using one or more design variables. In step S706, the cost function is expanded around the starting values ​​of all evaluation points in the design layout. In step S708, appropriate optimization techniques are applied to minimize or maximize the cost function. In optional step S710, a full-chip simulation is performed to cover all critical patterns in the full-chip design layout. The expected lithography response indicators (such as CD, EPE, or EPE and PPE) are obtained in step S714 and compared with the predicted values ​​of those quantities in step S712. In step S716, the process window is determined. Steps S718, S720, and S722 are similar to relative Fig. 12A The corresponding steps S514, S516 and S518 are described. As mentioned before, the final output may be, for example, a wavefront aberration map in the pupil plane, which is optimized to produce the desired imaging performance. The final output may be, for example, an optimized illumination map and / or an optimized design layout.

[0128] Fig. 12B An exemplary method for optimizing a cost function is shown, where the design variables (z1, z2, ..., z N) includes design variables that can assume only discrete values.

[0129] The method begins by defining pixel groups for illumination and patterned device tiles for patterned devices (step S802). In general, pixel groups or patterned device tiles may also be referred to as subdivisions of a lithography process component. In one exemplary method, illumination is divided into "117" pixel groups, and 94 patterned device tiles are defined for the patterned device, substantially as described above, resulting in a total of 211 subdivisions.

[0130] In step S804, a lithography model is selected as the basis for the lithography simulation. The results generated by the lithography simulation are used to calculate one or more lithography indicators or responses. Specific lithography indicators are defined as performance indicators to be optimized (step S806). In step S808, initial (pre-optimization) conditions for the irradiation and patterning devices are set. The initial conditions include the initial state of the irradiated pixel group and the patterning device block of the patterning device, so the initial irradiation shape and the initial patterning device pattern can be referenced. The initial conditions may also include patterning device pattern bias (sometimes referred to as mask bias), NA and / or focus slope range. Although steps S802, S804, S806 and S808 are depicted as sequential steps, it should be understood that in other embodiments, these steps may be performed in other sequences.

[0131] In step S810, the pixel groups and patterned device tiles are ranked. The pixel groups and patterned device tiles may be interleaved in the ranking. Various ranking methods may be used, including: sequentially (e.g., from pixel group "1" to pixel group "117" and from patterned device tile "1" to patterned device tile 94), randomly, based on the physical location of the pixel groups and patterned device tiles (e.g., ranking pixel groups closer to the center of the irradiation higher), and / or based on the degree to which changes to the pixel groups or patterned device tiles affect the performance indicators.

[0132] Once the pixel groups and patterned device tiles are graded, the illumination and patterned devices are adjusted to improve the performance index (step S812). In step S812, each of the pixel groups and patterned device tiles is analyzed in the order of the grades to determine whether the change of the pixel group or patterned device tile will result in an improved performance index. If it is determined that the performance index will be improved, the pixel group or patterned device tile is changed accordingly, and the resulting improved performance index and the modified illumination shape or modified patterned device pattern form a baseline for comparison, which is used for subsequent analysis of the lower graded pixel groups and patterned device tiles. In other words, the change to improve the performance index is retained. As the changes to the status of the pixel groups and patterned device tiles are made and retained, the initial illumination shape and the initial patterned device pattern are changed accordingly, so that the modified illumination shape and the modified patterned device pattern are generated by the optimization process in step S812.

[0133] In other approaches, patterning device polygon shape adjustment and paired polling of pixel groups and / or patterning device tiles are also performed within the optimization process of S812 .

[0134] In an embodiment, the staggered simultaneous optimization procedure may include changing the set of pixels that are illuminated, and if an improvement in the performance metric is found, the dose or intensity is stepped up and / or down to look for further improvements. In yet another embodiment, the stepwise increase and / or decrease of the dose or intensity may be replaced by a bias change of the patterning device pattern to look for further improvements in the simultaneous optimization procedure.

[0135] In step S814, a determination is made as to whether the performance metric has converged. For example, if little or no improvement to the performance metric has been demonstrated in the last few iterations of steps S810 and S812, then the performance metric may be considered to have converged. If the performance metric has not converged, then the steps of S810 and S812 are repeated in the next iteration, with the modified illumination shape and modified patterning device from the current iteration being used as the initial illumination shape and initial patterning device for the next iteration (step S816).

[0136] The above optimization method can be used to increase the throughput of the lithographic projection apparatus. For example, the cost function may include f p (z1,z2,…,z N ) (i.e., a function of exposure time). In an embodiment, the optimization of such a cost function is constrained or influenced by a measure of bandwidth or other indicators.

[0137] Fig.141 is a block diagram illustrating a computer system 100 that can assist in implementing the optimization methods and processes disclosed herein. The computer system 100 can be used to implement any of the entities, components, modules, or services depicted in the examples of the accompanying drawings (as well as any other entities, components, modules, or services described in this specification). The computer system 100 can be programmed to execute computer program instructions to perform the functions, methods, processes, or services described herein (e.g., of any entity, component, or module). The computer system 100 can be programmed to execute computer program instructions through at least one of software, hardware, or firmware.

[0138] The computer system 100 includes a bus 102 or other communication mechanism for communicating information and a processor 104 (or multiple processors 104 and 105) coupled to the bus 102 for processing information. The computer system 100 also includes a main memory 106 (such as a random access memory (RAM) or other dynamic storage device) coupled to the bus 102 for storing information and instructions to be executed by the processor 104. The main memory 106 may also be used to store temporary variables or other intermediate information during the execution of instructions to be executed by the processor 104. The computer system 100 also includes a read-only memory (ROM) 108 or other static storage device coupled to the bus 102 for storing static information and instructions for the processor 104. A storage device 110 (such as a magnetic or optical disk) is provided and coupled to the bus 102 for storing information and instructions.

[0139] The computer system 100 may be coupled to a display 112, such as a cathode ray tube (CRT) or a flat panel or touch pad display, via the bus 102 for displaying information to a computer user. An input device 114 including alphanumeric and other keys is coupled to the bus 102 for communicating information and command selections to the processor 104. Another type of user input device is a cursor control 116, such as a mouse, trackball, or cursor direction keys, for communicating direction information and command selections to the processor 104 and controlling cursor movement on the display 112. The input device typically has two degrees of freedom in two axes, a first axis (e.g., x) and a second axis (e.g., y), which allows the device to specify a position in a plane. A touch pad (screen) display may also be used as an input device.

[0140] According to one embodiment, portions of the optimization process may be performed by computer system 100 in response to processor 104 executing one or more sequences of one or more instructions contained in main memory 106. Such instructions may be read into main memory 106 from another computer-readable medium, such as storage device 110. Execution of the sequences of instructions contained in main memory 106 causes processor 104 to perform the process steps described herein. One or more processors in a multi-processing arrangement may also be employed to execute the sequences of instructions contained in main memory 106. In alternative embodiments, hard-wired circuitry may be used in place of or in combination with software instructions. Therefore, the description herein is not limited to any specific combination of hardware circuitry and software.

[0141] The term "computer-readable medium" as used herein refers to any medium that participates in providing instructions for execution to processor 104. Such media can take many forms, including but not limited to non-volatile media, volatile media, and transmission media. Non-volatile media include, for example, optical or magnetic disks (such as storage device 110). Volatile media include dynamic memory (such as main memory 106). Transmission media include coaxial cables, copper wires, and optical fibers, including the wires that make up bus 102. Transmission media can also take the form of sound waves or light waves, such as those generated during radio frequency (RF) and infrared (IR) data communications. Common forms of computer-readable media include, for example, floppy disks, foldable disks, hard disks, magnetic tape, any other magnetic media, CD-ROMs, DVDs, any other optical media, punch cards, paper tape, any other physical media with a pattern of holes, RAM, PROMs and EPROMs, flash EPROMs, any other memory chips or memory cartridges, carrier waves described below, or any other media from which a computer can read.

[0142] Various forms of computer readable media may be involved in carrying one or more sequences of one or more instructions to processor 104 for execution. For example, the instructions may initially be carried on a disk of a remote computer. The remote computer can load the instructions into its dynamic memory and send the instructions over a telephone line using a modem. A modem local to computer system 100 can receive the data over the telephone line and use an infrared transmitter to convert the data into an infrared signal. An infrared detector coupled to bus 102 can receive the data carried in the infrared signal and place the data on bus 102. Bus 102 carries the data to main memory 106, from which processor 104 retrieves and executes the instructions. The instructions received by main memory 106 may optionally be stored on storage device 110, whether before or after execution by processor 104.

[0143] The computer system 100 may also include a communication interface 118 coupled to the bus 102. The communication interface 118 provides a bidirectional data communication coupling to a network link 120, which is connected to a local network 122. For example, the communication interface 118 may be an integrated services digital network (ISDN) card or a modem to provide a data communication connection with a corresponding type of telephone line. As another example, the communication interface 118 may be a local area network (LAN) card to provide a data communication connection with a compatible LAN. A wireless link may also be implemented. In any such implementation, the communication interface 118 sends and receives electrical, electromagnetic, or optical signals that carry digital data streams representing various types of information.

[0144] The network link 120 typically provides data communication to other data devices through one or more networks. For example, the network link 120 can provide a connection to a host computer 124 or data equipment operated by an Internet service provider (ISP) 126 through a local network 122. The ISP 126 thus provides data communication services through a global packet data communication network, now generally referred to as the "Internet" 128. Both the local network 122 and the Internet 128 use electrical, electromagnetic or optical signals that carry digital data streams. The signals through the various networks and the signals on the network link 120 and through the communication interface 118, which carry the digital data to and from the computer system 100, are exemplary forms of carrier waves that transport the information.

[0145] The computer system 100 can send messages and receive data (including program code) through the network, network link 120 and communication interface 118. In the Internet example, the server 130 can transmit the request code for the application program through the Internet 128, ISP 126, local network 122 and communication interface 118. For example, one such downloaded application can provide the illumination optimization of the embodiment. The received code can be executed by the processor 104 when it is received, and / or stored in the storage device 110 or other non-volatile storage device for later execution. In this way, the computer system 100 can obtain the application code in the form of a carrier wave.

[0146] Although the concepts disclosed herein may be used for imaging on substrates such as silicon wafers, it should be understood that the disclosed concepts may be used with any type of lithography imaging system, such as those used for imaging on substrates other than silicon wafers.

[0147] The embodiments of the present disclosure can be further described by the following clauses.

[0148] 1. A non-transitory computer readable medium having instructions, which when executed by a computer, cause the computer to perform a method for determining a mask rule check violation associated with a mask feature, the method comprising:

[0149] placing a detector at a location on an edge of a mask feature, wherein the detector is a two-dimensional (2D) geometry;

[0150] changing the size of the detector until the detector contacts a specified point, the specified point being on an edge of a mask feature or on an edge of another mask feature;

[0151] determining a local feature size based on a size of the detector that caused contact with the specified point; and

[0152] Mask rule check (MRC) violations are determined based on local feature sizes.

[0153] 2. The computer-readable medium of clause 1, wherein the MRC violation comprises a maximum critical dimension (CD) violation.

[0154] 3. The computer-readable medium of clause 2, wherein a maximum CD violation occurs when a local feature size exceeds the maximum CD.

[0155] 4. A computer-readable medium according to clause 1, wherein the MRC violation comprises a violation of minimum CD.

[0156] 5. The computer-readable medium of clause 4, wherein a minimum CD violation occurs when a local feature size is less than the minimum CD.

[0157] 6. The computer-readable medium of clause 1, wherein determining the MRC violation comprises:

[0158] MRC violations are determined based on local feature sizes at a plurality of locations on the edge of the mask feature.

[0159] 7. The computer-readable medium of clause 1, further comprising:

[0160] A core function for obtaining local feature sizes; and

[0161] A cost function is determined based on the core function, wherein the cost function indicates a degree of MRC violation.

[0162] 8. The computer-readable medium of clause 7, further comprising:

[0163] A gradient of the cost function is obtained based on one or more of the cost function, local feature size, or geometry of the mask features.

[0164] 9. The computer-readable medium of clause 7, further comprising:

[0165] The mask features are adjusted based on the cost function and the gradient of the cost function to eliminate MRC violations.

[0166] 10. The computer-readable medium of clause 6, wherein adjusting the mask characteristics is an iterative process, wherein each iteration comprises:

[0167] (a) obtaining imaging characteristics of mask features;

[0168] (b) determining whether the imaging characteristics satisfy imaging criteria;

[0169] (c) determining whether the mask features satisfy the MRC criterion;

[0170] (d) calculating a cost function indicating an MRC violation; and

[0171] (e) In response to determining that the imaging criterion or the MRC criterion is not satisfied, adjusting the geometry of the mask features to reduce the cost function.

[0172] 11. The computer-readable medium of clause 10, wherein adjusting the geometry of the mask features comprises adjusting at least one of a shape or a size of the mask features.

[0173] 12. The computer-readable medium of clause 9, wherein the mask features are adjusted until the cost function is minimized.

[0174] 13. The computer-readable medium of clause 1, wherein the detector is a circle.

[0175] 14. The computer-readable medium of clause 13, wherein the local feature size is determined based on a radius of a circle.

[0176] 15. The computer-readable medium of clause 1, wherein the local feature size indicates an interior local feature size when the detector is placed within the mask feature and the detector contacts a specified point on an edge of the mask feature.

[0177] 16. The computer-readable medium of clause 1, wherein when the detector is positioned outside of a mask feature and the detector contacts a specified point on an edge of another mask feature, the local feature size indicates an exterior local feature size.

[0178] 17. The computer-readable medium of clause 1, further comprising:

[0179] The mask design is verified for MRC violations based on local feature sizes of a plurality of mask features in the mask design.

[0180] 18. The computer-readable medium of clause 1, further comprising:

[0181] The mask design is updated to determine a shape or size of the mask feature based on a local feature size of the mask feature of the mask design.

[0182] 19. The computer-readable medium of clause 18, wherein updating the mask design comprises:

[0183] (a) simulating a mask optimization process to determine mask features of a mask design using a design layout, the design layout corresponding to features to be printed on a substrate;

[0184] (b) determining the portion of the mask feature that violates the MRC via the local feature size;

[0185] (c) in response to violating the MRC, modifying a corresponding portion of the mask feature to satisfy the MRC; and

[0186] Repeat steps (a) to (c).

[0187] 20. The computer-readable medium of clause 19, the mask optimization process comprising at least one of a mask-only optimization process, a source mask optimization process, or an optical proximity effect correction process.

[0188] 21. The computer-readable medium of clause 1, wherein the shape of the mask feature is a curve.

[0189] 22. A computer-readable medium according to item 1, wherein the MRC includes one or more geometric characteristics associated with the mask feature, the geometric characteristics including at least one of: a minimum CD of the mask feature that can be manufactured, a minimum curvature of the mask feature that can be manufactured, or a minimum space between two mask features that can be manufactured.

[0190] 23. A non-transitory computer readable medium having instructions which, when executed by a computer, cause the computer to perform a method for updating a mask design to reduce mask rule check violations associated with mask features, the method comprising:

[0191] obtaining local feature sizes associated with mask features of a mask design;

[0192] determining a mask rule check (MRC) violation of a mask feature based on a local feature size; and

[0193] Based on the local feature size, the mask features are adjusted to satisfy the MRC.

[0194] 24. The computer-readable medium of clause 23, wherein the MRC violation comprises a maximum critical dimension (CD) violation.

[0195] 25. The computer-readable medium of clause 24, wherein a maximum CD violation occurs when a local feature size exceeds the maximum CD.

[0196] 26. A computer-readable medium according to clause 23, wherein the MRC violation comprises a violation of minimum CD.

[0197] 27. The computer-readable medium of clause 26, wherein a minimum CD violation occurs when a local feature size is less than the minimum CD.

[0198] 28. The computer-readable medium of clause 23, wherein determining the MRC violation comprises:

[0199] MRC violations are determined based on local feature sizes at a plurality of locations on the edge of the mask feature.

[0200] 29. The computer-readable medium of clause 23, wherein adjusting the mask characteristics comprises:

[0201] The core function for obtaining the local feature size;

[0202] determining a cost function based on the core function, wherein the cost function indicates a degree of MRC violation; and

[0203] A gradient of the cost function is obtained based on one or more of the cost function, local feature size, or geometry of the mask features.

[0204] 30. The computer-readable medium of clause 29, further comprising:

[0205] The mask features are adjusted based on the cost function and the gradient of the cost function to eliminate MRC violations.

[0206] 31. The computer-readable medium of clause 30, wherein adjusting the mask characteristics is an iterative process, wherein each iteration comprises:

[0207] (a) obtaining imaging characteristics of mask features;

[0208] (b) determining whether the imaging characteristics satisfy imaging criteria;

[0209] (c) determining whether the mask features satisfy the MRC criterion;

[0210] (d) calculating a cost function indicating an MRC violation; and

[0211] (e) In response to determining that the imaging criterion or the MRC criterion is not satisfied, adjusting the geometry of the mask features to reduce the cost function.

[0212] 32. The computer-readable medium of clause 31, wherein adjusting the geometry of the mask features comprises adjusting at least one of a shape or a size of the mask features.

[0213] 33. The computer-readable medium of clause 30, wherein the mask features are adjusted until the cost function is minimized.

[0214] 34. The computer-readable medium of clause 23, further comprising:

[0215] The mask design is verified for MRC violations based on local feature sizes of a plurality of mask features in the mask design.

[0216] 35. The computer-readable medium of clause 23, further comprising:

[0217] The mask design is updated to determine a shape or size of the mask feature based on a local feature size of the mask feature of the mask design.

[0218] 36. The computer-readable medium of clause 35, wherein updating the mask design comprises:

[0219] (a) simulating a mask optimization process to determine mask features of a mask design using a design layout, the design layout corresponding to features to be printed on a substrate;

[0220] (b) determining the portion of the mask feature that violates the MRC via the local feature size;

[0221] (c) in response to violating the MRC, modifying a corresponding portion of the mask feature to satisfy the MRC; and

[0222] Repeat steps (a) to (c).

[0223] 37. The computer-readable medium of clause 36, the mask optimization process comprising at least one of a mask-only optimization process, a source mask optimization process, or an optical proximity effect correction process.

[0224] 38. A method for determining a mask rule check violation associated with a mask feature, the method comprising:

[0225] placing a detector at a location on an edge of a mask feature, wherein the detector is a two-dimensional (2D) geometry;

[0226] changing the size of the detector until the detector contacts a specified point, the specified point being on an edge of a mask feature or on an edge of another mask feature;

[0227] determining a local feature size based on a size of the detector that caused contact with the specified point; and

[0228] Mask rule check (MRC) violations are determined based on local feature sizes.

[0229] 39. An apparatus for determining a mask rule check violation associated with a mask feature, the apparatus comprising:

[0230] a memory storing an instruction set; and

[0231] A processor configured to execute a set of instructions to cause the device to perform the following method:

[0232] placing a detector at a location on an edge of a mask feature, wherein the detector is a two-dimensional (2D) geometry;

[0233] changing the size of the detector until the detector contacts a specified point, the specified point being on an edge of a mask feature or on an edge of another mask feature;

[0234] determining a local feature size based on a size of the detector that caused contact with the specified point; and

[0235] Mask rule check (MRC) violations are determined based on local feature sizes.

[0236] As used herein, the terms "optimizing" and "optimization" refer to or mean adjusting a patterning device (e.g., a lithographic device), a patterning process, etc., so that the result and / or process has a more desired characterization, such as higher accuracy in projecting a design pattern onto a substrate, a larger process window, etc. Therefore, as used herein, the terms "optimizing" and "optimization" refer to or mean a process of identifying one or more values ​​of one or more parameters that provide an improvement (e.g., a local optimum) in at least one relevant metric compared to an initial set of one or more values ​​for those one or more parameters. "Optimal" and other related terms should be interpreted accordingly. In an embodiment, the optimization step may be applied iteratively to provide further improvements to one or more metrics.

[0237] Various aspects of the present invention may be implemented in any convenient form. For example, an embodiment may be implemented by one or more appropriate computer programs, which may be carried on an appropriate carrier medium, which may be a tangible carrier medium (e.g., a disk) or an intangible carrier medium (e.g., a communication signal). An embodiment of the present invention may be implemented using a suitable device, which may particularly take the form of a programmable computer running a computer program, which is arranged to implement the method described herein. Therefore, the embodiments of the present disclosure may be implemented in hardware, firmware, software, or any combination thereof. The embodiments of the present disclosure may also be implemented as instructions stored on a machine-readable medium, which may be read and executed by one or more processors. A machine-readable medium may include any mechanism for storing or sending information in a form readable by a machine (e.g., a computing device). For example, a machine-readable medium may include a read-only memory (ROM); a random access memory (RAM); a disk storage medium; an optical storage medium; a flash memory device; an electrical, optical, acoustic, or other form of propagation signal (e.g., a carrier wave, an infrared signal, a digital signal, etc.), and others. Further, firmware, software, routines, instructions may be described herein as performing certain actions. However, it should be understood that such description is for convenience only and that such actions are in fact caused by a computing device, processor, controller or other means executing firmware, software, routines, instructions or the like.

[0238] In the block diagram, the illustrated components are depicted as discrete functional blocks, but the embodiments are not limited to systems in which the functionality described herein is organized as illustrated. The functionality provided by each of the components may be provided by software or hardware modules that are organized in a manner different from that currently depicted (such as software or hardware that may be doped, combined, replicated, decomposed, distributed (e.g., within a data center or geographically), or organized in other different ways. The functionality described herein may be provided by one or more processors of one or more computers that execute code stored on a tangible, non-transient machine-readable medium. In some cases, a third-party content delivery network may host some or all of the information communicated over the network, in which case, to the extent that the information (e.g., content) is considered to be supplied or otherwise provided, the information may be provided by sending instructions to retrieve the information from the content delivery network.

[0239] Unless otherwise specifically stated, as will be apparent from the discussion, it should be understood that throughout this specification, discussions using terms such as "processing," "computing," "calculating," "determining," etc. refer to the actions or processes of a designated device, such as a special purpose computer or similar special purpose electronic processing / computing device.

[0240] The reader should understand that this application describes several inventions. These inventions are grouped into a single document rather than separating these inventions into multiple isolated patent applications because their related subject matter helps save costs in the application process. However, the different advantages and aspects of such inventions should not be combined. In some cases, embodiments solve all the defects mentioned herein, but it should be understood that the present invention is independently useful, and some embodiments only solve a subset of such problems or provide other unmentioned benefits that are obvious to those skilled in the art who review this disclosure. Due to cost constraints, some inventions disclosed herein may not currently be claimed for protection, and may be claimed in a later filing, such as a continuation application or by amending the current claims. Similarly, due to space constraints, the Abstract and Summary of the Invention sections of this document should not be regarded as a comprehensive list containing all such inventions or all aspects of such inventions.

[0241] It should be understood that the description and drawings are not intended to limit the disclosure to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

[0242] In view of this description, modifications and alternative embodiments of various aspects of the present invention will be apparent to those skilled in the art. Therefore, this description and the accompanying drawings are to be interpreted as illustrative only, and are intended to teach those skilled in the art the general manner of performing the present invention. It is to be understood that the forms of the present invention shown and described herein will be considered as examples of embodiments. Elements and materials may be replaced for those elements and materials illustrated and described herein, parts and processes may be reversed or omitted, certain features may be used independently, and embodiments or features of embodiments may be combined, all of which will be apparent to those skilled in the art after benefiting from this description. Changes may be made to the elements described herein without departing from the spirit and scope of the present invention described in the following claims. The titles used herein are for organizational purposes only and are not meant to be used to limit the scope of the description.

[0243] As used throughout this application, the word "may" is used in a permissive sense (i.e., meaning potential), rather than a mandatory sense (i.e., meaning must). The words "include", "including", and "includes" and the like mean, including but not limited to. As used in this application, the singular forms "a", "an", and "the" include plural indicators unless the content clearly indicates otherwise. Therefore, although other terms and phrases (such as "one or more") are used for one or more elements, for example, references to "one" element or "an" element include combinations of two or more elements. As used herein, unless otherwise specifically stated, the term "or" covers all possible combinations except those that are not feasible. For example, if a component is stated to include A or B, then unless otherwise specifically stated or not feasible, the component may include A, or B, or A and B. As a second example, if it is stated that a component may include A, B, or C, then unless otherwise specifically stated or not feasible, the component may include A, or B, or C, or A and B, or A and C, or B and C, or A, B, and C.

[0244] Terms describing conditional relationships (e.g., "in response to X, Y," "upon X then Y," "if X, then Y," "when X, Y," etc.) encompass causal relationships where the antecedent is a necessary causal condition, the antecedent is a sufficient causal condition, or the antecedent is a contributing causal condition of the effect, e.g., "upon condition Y being obtained then state X occurs" is common to "only upon Y then X occurs" and "upon Y and Z then X occurs." Such conditional relationships are not limited to the effect being obtained immediately following the antecedent, as some effects may be delayed, and in the conditional statement, the antecedent is connected to its effect, e.g., the antecedent is associated with the likelihood of the effect occurring. Unless otherwise indicated, a statement that multiple attributes or functions are mapped to multiple objects (e.g., one or more processors perform steps A, B, C, and D) encompasses all such attributes or functions mapped to all such objects and subsets of attributes or functions mapped to subsets of attributes or functions (e.g., all processors each perform steps A to D, and processor 1 performs step A, processor 2 performs steps B and part of step C, and processor 3 performs part of steps C and step D). Further, unless otherwise indicated, a statement that a value or action is "based on" another condition or value encompasses instances where that condition or value is the only factor as well as instances where that condition or value is one factor among multiple factors. Unless otherwise indicated, a statement that "each" instance of a set has a certain property should not be read as excluding the case where some other identical or similar members of the larger set do not have that property, i.e., each does not necessarily mean every one. References to selections from a range include the endpoints of the range.

[0245] In the above description, any process, description or box in the flowchart should be understood to represent a module, segment or code portion, which includes one or more executable instructions for implementing the specified logical function or step in the process, and alternative implementations are included within the scope of the exemplary embodiments of the present invention, in which functions may be performed out of order as shown or discussed, depending on the functionality involved, including substantially concurrently or in reverse order, as understood by those skilled in the art.

[0246] To the extent that certain U.S. patents, U.S. patent applications, or other materials (e.g., articles) have been incorporated by reference, the text of such U.S. patents, U.S. patent applications, and other materials is incorporated by reference only to the extent that there is no conflict between such materials and the statements and drawings set forth herein. In the event of such a conflict, any such conflicting text in such incorporated by reference U.S. patents, U.S. patent applications, and other materials is specifically not incorporated by reference herein.

[0247] Although certain embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the present disclosure. Indeed, the novel methods, devices, and systems described herein may be implemented in a variety of other forms; furthermore, various omissions, substitutions, and changes in the form of the methods, devices, and systems described herein may be made without departing from the spirit of the present disclosure. The appended claims and their equivalents are intended to cover such forms or modifications that fall within the scope and spirit of the present disclosure.

Claims

1. A non-transitory computer-readable medium having instructions, which, when executed by a computer, cause the computer to perform a method for determining a mask rule check violation associated with a mask feature, the method comprising: placing a detector at a location on an edge of a mask feature, wherein the detector is a two-dimensional (2D) geometry; changing the size of the detector until the detector contacts a specified point, the specified point being on the edge of the mask feature or on an edge of another mask feature; determining a local feature size based on the size of the detector that caused the contact with the specified point; and A mask rule check (MRC) violation is determined based on the local feature size.

2. The computer-readable medium of claim 1, wherein the MRC violation comprises a violation of a maximum critical dimension (CD) or a minimum CD.

3. The computer-readable medium of claim 1 , wherein determining the MRC violation comprises: The MRC violations are determined based on the local feature sizes at a plurality of locations on the edge of the mask features.

4. The computer-readable medium of claim 1 , further comprising: Obtaining a kernel function of the local feature size; and A cost function is determined based on the core function, wherein the cost function indicates a degree of the MRC violation.

5. The computer-readable medium of claim 4, further comprising: A gradient of the cost function is obtained based on one or more of the cost function, the local feature size, or a geometry of the mask features.

6. The computer-readable medium of claim 5, further comprising: The mask features are adjusted based on the cost function and a gradient of the cost function to eliminate the MRC violation.

7. The computer-readable medium of claim 1, wherein the detector is a circle, and wherein the local feature size is determined based on a radius of the circle.

8. The computer-readable medium of claim 1, wherein the local feature size indicates an internal local feature size when the detector is placed within the mask feature and the detector contacts the designated point on the edge of the mask feature.

9. The computer-readable medium of claim 1, wherein the local feature size indicates an exterior local feature size when the detector is positioned outside the mask feature and the detector contacts the designated point on the edge of another mask feature.

10. The computer-readable medium of claim 1, further comprising: The mask design is verified for MRC violations based on local feature sizes of a plurality of mask features in the mask design.

11. The computer-readable medium of claim 1 , further comprising: Based on local feature sizes of mask features of the mask design, the mask design is updated to determine a shape or size of the mask features.

12. The computer readable medium of claim 10, wherein updating the mask design comprises: (a) simulating a mask optimization process to determine the mask features of the mask design using a design layout, the design layout corresponding to the features to be printed on a substrate; (b) determining, via the local feature size, a portion of the mask feature that violates the MRC; (c) in response to violating the MRC, modifying the corresponding portion of the mask feature to satisfy the MRC; as well as Repeat steps (a) to (c).

13. The computer readable medium of claim 11, the mask optimization process comprising at least one of: a mask-only optimization process, a source mask optimization process, or an optical proximity effect correction process.

14. The computer-readable medium of claim 1, wherein the shape of the mask feature is a curve.

15. The computer-readable medium of claim 1, wherein the MRC comprises one or more geometric properties associated with the mask feature, the geometric properties comprising at least one of: a minimum CD of the mask feature that can be manufactured, a minimum curvature of the mask feature that can be manufactured, or a minimum space between two mask features that can be manufactured.

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